S71WS256NB0BAWYJ3 概述
Stacked Multi-Chip Product (MCP) 堆叠式多芯片产品( MCP )
S71WS256NB0BAWYJ3 数据手册
通过下载S71WS256NB0BAWYJ3数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载S71WS-N
Stacked Multi-Chip Product (MCP)
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with CellularRAM™
S71WS-N Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71WS-N_00
Revision A
Amendment 6
Issue Date July 19, 2006
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
ii
S71WS-N
S71WS-N_00_A6 July 19, 2006
S71WS-N
Stacked Multi-Chip Product (MCP)
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with CellularRAM™
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V
Burst Speed: 54 MHz, 66 MHz, 80 MHz
Package
– 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
– Wireless, –25° C to +85° C
General Description
The S71WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items:
One or more flash memory die (for the S71WS512N, two S29WS256N devices are used)
CellularRAM Type 2 pSRAM
The products covered by this document are listed in the table below. For details about their specifications, please refer to the
individual constituent datasheet for further details.
pSRAM
Flash Density
S29WS128N
S29WS256N
S29WS512N
32 Mb
64 Mb
128 Mb
S71WS128NB0
S71WS128NC0
S71WS256NC0
S71WS512NC0
S71WS256ND0
S71WS512ND0
For detailed specifications, please refer to the individual data sheets.
Document
Publication Identification Number (PID)
S29WS-N
S29WS-N_00
Cellram_04
Cellram_06
Cellram_07
128 M CellularRAM Type 2
32 M CellularRAM Type 2
64 M CellularRAM Type 2
Publication Number S71WS-N_00
Revision A
Amendment 6
Issue Date July 19, 2006
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
1. Product Selector Guide
DYB
Power-Up
State
pSRAM
Speed
(MHz)
pSRAM
Density Speed
(Mb)
Flash
pSRAM
(Cellular RAM)
Supplier
Model
Numbers
Package
(mm)
Device
Flash
(MHz)
(See Note)
AK
AP
AJ
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
54
54
66
80
54
66
80
54
66
80
54
66
80
54
66
80
54
66
80
S71WS128NB0
WS128N
32
66
80
54
66
80
54
66
80
54
66
80
54
66
80
54
66
80
2
8.0X11.6X1.2
8.0X11.6X1.2
11.6x8.0x1.2
9x12x1.2
AN
AH
AM
AK
AP
AJ
S71WS128NC0
S71WS256NC0
S71WS256ND0
S71WS512NC0
S71WS512ND0
WS128N
64
2
AN
AH
AM
AK
AP
AJ
2
2
2
64
AN
AH
AM
YK
YP
YJ
WS256N
128
2
YN
YH
YM
AK
AP
TJ
2
2
2
11.6x8.0x1.2
11.6x8.0x1.4
64
TN
TH
TM
EK
EP
EJ
WS512N
128
2
9x12x1.4
EN
EH
EM
Note:
0 (Protected), 1 (Unprotected [Default State])
2
S71WS-N
S71WS-N_00_A6 July 19, 2006
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
2. Ordering Information
The order number is formed by a valid combinations of the following:
S71WS 256
N
C
0
BA
W
A
K
0
Packing Type
0
2
3
= Tray
= 7” Tape and Reel
= 13” Tape and Reel
RAM Supplier, DYB Power Up, Speed Combinations
K
P
J
N
H
M
= 2 = CellularRAM 2, 0, 54 MHz
= 2 = CellularRAM 2, 1, 54 MHz
= 2 = CellularRAM 2, 0, 66 MHz
= 2 = CellularRAM 2, 1, 66 MHz
= 2 = CellularRAM 2, 0, 80 MHz
= 2 = CellularRAM 2, 1, 80 MHz
Package Modifier
A
T
E
Y
= 8x11.6x1.2 mm, 84-ball FBGA
= 8x11.6x1.4 mm, 84-ball FBGA
= 9x12x1.4 mm, 84-ball FBGA
= 9x12x1.2 mm, 84-ball FBGA
Temperature Range
W = Wireless (-25°C to +85°C)
Package Type
BA = Very Thin FIne-Pitch BGA, Lead (Pb)-free Compliant Package
BF = Very Thin FIne-Pitch BGA, Lead (Pb)-free Package
Chip Contents—2
No content
pSRAM Density
B
C
D
= 32 Mb
= 64 Mb
= 128 Mb
Process Technology
= 110-nm MirrorBit™ Technology
N
Code Flash Density
512= 512 Mb (2x256Mb)
256= 256 Mb
128= 128 Mb
Product Family
S71WS = Multi-Chip Product, 1.8 Volt-only Simultaneous Read/Write Burst
Mode Flash Memory + pSRAM
2.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Table 2.1 MCP Configurations and Valid Combinations
Valid Combinations
B
C
C
D
A
A
A
Y
A
T
E
K, P, J, N, H, M
K, P, J, N, H, M
K, P, J, N, H, M
K, P, J, N, H, M
K, P, H, M
S71WS128N
S71WS256N
0
BAW, BFW
C
D
S71WS512N
J, N, H, M
K, P, J, N, H, M
Package Marking Note:
The package marking omits the leading S from the ordering part number.
July 19, 2006 S71WS-N_00_A6
S71WS-N
3
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
3. Input/Output Descriptions
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
A23-A0
Description
Address inputs
DQ15-DQ0
OE#
Data input/output
Output Enable input. Asynchronous relative to CLK for the Burst mode.
WE#
Write Enable input.
V
Ground
SS
NC
No Connect; not connected internally
RDY
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal
CLK
address counter. Should be at V or V while in asynchronous mode
IL
IH
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched.
High = device ignores address inputs
AVD#
F-RST#
F-WP#
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At V , disables program and erase functions in the four outermost sectors. Should be
IL
at V for all other conditions.
IH
Accelerated input. At V , accelerates programming; automatically places device in unlock bypass mode. At V
,
IL
HH
F-ACC
disables all program and erase functions. Should be at V for all other conditions.
IH
R-CE1#
F1-CE#
F2-CE#
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
DNU
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb MCP only.
Control Register Enable (pSRAM). For CellularRAM only.
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
4
S71WS-N
S71WS-N_00_A6 July 19, 2006
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
4. MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
22
16
DQ15 to DQ0
CLK
WP#
ACC
ACC
CE#
OE#
WE#
RESET#
AVD#
Flash 1
(Note 2)
F1-CE#
(Note 4)
Flash 2
OE#
WE#
F-RST#
AVD#
RDY
RDY
VSS
(Note 2)
F2-CE#
R-VCC
22
VCCQ
VCC
16
I/O15 to I/O0
CLK
R-CE1#
CE#
WE#
OE#
pSRAM
WAIT#
R-UB#
R-LB#
R-CE2
UB#
LB#
V
SSQ
AVD#
CRE#
(Note 1)
R-CRE
Notes:
1. R-CRE is only present in CellularRAM-compatible pSRAM.
2. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash.
3. Only needed for S71WS512N.
4. For the 128M pSRAM devices, there are 23 shared addresses.
5. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71WS-N.
5.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
July 19, 2006 S71WS-N_00_A6
S71WS-N
5
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5.2
5.2.1
Connection Diagrams
CellularRAM Based Pinout
84-ball Fine-Pitch Ball Grid Array
CellularRAM-based Pinout (Top View, Balls Facing Down)
Legend
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
Shared
AVD#
C2
F-WP#
D2
Flash Shared only
RFU
D9
R-LB#
D4
ACC
D5
WE#
D6
A8
A11
D8
D7
1st Flash only
2nd Flash only
A3
R-UB# F-RST#
RFU
E6
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
A2
F2
A1
G2
A0
A5
F3
A20
F6
A9
A13
F8
A21
F9
F7
RAM only
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE# OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
L2
L3
L4
L5
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
Notes:
1. In MCPs based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two S29WS256N (S71WS512), ball B5 is
F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A20-A0
S71WS128NB0
S71WS128NC0
S71WS256NC0
S71WS256ND0
S71WS512NC0
S71WS512ND0
A22-A21
A22
A21-A0
A23 – A22
A23
A21 – A0
A22 – A0
A21-A0
A23 – A22
A23
A22-A0
6
S71WS-N
S71WS-N_00_A6 July 19, 2006
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5.2.2
Look-Ahead Pinout for Future Designs
Please refer to the Design-in Scalable Wireless Solutions with Spansion Products application note
(publication number: Design_Scalable_Wireless_A0_E). Contact your local Spansion sales representative for
more details.
5.3
5.3.1
Physical Dimensions
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
July 19, 2006 S71WS-N_00_A6
S71WS-N
7
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5.3.2
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.4 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
FTA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
1.02
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.17
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,E1,E10
F1,F10,G1,G10,H1,H10
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
3388 \ 16-038.21a
8
S71WS-N
S71WS-N_00_A6 July 19, 2006
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5.3.3
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.2 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TSD 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.94
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
A2,A3,A4,A5,A6,7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3426\ 16-038.22
July 19, 2006 S71WS-N_00_A6
S71WS-N
9
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5.3.4
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
0.15
b
M
C
C
A B
0.08
M
NOTES:
PACKAGE
JEDEC
FEA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.10
1.11
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.26
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
Note:
BSC is an ANSI standard for Basic Space Centering.
10
S71WS-N
S71WS-N_00_A6 July 19, 2006
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6. Revision History
Section
Description
Revision A (February 1, 2004)
Initial release.
Revision A1 (February 9, 2005)
Updated document to include Burst Speed of 66 MHz
Updated Publication Number
Global
Revision A2 (March 31, 2005)
Global
Updated Product Selector Guide and Ordering Information tables
Revision A3 (May 2, 2005)
Added 80 MHz speed options to:
Product Selector Guide
Global
Ordering Information table
Valid Combination table
Revision A4 (August 25, 2005)
Global
Replaced module cellRAM_00_A0 with cellRAM_03 and cellRAM_04
Revision A5 (February 7, 2006)
Updated Product Selector Guide with new options
Updated the Ordering Part Number table
Updated the Valid Combinations table
Removed the Look-ahead Diagram
Global
Revision A6 (July 19, 2006)
Reformatted document to new template
Global
Added reference to 32 Mb CellRAM module
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2004-2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations
thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
July 19, 2006 S71WS-N_00_A6
S71WS-N
11
S71WS256NB0BAWYJ3 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
S71WS256NB0BAWYK0 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYK2 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYK3 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYN0 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYN2 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYN3 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYP0 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYP2 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BAWYP3 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 | |
S71WS256NB0BFWAJ0 | SPANSION | Stacked Multi-Chip Product (MCP) | 获取价格 |
S71WS256NB0BAWYJ3 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6