S71WS256NC0BAWAK [SPANSION]
Memory Circuit, 16MX16, CMOS, PBGA84, 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84;
| 型号： | S71WS256NC0BAWAK |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 16MX16, CMOS, PBGA84, 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84 |
| 文件： | 总214页 (文件大小：3554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71WS-N
Stacked Multi-Chip Product (MCP)
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with CellularRAM™
ADVANCE
INFORMATION
Data Sheet
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Publication Number S71WS-N_00 Revision A Amendment 5 Issue Date February 7, 2006
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
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S71WS-N
S71WS-N_00_A5 February 7, 2006
S71WS-N
Stacked Multi-Chip Product (MCP)
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with CellularRAM™
ADVANCE
INFORMATION
Data Sheet
General Description
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pSRAM
Flash Density
32 Mb
64 Mb
128 Mb
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6ꢊꢋ:6ꢊꢉꢌ1
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6ꢇꢈ:6ꢉꢈꢊ1'ꢏ
Distinctive Characteristics
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Publication Number S71WS-N_00 Revision A Amendment 5 Issue Date February 7, 2006
A d v a n c e I n f o r m a t i o n
Contents
S71WS-N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Connection Diagrams/Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Special Handling Instructions for FBGA Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2
3
4
5
5.2.1
CellularRAM Based Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.2.2 Look-Ahead Pinout for Future Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.3 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.3.1
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm. . . . . . . . . . . . . . . . . . . . . . . . .16
5.3.2 FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.4 mm. . . . . . . . . . . . . . . . . . . . . . . . .17
5.3.3 TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . .18
5.3.4 FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . .19
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
7
8
9
10 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3 Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.4 Synchronous (Burst) Read Mode & Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.4.5 Continuous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4.6 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.4.7 8-, 16-, 32-Word Linear Burst without Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.4.8 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.5 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.6 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.6.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.6.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.6.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.6.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.6.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.6.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.6.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.7 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.8 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.9 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.10 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.11 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
11.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
11.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
11.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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11.7.1
WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.7.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.7.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.7.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.7.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
14.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
14.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
14.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
14.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
15.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
16 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
64Mb CellularRAM Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
17 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
18 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
18.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
19 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
19.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
19.2 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
19.3 Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.4 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
19.5 Wait Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
19.6 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
20 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
20.1 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
20.2 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
20.3 Partial Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
20.4 Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
21 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
21.1 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
21.2 Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
21.3 Bus Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
21.3.1 Burst Length (BCR[2:0]): Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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21.3.2 Burst Wrap (BCR[3]): Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
21.3.3 Output Impedance (BCR[5]): Default = Outputs Use Full Drive Strength. . . . . . . . . . . . . . . . . . . . . . . 121
21.3.4 Wait Configuration (BCR[8]): Default = Wait Transitions One Clock Before Data Valid/Invalid. . . .122
21.3.5 Wait Polarity (BCR[10]): Default = Wait Active High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
21.3.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
21.3.7 Operating Mode (BCR[15]): Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
21.4 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
21.4.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
21.4.2 Deep Power-Down (RCR[4]): Default = DPD Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
21.4.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC Operation . . . . . . . . . . . . . . . . . . . 125
21.4.4 Page Mode Operation (RCR[7]): Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
22 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
23 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
24 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
24.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
128Mb CellularRAM Type 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
25 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
26 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
26.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
27.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
27.2 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
27.3 Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
27.4 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
27.5 Wait Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
27.6 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
28 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
28.1 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
28.2 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
28.3 Partial Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
28.4 Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
29 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
29.1 Access Using Control Register Enable (CRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
29.2 Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
29.3 Bus Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
29.3.1 Burst Length (BCR[2:0]): Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
29.3.2 Burst Wrap (BCR[3]): Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
29.3.3 Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . 172
29.3.4 Wait Configuration (BCR[8]):
Default = Wait Transitions One Clock Before Data Valid/Invalid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
29.3.5 Wait Polarity (BCR[10]): Default = Wait Active High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
29.3.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
29.3.7 Initial Access Latency (BRC[14]): Default = Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
29.3.8 Operating Mode (BCR[15]):Default = Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
29.4 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
29.4.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
29.4.2 Deep Power-Down (RCR[4]): Default = DPD Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
29.4.3 Page Mode Operation (RCR[7]): Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
29.4.4 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
32 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
32.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
33 CellularRAM Type 2 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
33.1 Revision A (May 16, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
34 MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
4
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
Tables
7DEOHꢀꢊꢃꢈ
7DEOHꢀꢐꢃꢈ
7DEOHꢀꢌꢃꢈ
7DEOHꢀꢋꢃꢈ
0&3ꢀ&RQILJXUDWLRQVꢀDQGꢀ9DOLGꢀ&RPELQDWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢈꢈ
,QSXWꢑ2XWSXWꢀ'HVFULSWLRQVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢈꢊ
,QSXWꢑ2XWSXWꢀ'HVFULSWLRQVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢈ
6ꢊꢋ:6ꢊꢉꢌ1ꢀ6HFWRUꢀꢒꢀ0HPRU\ꢀ$GGUHVVꢀ0DSꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢓ
7DEOHꢀꢋꢃꢊꢃ 6ꢊꢋ:6ꢈꢊꢍ1ꢀ6HFWRUꢀꢒꢀ0HPRU\ꢀ$GGUHVVꢀ0DSꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢉ
7DEOHꢀꢈꢏꢃꢈ 'HYLFHꢀ2SHUDWLRQVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢌ
7DEOHꢀꢈꢏꢃꢊ :RUGꢀ6HOHFWLRQꢀZLWKLQꢀDꢀ3DJH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢇ
7DEOHꢀꢈꢏꢃꢐ $GGUHVVꢀ/DWHQF\ꢀꢁ6ꢊꢋ:6ꢊꢉꢌ1ꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢋ
7DEOHꢀꢈꢏꢃꢓ $GGUHVVꢀ/DWHQF\ꢀꢁ6ꢊꢋ:6ꢈꢊꢍ1ꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢋ
7DEOHꢀꢈꢏꢃꢉ $GGUHVVꢑ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢊꢋ:6ꢊꢉꢌ1ꢀ#ꢀꢍꢏ0+]ꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢋ
7DEOHꢀꢈꢏꢃꢌ $GGUHVVꢑ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢊꢋ:6ꢊꢉꢌ1ꢀ#ꢀꢌꢌꢀ0+]ꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢋ
7DEOHꢀꢈꢏꢃꢇ $GGUHVVꢑ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢊꢋ:6ꢊꢉꢌ1ꢀ#ꢀꢉꢓ0+]ꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢋ
7DEOHꢀꢈꢏꢃꢍ $GGUHVVꢑ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢊꢋ:6ꢈꢊꢍ1ꢂꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢋ
7DEOHꢀꢈꢏꢃꢋ %XUVWꢀ$GGUHVVꢀ*URXSVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢈ
7DEOHꢀꢈꢏꢃꢈꢏ &RQILJXUDWLRQꢀ5HJLVWHU ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢊ
7DEOHꢀꢈꢏꢃꢈꢈ $XWRVHOHFWꢀ$GGUHVVHVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢐ
7DEOHꢀꢈꢏꢃꢈꢊ $XWRVHOHFWꢀ(QWU\ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢓ
7DEOHꢀꢈꢏꢃꢈꢐ $XWRVHOHFWꢀ([LWꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢓ
7DEOHꢀꢈꢏꢃꢈꢓꢃ 6LQJOHꢀ:RUGꢀ3URJUDPꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢇ
7DEOHꢀꢈꢏꢃꢈꢉꢃ :ULWHꢀ%XIIHUꢀ3URJUDPꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢋ
7DEOHꢀꢈꢏꢃꢈꢌꢃ 6HFWRUꢀ(UDVHꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢈ
7DEOHꢀꢈꢏꢃꢈꢇꢃ &KLSꢀ(UDVHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢐ
7DEOHꢀꢈꢏꢃꢈꢍꢃ (UDVHꢀ6XVSHQGꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢓ
7DEOHꢀꢈꢏꢃꢈꢋꢃ (UDVHꢀ5HVXPH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢓ
7DEOHꢀꢈꢏꢃꢊꢏꢃ 3URJUDPꢀ6XVSHQGꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢉ
7DEOHꢀꢈꢏꢃꢊꢈꢃ 3URJUDPꢀ5HVXPH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢉ
7DEOHꢀꢈꢏꢃꢊꢊꢃ 8QORFNꢀ%\SDVVꢀ(QWU\ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢌ
7DEOHꢀꢈꢏꢃꢊꢐꢃ 8QORFNꢀ%\SDVVꢀ3URJUDP ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢇ
7DEOHꢀꢈꢏꢃꢊꢓꢃ 8QORFNꢀ%\SDVVꢀ5HVHW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢓꢇ
7DEOHꢀꢈꢏꢃꢊꢉꢃ '4ꢌꢀDQGꢀ'4ꢊꢀ,QGLFDWLRQVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢉꢈ
7DEOHꢀꢈꢏꢃꢊꢌꢃ :ULWHꢀ2SHUDWLRQꢀ6WDWXV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢉꢐ
7DEOHꢀꢈꢏꢃꢊꢇꢃ 5HVHWꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢉꢉ
7DEOHꢀꢈꢈꢃꢈ /RFNꢀ5HJLVWHUꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢉꢍ
7DEOHꢀꢈꢈꢃꢊ 6HFWRUꢀ3URWHFWLRQꢀ6FKHPHVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢌꢓ
7DEOHꢀꢈꢐꢃꢈ ꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ$GGUHVVHVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢌꢇ
7DEOHꢀꢈꢐꢃꢊꢃ 6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ(QWU\ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢌꢋ
7DEOHꢀꢈꢐꢃꢐꢃ 6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ3URJUDP ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢌꢋ
7DEOHꢀꢈꢐꢃꢓꢃ 6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ([LWꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢌꢋ
7DEOHꢀꢈꢓꢃꢈ 7HVWꢀ6SHFLILFDWLRQV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢇꢈ
7DEOHꢀꢈꢓꢃꢊ 6\QFKURQRXVꢀ:DLWꢀ6WDWHꢀ5HTXLUHPHQWV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢇꢉ
7DEOHꢀꢈꢉꢃꢈ ꢀ0HPRU\ꢀ$UUD\ꢀ&RPPDQGVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢋꢉ
7DEOHꢀꢈꢉꢃꢊꢃ 6HFWRUꢀ3URWHFWLRQꢀ&RPPDQGVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢋꢌ
7DEOHꢀꢈꢉꢃꢐꢃ &),ꢀ4XHU\ꢀ,GHQWLILFDWLRQꢀ6WULQJ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢋꢇ
7DEOHꢀꢈꢉꢃꢓꢃ 6\VWHPꢀ,QWHUIDFHꢀ6WULQJꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢋꢇ
7DEOHꢀꢈꢉꢃꢉꢃ 'HYLFHꢀ*HRPHWU\ꢀ'HILQLWLRQꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢋꢍ
7DEOHꢀꢈꢉꢃꢌꢃ 3ULPDU\ꢀ9HQGRUꢅ6SHFLILFꢀ([WHQGHGꢀ4XHU\ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢋꢋ
7DEOHꢀꢈꢇꢃꢈ 6LJQDOꢀ'HVFULSWLRQVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢏꢌ
7DEOHꢀꢈꢇꢃꢊ %XVꢀ2SHUDWLRQV²$V\QFKURQRXVꢀ0RGH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢏꢇ
7DEOHꢀꢈꢇꢃꢐ %XVꢀ2SHUDWLRQV²%XUVWꢀ0RGH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢏꢍ
7DEOHꢀꢈꢍꢃꢈ 3RZHUꢅ8Sꢀ,QLWLDOL]DWLRQꢀ7LPLQJ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢏꢋ
7DEOHꢀꢊꢈꢃꢈ %XVꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀ'HILQLWLRQꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢏ
7DEOHꢀꢊꢈꢃꢊ 6HTXHQFHꢀDQGꢀ%XUVWꢀ/HQJWKꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢈ
7DEOHꢀꢊꢈꢃꢐ 9DULDEOHꢀ/DWHQF\ꢀ&RQILJXUDWLRQꢀ&RGHVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢐ
February 7, 2006 S71WS-N_00_A5
S71WS-N
5
A d v a n c e I n f o r m a t i o n
7DEOHꢀꢊꢈꢃꢓ 5HIUHVKꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀ0DSSLQJꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢓ
7DEOHꢀꢊꢈꢃꢉ ꢌꢓ0Eꢀ$GGUHVVꢀ3DWWHUQVꢀIRUꢀ3$5ꢀꢁ5&5>ꢓ@ꢀ ꢀꢈꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢓ
7DEOHꢀꢊꢐꢃꢈ (OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ2SHUDWLQJꢀ&RQGLWLRQVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢇ
7DEOHꢀꢊꢐꢃꢊ 0D[LPXPꢀ6WDQGE\ꢀ&XUUHQWVꢀIRUꢀ$SSO\LQJꢀ3$5ꢀDQGꢀ7&5ꢀ6HWWLQJV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢍ
7DEOHꢀꢊꢐꢃꢐ 'HHSꢀ3RZHUꢅ'RZQꢀ6SHFLILFDWLRQV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢍ
7DEOHꢀꢊꢓꢃꢈ &DSDFLWDQFHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢋ
7DEOHꢀꢊꢓꢃꢊ 2XWSXWꢀ/RDGꢀ&LUFXLW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢊꢋ
7DEOHꢀꢊꢓꢃꢐ $V\QFKURQRXVꢀ5HDGꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢐꢏ
7DEOHꢀꢊꢓꢃꢓ %XUVWꢀ5HDGꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢐꢈ
7DEOHꢀꢊꢓꢃꢉ $V\QFKURQRXVꢀ:ULWHꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢐꢊ
7DEOHꢀꢊꢓꢃꢌ %XUVWꢀ:ULWHꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢐꢐ
7DEOHꢀꢊꢓꢃꢇ ,QLWLDOL]DWLRQꢀ7LPLQJꢀ3DUDPHWHUVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢐꢐ
7DEOHꢀꢊꢉꢃꢈ 6LJQDOꢀ'HVFULSWLRQVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢉꢇ
7DEOHꢀꢊꢉꢃꢊ %XVꢀ2SHUDWLRQVꢀ±ꢀ$V\QFKURQRXVꢀ0RGH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢉꢍ
7DEOHꢀꢊꢉꢃꢐ %XVꢀ2SHUDWLRQVꢀ±ꢀ%XUVWꢀ0RGH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢉꢍ
7DEOHꢀꢊꢋꢃꢈ 6HTXHQFHꢀDQGꢀ%XUVWꢀ/HQJWKꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢈ
7DEOHꢀꢊꢋꢃꢊ 'ULYHꢀ6WUHQJWKꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢊ
7DEOHꢀꢊꢋꢃꢐ 9DULDEOHꢀ/DWHQF\ꢀ&RQILJXUDWLRQꢀ&RGHVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢓ
7DEOHꢀꢊꢋꢃꢓ )L[HGꢀ/DWHQF\ꢀ&RQILJXUDWLRQꢀ&RGHVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢓ
7DEOHꢀꢊꢋꢃꢉ ꢈꢊꢍ0Eꢀ$GGUHVVꢀ3DWWHUQVꢀIRUꢀ3$5ꢀꢁ5&5>ꢓ@ꢀ ꢀꢈꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢌ
7DEOHꢀꢊꢋꢃꢌ 'HYLFHꢀ,GHQWLILFDWLRQꢀ5HJLVWHUꢀ0DSSLQJ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢌ
7DEOHꢀꢐꢈꢃꢈ (OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ2SHUDWLQJꢀ&RQGLWLRQVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢍ
7DEOHꢀꢐꢈꢃꢊ 3DUWLDOꢀ$UUD\ꢀ5HIUHVKꢀ6SHFLILFDWLRQVꢀDQGꢀ&RQGLWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢍ
7DEOHꢀꢐꢈꢃꢐ 'HHSꢀ3RZHUꢅ'RZQꢀ6SHFLILFDWLRQV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢋ
7DEOHꢀꢐꢈꢃꢓ &DSDFLWDQFHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢇꢋ
7DEOHꢀꢐꢊꢃꢈ $V\QFKURQRXVꢀ5HDGꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢈ
7DEOHꢀꢐꢊꢃꢊ %XUVWꢀ5HDGꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢊ
7DEOHꢀꢐꢊꢃꢐ $V\QFKURQRXVꢀ:ULWHꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢐ
7DEOHꢀꢐꢊꢃꢓ %XUVWꢀ:ULWHꢀ&\FOHꢀ7LPLQJꢀ5HTXLUHPHQWV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢐ
7DEOHꢀꢐꢊꢃꢉ ,QLWLDOL]DWLRQꢀ7LPLQJꢀ3DUDPHWHUVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢓ
7DEOHꢀꢐꢊꢃꢌ $V\QFKURQRXVꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢉ
7DEOHꢀꢐꢊꢃꢇ $V\QFKURQRXVꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ8VLQJꢀ$'9ꢔ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢌ
7DEOHꢀꢐꢊꢃꢍ $V\QFKURQRXVꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ3DJHꢀ0RGHꢀ2SHUDWLRQꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢇ
7DEOHꢀꢐꢊꢃꢋ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ6LQJOHꢀ$FFHVVꢄꢀ9DULDEOHꢀ/DWHQF\ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢍ
7DEOHꢀꢐꢊꢃꢈꢏ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀꢓꢅ:RUGꢀ%XUVW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢍꢋ
7DEOHꢀꢐꢊꢃꢈꢈ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ3DUDPHWHUVꢀ±ꢀ6LQJOHꢀ$FFHVVꢄꢀ)L[HGꢀ/DWHQF\ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢏ
7DEOHꢀꢐꢊꢃꢈꢊ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀꢓꢅ:RUGꢀ%XUVWꢄꢀ)L[HGꢀ/DWHQF\ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢈ
7DEOHꢀꢐꢊꢃꢈꢐ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ6XVSHQG ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢊ
7DEOHꢀꢐꢊꢃꢈꢓ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%&5>ꢍ@ꢀ ꢀꢏꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢐ
7DEOHꢀꢐꢊꢃꢈꢉ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ&(ꢔꢅ&RQWUROOHGꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢓ
7DEOHꢀꢐꢊꢃꢈꢌ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ/%ꢔꢑ8%ꢔꢅ&RQWUROOHG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢉ
7DEOHꢀꢐꢊꢃꢈꢇ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ:(ꢔꢅ&RQWUROOHGꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢌ
7DEOHꢀꢐꢊꢃꢈꢍ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ8VLQJꢀ$'9ꢔ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢇ
7DEOHꢀꢐꢊꢃꢈꢋ %XUVWꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ9DULDEOHꢀ/DWHQF\ꢀ0RGHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢍ
7DEOHꢀꢐꢊꢃꢊꢏ %XUVWꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ)L[HGꢀ/DWHQF\ꢀ0RGHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢋꢋ
7DEOHꢀꢐꢊꢃꢊꢈ %XUVWꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%&5>ꢍ@ꢀ ꢀꢏ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢏ
7DEOHꢀꢐꢊꢃꢊꢊ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ%XUVWꢀ5HDGꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢈ
7DEOHꢀꢐꢊꢃꢊꢐ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ%XUVWꢀ5HDG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢈ
7DEOHꢀꢐꢊꢃꢊꢓ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ:ULWHꢀ,QWHUUXSWHG ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢊ
7DEOHꢀꢐꢊꢃꢊꢉ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ:ULWHꢀ,QWHUUXSWHGꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢊ
7DEOHꢀꢐꢊꢃꢊꢌ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ5HDGꢀ,QWHUUXSWHGꢀ±ꢀ9DULDEOHꢀ/DWHQF\ꢀ0RGHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢐ
7DEOHꢀꢐꢊꢃꢊꢇ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ5HDGꢀ,QWHUUXSWHGꢀ±ꢀ9DULDEOHꢀ/DWHQF\ꢀ0RGH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢐ
7DEOHꢀꢐꢊꢃꢊꢍ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ5HDGꢀ,QWHUUXSWHGꢀ±ꢀ)L[HGꢀ/DWHQF\ꢀ0RGHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢓ
7DEOHꢀꢐꢊꢃꢊꢋ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ%XUVWꢀ5HDGꢀ,QWHUUXSWHGꢀ±ꢀ)L[HGꢀ/DWHQF\ꢀ0RGH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢓ
7DEOHꢀꢐꢊꢃꢐꢏ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ$V\QFKURQRXVꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ%XUVWꢀ5HDGꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢉ
6
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
7DEOHꢀꢐꢊꢃꢐꢈ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ$V\QFKURQRXVꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ%XUVWꢀ5HDG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢉ
7DEOHꢀꢐꢊꢃꢐꢊ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ$'9ꢔꢀ/RZ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢌ
7DEOHꢀꢐꢊꢃꢐꢐ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢌ
7DEOHꢀꢐꢊꢃꢐꢓ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢇ
7DEOHꢀꢐꢊꢃꢐꢉ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ:(ꢔꢅ&RQWUROOHGꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢇ
7DEOHꢀꢐꢊꢃꢐꢌ %XUVWꢀ5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢍ
7DEOHꢀꢐꢊꢃꢐꢇ $V\QFKURQRXVꢀ:ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ8VLQJꢀ$'9ꢔ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢍ
7DEOHꢀꢐꢊꢃꢐꢍ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ$'9ꢔꢀ/RZ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢋ
7DEOHꢀꢐꢊꢃꢐꢋ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ$'9ꢔꢀ/RZ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢏꢋ
7DEOHꢀꢐꢊꢃꢓꢏ :ULWHꢀ7LPLQJꢀ3DUDPHWHUVꢀ±
$V\QFKURQRXVꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ$V\QFKURQRXVꢀ5HDG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢈꢏ
7DEOHꢀꢐꢊꢃꢓꢈ 5HDGꢀ7LPLQJꢀ3DUDPHWHUVꢀ±ꢀ
$V\QFKURQRXVꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ$V\QFKURQRXVꢀ5HDG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢊꢈꢏ
February 7, 2006 S71WS-N_00_A5
S71WS-N
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A d v a n c e I n f o r m a t i o n
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)LJXUHꢀꢇꢃꢈꢃ
6ꢊꢋ:6ꢅ1ꢀ%ORFNꢀ'LDJUDPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢊꢊ
)LJXUHꢀꢈꢏꢃꢈꢃ 6\QFKURQRXVꢑ$V\QFKURQRXVꢀ6WDWHꢀ'LDJUDPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢊꢍ
)LJXUHꢀꢈꢏꢃꢊꢃ 6\QFKURQRXVꢀ5HDG ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢐꢏ
)LJXUHꢀꢈꢏꢃꢐꢃ 6LQJOHꢀ:RUGꢀ3URJUDPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢐꢌ
)LJXUHꢀꢈꢏꢃꢓꢃ :ULWHꢀ%XIIHUꢀ3URJUDPPLQJꢀ2SHUDWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢓꢏ
)LJXUHꢀꢈꢏꢃꢉꢃ 6HFWRUꢀ(UDVHꢀ2SHUDWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢓꢊ
)LJXUHꢀꢈꢏꢃꢌꢃ :ULWHꢀ2SHUDWLRQꢀ6WDWXVꢀ)ORZFKDUW ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢓꢋ
)LJXUHꢀꢈꢈꢃꢈꢃ $GYDQFHGꢀ6HFWRUꢀ3URWHFWLRQꢑ8QSURWHFWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢉꢇ
)LJXUHꢀꢈꢈꢃꢊꢃ 33%ꢀ3URJUDPꢑ(UDVHꢀ$OJRULWKP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢌꢏ
)LJXUHꢀꢈꢈꢃꢐꢃ /RFNꢀ5HJLVWHUꢀ3URJUDPꢀ$OJRULWKPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢌꢐ
)LJXUHꢀꢈꢓꢃꢈꢃ 0D[LPXPꢀ1HJDWLYHꢀ2YHUVKRRWꢀ:DYHIRUP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢇꢏ
)LJXUHꢀꢈꢓꢃꢊꢃ 0D[LPXPꢀ3RVLWLYHꢀ2YHUVKRRWꢀ:DYHIRUPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢇꢏ
)LJXUHꢀꢈꢓꢃꢐꢃ 7HVWꢀ6HWXS ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢇꢈ
)LJXUHꢀꢈꢓꢃꢓꢃ ,QSXWꢀ:DYHIRUPVꢀDQGꢀ0HDVXUHPHQWꢀ/HYHOVꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢇꢊ
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)LJXUHꢀꢊꢓꢃꢊꢈ %XUVWꢀ5HDGꢀ)ROORZHGꢀE\ꢀ$V\QFKURQRXVꢀ:ULWHꢀꢁ:(ꢔꢅ&RQWUROOHGꢂꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢈꢉꢈ
)LJXUHꢀꢊꢓꢃꢊꢊ %XUVWꢀ5HDGꢀ)ROORZHGꢀE\ꢀ$V\QFKURQRXVꢀ:ULWHꢀ8VLQJꢀ$'9ꢔ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢈꢉꢊ
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)LJXUHꢀꢊꢓꢃꢊꢓ $V\QFKURQRXVꢀ:ULWHꢀ)ROORZHGꢀE\ꢀ$V\QFKURQRXVꢀ5HDG ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢈꢉꢓ
February 7, 2006 S71WS-N_00_A5
S71WS-N
9
A d v a n c e I n f o r m a t i o n
1 Product Selector Guide
DYB
Power-Up
State
pSRAM
Density Speed
(Mb)
Flash
pSRAM
Speed
(MHz)
pSRAM
(Cellular RAM)
Supplier
Model
Numbers
Package
(mm)
Device
Flash
(MHz)
(See Note)
$.
$3ꢈ
$-
ꢏ
ꢉꢓ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢏ
ꢈ
ꢏ
ꢈ
ꢏ
6ꢇꢈ:6ꢈꢊꢍ1%ꢏ
:6ꢈꢊꢍ1
ꢐꢊ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢉꢓ
ꢌꢌ
ꢍꢏ
ꢊ
ꢍꢃꢏ;ꢈꢈꢃꢌ;ꢈꢃꢊ
ꢍꢃꢏ;ꢈꢈꢃꢌ;ꢈꢃꢊ
ꢈꢈꢃꢌ[ꢍꢃꢏ[ꢈꢃꢊ
ꢋ[ꢈꢊ[ꢈꢃꢊ
$1
$+
$0
$.
$3ꢈ
$-
ꢏ
ꢈ
ꢏ
ꢈ
ꢏ
6ꢇꢈ:6ꢈꢊꢍ1&ꢏ
6ꢇꢈ:6ꢊꢉꢌ1&ꢏ
6ꢇꢈ:6ꢊꢉꢌ1'ꢏ
6ꢇꢈ:6ꢉꢈꢊ1&ꢏ
6ꢇꢈ:6ꢉꢈꢊ1'ꢏ
:6ꢈꢊꢍ1
ꢌꢓ
ꢊ
$1
$+
$0
$.
$3ꢈ
$-
ꢊ
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ꢏ
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ꢌꢓ
$1
$+
$0
<.
:6ꢊꢉꢌ1
<3ꢈ
<-
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<+
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$.
$3ꢈ
7-
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ꢈꢈꢃꢌ[ꢍꢃꢏ[ꢈꢃꢓ
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71
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10
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
2 Ordering Information
7KHꢀRUGHULQJꢀSDUWꢀQXPEHUꢀLVꢀIRUPHGꢀE\ꢀDꢀYDOLGꢀFRPELQDWLRQꢀRIꢀWKHꢀIROORZLQJꢆ
S71WS 256
N
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0
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&HOOXODU5$0ꢀꢊꢄꢀꢏꢄꢀꢌꢌꢀ0+]
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7
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ꢋ[ꢈꢊ[ꢈꢃꢓPPꢄꢀꢍꢓꢅEDOOꢀ)%*$
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% ꢀꢐꢊꢀ0E
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1
ꢈꢈꢏꢅQPꢀ0LUURU%LWꢀ7HFKQRORJ\
)ODVKꢀ'HQVLW\
ꢉꢈꢊ
ꢊꢉꢌ
ꢈꢊꢍ
ꢉꢈꢊꢀ0Eꢀꢁꢊ[ꢊꢉꢌ0Eꢂ
ꢊꢉꢌꢀ0E
ꢈꢊꢍꢀ0E
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6ꢇꢈ:6 0XOWLꢅ&KLSꢀ3URGXFW
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)ODVKꢀ0HPRU\ꢀꢎꢀS65$0
Table 2.1 MCP Configurations and Valid Combinations
Valid Combinations
%
&
&
'
$
$
$
<
$
7
(
.ꢄꢀ3ꢄꢀ-ꢄꢀ1ꢄꢀ+ꢄꢀ0
.ꢄꢀ3ꢄꢀ-ꢄꢀ1ꢄꢀ+ꢄꢀ0
.ꢄꢀ3ꢄꢀ-ꢄꢀ1ꢄꢀ+ꢄꢀ0
.ꢄꢀ3ꢄꢀ-ꢄꢀ1ꢄꢀ+ꢄꢀ0
.ꢄꢀ3
6ꢇꢈ:6ꢈꢊꢍ1
6ꢇꢈ:6ꢊꢉꢌ1
ꢏ
%$:ꢄꢀ%):
ꢄꢀ+ꢄꢀ0
&
6ꢇꢈ:6ꢉꢈꢊ1
-ꢄꢀ1ꢄꢀ+ꢄꢀ0
'
.ꢄꢀ3ꢄꢀ-ꢄꢀ1ꢄꢀ+ꢄꢀ0
3DFNDJHꢁ0DUNLQJꢁ1RWHꢀ
7KHꢀSDFNDJHꢀPDUNLQJꢀRPLWVꢀWKHꢀOHDGLQJꢀ6ꢀIURPꢀWKHꢀRUGHULQJꢀSDUWꢀQXPEHUꢆ
9DOLGꢀ&RPELQDWLRQV
9DOLGꢀ&RPELQDWLRQVꢀOLVWꢀFRQILJXUDWLRQVꢀSODQQHGꢀWRꢀEHꢀVXSSRUWHGꢀLQꢀYROXPHꢀIRUꢀWKLVꢀGHYLFHꢃꢀ&RQVXOWꢀ
\RXUꢀORFDOꢀVDOHVꢀRIILFHꢀWRꢀFRQILUPꢀDYDLODELOLW\ꢀRIꢀVSHFLILFꢀYDOLGꢀFRPELQDWLRQVꢀDQGꢀWRꢀFKHFNꢀRQꢀQHZO\ꢀ
UHOHDVHGꢀFRPELQDWLRQVꢃ
February 7, 2006 S71WS-N_00_A5
S71WS-N
11
A d v a n c e I n f o r m a t i o n
3 Input/Output Descriptions
7DEOHꢀꢐꢃꢈꢀLGHQWLILHVꢀWKHꢀLQSXWꢀDQGꢀRXWSXWꢀSDFNDJHꢀFRQQHFWLRQVꢀSURYLGHGꢀRQꢀWKHꢀGHYLFHꢃ
Table 3.1 Input/Output Descriptions
Symbol
$ꢊꢐꢅ$ꢏ
Description
$GGUHVVꢀLQSXWVꢀ
'4ꢈꢉꢅ'4ꢏ
2(ꢔ
'DWDꢀLQSXWꢑRXWSXW
2XWSXWꢀ(QDEOHꢀLQSXWꢃꢀ$V\QFKURQRXVꢀUHODWLYHꢀWRꢀ&/.ꢀIRUꢀWKHꢀ%XUVWꢀPRGHꢃ
:(ꢔ
:ULWHꢀ(QDEOHꢀLQSXWꢃ
9
*URXQG
66
1&
1Rꢀ&RQQHFWꢕꢀQRWꢀFRQQHFWHGꢀLQWHUQDOO\
5'<
5HDG\ꢀRXWSXWꢃꢀ,QGLFDWHVꢀWKHꢀVWDWXVꢀRIꢀWKHꢀ%XUVWꢀUHDGꢃꢀ7KHꢀ:$,7ꢔꢀSLQꢀRIꢀWKHꢀS65$0ꢀLVꢀWLHGꢀWRꢀ5'<ꢃ
&ORFNꢀLQSXWꢃꢀ,QꢀEXUVWꢀPRGHꢄꢀDIWHUꢀWKHꢀLQLWLDOꢀZRUGꢀLVꢀRXWSXWꢄꢀVXEVHTXHQWꢀDFWLYHꢀHGJHVꢀRIꢀ&/.ꢀLQFUHPHQWꢀ
&/.
WKHꢀLQWHUQDOꢀDGGUHVVꢀFRXQWHUꢃꢀ6KRXOGꢀEHꢀDWꢀ9 ꢀRUꢀ9 ꢀZKLOHꢀLQꢀDV\QFKURQRXVꢀPRGH
,/
,+
$GGUHVVꢀ9DOLGꢀLQSXWꢃꢀ,QGLFDWHVꢀWRꢀGHYLFHꢀWKDWꢀWKHꢀYDOLGꢀDGGUHVVꢀLVꢀSUHVHQWꢀRQꢀWKHꢀDGGUHVVꢀLQSXWVꢃ
/RZꢀ ꢀIRUꢀDV\QFKURQRXVꢀPRGHꢄꢀLQGLFDWHVꢀYDOLGꢀDGGUHVVꢕꢀIRUꢀEXUVWꢀPRGHꢄꢀFDXVHVꢀVWDUWLQJꢀDGGUHVVꢀWRꢀEHꢀ
ODWFKHGꢃꢀ
$9'ꢔ
+LJKꢀ ꢀGHYLFHꢀLJQRUHVꢀDGGUHVVꢀLQSXWV
)ꢅ567ꢔ
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+DUGZDUHꢀZULWHꢀSURWHFWꢀLQSXWꢃꢀ$Wꢀ9 ꢄꢀGLVDEOHVꢀSURJUDPꢀDQGꢀHUDVHꢀIXQFWLRQVꢀLQꢀWKHꢀIRXUꢀRXWHUPRVWꢀ
,/
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,+
$FFHOHUDWHGꢀLQSXWꢃꢀ$Wꢀ9 ꢄꢀDFFHOHUDWHVꢀSURJUDPPLQJꢕꢀDXWRPDWLFDOO\ꢀSODFHVꢀGHYLFHꢀLQꢀXQORFNꢀE\SDVVꢀ
++
)ꢅ$&&
PRGHꢃꢀ$Wꢀ9 ꢄꢀGLVDEOHVꢀDOOꢀSURJUDPꢀDQGꢀHUDVHꢀIXQFWLRQVꢃꢀ6KRXOGꢀEHꢀDWꢀ9 ꢀIRUꢀDOOꢀRWKHUꢀFRQGLWLRQVꢃ
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&KLSꢅHQDEOHꢀLQSXWꢀIRUꢀ)ODVKꢀꢊꢃꢀ$V\QFKURQRXVꢀUHODWLYHꢀWRꢀ&/.ꢀIRUꢀ%XUVWꢀ0RGHꢃꢀ7KLVꢀDSSOLHVꢀWRꢀWKHꢀꢉꢈꢊ0Eꢀ
0&3ꢀRQO\ꢃ
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5ꢅ9&&
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)ODVKꢀꢈꢃꢍꢀ9ROWꢅRQO\ꢀVLQJOHꢀSRZHUꢀVXSSO\ꢃ
S65$0ꢀ3RZHUꢀ6XSSO\ꢃ
8SSHUꢀ%\WHꢀ&RQWUROꢀꢁS65$0ꢂꢃ
/RZHUꢀ%\WHꢀ&RQWUROꢀꢁS65$0ꢂ
'Rꢀ1RWꢀ8VH
12
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
4 MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
22
16
DQ15 to DQ0
CLK
WP#
ACC
ACC
CE#
OE#
WE#
RESET#
AVD#
Flash 1
ꢁ1RWHꢀꢊꢂ
F1-CE#
ꢁ1RWHꢀꢓꢂ
Flash 2
OE#
WE#
F-RST#
AVD#
RDY
RDY
VSS
ꢁ1RWHꢀꢊꢂ
F2-CE#
R-VCC
22
VCCQ
VCC
16
I/O15 to I/O0
CLK
R-CE1#
CE#
WE#
OE#
pSRAM
WAIT#
R-UB#
R-LB#
R-CE2
UB#
LB#
V
SSQ
AVD#
CRE#
ꢁ1RWHꢀꢈꢂ
R-CRE
1RWHVꢀ
ꢅꢆ 5ꢇ&5(ꢀLVꢀRQO\ꢀSUHVHQWꢀLQꢀ&HOOXODU5$0ꢇFRPSDWLEOHꢀS65$0ꢆ
ꢈꢆ )RUꢀꢅꢀ)ODVKꢀꢉꢀS65$0ꢄꢀ)ꢅꢇ&(-ꢀ ꢀ&(-ꢆꢀ)RUꢀꢈꢀ)ODVKꢀꢉꢀS65$0ꢄꢀ&(-ꢀ ꢀ)ꢅꢇ&(-ꢀDQGꢀ)ꢈꢇ&(-ꢀLVꢀWKHꢀFKLSꢇHQDEOHꢀSLQꢀIRUꢀWKHꢀ
VHFRQGꢀ)ODVKꢆ
ꢊꢆ 2QO\ꢀQHHGHGꢀIRUꢀ6ꢋꢅ:6ꢌꢅꢈ1ꢆ
ꢍꢆ )RUꢀWKHꢀꢅꢈꢎ0ꢀS65$0ꢀGHYLFHVꢄꢀWKHUHꢀDUHꢀꢈꢊꢀVKDUHGꢀDGGUHVVHVꢆ
February 7, 2006 S71WS-N_00_A5
S71WS-N
13
A d v a n c e I n f o r m a t i o n
5 Connection Diagrams/Physical Dimensions
7KLVꢀVHFWLRQꢀFRQWDLQVꢀWKHꢀ,ꢑ2ꢀGHVLJQDWLRQVꢀDQGꢀSDFNDJHꢀVSHFLILFDWLRQVꢀIRUꢀWKHꢀ6ꢇꢈ:6ꢅ1ꢃ
5.1
Special Handling Instructions for FBGA Packages
6SHFLDOꢀKDQGOLQJꢀLVꢀUHTXLUHGꢀIRUꢀ)ODVKꢀ0HPRU\ꢀSURGXFWVꢀLQꢀ)%*$ꢀSDFNDJHVꢃ
)ODVKꢀPHPRU\ꢀGHYLFHVꢀLQꢀ)%*$ꢀSDFNDJHVꢀPD\ꢀEHꢀGDPDJHGꢀLIꢀH[SRVHGꢀWRꢀXOWUDVRQLFꢀFOHDQLQJꢀPHWKꢅ
RGVꢃꢀ7KHꢀSDFNDJHꢀDQGꢑRUꢀGDWDꢀLQWHJULW\ꢀPD\ꢀEHꢀFRPSURPLVHGꢀLIꢀWKHꢀSDFNDJHꢀERG\ꢀLVꢀH[SRVHGꢀWRꢀ
WHPSHUDWXUHVꢀDERYHꢀꢈꢉꢏ&ꢀIRUꢀSURORQJHGꢀSHULRGVꢀRIꢀWLPHꢃ
14
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
5.2 Connection Diagrams
ꢈꢅꢎꢅꢄ
&HOOXODU5$0ꢀ%DVHGꢀ3LQRXW
ꢍꢓꢅEDOOꢀ)LQHꢅ3LWFKꢀ%DOOꢀ*ULGꢀ$UUD\
&HOOXODU5$0ꢅEDVHGꢀ3LQRXWꢀꢁ7RSꢀ9LHZꢄꢀ%DOOVꢀ)DFLQJꢀ'RZQꢂ
Legend
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
Shared
AVD#
C2
F-WP#
D2
Flash Shared only
RFU
D9
R-LB#
D4
ACC
D5
WE#
D6
A8
A11
D8
D7
1st Flash only
2nd Flash only
A3
R-UB# F-RST#
RFU
E6
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
A2
F2
A1
G2
A0
A5
F3
A20
F6
A9
A13
F8
A21
F9
F7
RAM only
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE# OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
L2
L3
L4
L5
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
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15
A d v a n c e I n f o r m a t i o n
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J
H
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E
D
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B
A
M
L K
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10
PIN A1
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PIN A1
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7
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C
TOP VIEW
BOTTOM VIEW
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C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
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0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
16
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
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J
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C
B
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M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
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C
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0.20
0.08
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C
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A
C
A1
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6
84X
b
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C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
FTA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
1.02
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.17
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,E1,E10
F1,F10,G1,G10,H1,H10
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
3388 \ 16-038.21a
February 7, 2006 S71WS-N_00_A5
S71WS-N
17
A d v a n c e I n f o r m a t i o n
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J
H
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F
E
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C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
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CORNER
7
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0.15
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0.20
0.08
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C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TSD 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.94
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
A2,A3,A4,A5,A6,7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3426\ 16-038.22
18
S71WS-N
S71WS-N_00_A5 February 7, 2006
A d v a n c e I n f o r m a t i o n
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H
G
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E
D
C
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A
M
L K
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PIN A1
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7
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0.15
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C
TOP VIEW
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0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
0.15
b
M
C
C
A B
0.08
M
NOTES:
PACKAGE
JEDEC
FEA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.10
1.11
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.26
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
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February 7, 2006 S71WS-N_00_A5
S71WS-N
19
S29WS-N MirrorBitTM Flash Family
S29WS256N, S29WS128N
256/128 Megabit (16/8 M x 16 bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory
PRELIMINARY
Data Sheet
General Description
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Publication Number S29WS-N_m0 Revision I Amendment 0 Issue Date December 3, 2005
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6 Input/Output Descriptions & Logic Symbol
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Table 6.1 Input/Output Descriptions
Symbol
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Description
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December 3, 2005 S29WS-N_m0_I0
21
P r e l i m i n a r y
7 Block Diagram
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22
S29WS-N_m0_I0 December3,2005
P r e l i m i n a r y
8 Additional Resources
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December 3, 2005 S29WS-N_m0_I0
23
P r e l i m i n a r y
9 Product Overview
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9.1
Memory Map
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Table 9.1 S29WS256N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
Sector/
Sector Range
(KB)
Bank
Address Range
Notes
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'ꢏꢏꢏꢏꢏK±'ꢏ))))KꢀWRꢀ')ꢏꢏꢏꢏK±')))))K
(ꢏꢏꢏꢏꢏK±(ꢏ))))KꢀWRꢀ()ꢏꢏꢏꢏK±()))))K
)ꢏꢏꢏꢏꢏK±)ꢏ))))KꢀWRꢀ)(ꢏꢏꢏꢏK±)())))K
))ꢏꢏꢏꢏK±))ꢐ)))K
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢊꢀ0%
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍ
ꢈ
ꢊ
ꢐ
ꢓ
ꢉ
ꢌ
$OOꢀꢈꢊꢍꢀ.%ꢀVHFWRUVꢃꢀ
3DWWHUQꢀIRUꢀVHFWRUꢀDGGUHVVꢀUDQJHꢀ
LVꢀ[[ꢏꢏꢏꢏK±[[))))Kꢃ
ꢁVHHꢀQRWHꢂ
ꢇ
ꢍ
ꢋ
ꢈꢏ
ꢈꢈ
ꢈꢊ
ꢈꢐ
ꢈꢓ
ꢊꢀ0%
ꢈꢉ
6$ꢊꢉꢋ
))ꢓꢏꢏꢏK±))ꢇ)))K
&RQWDLQVꢀIRXUꢀVPDOOHUꢀVHFWRUVꢀDWꢀ
WRSꢀRIꢀDGGUHVVDEOHꢀPHPRU\ꢃ
ꢓ
ꢐꢊ
6$ꢊꢌꢏ
))ꢍꢏꢏꢏK±))%)))K
6$ꢊꢌꢈ
))&ꢏꢏꢏK±))))))Kꢀ
1RWHꢀ 7KLVꢀWDEOHꢀKDVꢀEHHQꢀFRQGHQVHGꢀWRꢀVKRZꢀVHFWRUꢇUHODWHGꢀLQIRUPDWLRQꢀIRUꢀDQꢀHQWLUHꢀGHYLFHꢀRQꢀDꢀVLQJOHꢀSDJHꢆꢀ6HFWRUVꢀDQGꢀWKHLUꢀDGGUHVVꢀUDQJHVꢀ
WKDWꢀDUHꢀQRWꢀH[SOLFLWO\ꢀOLVWHGꢀꢂVXFKꢀDVꢀ6$ꢁꢁꢌ±6$ꢁꢅꢋꢃꢀKDYHꢀVHFWRUꢀVWDUWLQJꢀDQGꢀHQGLQJꢀDGGUHVVHVꢀWKDWꢀIRUPꢀWKHꢀVDPHꢀSDWWHUQꢀDVꢀDOOꢀRWKHUꢀVHFWRUVꢀ
RIꢀWKDWꢀVL]Hꢆꢀ)RUꢀH[DPSOHꢄꢀDOOꢀꢅꢈꢎꢀ.%ꢀVHFWRUVꢀKDYHꢀWKHꢀSDWWHUQꢀ[[ꢁꢁꢁꢁꢁK±[[))))Kꢆ
24
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 9.2. S29WS128N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
Notes
ꢐꢊ
6$ꢏꢏꢏ
ꢏꢏꢏꢏꢏꢏK±ꢏꢏꢐ)))K
ꢐꢊ
6$ꢏꢏꢈ
ꢏꢏꢓꢏꢏꢏK±ꢏꢏꢇ)))K
&RQWDLQVꢀIRXUꢀVPDOOHUꢀVHFWRUVꢀDWꢀ
ERWWRPꢀRIꢀDGGUHVVDEOHꢀPHPRU\ꢃ
ꢓ
ꢈꢀ0%
ꢐꢊ
ꢀꢏ
6$ꢏꢏꢊ
ꢏꢏꢍꢏꢏꢏK±ꢏꢏ%)))K
ꢐꢊ
6$ꢏꢏꢐ
ꢏꢏ&ꢏꢏꢏK±ꢏꢏ))))K
ꢇ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢍ
ꢇ
ꢈꢊꢍ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍꢀ
ꢈꢊꢍ
ꢐꢊ
6$ꢏꢏꢓꢀWRꢀ6$ꢏꢈꢏ
6$ꢏꢈꢈꢀWRꢀ6$ꢏꢈꢍ
6$ꢏꢈꢋꢀWRꢀ6$ꢏꢊꢌ
6$ꢏꢊꢇꢀWRꢀ6$ꢏꢐꢓ
6$ꢏꢐꢉꢀWRꢀ6$ꢏꢓꢊ
6$ꢏꢓꢐꢀWRꢀ6$ꢏꢉꢏ
6$ꢏꢉꢈꢀWRꢀ6$ꢏꢉꢍ
6$ꢏꢉꢋꢀWRꢀ6$ꢏꢌꢌ
6$ꢏꢌꢇꢀWRꢀ6$ꢏꢇꢓ
6$ꢏꢇꢉꢀWRꢀ6$ꢏꢍꢊ
6$ꢏꢍꢐꢀWRꢀ6$ꢏꢋꢏ
6$ꢏꢋꢈꢀWRꢀ6$ꢏꢋꢍ
6$ꢏꢋꢋꢀWRꢀ6$ꢈꢏꢌ
6$ꢈꢏꢇꢀWRꢀ6$ꢈꢈꢓ
6$ꢈꢈꢉꢀWRꢀ6$ꢈꢊꢊ
6$ꢈꢊꢐꢀWRꢀ6$ꢈꢊꢋ
6$ꢈꢐꢏꢀ
ꢏꢈꢏꢏꢏꢏK±ꢏꢈ))))KꢀWRꢀꢏꢇꢏꢏꢏꢏK±ꢏꢇ))))K
ꢏꢍꢏꢏꢏꢏK±ꢏꢍ))))KꢀWRꢀꢏ)ꢏꢏꢏꢏK±ꢏ)))))K
ꢈꢏꢏꢏꢏꢏK±ꢈꢏ))))KꢀWRꢀꢈꢇꢏꢏꢏꢏK±ꢈꢇ))))K
ꢈꢍꢏꢏꢏꢏK±ꢈꢍ))))KꢀWRꢀꢈ)ꢏꢏꢏꢏK±ꢈ)))))K
ꢊꢏꢏꢏꢏꢏK±ꢊꢏ))))KꢀWRꢀꢊꢇꢏꢏꢏꢏK±ꢊꢇ))))K
ꢊꢍꢏꢏꢏꢏK±ꢊꢍ))))KꢀWRꢀꢊ)ꢏꢏꢏꢏK±ꢊ)))))K
ꢐꢏꢏꢏꢏꢏK±ꢐꢏ))))KꢀWRꢀꢐꢇꢏꢏꢏꢏK±ꢐꢇ))))K
ꢐꢍꢏꢏꢏꢏK±ꢐꢍ))))KꢀWRꢀꢐ)ꢏꢏꢏꢏK±ꢐ)))))K
ꢓꢏꢏꢏꢏꢏK±ꢓꢏ))))KꢀWRꢀꢓꢇꢏꢏꢏꢏK±ꢓꢇ))))K
ꢓꢍꢏꢏꢏꢏK±ꢓꢍ))))KꢀWRꢀꢓ)ꢏꢏꢏꢏK±ꢓ)))))K
ꢉꢏꢏꢏꢏꢏK±ꢉꢏ))))KꢀWRꢀꢉꢇꢏꢏꢏꢏK±ꢉꢇ))))K
ꢉꢍꢏꢏꢏꢏK±ꢉꢍ))))KꢀWRꢀꢉ)ꢏꢏꢏꢏK±ꢉ)))))K
ꢌꢏꢏꢏꢏꢏK±ꢌꢏ))))KꢀWRꢀꢌꢇꢏꢏꢏꢏK±ꢌꢇ))))K
ꢌꢍꢏꢏꢏꢏK±ꢌꢍ))))KꢀWRꢀꢌ)ꢏꢏꢏꢏK±ꢌ)))))K
ꢇꢏꢏꢏꢏꢏK±ꢇꢏ))))KꢀWRꢀꢇꢇꢏꢏꢏꢏK±ꢇꢇ))))K
ꢇꢍꢏꢏꢏꢏK±ꢇꢍ))))KꢀWRꢀꢇ(ꢏꢏꢏꢏK±ꢇ())))K
ꢇ)ꢏꢏꢏꢏK±ꢇ)ꢐ)))K
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ꢈꢀ0%
ꢈ
ꢊ
ꢐ
ꢓ
ꢉ
ꢌ
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LVꢀ[[ꢏꢏꢏꢏK±[[))))Kꢃ
ꢁVHHꢀQRWHꢂ
ꢇ
ꢍ
ꢋ
ꢈꢏ
ꢈꢈ
ꢈꢊ
ꢈꢐ
ꢈꢓ
ꢈꢀ0%
ꢐꢊ
ꢈꢉ
6$ꢈꢐꢈ
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6$ꢈꢐꢊ
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ꢐꢊ
6$ꢈꢐꢐ
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WKDWꢀDUHꢀQRWꢀH[SOLFLWO\ꢀOLVWHGꢀꢂVXFKꢀDVꢀ6$ꢁꢁꢌ±6$ꢁꢁꢏꢃꢀKDYHꢀVHFWRUꢀVWDUWLQJꢀDQGꢀHQGLQJꢀDGGUHVVHVꢀWKDWꢀIRUPꢀWKHꢀVDPHꢀSDWWHUQꢀDVꢀDOOꢀRWKHUꢀVHFWRUVꢀ
RIꢀWKDWꢀVL]Hꢆꢀ)RUꢀH[DPSOHꢄꢀDOOꢀꢅꢈꢎꢀ.%ꢀVHFWRUVꢀKDYHꢀWKHꢀSDWWHUQꢀ[[ꢁꢁꢁꢁꢁK±[[))))Kꢆ
December 3, 2005 S29WS-N_m0_I0
25
P r e l i m i n a r y
10 Device Operations
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GDWDꢀSDWWHUQVꢀLQWRꢀWKHꢀFRPPDQGꢀUHJLVWHUVꢀꢁVHHꢀ7DEOHVꢀꢈꢉꢃꢈꢀDQGꢀꢈꢉꢃꢊꢂꢃꢀ7KHꢀFRPPDQGꢀUHJLVWHU
LWVHOIꢀGRHVꢀQRWꢀRFFXS\ꢀDQ\ꢀDGGUHVVDEOHꢀPHPRU\ꢀORFDWLRQꢕꢀUDWKHUꢄꢀLWꢀLVꢀFRPSRVHGꢀRIꢀODWFKHVꢀWKDW
VWRUHꢀWKHꢀFRPPDQGVꢄꢀDORQJꢀZLWKꢀWKHꢀDGGUHVVꢀDQGꢀGDWDꢀLQIRUPDWLRQꢀQHHGHGꢀWRꢀH[HFXWHꢀWKHꢀFRPꢅ
PDQGꢃꢀ7KHꢀFRQWHQWVꢀRIꢀWKHꢀUHJLVWHUꢀVHUYHꢀDVꢀLQSXWꢀWRꢀWKHꢀLQWHUQDOꢀVWDWHꢀPDFKLQHꢀDQGꢀWKHꢀVWDWH
PDFKLQHꢀRXWSXWVꢀGLFWDWHꢀWKHꢀIXQFWLRQꢀRIꢀWKHꢀGHYLFHꢃꢀ:ULWLQJꢀLQFRUUHFWꢀDGGUHVVꢀDQGꢀGDWDꢀYDOXHVꢀRU
ZULWLQJꢀWKHPꢀLQꢀDQꢀLPSURSHUꢀVHTXHQFHꢀPD\ꢀSODFHꢀWKHꢀGHYLFHꢀLQꢀDQꢀXQNQRZQꢀVWDWHꢄꢀLQꢀZKLFKꢀFDVH
WKHꢀV\VWHPꢀPXVWꢀZULWHꢀWKHꢀUHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀWKHꢀGHYLFHꢀWRꢀWKHꢀUHDGLQJꢀDUUD\ꢀGDWDꢀPRGHꢃ
10.1 Device Operation Table
7KHꢀGHYLFHꢀPXVWꢀEHꢀVHWXSꢀDSSURSULDWHO\ꢀIRUꢀHDFKꢀRSHUDWLRQꢃꢀ7DEOHꢀ ꢈꢏꢃꢈꢀGHVFULEHVꢀWKHꢀUHTXLUHG
VWDWHꢀRIꢀHDFKꢀFRQWUROꢀSLQꢀIRUꢀDQ\ꢀSDUWLFXODUꢀRSHUDWLRQꢃ
Table 10.1 Device Operations
Operation
CE#
/
OE#
/
WE#
Addresses
$GGUꢀ,Q
$GGUꢀ,Q
$GGUꢀ,Q
$GGUꢀ,Qꢀ
;
DQ15–0
'DWDꢀ2XW
'DWDꢀ2XW
,ꢑ2
RESET#
CLK
;
AVD#
$V\QFKURQRXVꢀ5HDGꢀꢅꢀ$GGUHVVHVꢀ/DWFKHG
$V\QFKURQRXVꢀ5HDGꢀꢅꢀ$GGUHVVHVꢀ6WHDG\ꢀ6WDWH
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+
+
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+
+
+
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+
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;
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+
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/
+
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,ꢑ2
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+
;
;
;
;
+,*+ꢀ=
+,*+ꢀ=
;
;
;
;
+DUGZDUHꢀ5HVHW
;
;
Burst Read Operations (Synchronous)
/RDGꢀ6WDUWLQJꢀ%XUVWꢀ$GGUHVV
/
/
;
/
+
+
$GGUꢀ,Q
;
;
+
+
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+
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+
;
;
;
+
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;
+,*+ꢀ=
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+
/
;
;
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;
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/
;
+
$GGUꢀ,Q
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+
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10.2 Asynchronous Read
$OOꢀPHPRULHVꢀUHTXLUHꢀDFFHVVꢀWLPHꢀWRꢀRXWSXWꢀDUUD\ꢀGDWDꢃꢀ,QꢀDQꢀDV\QFKURQRXVꢀUHDGꢀRSHUDWLRQꢄꢀGDWD
LVꢀUHDGꢀIURPꢀRQHꢀPHPRU\ꢀORFDWLRQꢀDWꢀDꢀWLPHꢃꢀ$GGUHVVHVꢀDUHꢀSUHVHQWHGꢀWRꢀWKHꢀGHYLFHꢀLQꢀUDQGRP
RUGHUꢄꢀDQGꢀWKHꢀSURSDJDWLRQꢀGHOD\ꢀWKURXJKꢀWKHꢀGHYLFHꢀFDXVHVꢀWKHꢀGDWDꢀRQꢀLWVꢀRXWSXWVꢀWRꢀDUULYH
DV\QFKURQRXVO\ꢀZLWKꢀWKHꢀDGGUHVVꢀRQꢀLWVꢀLQSXWVꢃꢀ
7KHꢀGHYLFHꢀGHIDXOWVꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢀDV\QFKURQRXVO\ꢀDIWHUꢀGHYLFHꢀSRZHUꢅXSꢀRUꢀKDUGZDUHꢀUHꢅ
VHWꢃꢀ7RꢀUHDGꢀGDWDꢀIURPꢀWKHꢀPHPRU\ꢀDUUD\ꢄꢀWKHꢀV\VWHPꢀPXVWꢀILUVWꢀDVVHUWꢀDꢀYDOLGꢀDGGUHVVꢀRQꢀ$PD[
$ꢏꢄꢀZKLOHꢀGULYLQJꢀ$9'ꢔꢀDQGꢀ&(ꢔꢀWRꢀ9,/ꢃꢀ:(ꢔꢀPXVWꢀUHPDLQꢀDWꢀ9,+ꢃꢀ7KHꢀULVLQJꢀHGJHꢀRIꢀ$9'ꢔ
ODWFKHVꢀWKHꢀDGGUHVVꢃꢀ7KHꢀ2(ꢔꢀVLJQDOꢀPXVWꢀEHꢀGULYHQꢀWRꢀ9,/ꢄꢀRQFHꢀ$9'ꢔꢀKDVꢀEHHQꢀGULYHQꢀWRꢀ9,+
±
ꢃ
'DWDꢀLVꢀRXWSXWꢀRQꢀ$ꢑ'4ꢈꢉꢅ$ꢑ'4ꢏꢀSLQVꢀDIWHUꢀWKHꢀDFFHVVꢀWLPHꢀꢁW2(ꢂꢀKDVꢀHODSVHGꢀIURPꢀWKHꢀIDOOLQJ
HGJHꢀRIꢀ2(ꢔꢃ
26
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
10.3 Page Read Mode
7KHꢀGHYLFHꢀLVꢀFDSDEOHꢀRIꢀIDVWꢀSDJHꢀPRGHꢀUHDGꢀDQGꢀLVꢀFRPSDWLEOHꢀZLWKꢀWKHꢀSDJHꢀPRGHꢀ0DVNꢀ520
UHDGꢀRSHUDWLRQꢃꢀ7KLVꢀPRGHꢀSURYLGHVꢀIDVWHUꢀUHDGꢀDFFHVVꢀVSHHGꢀIRUꢀUDQGRPꢀORFDWLRQVꢀZLWKLQꢀDꢀSDJHꢃ
7KHꢀUDQGRPꢀRUꢀLQLWLDOꢀSDJHꢀDFFHVVꢀLVꢀW$&&ꢀRUꢀW&(ꢀDQGꢀVXEVHTXHQWꢀSDJHꢀUHDGꢀDFFHVVHVꢀꢁDVꢀORQJꢀDV
WKHꢀORFDWLRQVꢀVSHFLILHGꢀE\ꢀWKHꢀPLFURSURFHVVRUꢀIDOOVꢀZLWKLQꢀWKDWꢀSDJHꢂꢀLVꢀHTXLYDOHQWꢀWRꢀW3$&&ꢃꢀ:KHQ
&(ꢔꢀLVꢀGHDVVHUWHGꢀꢁ 9,+ꢂꢄꢀWKHꢀUHDVVHUWLRQꢀRIꢀ&(ꢔꢀIRUꢀVXEVHTXHQWꢀDFFHVVꢀKDVꢀDFFHVVꢀWLPHꢀRIꢀW$&&
RUꢀW&(ꢃꢀ+HUHꢀDJDLQꢄꢀ&(ꢔꢀVHOHFWVꢀWKHꢀGHYLFHꢀDQGꢀ2(ꢔꢀLVꢀWKHꢀRXWSXWꢀFRQWUROꢀDQGꢀVKRXOGꢀEHꢀXVHGꢀWR
JDWHꢀGDWDꢀWRꢀWKHꢀRXWSXWꢀLQSXWVꢀLIꢀWKHꢀGHYLFHꢀLVꢀVHOHFWHGꢃꢀ)DVWꢀSDJHꢀPRGHꢀDFFHVVHVꢀDUHꢀREWDLQHG
E\ꢀNHHSLQJꢀ$PD[ ± $ꢊꢀFRQVWDQWꢀDQGꢀFKDQJLQJꢀ$ꢈ ± $ꢏꢀWRꢀVHOHFWꢀWKHꢀVSHFLILFꢀZRUGꢀZLWKLQꢀWKDW
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HUDVHꢅVXVSHQGHGꢀVHFWRUꢀZLWKLQꢀWKHꢀVDPHꢀEDQNꢃꢀ7KHꢀV\VWHPꢀFDQꢀUHDGꢀDUUD\ꢀGDWDꢀXVLQJꢀWKHꢀVWDQꢅ
GDUGꢀUHDGꢀWLPLQJꢄꢀH[FHSWꢀWKDWꢀLIꢀLWꢀUHDGVꢀDWꢀDQꢀDGGUHVVꢀZLWKLQꢀHUDVHꢅVXVSHQGHGꢀVHFWRUVꢄꢀWKHꢀGHYLFH
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ZKLFKꢀWKHꢀV\VWHPꢀFDQꢀUHDGꢀGDWDꢀIURPꢀDQ\ꢀQRQꢅSURJUDPꢅVXVSHQGHGꢀVHFWRUꢀZLWKLQꢀWKHꢀVDPHꢀEDQNꢃ
7KHꢀGHꢅDVVHUWLRQꢀDQGꢀUHꢅDVVHUWLRQꢀRIꢀ$9'ꢔꢀFUHDWHVꢀDꢀQHZꢀW$&&ꢃꢀꢀ7KHꢀXVHUꢀPXVWꢀNHHSꢀ$9'ꢔꢀORZ
GXULQJꢀDQGꢀEHWZHHQꢀSDJHꢀUHDGVꢀRQꢀDGGUHVVꢀ$ꢁꢈꢆꢏꢂꢃ
'XULQJꢀ6LPXOWDQHRXVꢀ2SHUDWLRQꢀꢁ62ꢂꢄꢀWKHꢀXVHUꢀQHHGVꢀWRꢀGHꢅDVVHUWꢀDQGꢀUHꢅꢀDVVHUWꢀHLWKHUꢀꢑ&(ꢔꢀRU
ꢑ$9'ꢔꢀZKHQꢀSHUIRUPLQJꢀGDWDꢀSROOLQJꢀWRꢀ62ꢀUHDGꢃꢀ
Table 10.2 Word Selection within a Page
:RUG
$ꢄ
ꢏ
$ꢍ
ꢏ
ꢀ:RUGꢀꢏ
ꢀ:RUGꢀꢈ
ꢀ:RUGꢀꢊ
ꢀ:RUGꢀꢐ
ꢏ
ꢈ
ꢈ
ꢏ
ꢈ
ꢈ
10.4 Synchronous (Burst) Read Mode & Configuration Register
:KHQꢀDꢀVHULHVꢀRIꢀDGMDFHQWꢀDGGUHVVHVꢀQHHGVꢀWRꢀEHꢀUHDGꢀIURPꢀWKHꢀGHYLFHꢀꢁLQꢀRUGHUꢀIURPꢀORZHVWꢀWR
KLJKHVWꢀDGGUHVVꢂꢄꢀWKHꢀV\QFKURQRXVꢀꢁRUꢀEXUVWꢀUHDGꢂꢀPRGHꢀFDQꢀEHꢀXVHGꢀWRꢀVLJQLILFDQWO\ꢀUHGXFHꢀWKH
RYHUDOOꢀWLPHꢀQHHGHGꢀIRUꢀWKHꢀGHYLFHꢀWRꢀRXWSXWꢀDUUD\ꢀGDWDꢃꢀ$IWHUꢀDQꢀLQLWLDOꢀDFFHVVꢀWLPHꢀUHTXLUHGꢀIRU
WKHꢀGDWDꢀIURPꢀWKHꢀILUVWꢀDGGUHVVꢀORFDWLRQꢄꢀVXEVHTXHQWꢀGDWDꢀLVꢀRXWSXWꢀV\QFKURQL]HGꢀWRꢀDꢀFORFNꢀLQSXW
SURYLGHGꢀE\ꢀWKHꢀV\VWHPꢃꢀ
7KHꢀGHYLFHꢀRIIHUVꢀERWKꢀFRQWLQXRXVꢀDQGꢀOLQHDUꢀPHWKRGVꢀRIꢀEXUVWꢀUHDGꢀRSHUDWLRQꢄꢀZKLFKꢀDUHꢀGLVꢅ
FXVVHGꢀLQꢀVXEVHFWLRQVꢀꢈꢏꢃꢓꢃꢉꢀDQGꢀꢈꢏꢃꢓꢃꢌꢄꢀDQGꢀꢈꢏꢃꢓꢃꢇꢃ
6LQFHꢀWKHꢀGHYLFHꢀGHIDXOWVꢀWRꢀDV\QFKURQRXVꢀUHDGꢀPRGHꢀDIWHUꢀSRZHUꢅXSꢀRUꢀDꢀKDUGZDUHꢀUHVHWꢄꢀWKH
FRQILJXUDWLRQꢀUHJLVWHUꢀPXVWꢀEHꢀVHWꢀWRꢀHQDEOHꢀWKHꢀEXUVWꢀUHDGꢀPRGHꢃꢀ2WKHUꢀ&RQILJXUDWLRQꢀ5HJLVWHU
VHWWLQJVꢀLQFOXGHꢀWKHꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀWRꢀLQVHUWꢀEHIRUHꢀWKHꢀLQLWLDOꢀZRUGꢀꢁW,$&&ꢂꢀRIꢀHDFKꢀEXUVW
December 3, 2005 S29WS-N_m0_I0
27
P r e l i m i n a r y
DFFHVVꢄꢀWKHꢀEXUVWꢀPRGHꢀLQꢀZKLFKꢀWRꢀRSHUDWHꢄꢀDQGꢀZKHQꢀ5'<ꢀLQGLFDWHVꢀGDWDꢀLVꢀUHDG\ꢀWRꢀEHꢀUHDGꢃ
3ULRUꢀWRꢀHQWHULQJꢀWKHꢀEXUVWꢀPRGHꢄꢀWKHꢀV\VWHPꢀVKRXOGꢀILUVWꢀGHWHUPLQHꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHU
VHWWLQJVꢀꢁDQGꢀUHDGꢀWKHꢀFXUUHQWꢀUHJLVWHUꢀVHWWLQJVꢀLIꢀGHVLUHGꢀYLDꢀWKHꢀ5HDGꢀ&RQILJXUDWLRQꢀ5HJLVWHU
FRPPDQGꢀVHTXHQFHꢂꢄꢀDQGꢀWKHQꢀZULWHꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀFRPPDQGꢀVHTXHQFHꢃꢀ6HHꢀ6HFWLRQ
ꢈꢏꢃꢓꢃꢍꢄꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢄꢀDQGꢀ7DEOHꢀꢈꢉꢃꢈꢄꢀ 0HPRU\ꢀ$UUD\ꢀ&RPPDQGVꢀIRUꢀIXUWKHUꢀGHWDLOVꢃ
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 10.1. Synchronous/Asynchronous State Diagram
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W,$&&ꢀVSHFLILFDWLRQꢆꢀWKHꢀWLPHꢀIURPꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILUVWꢀFORFNꢀF\FOHꢀDIWHUꢀDGGUHVVHVꢀDUH
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28
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 10.3 Address Latency (S29WS256N)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢏ
ꢈ
ꢊ
ꢐ
[ꢀZV
'ꢏ
'ꢈ
'ꢊ
'ꢐ
'ꢈ
'ꢊ
'ꢊ
'ꢐ
'ꢐ
'ꢓ
'ꢓ
'ꢓ
'ꢓ
'ꢉ
'ꢉ
'ꢉ
'ꢉ
'ꢌ
'ꢌ
'ꢌ
'ꢌ
'ꢇ
'ꢇ
'ꢇ
'ꢇ
'ꢍ
'ꢍ
'ꢍ
'ꢍ
[ꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
[ꢀZV
'ꢐ
ꢈꢀZV
ꢈꢀZV
[ꢀZV
ꢈꢀZV
Table 10.4 Address Latency (S29WS128N)
:RUG
:DLWꢀ6WDWHV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
&\FOH
ꢏ
ꢈ
ꢊ
ꢐ
'ꢏ
'ꢈ
'ꢊ
'ꢐ
'ꢈ
'ꢊ
'ꢊ
'ꢐ
'ꢐ
'ꢓ
'ꢓ
'ꢓ
'ꢓ
'ꢉ
'ꢉ
'ꢉ
'ꢉ
'ꢌ
'ꢌ
'ꢌ
'ꢌ
'ꢇ
'ꢇ
'ꢇ
'ꢇ
'ꢍ
'ꢍ
'ꢍ
'ꢍ
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
'ꢐ
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
Table 10.5 Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢏ
ꢈ
ꢊ
ꢐ
ꢇꢀZV
'ꢏ
'ꢈ
'ꢊ
'ꢐ
'ꢈ
'ꢊ
'ꢊ
'ꢐ
'ꢐ
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
'ꢓ
'ꢓ
'ꢓ
'ꢓ
'ꢉ
'ꢉ
'ꢉ
'ꢉ
'ꢌ
'ꢌ
'ꢌ
'ꢌ
ꢇꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢇꢀZV
'ꢐ
ꢈꢀZV
ꢈꢀZV
ꢇꢀZV
ꢈꢀZV
Table 10.6 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢏ
ꢈ
ꢊ
ꢐ
ꢀꢌꢀZV
'ꢏ
'ꢈ
'ꢊ
'ꢐ
'ꢈ
'ꢊ
'ꢊ
'ꢐ
'ꢐ
'ꢓ
'ꢓ
'ꢓ
'ꢓ
'ꢉ
'ꢉ
'ꢉ
'ꢉ
'ꢌ
'ꢌ
'ꢌ
'ꢌ
'ꢇ
'ꢇ
'ꢇ
'ꢇ
ꢌꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢌꢀZV
'ꢐ
ꢈꢀZV
ꢈꢀZV
ꢌꢀZV
ꢈꢀZV
Table 10.7 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢏ
ꢈ
ꢊ
ꢐ
ꢉꢀZV
'ꢏ
'ꢈ
'ꢊ
'ꢐ
'ꢈ
'ꢊ
'ꢊ
'ꢐ
'ꢐ
'ꢓ
'ꢉ
'ꢉ
'ꢉ
'ꢉ
'ꢌ
'ꢌ
'ꢌ
'ꢌ
'ꢇ
'ꢇ
'ꢇ
'ꢇ
'ꢍ
'ꢍ
'ꢍ
'ꢍ
ꢉꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
'ꢓ
ꢉꢀZV
'ꢐ
ꢈꢀZV
ꢈꢀZV
'ꢓ
ꢉꢀZV
ꢈꢀZV
'ꢓ
Table 10.8 Address/Boundary Crossing Latency (S29WS128N)
:RUG
:DLWꢀ6WDWHV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
ꢉꢄꢀꢌꢄꢀꢇꢀZV
&\FOH
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢈꢀZV
ꢏ
ꢈ
ꢊ
ꢐ
'ꢏ
'ꢈ
'ꢊ
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December 3, 2005 S29WS-N_m0_I0
29
P r e l i m i n a r y
Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
Read Initial Data
RD = DQ[15:0]
RD = Read Data
Wait X Clocks:
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Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
Read Next Data
RD = DQ[15:0]
No
Delay X Clocks
Crossing
Boundary?
No
End of Data?
Yes
Yes
Completed
Figure 10.2. Synchronous Read
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30
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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Group Size
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December 3, 2005 S29WS-N_m0_I0
31
P r e l i m i n a r y
Table 10.10 Configuration Register
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32
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
10.5 Autoselect
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7RꢀDFFHVVꢀWKHꢀ$XWRVHOHFWꢀFRGHVꢄꢀWKHꢀKRVWꢀV\VWHPꢀPXVWꢀLVVXHꢀWKHꢀ$XWRVHOHFWꢀFRPPDQGꢃ
7KHꢀ$XWRVHOHFWꢀFRPPDQGꢀVHTXHQFHꢀPD\ꢀEHꢀZULWWHQꢀWRꢀDQꢀDGGUHVVꢀZLWKLQꢀDꢀEDQNꢀWKDWꢀLVꢀHLWKHU
LQꢀWKHꢀUHDGꢀRUꢀHUDVHꢅVXVSHQGꢅUHDGꢀPRGHꢃꢀ
7KHꢀ$XWRVHOHFWꢀFRPPDQGꢀPD\ꢀQRWꢀEHꢀZULWWHQꢀZKLOHꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀSURJUDPPLQJꢀRU
HUDVLQJꢃꢀ$XWRVHOHFWꢀGRHVꢀQRWꢀVXSSRUWꢀVLPXOWDQHRXVꢀRSHUDWLRQVꢀRUꢀEXUVWꢀPRGHꢃꢀ
7KHꢀV\VWHPꢀPXVWꢀZULWHꢀWKHꢀUHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀWRꢀWKHꢀUHDGꢀPRGHꢀꢁRUꢀHUDVHꢅVXVSHQGꢅ
UHDGꢀPRGHꢀLIꢀWKHꢀEDQNꢀZDVꢀSUHYLRXVO\ꢀLQꢀ(UDVHꢀ6XVSHQGꢂꢃꢀ
6HHꢀ7DEOHꢀꢈꢉꢃꢈꢀIRUꢀFRPPDQGꢀVHTXHQFHꢀGHWDLOVꢃ
Table 10.11 Autoselect Addresses
Description
0DQXIDFWXUHUꢀ,'
'HYLFHꢀ,'ꢄꢀ:RUGꢀꢈ
Address
Read Data
ꢁ%$ꢂꢀꢎꢀꢏꢏK ꢏꢏꢏꢈK
ꢁ%$ꢂꢀꢎꢀꢏꢈK ꢊꢊꢇ(K
ꢊꢊꢐꢏꢀꢁ:6ꢊꢉꢌ1ꢂ
ꢊꢊꢐꢈꢀꢁ:6ꢈꢊꢍ1ꢂ
ꢁ%$ꢂꢀꢎꢀꢏ)K ꢊꢊꢏꢏ
'4ꢈꢉꢀꢅꢀ'4ꢍꢀ ꢀ5HVHUYHG
'HYLFHꢀ,'ꢄꢀ:RUGꢀꢊ
'HYLFHꢀ,'ꢄꢀ:RUGꢀꢐ
ꢁ%$ꢂꢀꢎꢀꢏ(K
'4ꢇꢀꢁ)DFWRU\ꢀ/RFNꢀ%LWꢂꢆꢀꢈꢀ ꢀ/RFNHGꢄꢀꢏꢀ ꢀ1RWꢀ/RFNHG
'4ꢌꢀꢁ&XVWRPHUꢀ/RFNꢀ%LWꢂꢆꢀꢈꢀ ꢀ/RFNHGꢄꢀꢏꢀ ꢀ1RWꢀ/RFNHG
'4ꢉꢀꢁ+DQGVKDNHꢀ%LWꢂꢆꢀꢈꢀ ꢀ5HVHUYHGꢄꢀꢏꢀ ꢀ6WDQGDUGꢀ+DQGVKDNH
'4ꢓꢄꢀ'4ꢐꢀꢁ:3ꢔꢀ3URWHFWLRQꢀ%RRWꢀ&RGHꢂꢆꢀꢏꢏꢀ ꢀ:3ꢔꢀ3URWHFWVꢀERWKꢀ7RSꢀ%RRWꢀDQGꢀ
%RWWRPꢀ%RRWꢀ6HFWRUVꢃꢀꢏꢈꢄꢀꢈꢏꢄꢀꢈꢈꢀ ꢀ5HVHUYHG
,QGLFDWRUꢀ%LWVꢀ
ꢁ6HHꢀ1RWHꢂ
ꢁ%$ꢂꢀꢎꢀꢏꢐK
'4ꢊꢀ ꢀ5HVHUYHG
'4ꢈꢀꢁ'<%ꢀ3RZHUꢀXSꢀ6WDWHꢀ>/RFNꢀ5HJLVWHUꢀ'4ꢓ@ꢂꢆꢀꢈꢀ ꢀ8QORFNHGꢀꢁXVHUꢀRSWLRQꢂꢄꢀ
ꢏꢀ ꢀ/RFNHGꢀꢁGHIDXOWꢂ
'4ꢏꢀꢁ33%ꢀ(UDVHDELOLW\ꢀ>/RFNꢀ5HJLVWHUꢀ'4ꢐ@ꢂꢆꢀꢈꢀ ꢀ(UDVHꢀDOORZHGꢄꢀ
ꢏꢀ ꢀ(UDVHꢀGLVDEOHG
6HFWRUꢀ%ORFNꢀ/RFNꢑ
8QORFNꢀ
ꢁ6$ꢂꢀꢎꢀꢏꢊK ꢏꢏꢏꢈKꢀ ꢀ/RFNHGꢄꢀꢏꢏꢏꢏKꢀ ꢀ8QORFNHG
1RWHꢀꢀ)RUꢀ:6ꢅꢈꢎ1ꢀDQGꢀ:6ꢁꢐꢍꢄꢀ'4ꢅꢀDQGꢀ'4ꢁꢀDUHꢀUHVHUYHGꢆ
December 3, 2005 S29WS-N_m0_I0
33
P r e l i m i n a r y
Software Functions and Sample Code
Table 10.12 Autoselect Entry
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB$XWRVHOHFW(QWU\&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%$[$$$K
%$[ꢉꢉꢉK
Word Address
%$[ꢉꢉꢉK
Data
8QORFNꢀ&\FOHꢀꢈ
8QORFNꢀ&\FOHꢀꢊ
$XWRVHOHFWꢀ&RPPDQG
ꢏ[ꢏꢏ$$K
ꢏ[ꢏꢏꢉꢉK
ꢏ[ꢏꢏꢋꢏK
:ULWH
%$[ꢊ$$K
:ULWH
%$[$$$K
%$[ꢉꢉꢉK
Table 10.13 Autoselect Exit
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB$XWRVHOHFW([LW&PGꢂ
Cycle
Operation
:ULWH
Byte Address
Word Address
EDVHꢀꢎꢀ;;;K
Data
8QORFNꢀ&\FOHꢀꢈ
EDVHꢀꢎꢀ;;;K
ꢏ[ꢏꢏ)ꢏK
1RWHVꢀ
ꢅꢆ $Q\ꢀRIIVHWꢀZLWKLQꢀWKHꢀGHYLFHꢀZRUNVꢆ
ꢈꢆ %$ꢀ ꢀ%DQNꢀ$GGUHVVꢆꢀ7KHꢀEDQNꢀDGGUHVVꢀLVꢀUHTXLUHGꢆ
ꢊꢆ EDVHꢀ ꢀEDVHꢀDGGUHVVꢆ
7KHꢀIROORZLQJꢀLVꢀDꢀ&ꢀVRXUFHꢀFRGHꢀH[DPSOHꢀRIꢀXVLQJꢀWKHꢀDXWRVHOHFWꢀIXQFWLRQꢀWRꢀUHDGꢀWKHꢀPDQXIDFꢅ
WXUHUꢀ,'ꢃꢀ5HIHUꢀWRꢀWKHꢀ6SDQVLRQꢀ/RZꢀ/HYHOꢀ'ULYHUꢀ8VHU¶Vꢀ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQG
ZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDOꢀLQIRUPDWLRQꢀRQꢀ6SDQVLRQꢀ)ODVKꢀPHPRU\ꢀVRIWZDUHꢀGHYHORSPHQW
JXLGHOLQHVꢃ
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
34
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
10.6 Program/Erase Operations
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ꢈꢏꢃꢋꢂꢃ
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GULYHꢀ:(ꢔꢀDQGꢀ&(ꢔꢀWRꢀ9,/ꢄꢀDQGꢀ2(ꢔꢀWRꢀ9,+ꢀZKHQꢀZULWLQJꢀFRPPDQGVꢀRUꢀSURJUDPPLQJꢀGDWDꢃꢀ
$GGUHVVHVꢀDUHꢀODWFKHGꢀRQꢀWKHꢀODVWꢀIDOOLQJꢀHGJHꢀRIꢀ:(ꢔꢀRUꢀ&(ꢔꢄꢀZKLOHꢀGDWDꢀLVꢀODWFKHGꢀRQꢀWKHꢀꢈVW
ULVLQJꢀHGJHꢀRIꢀ:(ꢔꢀRUꢀ&(ꢔꢃ
1RWHꢀWKHꢀIROORZLQJꢆ
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FRPPDQGꢀZULWHꢀF\FOHVꢀDUHꢀXVHGꢀWRꢀSURJUDPꢀDQꢀLQGLYLGXDOꢀ)ODVKꢀDGGUHVVꢃꢀ7KHꢀGDWDꢀIRUꢀWKLVꢀSURꢅ
JUDPPLQJꢀRSHUDWLRQꢀFRXOGꢀEHꢀꢍꢅꢄꢀꢈꢌꢅꢀRUꢀꢐꢊꢅELWVꢀZLGHꢃꢀ:KLOHꢀWKLVꢀPHWKRGꢀLVꢀVXSSRUWHGꢀE\ꢀDOO
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JUDPPLQJꢃꢀ6HHꢀ7DEOHꢀꢈꢉꢃꢈꢀIRUꢀWKHꢀUHTXLUHGꢀEXVꢀF\FOHVꢀDQGꢀ)LJXUHꢀꢈꢏꢃꢐꢀIRUꢀWKHꢀIORZFKDUWꢃ
:KHQꢀWKHꢀ(PEHGGHGꢀ3URJUDPꢀDOJRULWKPꢀLVꢀFRPSOHWHꢄꢀWKHꢀGHYLFHꢀWKHQꢀUHWXUQVꢀWRꢀWKHꢀUHDGꢀPRGH
DQGꢀDGGUHVVHVꢀDUHꢀQRꢀORQJHUꢀODWFKHGꢃꢀ7KHꢀV\VWHPꢀFDQꢀGHWHUPLQHꢀWKHꢀVWDWXVꢀRIꢀWKHꢀSURJUDPꢀRSꢅ
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7KHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢄꢀ$XWRVHOHFWꢄꢀDQGꢀ&),ꢀIXQFWLRQVꢀDUHꢀXQDYDLODEOHꢀZKHQꢀDꢀSURJUDP
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December 3, 2005 S29WS-N_m0_I0
35
P r e l i m i n a r y
$ꢀKDUGZDUHꢀUHVHWꢀLPPHGLDWHO\ꢀWHUPLQDWHVꢀWKHꢀSURJUDPꢀRSHUDWLRQꢃꢀ7KHꢀSURJUDPꢀFRPPDQGꢀVHꢅ
TXHQFHꢀVKRXOGꢀEHꢀUHLQLWLDWHGꢀRQFHꢀWKHꢀGHYLFHꢀKDVꢀUHWXUQHGꢀWRꢀWKHꢀUHDGꢀPRGHꢄꢀWRꢀHQVXUHꢀGDWD
LQWHJULW\ꢃꢀ
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 10.3. Single Word Program
36
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Software Functions and Sample Code
Table 10.14. Single Word Program
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
:RUGꢀ$GGUHVV
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
:RUGꢀ$GGUHVV
Data
ꢏꢏ$$K
8QORFNꢀ&\FOHꢀꢈ
8QORFNꢀ&\FOHꢀꢊ
3URJUDPꢀ6HWXS
:ULWH
ꢏꢏꢉꢉK
:ULWH
ꢏꢏ$ꢏK
3URJUDP
:ULWH
'DWDꢀ:RUG
1RWHꢀꢀ%DVHꢀ ꢀ%DVHꢀ$GGUHVVꢆ
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6SDQVLRQꢀ/RZꢀ/HYHOꢀ'ULYHUꢀ8VHU¶Vꢀ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRU
JHQHUDOꢀLQIRUPDWLRQꢀRQꢀ6SDQVLRQꢀ)ODVKꢀPHPRU\ꢀVRIWZDUHꢀGHYHORSPHQWꢀJXLGHOLQHVꢃ
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
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S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Software Functions and Sample Code
Table 10.15. Write Buffer Program
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Cycle
Description
8QORFN
Operation
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Byte Address
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Word Address
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Data
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/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
UINT16 wc
= words_to_program -1;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
wc--;
goto loop;
/* done when word count equals zero */
/* decrement word count
/* do it again
*/
*/
confirm:
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
December 3, 2005 S29WS-N_m0_I0
39
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA = 0x29h
Wait 4 µs
(Recommended)
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write Buffer
Abort?
Yes
Polling Status
= Done?
No
No
Error?
Yes
FAIL. Issue reset command
to return to read array mode.
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
Figure 10.4. Write Buffer Programming Operation
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Software Functions and Sample Code
Table 10.16. Sector Erase
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB6HFWRU(UDVH&PGꢂ
Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
6HFWRUꢀ$GGUHVV
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
6HFWRUꢀ$GGUHVV
Data
ꢈ
ꢊ
ꢐ
ꢓ
ꢉ
ꢌ
ꢏꢏ$$K
ꢏꢏꢉꢉK
ꢏꢏꢍꢏK
ꢏꢏ$$K
ꢏꢏꢉꢉK
ꢏꢏꢐꢏK
8QORFN
:ULWH
6HWXSꢀ&RPPDQG
8QORFN
:ULWH
:ULWH
8QORFN
:ULWH
6HFWRUꢀ(UDVHꢀ&RPPDQG
:ULWH
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/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
December 3, 2005 S29WS-N_m0_I0
41
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
(Recommended)
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
ꢁVHHꢀ)LJXUHꢀꢈꢏꢃꢌꢂ
Yes
Done?
No
No
Error condition (Exceeded Timing Limits)
DQ5 = 1?
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
1RWHVꢀ
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Figure 10.5. Sector Erase Operation
42
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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Software Functions and Sample Code
Table 10.17. Chip Erase
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB&KLS(UDVH&PGꢂ
Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
Data
ꢈ
ꢊ
ꢐ
ꢓ
ꢉ
ꢌ
ꢏꢏ$$K
ꢏꢏꢉꢉK
ꢏꢏꢍꢏK
ꢏꢏ$$K
ꢏꢏꢉꢉK
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8QORFN
:ULWH
6HWXSꢀ&RPPDQG
8QORFN
:ULWH
:ULWH
8QORFN
:ULWH
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/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
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Software Functions and Sample Code
Table 10.18. Erase Suspend
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB(UDVH6XVSHQG&PGꢂ
Cycle
Operation
Byte Address
Word Address
Data
ꢈ
:ULWH
%DQNꢀ$GGUHVV
%DQNꢀ$GGUHVV
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/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 10.19. Erase Resume
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB(UDVH5HVXPH&PGꢂ
Cycle
Operation
Byte Address
Word Address
%DQNꢀ$GGUHVV
Data
ꢈ
:ULWH
%DQNꢀ$GGUHVV
ꢏꢏꢐꢏK
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/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
44
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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Software Functions and Sample Code
Table 10.20. Program Suspend
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP6XVSHQG&PGꢂ
Cycle
Operation
Byte Address
Word Address
Data
ꢈ
:ULWH
%DQNꢀ$GGUHVV
%DQNꢀ$GGUHVV
ꢏꢏ%ꢏK
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6SDQVLRQꢀ/RZꢀ/HYHOꢀ'ULYHUꢀ8VHU¶Vꢀ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRU
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/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 10.21. Program Resume
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP5HVXPH&PGꢂ
Cycle
Operation
Byte Address
Word Address
%DQNꢀ$GGUHVV
Data
ꢈ
:ULWH
%DQNꢀ$GGUHVV
ꢏꢏꢐꢏK
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/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
December 3, 2005 S29WS-N_m0_I0
45
P r e l i m i n a r y
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Table 10.22. Unlock Bypass Entry
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB8QORFN%\SDVV(QWU\&PGꢂ
Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
Data
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46
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
/* Example: Unlock Bypass Entry Command
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
*/
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
Table 10.23. Unlock Bypass Program
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB8QORFN%\SDVV3URJUDP&PGꢂ
Cycle
Description
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ[[[K
Word Address
%DVHꢀꢎ[[[K
Data
ꢈ
ꢊ
3URJUDPꢀ6HWXSꢀ&RPPDQG
3URJUDPꢀ&RPPDQG
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/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Table 10.24. Unlock Bypass Reset
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB8QORFN%\SDVV5HVHW&PGꢂ
Cycle
Description
5HVHWꢀ&\FOHꢀꢈ
5HVHWꢀ&\FOHꢀꢊ
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ[[[K
%DVHꢀꢎꢀ[[[K
Word Address
%DVHꢀꢎ[[[K
%DVHꢀꢎ[[[K
Data
ꢈ
ꢊ
ꢏꢏꢋꢏK
ꢏꢏꢏꢏK
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/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
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December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
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48
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 10.6. Write Operation Status Flowchart
December 3, 2005 S29WS-N_m0_I0
49
P r e l i m i n a r y
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50
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 10.25. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
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December 3, 2005 S29WS-N_m0_I0
51
P r e l i m i n a r y
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52
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 10.26. Write Operation Status
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December 3, 2005 S29WS-N_m0_I0
53
P r e l i m i n a r y
10.7 Simultaneous Read/Write
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10.8 Writing Commands/Command Sequences
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DGGUHVV´ꢀLVꢀWKHꢀDGGUHVVꢀELWVꢀUHTXLUHGꢀWRꢀXQLTXHO\ꢀVHOHFWꢀDꢀVHFWRUꢃꢀ,&&ꢊꢀLQꢀ³'&ꢀ&KDUDFWHULVWLFV´ꢀUHSꢅ
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10.9 Handshaking
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54
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
10.10 Hardware Reset
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RSHUDWLRQꢀLQꢀSURJUHVVꢄꢀWULVWDWHVꢀDOOꢀRXWSXWVꢄꢀUHVHWVꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUꢄꢀDQGꢀLJQRUHVꢀDOOꢀUHDGꢑ
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10.11 Software Reset
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Software Functions and Sample Code
Table 10.27. Reset
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Cycle
Operation
Byte Address
Word Address
Data
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/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
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December 3, 2005 S29WS-N_m0_I0
55
P r e l i m i n a r y
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56
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
11 Advanced Sector Protection/Unprotection
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Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
Password Method
(
(DQ1)
(DQ2)
WP# = V
IL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(DYB)6,7,8
Memory Array
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N3
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 11.1. Advanced Sector Protection/Unprotection
December 3, 2005 S29WS-N_m0_I0
57
P r e l i m i n a r y
11.1 Lock Register
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Table 11.1 Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
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December 3, 2005 S29WS-N_m0_I0
59
P r e l i m i n a r y
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Yes
Wait 500 µs
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
PASS
Exit PPB
Command Set
Figure 11.2. PPB Program/Erase Algorithm
60
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
11.3 Dynamic Protection Bits
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S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
(Recommended)
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 11.3. Lock Register Program Algorithm
December 3, 2005 S29WS-N_m0_I0
63
P r e l i m i n a r y
11.6 Advanced Sector Protection Software Examples
Table 11.2 Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
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12 Power Conservation Modes
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:KHQꢀ5(6(7ꢔꢀLVꢀKHOGꢀDWꢀ966ꢀꢀꢏꢃꢊꢀ9ꢄꢀWKHꢀGHYLFHꢀGUDZVꢀ&026ꢀVWDQGE\ꢀFXUUHQWꢀꢁ,&&ꢓꢂꢃꢀ,Iꢀ5(6(7ꢔ
LVꢀKHOGꢀDWꢀ9,/ꢀEXWꢀQRWꢀZLWKLQꢀ966ꢀꢀꢏꢃꢊꢀ9ꢄꢀWKHꢀVWDQGE\ꢀFXUUHQWꢀLVꢀJUHDWHUꢃ
5(6(7ꢔꢀPD\ꢀEHꢀWLHGꢀWRꢀWKHꢀV\VWHPꢀUHVHWꢀFLUFXLWU\ꢀDQGꢀWKXVꢄꢀDꢀV\VWHPꢀUHVHWꢀZRXOGꢀDOVRꢀUHVHWꢀWKH
)ODVKꢀPHPRU\ꢄꢀHQDEOLQJꢀWKHꢀV\VWHPꢀWRꢀUHDGꢀWKHꢀERRWꢅXSꢀILUPZDUHꢀIURPꢀWKHꢀ)ODVKꢀPHPRU\ꢃ
12.4 Output Disable (OE#)
:KHQꢀWKHꢀ2(ꢔꢀLQSXWꢀLVꢀDWꢀ9,+ꢄꢀRXWSXWꢀIURPꢀWKHꢀGHYLFHꢀLVꢀGLVDEOHGꢃꢀ7KHꢀRXWSXWVꢀDUHꢀSODFHGꢀLQꢀWKH
KLJKꢀLPSHGDQFHꢀVWDWHꢃ
66
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
13 Secured Silicon Sector Flash Memory Region
7KHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀSURYLGHVꢀDQꢀH[WUDꢀ)ODVKꢀPHPRU\ꢀUHJLRQꢀWKDWꢀHQDEOHVꢀSHUPDQHQWꢀSDUW
LGHQWLILFDWLRQꢀWKURXJKꢀDQꢀ(OHFWURQLFꢀ6HULDOꢀ1XPEHUꢀꢁ(61ꢂꢃꢀ7KHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀꢊꢉꢌ
ZRUGVꢀLQꢀOHQJWKꢀWKDWꢀFRQVLVWVꢀRIꢀꢈꢊꢍꢀZRUGVꢀIRUꢀIDFWRU\ꢀGDWDꢀDQGꢀꢈꢊꢍꢀZRUGVꢀIRUꢀFXVWRPHUꢅVHFXUHG
DUHDVꢃꢀ$OOꢀ6HFXUHGꢀ6LOLFRQꢀUHDGVꢀRXWVLGHꢀRIꢀWKHꢀꢊꢉꢌꢅZRUGꢀDGGUHVVꢀUDQJHꢀUHWXUQVꢀLQYDOLGꢀGDWDꢃꢀ7KH
)DFWRU\ꢀ,QGLFDWRUꢀ%LWꢄꢀ'4ꢇꢄꢀꢁDWꢀ$XWRVHOHFWꢀDGGUHVVꢀꢏꢐKꢂꢀLVꢀXVHGꢀWRꢀLQGLFDWHꢀZKHWKHUꢀRUꢀQRWꢀWKH
)DFWRU\ꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀORFNHGꢀZKHQꢀVKLSSHGꢀIURPꢀWKHꢀIDFWRU\ꢃꢀ7KHꢀ&XVWRPHUꢀ,QGLFDWRU
%LWꢀꢁ'4ꢌꢂꢀLVꢀXVHGꢀWRꢀLQGLFDWHꢀZKHWKHUꢀRUꢀQRWꢀWKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀORFNHGꢀZKHQ
VKLSSHGꢀIURPꢀWKHꢀIDFWRU\ꢃꢀ
3OHDVHꢀQRWHꢀWKHꢀIROORZLQJꢀJHQHUDOꢀFRQGLWLRQVꢆ
:KLOHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀDFFHVVꢀLVꢀHQDEOHGꢄꢀVLPXOWDQHRXVꢀRSHUDWLRQVꢀDUHꢀDOORZHGꢀH[FHSW
IRUꢀ%DQNꢀꢏꢃꢀ
2QꢀSRZHUꢅXSꢄꢀRUꢀIROORZLQJꢀDꢀKDUGZDUHꢀUHVHWꢄꢀWKHꢀGHYLFHꢀUHYHUWVꢀWRꢀVHQGLQJꢀFRPPDQGVꢀWRꢀWKH
QRUPDOꢀDGGUHVVꢀVSDFHꢃꢀ
5HDGVꢀFDQꢀEHꢀSHUIRUPHGꢀLQꢀWKHꢀ$V\QFKURQRXVꢀRUꢀ6\QFKURQRXVꢀPRGHꢃꢀ
%XUVWꢀPRGHꢀUHDGVꢀZLWKLQꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀZUDSꢀIURPꢀDGGUHVVꢀ))KꢀEDFNꢀWRꢀDGGUHVVꢀꢏꢏKꢃꢀ
5HDGVꢀRXWVLGHꢀRIꢀVHFWRUꢀꢏꢀUHWXUQꢀPHPRU\ꢀDUUD\ꢀGDWDꢃꢀ
&RQWLQXRXVꢀEXUVWꢀUHDGꢀSDVWꢀWKHꢀPD[LPXPꢀDGGUHVVꢀLVꢀXQGHILQHGꢃ
6HFWRUꢀꢏꢀLVꢀUHPDSSHGꢀIURPꢀPHPRU\ꢀDUUD\ꢀWRꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀDUUD\ꢃꢀ
2QFHꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ(QWU\ꢀ&RPPDQGꢀLVꢀLVVXHGꢄꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ([LW
FRPPDQGꢀPXVWꢀEHꢀLVVXHGꢀWRꢀH[LWꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ0RGHꢃ
7KHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀQRWꢀDFFHVVLEOHꢀZKHQꢀWKHꢀGHYLFHꢀLVꢀH[HFXWLQJꢀDQꢀ(PEHGGHGꢀ3URꢅ
JUDPꢀRUꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢃꢀ
Table 13.1 Secured Silicon Sector Addresses
Sector
&XVWRPHU
)DFWRU\
Sector Size
ꢈꢊꢍꢀZRUGV
ꢈꢊꢍꢀZRUGV
Address Range
ꢏꢏꢏꢏꢍꢏKꢅꢏꢏꢏꢏ))K
ꢏꢏꢏꢏꢏꢏKꢅꢏꢏꢏꢏꢇ)K
13.1 Factory Secured SiliconSector
7KHꢀ)DFWRU\ꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀDOZD\VꢀSURWHFWHGꢀZKHQꢀVKLSSHGꢀIURPꢀWKHꢀIDFWRU\ꢀDQGꢀKDV
WKHꢀ)DFWRU\ꢀ,QGLFDWRUꢀ%LWꢀꢁ'4ꢇꢂꢀSHUPDQHQWO\ꢀVHWꢀWRꢀDꢀ³ꢈ´ꢃꢀ7KLVꢀSUHYHQWVꢀFORQLQJꢀRIꢀDꢀIDFWRU\ꢀORFNHG
SDUWꢀDQGꢀHQVXUHVꢀWKHꢀVHFXULW\ꢀRIꢀWKHꢀ(61ꢀDQGꢀFXVWRPHUꢀFRGHꢀRQFHꢀWKHꢀSURGXFWꢀLVꢀVKLSSHGꢀWRꢀWKH
ILHOGꢃꢀ
7KHVHꢀGHYLFHVꢀDUHꢀDYDLODEOHꢀSUHꢀSURJUDPPHGꢀZLWKꢀRQHꢀRIꢀWKHꢀIROORZLQJꢆ
$ꢀUDQGRPꢄꢀꢍꢀ:RUGꢀVHFXUHꢀ(61ꢀRQO\ꢀZLWKLQꢀWKHꢀ)DFWRU\ꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRU
&XVWRPHUꢀFRGHꢀZLWKLQꢀWKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀWKURXJKꢀWKHꢀ6SDQVLRQ ꢀSURJUDPꢅ
PLQJꢀVHUYLFHꢃ
%RWKꢀDꢀUDQGRPꢄꢀVHFXUHꢀ(61ꢀDQGꢀFXVWRPHUꢀFRGHꢀWKURXJKꢀWKHꢀ6SDQVLRQꢀSURJUDPPLQJꢀVHUYLFHꢃ
&XVWRPHUVꢀPD\ꢀRSWꢀWRꢀKDYHꢀWKHLUꢀFRGHꢀSURJUDPPHGꢀWKURXJKꢀWKHꢀ6SDQVLRQꢀSURJUDPPLQJꢀVHUꢅ
YLFHVꢃꢀ6SDQVLRQꢀSURJUDPVꢀWKHꢀFXVWRPHUꢗVꢀFRGHꢄꢀZLWKꢀRUꢀZLWKRXWꢀWKHꢀUDQGRPꢀ(61ꢃꢀ7KHꢀGHYLFHVꢀDUH
WKHQꢀVKLSSHGꢀIURPꢀWKHꢀ6SDQVLRQꢀIDFWRU\ꢀZLWKꢀWKHꢀ)DFWRU\ꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀDQGꢀ&XVWRPHU
6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀSHUPDQHQWO\ꢀORFNHGꢃꢀ&RQWDFWꢀ\RXUꢀORFDOꢀUHSUHVHQWDWLYHꢀIRUꢀGHWDLOVꢀRQꢀXVLQJ
6SDQVLRQꢀSURJUDPPLQJꢀVHUYLFHVꢃꢀ
December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
13.2 Customer Secured Silicon Sector
7KHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀW\SLFDOO\ꢀVKLSSHGꢀXQSURWHFWHGꢀꢁ'4ꢌꢀVHWꢀWRꢀ³ꢏ´ꢂꢄꢀDOORZLQJ
FXVWRPHUVꢀWRꢀXWLOL]HꢀWKDWꢀVHFWRUꢀLQꢀDQ\ꢀPDQQHUꢀWKH\ꢀFKRRVHꢃꢀ,IꢀWKHꢀVHFXULW\ꢀIHDWXUHꢀLVꢀQRWꢀUHTXLUHGꢄ
WKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀFDQꢀEHꢀWUHDWHGꢀDVꢀDQꢀDGGLWLRQDOꢀ)ODVKꢀPHPRU\ꢀVSDFHꢃꢀ
3OHDVHꢀQRWHꢀWKHꢀIROORZLQJꢆ
2QFHꢀWKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀDUHDꢀLVꢀSURWHFWHGꢄꢀWKHꢀ&XVWRPHUꢀ,QGLFDWRUꢀ%LWꢀLV
SHUPDQHQWO\ꢀVHWꢀWRꢀ³ꢈꢃ´
7KHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀFDQꢀEHꢀUHDGꢀDQ\ꢀQXPEHUꢀRIꢀWLPHVꢄꢀEXWꢀFDQꢀEHꢀSURꢅ
JUDPPHGꢀDQGꢀORFNHGꢀRQO\ꢀRQFHꢃꢀ7KHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀORFNꢀPXVWꢀEHꢀXVHGꢀZLWK
FDXWLRQꢀDVꢀRQFHꢀORFNHGꢄꢀWKHUHꢀLVꢀQRꢀSURFHGXUHꢀDYDLODEOHꢀIRUꢀXQORFNLQJꢀWKHꢀ&XVWRPHUꢀ6HFXUHG
6LOLFRQꢀ6HFWRUꢀDUHDꢀDQGꢀQRQHꢀRIꢀWKHꢀELWVꢀLQꢀWKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀPHPRU\
VSDFHꢀFDQꢀEHꢀPRGLILHGꢀLQꢀDQ\ꢀZD\ꢃ
7KHꢀDFFHOHUDWHGꢀSURJUDPPLQJꢀꢁ$&&ꢂꢀDQGꢀXQORFNꢀE\SDVVꢀIXQFWLRQVꢀDUHꢀQRWꢀDYDLODEOHꢀZKHQ
SURJUDPPLQJꢀWKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢄꢀEXWꢀUHDGLQJꢀLQꢀ%DQNVꢀꢈꢀWKURXJKꢀꢈꢉꢀLV
DYDLODEOHꢃꢀ
2QFHꢀWKHꢀ&XVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀORFNHGꢀDQGꢀYHULILHGꢄꢀWKHꢀV\VWHPꢀPXVWꢀZULWHꢀWKH
([LWꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ5HJLRQꢀFRPPDQGꢀVHTXHQFHꢀZKLFKꢀUHWXUQꢀWKHꢀGHYLFHꢀWRꢀWKHꢀPHPꢅ
RU\ꢀDUUD\ꢀDWꢀVHFWRUꢀꢏꢃ
13.3 Secured Silicon Sector Entry/Exit Command Sequences
7KHꢀV\VWHPꢀFDQꢀDFFHVVꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀUHJLRQꢀE\ꢀLVVXLQJꢀWKHꢀWKUHHꢅF\FOHꢀ(QWHUꢀ6Hꢅ
FXUHGꢀ6LOLFRQꢀ6HFWRUꢀFRPPDQGꢀVHTXHQFHꢃꢀ7KHꢀGHYLFHꢀFRQWLQXHVꢀWRꢀDFFHVVꢀWKHꢀ6HFXUHGꢀ6LOLFRQ
6HFWRUꢀUHJLRQꢀXQWLOꢀWKHꢀV\VWHPꢀLVVXHVꢀWKHꢀIRXUꢅF\FOHꢀ([LWꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀFRPPDQG
VHTXHQFHꢃꢀ
6HHꢀ&RPPDQGꢀ'HILQLWLRQꢀ7DEOHꢀ>6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ&RPPDQGꢀ7DEOHꢄꢀ$SSHQGL[ꢀ
7DEOHꢀꢈꢉꢃꢈꢀIRUꢀDGGUHVVꢀDQGꢀGDWDꢀUHTXLUHPHQWVꢀIRUꢀERWKꢀFRPPDQGꢀVHTXHQFHVꢃ
7KHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ(QWU\ꢀ&RPPDQGꢀDOORZVꢀWKHꢀIROORZLQJꢀFRPPDQGVꢀWRꢀEHꢀH[HFXWHG
5HDGꢀFXVWRPHUꢀDQGꢀIDFWRU\ꢀ6HFXUHGꢀ6LOLFRQꢀDUHDV
3URJUDPꢀWKHꢀFXVWRPHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRU
$IWHUꢀWKHꢀV\VWHPꢀKDVꢀZULWWHQꢀWKHꢀ(QWHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀFRPPDQGꢀVHTXHQFHꢄꢀLWꢀPD\ꢀUHDG
WKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀE\ꢀXVLQJꢀWKHꢀDGGUHVVHVꢀQRUPDOO\ꢀRFFXSLHGꢀE\ꢀVHFWRUꢀ6$ꢏꢀZLWKLQꢀWKH
PHPRU\ꢀDUUD\ꢃꢀ7KLVꢀPRGHꢀRIꢀRSHUDWLRQꢀFRQWLQXHVꢀXQWLOꢀWKHꢀV\VWHPꢀLVVXHVꢀWKHꢀ([LWꢀ6HFXUHGꢀ6LOLFRQ
6HFWRUꢀFRPPDQGꢀVHTXHQFHꢄꢀRUꢀXQWLOꢀSRZHUꢀLVꢀUHPRYHGꢀIURPꢀWKHꢀGHYLFHꢃꢀ
Software Functions and Sample Code
7KHꢀIROORZLQJꢀDUHꢀ&ꢀIXQFWLRQVꢀDQGꢀVRXUFHꢀFRGHꢀH[DPSOHVꢀRIꢀXVLQJꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ(QWU\ꢄ
3URJUDPꢄꢀDQGꢀH[LWꢀFRPPDQGVꢃꢀ5HIHUꢀWRꢀWKHꢀ6SDQVLRQꢀ/RZꢀ/HYHOꢀ'ULYHUꢀ8VHU¶Vꢀ*XLGHꢀꢁDYDLODEOH
VRRQꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDOꢀLQIRUPDWLRQꢀRQꢀ6SDQVLRQꢀ)ODVKꢀPHPRU\
VRIWZDUHꢀGHYHORSPHQWꢀJXLGHOLQHVꢃ
68
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P r e l i m i n a r y
Table 13.2. Secured Silicon Sector Entry
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB6HF6L6HFWRU(QWU\&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
Data
8QORFNꢀ&\FOHꢀꢈ
8QORFNꢀ&\FOHꢀꢊ
ꢏꢏ$$K
ꢏꢏꢉꢉK
ꢏꢏꢍꢍK
:ULWH
(QWU\ꢀ&\FOH
:ULWH
1RWHꢀꢀ%DVHꢀ ꢀ%DVHꢀ$GGUHVVꢆ
/* Example: SecSi Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 13.3. Secured Silicon Sector Program
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
:RUGꢀ$GGUHVV
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
:RUGꢀ$GGUHVV
Data
ꢏꢏ$$K
8QORFNꢀ&\FOHꢀꢈ
8QORFNꢀ&\FOHꢀꢊ
3URJUDPꢀ6HWXS
:ULWH
ꢏꢏꢉꢉK
:ULWH
ꢏꢏ$ꢏK
3URJUDP
:ULWH
'DWDꢀ:RUG
1RWHꢀꢀ%DVHꢀ ꢀ%DVHꢀ$GGUHVVꢆ
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Table 13.4. Secured Silicon Sector Exit
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB6HF6L6HFWRU([LW&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢎꢀ$$$K
%DVHꢀꢎꢀꢉꢉꢓK
%DVHꢀꢎꢀ$$$K
Word Address
%DVHꢀꢎꢀꢉꢉꢉK
%DVHꢀꢎꢀꢊ$$K
%DVHꢀꢎꢀꢉꢉꢉK
Data
8QORFNꢀ&\FOHꢀꢈ
8QORFNꢀ&\FOHꢀꢊ
ꢏꢏ$$K
ꢏꢏꢉꢉK
ꢏꢏꢋꢏK
:ULWH
([LWꢀ&\FOH
:ULWH
1RWHꢀꢀ%DVHꢀ ꢀ%DVHꢀ$GGUHVVꢆ
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
*/
*/
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P r e l i m i n a r y
14 Electrical Specifications
14.1 Absolute Maximum Ratings
6WRUDJHꢀ7HPSHUDWXUH
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14.2 Operating Ranges
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ꢍꢆ , ꢀDFWLYHꢀZKLOHꢀ(PEHGGHGꢀ(UDVHꢀRUꢀ(PEHGGHGꢀ3URJUDPꢀLVꢀLQꢀSURJUHVVꢆ
&&
ꢌꢆ 'HYLFHꢀHQWHUVꢀDXWRPDWLFꢀVOHHSꢀPRGHꢀZKHQꢀDGGUHVVHVꢀDUHꢀVWDEOHꢀIRUꢀW
ꢀꢉꢀꢈꢁꢀQVꢆꢀ
$&&
7\SLFDOꢀVOHHSꢀPRGHꢀFXUUHQWꢀLVꢀHTXDOꢀWRꢀ,
ꢆ
&&ꢊ
ꢐꢆ 9 ꢀ ꢀ9 ꢀꢀꢁꢆꢈꢀ9ꢀDQGꢀ9 ꢀ!ꢀ±ꢁꢆꢅꢀ9ꢆ
,+
&&
,/
ꢋꢆ 7RWDOꢀFXUUHQWꢀGXULQJꢀDFFHOHUDWHGꢀSURJUDPPLQJꢀLVꢀWKHꢀVXPꢀRIꢀ9
FXUUHQWVꢆ
ꢀDQGꢀ9
ꢀ
&&
$&&
ꢎꢆ 9
ꢀ ꢀ9 ꢀRQꢀ$&&ꢀLQSXWꢆ
++
$&&
December 3, 2005 S29WS-N_m0_I0
73
P r e l i m i n a r y
14.8 AC Characteristics
ꢄꢉꢅꢌꢅꢄ &/.ꢀ&KDUDFWHUL]DWLRQ
Parameter
I&/.
Description
&/.ꢀ)UHTXHQF\
54 MHz
66 MHz
ꢌꢌ
80 MHz
ꢍꢏ
Unit
0+]
QV
0D[
0LQ
ꢉꢓ
W&/.
W&+
&/.ꢀ3HULRG
ꢈꢍꢃꢉ
ꢈꢉꢃꢈ
ꢈꢊꢃꢉ
&/.ꢀ+LJKꢀ7LPH
&/.ꢀ/RZꢀ7LPH
&/.ꢀ5LVHꢀ7LPH
&/.ꢀ)DOOꢀ7LPH
0LQ
ꢇꢃꢓ
ꢐ
ꢌꢃꢈ
ꢐ
ꢉꢃꢏ
ꢊꢃꢉ
QV
QV
W&/
W&5
0D[
W&)
1RWHꢀ 1RWꢀꢅꢁꢁꢖꢀWHVWHGꢆꢀ
t
CLK
t
t
CH
CL
CLK
t
t
CF
CR
Figure 14.6. CLK Characterization
74
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
ꢄꢉꢅꢌꢅꢎ 6\QFKURQRXVꢑ%XUVWꢀ5HDG
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz
ꢍꢏ
80 MHz
Unit
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
0+]
W,$&&
W%$&&
W$&6
W$&+
W%'+
W&5
/DWHQF\
0D[
%XUVWꢀ$FFHVVꢀ7LPHꢀ9DOLGꢀ&ORFNꢀWRꢀ2XWSXWꢀ'HOD\ 0D[
ꢈꢐꢃꢉ
ꢉ
ꢈꢈꢃꢊ
ꢋ
$GGUHVVꢀ6HWXSꢀ7LPHꢀWRꢀ&/.ꢀꢁ1RWHꢀꢈꢂ
$GGUHVVꢀ+ROGꢀ7LPHꢀIURPꢀ&/.ꢀꢁ1RWHꢀꢈꢂ
'DWDꢀ+ROGꢀ7LPHꢀIURPꢀ1H[Wꢀ&ORFNꢀ&\FOH
&KLSꢀ(QDEOHꢀWRꢀ5'<ꢀ9DOLGꢀ
2XWSXWꢀ(QDEOHꢀWRꢀ2XWSXWꢀ9DOLG
&KLSꢀ(QDEOHꢀWRꢀ+LJKꢀ=ꢀꢁ1RWHꢀꢊꢂ
2XWSXWꢀ(QDEOHꢀWRꢀ+LJKꢀ=ꢀꢁ1RWHꢀꢊꢂ
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
0LQ
0LQ
0LQ
0D[
0D[
0D[
0D[
0LQ
0LQ
0D[
0LQ
0LQ
0LQ
0LQ
0LQ
ꢓ
ꢌ
ꢐ
ꢇ
ꢓ
ꢈꢐꢃꢉ
ꢈꢐꢃꢉ
ꢈꢈꢃꢊ
ꢋ
W2(
ꢈꢈꢃꢊ
W&(=
W2(=
W&(6
W5'<6
W5$&&
W&$6
W$9&
W$9'
W$9'+
I&/.
ꢈꢏ
ꢈꢏ
ꢓ
5'<ꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
ꢉ
ꢓ
ꢐꢃꢉ
ꢍꢃꢉ
5HDG\ꢀ$FFHVVꢀ7LPHꢀIURPꢀ&/.
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ$9'ꢔꢀ
$9'ꢔꢀ/RZꢀWRꢀ&/.
ꢈꢐꢃꢉ
ꢈꢈꢃꢊ
ꢏ
ꢓ
$9'ꢔꢀ3XOVH
ꢇ
$9'ꢔꢀ+ROG
ꢐ
ꢈ
ꢈ
ꢈ
0LQLPXPꢀFORFNꢀIUHTXHQF\
1RWHVꢀ
ꢅꢆ $GGUHVVHVꢀDUHꢀODWFKHGꢀRQꢀWKHꢀILUVWꢀULVLQJꢀHGJHꢀRIꢀ&/.ꢆ
ꢈꢆ 1RWꢀꢅꢁꢁꢖꢀWHVWHGꢆ
Table 14.2 Synchronous Wait State Requirements
0D[ꢀ)UHTXHQF\
:DLWꢀ6WDWHꢀ5HTXLUHPHQW
ꢏꢈ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢈꢓ 0+]
ꢈꢓ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢊꢇ 0+]
ꢊꢇ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢓꢏ 0+]
ꢓꢏ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢉꢓ 0+]
ꢉꢓ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢌꢇ 0+]
ꢌꢇ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢍꢏ 0+]
ꢊ
ꢐ
ꢓ
ꢉ
ꢌ
ꢇ
December 3, 2005 S29WS-N_m0_I0
75
P r e l i m i n a r y
ꢄꢉꢅꢌꢅꢐ 7LPLQJꢀ'LDJUDPV
5 cycles for initial access shown.
tCEZ
tCES
18.5 ns typ. (54 MHz)
5
CE#
1
2
3
4
6
7
CLK
tAVC
AVD#
tAVD
tAVDH
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
Da + 3
tBDH
OE#
tRACC
tOE
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
RDY (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
1RWHVꢀ
ꢅꢆ )LJXUHꢀVKRZVꢀWRWDOꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀVHWꢀWRꢀILYHꢀF\FOHVꢆꢀ7KHꢀWRWDOꢀQXPEHUꢀRIꢀ
ZDLWꢀVWDWHVꢀFDQꢀEHꢀSURJUDPPHGꢀIURPꢀWZRꢀF\FOHVꢀWRꢀVHYHQꢀF\FOHVꢆꢀ
ꢈꢆ ,IꢀDQ\ꢀEXUVWꢀDGGUHVVꢀRFFXUVꢀDWꢀ³DGGUHVVꢀꢉꢀꢅ´ꢄꢀ³DGGUHVVꢀꢉꢀꢈ´ꢄꢀRUꢀ³DGGUHVVꢀꢉꢀꢊ´ꢄꢀ
DGGLWLRQDOꢀFORFNꢀGHOD\ꢀF\FOHVꢀDUHꢀLQVHUWHGꢄꢀDQGꢀDUHꢀLQGLFDWHGꢀE\ꢀ5'<ꢆ
ꢊꢆ 7KHꢀGHYLFHꢀLVꢀLQꢀV\QFKURQRXVꢀPRGHꢆ
Figure 14.7. CLK Synchronous Burst Mode Read
76
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
tAVDH
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
1RWHVꢀ
ꢅꢆ )LJXUHꢀVKRZVꢀWRWDOꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀVHWꢀWRꢀVHYHQꢀF\FOHVꢆꢀ7KHꢀWRWDOꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀFDQꢀEHꢀSURJUDPPHGꢀIURPꢀWZRꢀF\FOHVꢀWRꢀVHYHQꢀ
F\FOHVꢆ
ꢈꢆ ,IꢀDQ\ꢀEXUVWꢀDGGUHVVꢀRFFXUVꢀDWꢀ³DGGUHVVꢀꢉꢀꢅ´ꢄꢀ³DGGUHVVꢀꢉꢀꢈ´ꢄꢀRUꢀ³DGGUHVVꢀꢉꢀꢊ´ꢄꢀDGGLWLRQDOꢀFORFNꢀGHOD\ꢀF\FOHVꢀDUHꢀLQVHUWHGꢄꢀDQ GꢀDUHꢀLQGLFDWHGꢀ
E\ꢀ5'<ꢆ
ꢊꢆ 7KHꢀGHYLFHꢀLVꢀLQꢀV\QFKURQRXVꢀPRGHꢀZLWKꢀZUDSꢀDURXQGꢆ
ꢍꢆ 'ꢎ±')ꢀLQꢀGDWDꢀZDYHIRUPꢀLQGLFDWHꢀWKHꢀRUGHUꢀRIꢀGDWDꢀZLWKLQꢀDꢀJLYHQꢀꢎꢇZRUGꢀDGGUHVVꢀUDQJHꢄꢀIURPꢀORZHVWꢀWRꢀKLJKHVWꢆꢀ6WDUWLQJꢀDGGUHVVꢀLQꢀILJXUHꢀ
LVꢀWKHꢀꢍWKꢀDGGUHVVꢀLQꢀUDQJHꢀꢂꢁꢇ)ꢃꢆꢀ
Figure 14.8. 8-word Linear Burst with Wrap Around
7
cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
tAVDH
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
1RWHVꢀ
ꢅꢆ )LJXUHꢀVKRZVꢀWRWDOꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀVHWꢀWRꢀVHYHQꢀF\FOHVꢆꢀ7KHꢀWRWDOꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀFDQꢀEHꢀSURJUDPPHGꢀIURPꢀWZRꢀF\FOHVꢀWRꢀVHYHQꢀ
F\FOHVꢆꢀ&ORFNꢀLVꢀVHWꢀIRUꢀDFWLYHꢀULVLQJꢀHGJHꢆ
ꢈꢆ ,IꢀDQ\ꢀEXUVWꢀDGGUHVVꢀRFFXUVꢀDWꢀ³DGGUHVVꢀꢉꢀꢅ´ꢄꢀ³DGGUHVVꢀꢉꢀꢈ´ꢄꢀRUꢀ³DGGUHVVꢀꢉꢀꢊ´ꢄꢀDGGLWLRQDOꢀFORFNꢀGHOD\ꢀF\FOHVꢀDUHꢀLQVHUWHGꢄꢀDQ GꢀDUHꢀLQGLFDWHGꢀ
E\ꢀ5'<ꢆ
ꢊꢆ 7KHꢀGHYLFHꢀLVꢀLQꢀDV\QFKURQRXVꢀPRGHꢀZLWKꢀRXWꢀZUDSꢀDURXQGꢆ
ꢍꢆ '&±'ꢅꢊꢀLQꢀGDWDꢀZDYHIRUPꢀLQGLFDWHꢀWKHꢀRUGHUꢀRIꢀGDWDꢀZLWKLQꢀDꢀJLYHQꢀꢎꢇZRUGꢀDGGUHVVꢀUDQJHꢄꢀIURPꢀORZHVWꢀWRꢀKLJKHVWꢆꢀ6WDUWLQJꢀDGGUHVVꢀLQꢀILJXUHꢀ
LVꢀWKHꢀꢅVWꢀDGGUHVVꢀLQꢀUDQJHꢀꢂFꢇꢅꢊꢃꢆꢀ
Figure 14.9. 8-word Linear Burst without Wrap Around
December 3, 2005 S29WS-N_m0_I0
77
P r e l i m i n a r y
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
5
6
7
tAVC
tAVDH
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
1RWHVꢀ
ꢅꢆ )LJXUHꢀDVVXPHVꢀꢐꢀZDLWꢀVWDWHVꢀIRUꢀLQLWLDOꢀDFFHVVꢀDQGꢀV\QFKURQRXVꢀUHDGꢆ
ꢈꢆ 7KHꢀ6HWꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀFRPPDQGꢀVHTXHQFHꢀKDVꢀEHHQꢀZULWWHQꢀZLWKꢀ&5ꢎ ꢁꢓꢀGHYLFHꢀRXWSXWVꢀ5'<ꢀRQHꢀF\FOHꢀEHIRUHꢀYDOLGꢀGDWDꢆꢀ
Figure 14.10. Linear Burst with RDY Set One Cycle Before Data
ꢄꢉꢅꢌꢅꢉ $&ꢀ&KDUDFWHULVWLFV²$V\QFKURQRXVꢀ5HDG
3DUDPHWHU
'HVFULSWLRQ
$FFHVVꢀ7LPHꢀIURPꢀ&(ꢔꢀ/RZ
ꢈꢉꢀ0+] ꢋꢋꢀ0+] ꢌꢍꢀ0+] 8QLW
-('(& 6WDQGDUG
W
0D[
0D[
0LQ
0LQ
0LQ
0D[
0LQ
ꢍꢏ
ꢍꢏ
ꢍ
QV
QV
QV
QV
QV
QV
QV
&(
W
$V\QFKURQRXVꢀ$FFHVVꢀ7LPH
$9'ꢔꢀ/RZꢀ7LPH
$&&
W
$9'3
W
$GGUHVVꢀ6HWXSꢀ7LPHꢀWRꢀ5LVLQJꢀ(GJHꢀRIꢀ$9'ꢔ
$GGUHVVꢀ+ROGꢀ7LPHꢀIURPꢀ5LVLQJꢀ(GJHꢀRIꢀ$9'ꢔ
2XWSXWꢀ(QDEOHꢀWRꢀ2XWSXWꢀ9DOLG
5HDG
ꢓ
$$9'6
$$9'+
W
ꢇ
ꢌ
W
ꢈꢐꢃꢉ
ꢏ
2(
W
2XWSXWꢀ(QDEOHꢀ+ROGꢀ7LPH
2(+
7RJJOHꢀDQG
0LQ
ꢈꢏ
QV
'DWDꢔꢀ3ROOLQJ
2XWSXWꢀ(QDEOHꢀWRꢀ+LJKꢀ=ꢀꢁVHHꢀ1RWHꢂ
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ$9'ꢔ
W
0D[
0LQ
ꢈꢏ
ꢏ
QV
QV
QV
2(=
&$6
W
W
3DJHꢀ$FFHVVꢀ7LPH
0D[
ꢊꢏ
3$&&
2XWSXWꢀ+ROGꢀ7LPHꢀ)URPꢀ$GGUHVVHVꢄꢀ&(ꢔ
RUꢀ2(ꢔꢄꢀZKLFKHYHUꢀRFFXUVꢀILUVWꢀꢁ1RWHꢀꢊꢂ
ꢀW
0LQ
ꢏ
QV
QV
2+
&KLSꢀ(QDEOHꢀWRꢀ2XWSXWꢀ7ULVWDWH
0D[
ꢈꢏ
ꢀW&(=
1RWHVꢀ
ꢅꢆ 1RWꢀꢅꢁꢁꢖꢀWHVWHGꢆ
ꢈꢆ ꢀ ꢀꢅꢀQVꢀIRUꢀ6ꢈꢏ:6ꢅꢈꢎ1ꢆ
W
2(+
78
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
1RWHꢀ 5$ꢀ ꢀ5HDGꢀ$GGUHVVꢄꢀ5'ꢀ ꢀ5HDGꢀ'DWDꢆ
Figure 14.11. Asynchronous Mode Read
A22-A2
Same Page Address
A1-A0
CE#
A0
A1
A2
A3
t
CE
t
t
COEZ
ACC
Optional
AVD#
OE#
t
OE
t
PACC
t
OEZ
WE#
Data
t
PACC
t
t
t
OEZ
OH
PACC
D0
D1
D1
D2
D3
t
t
OH
OH
Figure 14.12. Four-Word Page-Mode Operation
December 3, 2005 S29WS-N_m0_I0
79
P r e l i m i n a r y
ꢄꢉꢅꢌꢅꢈ +DUGZDUHꢀ5HVHWꢀꢂ5(6(7ꢒꢃꢀ
Parameter
JEDEC
Std.
W53
Description
All Speed Options
Unit
V
5(6(7ꢔꢀ3XOVHꢀ:LGWK
5HVHWꢀ+LJKꢀ7LPHꢀ%HIRUHꢀ5HDGꢀꢁ6HHꢀ1RWHꢂ
0LQ
0LQ
ꢐꢏ
W5+
ꢊꢏꢏ
QV
1RWHꢀꢀ1RWꢀꢅꢁꢁꢖꢀWHVWHGꢆ
CE#, OE#
tRH
RESET#
tRP
Figure 14.13. Reset Timings
80
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
ꢄꢉꢅꢌꢅꢋ (UDVHꢑ3URJUDPꢀ7LPLQJ
Parameter
JEDEC Standard
Description
54 MHz
66 MHz
80 MHz Unit
W
W
:ULWHꢀ&\FOHꢀ7LPHꢀꢁ1RWHꢀꢈꢂ
0LQ
0LQ
ꢍꢏ
ꢉ
QV
QV
QV
$9$9
:&
6\QFKURQRXV
$V\QFKURQRXV
6\QFKURQRXV
$V\QFKURQRXV
W
W
$GGUHVVꢀ6HWXSꢀ7LPHꢀꢁ1RWHVꢀꢊꢄꢀꢐꢂ
$GGUHVVꢀ+ROGꢀ7LPHꢀꢁ1RWHVꢀꢊꢄꢀꢐꢂ
$9:/
$6
ꢏ
ꢋ
W
W
0LQ
QV
:/$;
$+
ꢊꢏ
ꢍ
W
$9'ꢔꢀ/RZꢀ7LPH
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0LQ
0D[
0D[
0D[
0D[
7\S
7\S
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
V
QV
QV
QV
QV
QV
QV
QV
V
V
V
V
V
$9'3
W
W
W
'DWDꢀ6HWXSꢀ7LPH
ꢓꢉ
ꢊꢏ
'9:+
'6
W
'DWDꢀ+ROGꢀ7LPH
ꢏ
ꢏ
:+';
'+
W
W
5HDGꢀ5HFRYHU\ꢀ7LPHꢀ%HIRUHꢀ:ULWH
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ$9'ꢔ
&(ꢔꢀ+ROGꢀ7LPH
*+:/
*+:/
W
ꢏ
&$6
W
W
ꢏ
:+(+
:/:+
:+:/
&+
W
W
W
:ULWHꢀ3XOVHꢀ:LGWK
ꢐꢏ
ꢊꢏ
ꢏ
:3
W
:ULWHꢀ3XOVHꢀ:LGWKꢀ+LJK
:3+
W
/DWHQF\ꢀ%HWZHHQꢀ5HDGꢀDQGꢀ:ULWHꢀ2SHUDWLRQV
65ꢑ:
W
9
9
ꢀ5LVHꢀDQGꢀ)DOOꢀ7LPH
ꢉꢏꢏ
ꢈ
9,'
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December 3, 2005 S29WS-N_m0_I0
81
P r e l i m i n a r y
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
VA
VA
Addresses
Data
2AAh
555h for
chip erase
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 14.14. Chip/Sector Erase Operation Timings
82
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
Data
555h
VA
VA
PA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
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Figure 14.15. Program Operation Timing Using AVD#
December 3, 2005 S29WS-N_m0_I0
83
P r e l i m i n a r y
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
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Figure 14.16. Program Operation Timing Using CLK in Relationship to AVD#
84
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IL
IH
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Figure 14.17. Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
Addresses
VA
High Z
Status Data
Status Data
Data
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Figure 14.18. Data# Polling Timings (During Embedded Algorithm)
December 3, 2005 S29WS-N_m0_I0
85
P r e l i m i n a r y
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
Data
VA
Status Data
Status Data
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Figure 14.19. Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
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Figure 14.20. Synchronous Data Polling Timings/Toggle Bit Timings
86
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ADDR
CE#
AVD#
OE#
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Figure 14.21. Conditions for Incorrect DQ2 Polling During Erase Suspend
0ns
20ns
40ns
60ns
80ns
100ns 120ns 140ns 160ns 180ns 200ns
2
ADDR
CE#
AVD#
OE#
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HYHQꢀLIꢀ$9'-ꢀGRHVꢀQRWꢆ
Figure 14.22. Correct DQ2 Polling during Erase Suspend #1
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns 200ns
ADDR
CE#
AVD#
OE#
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Figure 14.23. Correct DQ2 Polling during Erase Suspend #2
0ns
20ns
40ns
60ns
80ns
100ns
120ns 140ns
160ns 180ns
200ns
ADDR
CE#
AVD#
OE#
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Figure 14.24. Correct DQ2 Polling during Erase Suspend #3
December 3, 2005 S29WS-N_m0_I0
87
P r e l i m i n a r y
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
1RWHꢀꢁ'4ꢈꢀWRJJOHVꢀRQO\ꢀZKHQꢀUHDGꢀDWꢀDQꢀDGGUHVVꢀZLWKLQꢀDQꢀHUDVHꢇVXVSHQGHGꢀVHFWRUꢆꢀ7KHꢀV\VWHPꢀPD\ꢀXVHꢀ2(-ꢀRUꢀ&(-ꢀ
WRꢀWRJJOHꢀ'4ꢈꢀDQGꢀ'4ꢐꢆ
Figure 14.25. DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
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Figure 14.26. Latency with Boundary Crossing when Frequency > 66 MHz
88
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
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Figure 14.27. Latency with Boundary Crossing into Program/Erase Bank
December 3, 2005 S29WS-N_m0_I0
89
P r e l i m i n a r y
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
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Figure 14.28. Example of Wait States Insertion
90
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWrite Cycle
tWrite Cycle
tRead Cycle
tRead Cycle
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
PA/SA
tAS
RA
555h
AVD#
tAH
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December 3, 2005 S29WS-N_m0_I0
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Parameter
Typ (Note 1)
ꢏꢃꢌ
Max (Note 2)
Unit
Comments
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Symbol
Parameter Description
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15 Appendix
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94
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 15.1 Memory Array Commands
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December 3, 2005 S29WS-N_m0_I0
95
P r e l i m i n a r y
Table 15.2. Sector Protection Commands
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96
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
15.1 Common Flash Memory Interface
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/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
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Table 15.3. CFI Query Identification String
Addresses
Data
Description
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Table 15.4. System Interface String
Addresses
Data
Description
9
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December 3, 2005 S29WS-N_m0_I0
97
P r e l i m i n a r y
Table 15.5. Device Geometry Definition
Addresses
Data
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98
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 15.6. Primary Vendor-Specific Extended Query
Addresses
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December 3, 2005 S29WS-N_m0_I0
99
P r e l i m i n a r y
Table 15.6. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
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100
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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GHFUHDVHVꢀDWꢀORZHUꢀWHPSHUDWXUHVꢀWRꢀPLQLPL]HꢀFXUUHQWꢀFRQVXPSWLRQꢀGXULQJꢀVWDQGE\ꢃꢀ'HHSꢀSRZHUꢅGRZQꢀ
ꢁ'3'ꢂꢀHQDEOHVꢀWKHꢀV\VWHPꢀWRꢀKDOWꢀWKHꢀUHIUHVKꢀRSHUDWLRQꢀDOWRJHWKHUꢀZKHQꢀQRꢀYLWDOꢀLQIRUPDWLRQꢀLVꢀVWRUHGꢀLQꢀ
WKHꢀGHYLFHꢃꢀ7KHꢀV\VWHPꢅFRQILJXUDEOHꢀUHIUHVKꢀPHFKDQLVPVꢀDUHꢀDFFHVVHGꢀWKURXJKꢀWKHꢀ5&5ꢃ
Publication Number CellRam_03 Revision A Amendment 0 Issue Date March 9, 2005
A d v a n c e I n f o r m a t i o n
17 Functional Block Diagram
64M: A[21:0]
Address Decode
Logic
Input/
Output
MUX
and
Buffers
DQ[7:0]
DRAM
MEMORY
ARRAY
DQ[15:8]
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
WAIT
LB#
UB#
1RWHꢀꢀ)XQFWLRQDOꢀEORFNꢀGLDJUDPVꢀLOOXVWUDWHꢀVLPSOLILHGꢀGHYLFHꢀRSHUDWLRQꢆꢀ6HHꢀWUXWKꢀWDEOHꢄꢀEDOOꢀGHVFULSWLRQVꢄꢀDQGꢀWLPLQJꢀGLꢇ
DJUDPVꢀIRUꢀGHWDLOHGꢀLQIRUPDWLRQꢆ
Figure 17.1 Functional Block Diagram
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
105
A d v a n c e I n f o r m a t i o n
Table 17.1 Signal Descriptions
Symbol
Type
Description
$GGUHVVꢀ,QSXWVꢆꢀ,QSXWVꢀIRUꢀDGGUHVVHVꢀGXULQJꢀ5HDGꢀDQGꢀ:ULWHꢀRSHUDWLRQVꢃꢀ$GGUHVVHVꢀDUHꢀ
LQWHUQDOO\ꢀODWFKHGꢀGXULQJꢀ5HDGꢀDQGꢀ:ULWHꢀF\FOHVꢃꢀ7KHꢀDGGUHVVꢀOLQHVꢀDUHꢀDOVRꢀXVHGꢀWRꢀGHILQHꢀ
WKHꢀYDOXHꢀWRꢀEHꢀORDGHGꢀLQWRꢀWKHꢀ%&5ꢀRUꢀWKHꢀ5&5ꢃ
ꢌꢓ0ꢆꢀ$>ꢊꢈꢆꢏ@
,QSXW
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RSHUDWLRQVꢃꢀ:KHQꢀFRQILJXUHGꢀIRUꢀV\QFKURQRXVꢀRSHUDWLRQꢄꢀWKHꢀDGGUHVVꢀLVꢀODWFKHGꢀRQꢀWKHꢀILUVWꢀ
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DFFHVVꢀ5HDGꢀDQGꢀ:ULWHꢀRSHUDWLRQVꢀDQGꢀGXULQJꢀ3DJHꢀ5HDGꢀ$FFHVVꢀRSHUDWLRQVꢃ
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FDQꢀEHꢀODWFKHGꢀRQꢀWKHꢀULVLQJꢀHGJHꢀRIꢀ$'9ꢔꢀGXULQJꢀDV\QFKURQRXVꢀ5HDGꢀDQGꢀ:ULWHꢀRSHUDWLRQVꢃꢀ
$'9ꢔꢀFDQꢀEHꢀKHOGꢀ/RZꢀGXULQJꢀDV\QFKURQRXVꢀ5HDGꢀDQGꢀ:ULWHꢀRSHUDWLRQVꢃ
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JRHVꢀLQWRꢀVWDQGE\ꢀRUꢀGHHSꢀSRZHUꢅGRZQꢀPRGHꢃ
2XWSXWꢀ(QDEOHꢆꢀ(QDEOHVꢀWKHꢀRXWSXWꢀEXIIHUVꢀZKHQꢀ/RZꢃꢀ:KHQꢀ2(ꢔꢀLVꢀ+LJKꢄꢀWKHꢀRXWSXWꢀEXIIHUVꢀ
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106
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
Table 17.2 Bus Operations—Asynchronous Mode
CLK
(Note 1) ADV#
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)
Mode
5HDG
Power
$FWLYH
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6WDQGE\
,GOH
CE#
/
OE#
/
WE#
CRE
Notes
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,1 &&
ꢋꢆ '3'ꢀLVꢀPDLQWDLQHGꢀXQWLOꢀ5&5ꢀLVꢀUHFRQILJXUHGꢆ
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
107
A d v a n c e I n f o r m a t i o n
Table 17.3 Bus Operations—Burst Mode
CLK
(Note 1) ADV#
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)
Mode
Power
$FWLYH
$FWLYH
6WDQGE\
,GOH
CE#
/
OE#
/
WE#
CRE
Notes
ꢓ
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108
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
18 Functional Description
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18.1 Power-Up Initialization
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>
V
= 1.7 V
t
150 μs
CC
PU
Device ready for
normal operation
V
CC
Device Initialization
V
Q
CC
Table 18.1 Power-Up Initialization Timing
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
109
A d v a n c e I n f o r m a t i o n
19 Bus Operating Modes
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19.1 Asynchronous Mode
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5HDGꢑ:ULWHꢀRSHUDWLRQꢃ
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OLPLWHGꢀWRꢀW&(0
ꢃ
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WE#
ADDRESS
Address Valid
Data Valid
DATA
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t
RC
= READ Cycle Time
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Figure 19.1 Read Operation (ADV# Low)
110
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
= WRITE Cycle Time
WC
Don't Care
Figure 19.2 Write Operation (ADV# Low)
19.2 Page Mode Read Operation
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ꢃ
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
111
A d v a n c e I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1] ADD[2] ADD[3]
t
AA
t
t
t
APA
APA
APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
Don't Care
Figure 19.3 Page Mode Read Operation (ADV# Low)
19.3 Burst Mode Operation
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112
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
CLK
A[22:0]
ADV#
Address
Valid
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
READ Burst Identified
Don't care
Undefined
(WE# = HIGH)
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Figure 19.4 Burst Mode Read (4-word burst)
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
Don't care
WRITE Burst Identified
(WE# = LOW)
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Figure 19.5 Burst Mode Write (4-word burst)
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
113
A d v a n c e I n f o r m a t i o n
19.4 Mixed-Mode Operation
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19.5 Wait Operation
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External
Pull-Up/
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Other
Other
Device
Device
Processor
Figure 19.6 Wired or Wait Configuration
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19.6 LB#/UB# Operation
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114
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
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V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
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Figure 19.7 Refresh Collision During Read Operation
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
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Figure 19.8 Refresh Collision During Write Operation
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
115
A d v a n c e I n f o r m a t i o n
20 Low-Power Operation
20.1 Standby Mode Operation
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20.2 Temperature Compensated Refresh
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20.3 Partial Array Refresh
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20.4 Deep Power-Down Operation
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116
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
21 Configuration Registers
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21.1 Access Using CRE
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CLK
A[21:0]
(except A19)
OPCODE
ADDRESS
ADDRESS
t
AVH
AVH
t
AVS
Select Control Register
A191
CRE
t
AVS
t
t
VPH
ADV#
CE#
t
VP
t
CBPH
Initiate Control Register Access
t
CW
OE#
t
WP
Write Address Bus Value
to Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
DON’T CARE
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Figure 21.1 Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
117
A d v a n c e I n f o r m a t i o n
CLK
Latch Control Register Value
OPCODE
A[21:0]
ADDRESS
(except A19)
t
HD
t
Latch Control Register Address
SP
A192
CRE
ADDRESS
t
SP
t
t
HD
t
SP
ADV#
HD
3
t
CBPH
t
CSP
CE#
OE#
t
SP
t
WE#
HD
LB#/UB#
t
CW
WAIT
High-Z
High-Z
Data
Valid
DQ[15:0]
DON’T CARE
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Figure 21.2 Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation
21.2 Software Access
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118
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
READ
READ
WRIT1E
WRITE
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
CE#
OE#
WE#
LB#/UB#
CRVALUE
IN
DATA
XXXXh
XXXXh
RCR0:000h
BCR0:001h
DON'TCARE
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Figure 21.3 Load Configuration Register
READ
READ
WRITE 1
READ
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
CE#
NOTE 2
OE#
WE#
LB#/UB#
CRValue
Out
DATA
XXXXh
XXXXh
RCR0:000h
BCR0:001h
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Figure 21.4 Read Configuration Register
21.3 Bus Configuration Register
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March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
119
A d v a n c e I n f o r m a t i o n
Table 21.1 Bus Configuration Register Definition
A[21:20]A19 A[18:16] A15
A14 A13A12A11 A10
A9
A8
A7
A6
A5
A4
A3
3
A2A1A0
21–20
19
18–16
15
14
13 12 11
10
9
8
7
6
5
4
2
1
0
Register
Select
Operating
Mode
Latency
Counter
WAIT
Polarity
WAIT
Configuration (WC)
Clock
Output
Burst
Burst
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Configuration (CC) Impedance
Wrap (BW)*Length (BL)*
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
All must be set to "0"
BCR[13]BCR[12] BCR[11]
Latency Counter
Code 0–Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 1–Reserved
Code
Code
2
3
(Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
BCR[3]
0
Burst Wrap (Note 1)
Burst wraps within the burst length
Burst no wrap (default)
1
BCR[10]
0
WAIT Polarity
Active LOW
1
Active HIGH (default)
Output Impedance
BCR[5]
Full Drive (default)
1/4 Drive
0
1
BCR[8]
WAIT Configuration
Asserted during delay
BCR[6]
0
1
Clock Configuration
Not supported
Rising edge (default)
Asserted one data cycle before delay (default)
0
1
BCR[15]
Operation Mode
0
1
Synchronous burst access mode
Asynchronous access mode (default)
Burst Length (Note 1)
BCR[2] BCR[1]BCR[0]
0
0
0
1
0
1
1
1
1
0
1
1
4
8
words
words
BCR[19]
Register Select
16 words
Continuous burst (default)
0
1
Select RCR
Select BCR
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120
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
Table 21.2 Sequence and Burst Length
4-word
Burst
Address Length 8-word Burst Length
Starting
Burst Wrap
16-word Burst Length
Continuous Burst
BCR[3] Wrap (Decimal) Linear
Linear
Linear
Linear
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March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
121
A d v a n c e I n f o r m a t i o n
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DVVHUWHGꢀVWDWHꢃ
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data[1]
Data immediately valid (or invalid)
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Figure 21.5 Wait Configuration (BCR[8] = 0)
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
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Figure 21.6 Wait Configuration (BCR[8] = 1)
CLK
BCR[8]
= 0
WAIT
DATA VALID IN CURRENT CYCLE
BCR[8]
= 1
WAIT
DATA VALID IN NEXT CYCLE
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
1RWHꢀꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJꢔꢀ:DLWꢀDFWLYHꢀ/RZꢆ
Figure 21.7 Wait Configuration During Burst Operation
122
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
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Table 21.3 Variable Latency Configuration Codes
Max Input Clk Frequency (MHz)
Latency Configuration Code
ꢊꢀꢁꢐꢀFORFNVꢂ
70 ns/80 MHz
ꢉꢐꢀꢁꢈꢍꢃꢇꢉꢀQVꢂ
ꢍꢏꢀꢁꢈꢊꢃꢉꢀQVꢂ
70 ns/66 MHz
ꢓꢓꢀꢁꢊꢊꢃꢇꢀQVꢂ
ꢌꢌꢀꢁꢈꢉꢃꢊꢀQVꢂ
ꢐꢀꢁꢓꢀFORFNVꢂ²GHIDXOW
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&63
V
IH
CLK
V
IL
V
IH
A[21:0]
Valid Address
V
IL
V
IH
ADV#
A/DQ[15:0]
A/DQ[15:0]
V
IL
Code 2
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
(Default)
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Legend:
Don't care
Undefined
Figure 21.8 Latency Counter (Variable Initial Latency, No Refresh Collision)
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21.4 Refresh Configuration Register
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March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
123
A d v a n c e I n f o r m a t i o n
Table 21.4 Refresh Configuration Register Mapping
A[21:20]
A19
A[18:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
21–20
Reserved
19
18–8
Reserved
7
6
5
4
3
2
1
0
Read Configuration
Register
Register
Select
Page
TCR
DPD
Reserved
PAR
Must be set to "0"
All must be set to "0"
All must be set to "0"
RCR[19] Register Select
RCR[2] RCR[1] RCR[0] Refresh Coverage
0
1
Select RCR
Select BCR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
RCR[7]
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
0
1
Top 1/2 array
Top 1/4 array
Maximum Case Temp
RCR[6]
RCR[5]
Top 3/4 array
1
1
0
1
0
+85ºC (default)
+70ºC
0
0
1
RCR[4]
Deep Power-Down
DPD Enable
+45ºC
0
1
+15ºC
DPD Disable (default)
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Table 21.5 64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
)XOOꢀGLH
Address Space
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Size
Density
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124
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
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ꢎꢄꢅꢉꢅꢐ 7HPSHUDWXUHꢀ&RPSHQVDWHGꢀ5HIUHVKꢀꢂ5&5>ꢋꢁꢈ@ꢃꢁꢀ'HIDXOWꢀ ꢀꢕꢌꢈ&ꢀ
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ꢎꢓꢉꢀ&ꢄꢀꢎꢇꢏꢀ&ꢄꢀDQGꢀꢎꢍꢉꢀ&ꢂꢃꢀ7KHꢀVHWWLQJꢀVHOHFWHGꢀPXVWꢀEHꢀIRUꢀDꢀWHPSHUDWXUHꢀKLJKHUꢀWKDQꢀWKHꢀ
FDVHꢀWHPSHUDWXUHꢀRIꢀWKHꢀ&HOOXUODU5$0ꢀGHYLFHꢃꢀ,IꢀWKHꢀFDVHꢀWHPSHUDWXUHꢀLVꢀꢎꢉꢏꢀ&ꢄꢀWKHꢀV\VWHPꢀFDQꢀ
PLQLPL]HꢀVHOIꢀUHIUHVKꢀFXUUHQWꢀFRQVXPSWLRQꢀE\ꢀVHOHFWLQJꢀWKHꢀꢎꢇꢏꢀ&ꢀVHWWLQJꢃꢀ7KHꢀꢎꢈꢉꢀ&ꢀDQGꢀ
ꢎꢓꢉꢀ&ꢀVHWWLQJVꢀZRXOGꢀUHVXOWꢀLQꢀLQDGHTXDWHꢀUHIUHVKLQJꢀDQGꢀFDXVHꢀGDWDꢀFRUUXSWLRQꢃ
ꢎꢄꢅꢉꢅꢉ 3DJHꢀ0RGHꢀ2SHUDWLRQꢀꢂ5&5>ꢆ@ꢃꢁꢀ'HIDXOWꢀ ꢀ'LVDEOHG
7KHꢀSDJHꢀPRGHꢀRSHUDWLRQꢀELWꢀGHWHUPLQHVꢀZKHWKHUꢀSDJHꢀPRGHꢀLVꢀHQDEOHGꢀIRUꢀDV\QFKURQRXVꢀ5HDGꢀ
RSHUDWLRQVꢃꢀ,QꢀWKHꢀSRZHUꢅXSꢀGHIDXOWꢀVWDWHꢄꢀSDJHꢀPRGHꢀLVꢀGLVDEOHGꢃ
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
125
A d v a n c e I n f o r m a t i o n
22 Absolute Maximum Ratings
9ROWDJHꢀWRꢀ$Q\ꢀ%DOOꢀ([FHSWꢀ9&&ꢄꢀ9&&4ꢀ5HODWLYHꢀWRꢀ966 ꢀꢃꢀꢃ ꢅꢏꢃꢉꢏ9ꢀWRꢀꢁꢓꢃꢏ9ꢀRUꢀ9&&4ꢀꢎꢀꢏꢃꢐ9ꢄꢀZKLFKHYHUꢀLVꢀOHVVꢂ
9ROWDJHꢀRQꢀ9&&ꢀ6XSSO\ꢀ5HODWLYHꢀWRꢀ966 ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ ꢀꢅꢏꢃꢊ9ꢀWRꢀꢎꢊꢃꢓꢉ9
9ROWDJHꢀRQꢀ9&&4ꢀ6XSSO\ꢀ5HODWLYHꢀWRꢀ966 ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢅꢏꢃꢊ9ꢀWRꢀꢎꢓꢃꢏ9
6WRUDJHꢀ7HPSHUDWXUHꢀꢁSODVWLFꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ ꢅꢉꢉ&ꢀWRꢀꢎꢈꢉꢏ&
2SHUDWLQJꢀ7HPSHUDWXUHꢀꢁFDVHꢂ
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,QGXVWULDO ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ ꢅꢓꢏ&ꢀWRꢀꢎꢍꢉ&
6ROGHULQJꢀ7HPSHUDWXUHꢀDQGꢀ7LPH
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1RWHꢀꢀꢇꢊꢁ&ꢀH[FHHGVꢀWKHꢀ&HOOXODU5$0ꢀ:RUNJURXSꢀꢅꢆꢁꢀVSHFLILFDWLRQꢀRIꢀꢇꢈꢌ&ꢆ
6WUHVVHVꢀJUHDWHUꢀWKDQꢀWKRVHꢀOLVWHGꢀPD\ꢀFDXVHꢀSHUPDQHQWꢀGDPDJHꢀWRꢀWKHꢀGHYLFHꢃꢀ7KLVꢀLVꢀDꢀVWUHVVꢀ
UDWLQJꢀRQO\ꢄꢀDQGꢀIXQFWLRQDOꢀRSHUDWLRQꢀRIꢀWKHꢀGHYLFHꢀDWꢀWKHVHꢀRUꢀDQ\ꢀRWKHUꢀFRQGLWLRQVꢀDERYHꢀWKRVHꢀ
LQGLFDWHGꢀLQꢀWKHꢀRSHUDWLRQDOꢀVHFWLRQVꢀRIꢀWKLVꢀVSHFLILFDWLRQꢀLVꢀQRWꢀLPSOLHGꢃꢀ([SRVXUHꢀWRꢀDEVROXWHꢀPD[ꢅ
LPXPꢀUDWLQJꢀFRQGLWLRQVꢀIRUꢀH[WHQGHGꢀSHULRGVꢀPD\ꢀDIIHFWꢀUHOLDELOLW\ꢃ
126
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
23 DC Characteristics
Table 23.1 Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
ꢈꢃꢇꢏ
Max
ꢈꢃꢋꢉ
Units
9
Notes
6XSSO\ꢀ9ROWDJH
9&&
,ꢑ2ꢀ6XSSO\ꢀ9ROWDJH
,QSXWꢀ+LJKꢀ9ROWDJH
,QSXWꢀ/RZꢀ9ROWDJH
2XWSXWꢀ+LJKꢀ9ROWDJH
2XWSXWꢀ/RZꢀ9ROWDJH
,QSXWꢀ/HDNDJHꢀ&XUUHQW
9&&
9,+
9,/
4
:ꢆꢀꢈꢃꢍ9
ꢈꢃꢇꢏ
ꢐꢃꢐꢏ
9
ꢈꢃꢓ
9&&4ꢀꢎꢀꢏꢃꢊ
ꢏꢃꢓ
9
ꢊ
ꢐ
ꢓ
ꢓ
ꢅꢏꢃꢊꢏ
ꢏꢃꢍꢏꢀ9&&
9
,
2+ꢀ ꢀꢅꢏꢃꢊP$
92+
92/
4
9
,2/ꢀ ꢀꢎꢏꢃꢊP$
ꢏꢃꢊꢏꢀ9&&
4
9
9,1ꢀ ꢀꢏꢀWRꢀ9&&
4
,
ꢈ
$
/,
2(ꢔꢀ ꢀ9,+ꢀRUꢀ
&KLSꢀ'LVDEOHG
2XWSXWꢀ/HDNDJHꢀ&XUUHQW
,
ꢈ
$
/2
2SHUDWLQJꢀ&XUUHQW
ꢅꢇꢏ
$V\QFKURQRXVꢀ5DQGRPꢀ5HDG
$V\QFKURQRXVꢀ3DJHꢀ5HDG
9
,1ꢀ ꢀ9&&4ꢀRUꢀꢏ9ꢀ
&KLSꢀ(QDEOHGꢄꢀ
,287ꢀ ꢀꢏ
ꢊꢉ
ꢈꢉ
,&&ꢈ
P$
ꢉ
ꢉ
ꢅꢇꢏ
ꢍꢏꢀ0+]
ꢌꢌꢀ0+]
ꢍꢏꢀ0+]
ꢌꢌꢀ0+]
ꢍꢏꢀ0+]
ꢌꢌꢀ0+]
ꢐꢉ
ꢐꢏ
ꢈꢍ
ꢈꢉ
ꢐꢉ
ꢐꢏ
,QLWLDOꢀ$FFHVVꢄꢀ%XUVWꢀ5HDG
&RQWLQXRXVꢀ%XUVWꢀ5HDGꢀ
&RQWLQXRXVꢀ%XUVWꢀ:ULWH
9,1ꢀ ꢀ9&&4ꢀRUꢀꢏ9ꢀ
&KLSꢀ(QDEOHGꢄꢀ
,287ꢀ ꢀꢏ
,
&&ꢈ
P$
9,1ꢀ ꢀ9&&4ꢀRUꢀꢏ9ꢀ
,&&ꢊ
P$
$
ꢉ
ꢌ
&KLSꢀ(QDEOHGꢄꢀ,287ꢀ ꢀꢏ
9,1ꢀ ꢀ9&&4ꢀRUꢀꢏ9ꢀ
6WDQGE\ꢀ&XUUHQW
,
ꢌꢓꢀ0
ꢈꢊꢏ
6%
&(ꢔꢀ ꢀ9&&
4
1RWHVꢀ
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ꢈꢆ ,QSXWꢀVLJQDOVꢀPD\ꢀRYHUVKRRWꢀWRꢀ9 4ꢀꢉꢀꢅꢆꢁꢀ9ꢀIRUꢀSHULRGVꢀOHVVꢀWKDQꢀꢈꢀQVꢀGXULQJꢀWUDQVLWLRQVꢆ
&&
ꢊꢆ ,QSXWꢀVLJQDOVꢀPD\ꢀXQGHUVKRRWꢀWRꢀ9 ꢀꢇꢀꢅꢆꢁꢀ9ꢀIRUꢀSHULRGVꢀOHVVꢀWKDQꢀꢈꢀQVꢀGXULQJꢀWUDQVLWLRQVꢆ
66
ꢍꢆ %&5>ꢌꢔꢍ@ꢀ ꢀꢁꢁEꢆ
ꢌꢆ 7KLVꢀSDUDPHWHUꢀLVꢀVSHFLILHGꢀZLWKꢀWKHꢀRXWSXWVꢀGLVDEOHGꢀWRꢀDYRLGꢀH[WHUQDOꢀORDGLQJꢀHIIHFWVꢆꢀ7KHꢀXVHUꢀPXVWꢀDGGꢀWKHꢀFXUUHQWꢀUHTXLUHGꢀWRꢀGULYHꢀ
RXWSXWꢀFDSDFLWDQFHꢀH[SHFWHGꢀLQꢀWKHꢀDFWXDOꢀV\VWHPꢆꢀ
ꢐꢆ ,6%ꢀꢂ0$;ꢃꢀYDOXHVꢀPHDVXUHGꢀZLWKꢀ3$5ꢀVHWꢀWRꢀ)8//ꢀ$55$<ꢀDQGꢀ7&5ꢀVHWꢀWRꢀꢉꢎꢌꢀ&ꢆꢀ7RꢀDFKLHYHꢀ/RZꢀVWDQGE\ꢀFXUUHQWꢄꢀDOOꢀLQSXWVꢀPXVWꢀEHꢀGULYHQꢀ
WRꢀHLWKHUꢀ9 4ꢀRUꢀ9
ꢆ
&&
66
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
127
A d v a n c e I n f o r m a t i o n
Table 23.2 Maximum Standby Currents for Applying PAR and TCR Settings
TCR
PAR
+15°C (RCR[6:5] = 10b)
+45°C (RCR[6:5] = 01b)
+85°C (RCR[6:5] = 11b)
)XOOꢀ$UUD\
ꢈꢑꢊꢀ$UUD\
ꢈꢑꢓꢀ$UUD\
ꢈꢑꢍꢀ$UUD\
ꢏꢀ$UUD\
ꢇꢏ
ꢌꢉ
ꢌꢏ
ꢉꢇ
ꢉꢏ
ꢈꢊꢏ
ꢈꢈꢉ
ꢈꢈꢏ
ꢈꢏꢉ
ꢇꢏ
ꢍꢉ
ꢍꢏ
ꢇꢉ
ꢇꢏ
ꢉꢉ
1RWHVꢀ
ꢅꢆ )RUꢀ5&5>ꢐꢔꢌ@ꢀ ꢀꢁꢁEꢀꢂGHIDXOWꢃꢄꢀUHIHUꢀWRꢀ)LJXUHꢀꢈꢊꢆꢅꢀIRUꢀW\SLFDOꢀYDOXHVꢆ
ꢈꢆ ,QꢀRUGHUꢀWRꢀDFKLHYHꢀORZꢀVWDQGE\ꢀFXUUHQWꢄꢀDOOꢀLQSXWVꢀPXVWꢀEHꢀGULYHQꢀWRꢀHLWKHUꢀ9
SRZHUꢇXSꢄꢀRUꢀDIWHUꢀFKDQJHVꢀWRꢀWKHꢀ3$5ꢀDUUD\ꢀSDUWLWLRQꢆ
ꢀRUꢀ9 ꢆꢀ,6%ꢀPLJKWꢀEHꢀVOLJKWO\ꢀKLJKHUꢀIRUꢀXSꢀWRꢀꢌꢁꢁꢀPVꢀDIWHUꢀ
&&4
66
ꢊꢆ 9DOXHVꢀRIꢀ7&5ꢀIRUꢀꢎꢌꢀDUHꢀꢅꢁꢁꢖꢀWHVWHGꢆꢀ9DOXHVꢀRIꢀ7&5ꢀIRUꢀꢅꢌꢀDQGꢀꢍꢌꢀDUHꢀVDPSOHGꢀRQO\ꢆ
70
60
50
40
30
20
10
0
PAR = Full Array
PAR = 1/2 of Array
PAR = 1/4 of Array
PAR = 1/8 of Array
PAR = None of Array
-30
-20
-10
0
10
20
Temperature (°C)
1RWHꢀꢀ7\SLFDOꢀ,6%ꢀFXUUHQWVꢀIRUꢀHDFKꢀ3$5ꢀVHWWLQJꢀZLWKꢀWKHꢀDSSURSULDWHꢀ7&5ꢀVHOHFWHGꢄꢀRUꢀWHPSHUDWXUHꢀVHQVRUꢀHQDEOHGꢆ
30
40
50
60
70
80
90
Figure 23.1 Typical Refresh Current vs. Temperature (I
Table 23.3 Deep Power-Down Specifications
)
TCR
Description
Conditions
Symbol
Typ
ꢈꢏ
Units
'HHSꢀ3RZHUꢅGRZQ
9,1ꢀ ꢀ9&&4ꢀRUꢀꢏ9ꢕꢀꢎꢊꢉ&
,
$
==
128
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
24 AC Characteristics
V
CC
Q
V
Q/2
VCC/2
Note 2
CC
Input
(Note 1)
Output
Test Points
(Note 3)
V
SS
1RWHVꢀ
ꢅꢆ $&ꢀWHVWꢀLQSXWVꢀDUHꢀGULYHQꢀDWꢀ9 4ꢀIRUꢀDꢀORJLFꢀꢅꢀDQGꢀ9 ꢀIRUꢀDꢀORJLFꢀꢁꢆꢀ,QSXWꢀULVHꢀDQGꢀIDOOꢀWLPHVꢀꢂꢅꢁꢖꢀWRꢀꢏꢁꢖꢃꢀꢕꢀꢅꢆꢐQVꢆ
&&
66
ꢈꢆ ,QSXWꢀWLPLQJꢀEHJLQVꢀDWꢀ9 ꢒꢈꢆꢀ'XHꢀWRꢀWKHꢀSRVVLELOLW\ꢀRIꢀDꢀGLIIHUHQFHꢀEHWZHHQꢀ9 ꢀDQGꢀ9 ꢄꢀWKHꢀLQSXWꢀWHVWꢀSRLQWꢀPD\ꢀQRWꢀEHꢀVKRZQꢀWRꢀVFDOHꢆ
&&
&&
&&4
ꢊꢆ 2XWSXWꢀWLPLQJꢀHQGVꢀDWꢀ9 4ꢒꢈꢆ
&&
Figure 24.1 AC Input/Output Reference Waveform
Table 24.1 Capacitance
Description
,QSXWꢀ&DSDFLWDQFH
Conditions
Symbol
Min
ꢊꢃꢏ
ꢐꢃꢉ
Max
ꢌ
Units
S)
Notes
&
&
ꢈ
ꢈ
,1
,2
7&ꢀ ꢀꢎꢊꢉ&ꢕꢀIꢀ ꢀꢈꢀ0+]ꢕꢀ9,1ꢀ ꢀꢏ9
,QSXWꢑ2XWSXWꢀ&DSDFLWDQFHꢀꢁ'4ꢂ
ꢌ
S)
1RWHVꢀ
ꢅꢆ 7KHVHꢀSDUDPHWHUVꢀDUHꢀYHULILHGꢀLQꢀGHYLFHꢀFKDUDFWHUL]DWLRQꢀDQGꢀDUHꢀQRWꢀꢅꢁꢁꢖꢀWHVWHGꢆ
V
Q
CC
R1
Test Point
DUT
30pF
R2
1RWHꢀꢀ$OOꢀWHVWVꢀDUHꢀSHUIRUPHGꢀZLWKꢀWKHꢀRXWSXWVꢀFRQILJXUHGꢀIRUꢀIXOOꢀGULYHꢀVWUHQJWKꢀꢂ%&5>ꢌ@ꢀ ꢀꢁꢃꢆ
Figure 24.2 Output Load Circuit
Table 24.2 Output Load Circuit
V
Q
R1/R2
ꢊꢃꢇꢀ.
ꢐꢃꢇꢀ.
ꢓꢃꢉꢀ.
CC
ꢈꢃꢍꢀ9
ꢊꢃꢉꢀ9
ꢐꢃꢏꢀ9
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
129
A d v a n c e I n f o r m a t i o n
Table 24.3 Asynchronous Read Cycle Timing Requirements
70ns
Units
Notes
Parameter
$GGUHVVꢀ$FFHVVꢀ7LPH
Symbol
W$$
Min
Max
ꢇꢏ
QV
QV
QV
QV
QV
QV
QV
QV
V
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
$'9ꢔꢀ$FFHVVꢀ7LPH
W$$'9
W$3$
ꢇꢏ
3DJHꢀ$FFHVVꢀ7LPH
ꢊꢏ
$GGUHVVꢀ+ROGꢀIURPꢀ$'9ꢔꢀ+LJK
$GGUHVVꢀ6HWXSꢀWRꢀ$'9ꢔꢀ+LJK
/%ꢔꢑ8%ꢔꢀ$FFHVVꢀ7LPH
W$9+
W$96
W%$
ꢉ
ꢈꢏ
ꢇꢏ
ꢍ
/%ꢔꢑ8%ꢔꢀ'LVDEOHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
/%ꢔꢑ8%ꢔꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
0D[LPXPꢀ&(ꢔꢀ3XOVHꢀ:LGWK
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLG
W%+=
ꢀ
ꢓ
ꢐ
W%/=
ꢈꢏ
ꢈ
W&(0
W&(:
W&2
ꢍ
ꢇꢃꢉ
ꢇꢏ
&KLSꢀ6HOHFWꢀ$FFHVVꢀ7LPH
&(ꢔꢀ/RZꢀWRꢀ$'9ꢔꢀ+LJK
W&96
W+=
ꢈꢏ
ꢈꢏ
ꢉ
&KLSꢀ'LVDEOHꢀWRꢀ'4ꢀDQGꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXW
&KLSꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
2XWSXWꢀ(QDEOHꢀWRꢀ9DOLGꢀ2XWSXW
2XWSXWꢀ+ROGꢀIURPꢀ$GGUHVVꢀ&KDQJH
2XWSXWꢀ'LVDEOHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
2XWSXWꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
3DJHꢀ&\FOHꢀ7LPH
ꢍ
ꢊꢏ
ꢍ
ꢓ
ꢐ
W/=
W2(
W2+
W2+=
W2/=
W3&
ꢓ
ꢐ
ꢉ
ꢊꢏ
ꢇꢏ
ꢈꢏ
ꢈꢏ
5HDGꢀ&\FOHꢀ7LPH
W5&
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ/RZ
W93
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ+LJK
W93+
1RWHVꢀ
ꢅꢆ $OOꢀWHVWVꢀDUHꢀSHUIRUPHGꢀZLWKꢀWKHꢀRXWSXWVꢀFRQILJXUHGꢀIRUꢀIXOOꢀGULYHꢀVWUHQJWKꢀꢂ%&5>ꢌ@ꢀ ꢀꢁꢃꢆ
ꢈꢆ +LJKꢇ=ꢀWRꢀ/RZꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢈꢍꢆꢈꢆꢀ7KHꢀ/RZꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢇP9ꢀWUDQVLWLRQꢀDZD\ꢀIURPꢀWKHꢀ
+LJKꢇ=ꢀꢂ9 4ꢒꢈꢃꢀOHYHOꢀWRZDUGꢀHLWKHUꢀ9 ꢀRUꢀ9
ꢆ
2/
&&
2+
ꢊꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢈꢍꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢇP9ꢀWUDQVLWLRQꢀIURPꢀHLWKHUꢀ9
ꢀ
2+
RUꢀ9 ꢀWRZDUGꢀ9 4ꢒꢈꢆ
2/
&&
130
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
Table 24.4 Burst Read Cycle Timing Requirements
70ns/80 MHz
70ns/66 MHz
Parameter
%XUVWꢀWRꢀ5HDGꢀ$FFHVVꢀ7LPHꢀꢁ9DULDEOHꢀ/DWHQF\ꢂ
&/.ꢀWRꢀ2XWSXWꢀ'HOD\
Symbol
W$%$
W$&/.
W%2(
W&%3+
W&(:
W&/.
Min
Max
ꢓꢌꢃꢉ
ꢋ
Min
Max
ꢉꢌ
Units
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
V
Notes
ꢈꢈ
%XUVWꢀ2(ꢔꢀ/RZꢀWRꢀ2XWSXWꢀ'HOD\
&(ꢔꢀ+LJKꢀEHWZHHQꢀ6XEVHTXHQWꢀ0L[HGꢅ0RGHꢀ2SHUDWLRQV
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLG
ꢊꢏ
ꢊꢏ
ꢉ
ꢀꢈ
ꢉ
ꢈ
ꢇꢃꢉ
ꢊꢏ
ꢊꢏ
ꢇꢃꢉ
ꢊꢏ
ꢊꢏ
&/.ꢀ3HULRG
ꢈꢊꢃꢉ
ꢓꢃꢉ
ꢊ
ꢈꢉ
ꢉ
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ$FWLYHꢀ&/.ꢀ(GJH
+ROGꢀ7LPHꢀIURPꢀ$FWLYHꢀ&/.ꢀ(GJH
&KLSꢀ'LVDEOHꢀWRꢀ'4ꢀDQGꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXW
&/.ꢀ5LVHꢀRUꢀ)DOOꢀ7LPH
W&63
W+'
ꢊ
W+=
ꢍ
ꢈꢃꢍ
ꢋ
ꢍ
ꢊꢃꢏ
ꢈꢈ
ꢍ
ꢊ
W.+./
W.+7/
W.+=
W./=
&/.ꢀWRꢀ:DLWꢀ9DOLG
&/.ꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
ꢐ
ꢊ
ꢊ
ꢓ
ꢍ
ꢐ
ꢊ
ꢊ
ꢉ
&/.ꢀWRꢀ/RZꢅ=ꢀ2XWSXW
ꢉ
ꢉ
2XWSXWꢀ+ROGꢀIURPꢀ&/.
W.2+
W.3
&/.ꢀ+LJKꢀRUꢀ/RZꢀ7LPH
2XWSXWꢀ'LVDEOHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
2XWSXWꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
6HWXSꢀ7LPHꢀWRꢀ$FWLYHꢀ&/.ꢀ(GJH
0D[LPXPꢀ&(ꢔꢀ3XOVHꢀ:LGWK
W2+=
W2/=
W63
ꢍ
ꢍ
ꢍ
ꢍ
ꢊ
ꢐ
ꢉ
ꢐ
ꢉ
ꢐ
W&%3+
ꢊ
1RWHVꢀ
ꢅꢆ $OOꢀWHVWVꢀDUHꢀSHUIRUPHGꢀZLWKꢀWKHꢀRXWSXWVꢀFRQILJXUHGꢀIRUꢀIXOOꢀGULYHꢀVWUHQJWKꢀꢂ%&5>ꢌ@ꢀ ꢀꢁꢃꢆ
ꢈꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢈꢍꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢇP9ꢀWUDQVLWLRQꢀIURPꢀHLWKHUꢀ9
ꢀ
2+
RUꢀ9 ꢀWRZDUGꢀ9 4ꢒꢈꢆ
2/
&&
ꢊꢆ +LJKꢇ=ꢀWRꢀ/RZꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢈꢍꢆꢈꢆꢀ7KHꢀ/RZꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢇP9ꢀWUDQVLWLRQꢀDZD\ꢀIURPꢀWKHꢀ
+LJKꢇ=ꢀꢂ9 4ꢒꢈꢃꢀOHYHOꢀWRZDUGꢀHLWKHUꢀ9 ꢀRUꢀ9 ꢆ
&&
2+
2/
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
131
A d v a n c e I n f o r m a t i o n
Table 24.5 Asynchronous Write Cycle Timing Requirements
70 ns
Parameter
$GGUHVVꢀDQGꢀ$'9ꢔꢀ/RZꢀ6HWXSꢀ7LPH
$GGUHVVꢀ+ROGꢀIURPꢀ$'9ꢔꢀ*RLQJꢀ+LJK
$GGUHVVꢀ6HWXSꢀWRꢀ$'9ꢔꢀ*RLQJꢀ+LJK
$GGUHVVꢀ9DOLGꢀWRꢀ(QGꢀRIꢀ:ULWH
/%ꢔꢑ8%ꢔꢀ6HOHFWꢀWRꢀ(QGꢀRIꢀ:ULWH
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLG
Symbol
W$6
Min
ꢏ
Max
ꢇꢃꢉ
ꢍ
Units
QV
Notes
W$9+
W$96
W$:
ꢉ
QV
ꢈꢏ
ꢇꢏ
ꢇꢏ
ꢈ
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
W%:
W&(:
W&.$
W&96
W&:
W'+
$V\QFꢀ$GGUHVVꢅWRꢅ%XUVWꢀ7UDQVLWLRQꢀ7LPH
&(ꢔꢀ/RZꢀWRꢀ$'9ꢔꢀ+LJK
ꢇꢏ
ꢈꢏ
ꢇꢏ
ꢏ
&KLSꢀ(QDEOHꢀWRꢀ(QGꢀRIꢀ:ULWH
'DWDꢀ+ROGꢀIURPꢀ:ULWHꢀ7LPH
'DWDꢀ:ULWHꢀ6HWXSꢀ7LPH
W':
W+=
ꢊꢐ
&KLSꢀ'LVDEOHꢀWRꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXW
&KLSꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
(QGꢀ:ULWHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
$'9ꢔꢀ3XOVHꢀ:LGWK
W/=
ꢈꢏ
ꢉ
ꢐ
ꢐ
W2:
W93
W93+
W96
ꢈꢏ
ꢈꢏ
ꢇꢏ
ꢇꢏ
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ+LJK
$'9ꢔꢀ6HWXSꢀWRꢀ(QGꢀRIꢀ:ULWH
:ULWHꢀ&\FOHꢀ7LPH
W:&
W:+=
W:3
:ULWHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
:ULWHꢀ3XOVHꢀ:LGWK
ꢍ
ꢊ
ꢓꢌ
ꢈꢏ
ꢏ
:ULWHꢀ3XOVHꢀ:LGWKꢀ+LJK
W:3+
W:5
W&3+
:ULWHꢀ5HFRYHU\ꢀ7LPH
&(ꢔꢀ+LJKꢀEHWZHHQꢀVXEVHTXHQWꢀDV\QFKURQRXVꢀRSHUDWLRQV
ꢉ
1RWHVꢀ
ꢅꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢈꢍꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢇP9ꢀWUDQVLWLRQꢀIURPꢀHLWKHUꢀ9
ꢀ
2+
RUꢀ9 ꢀWRZDUGꢀ9 4ꢒꢈꢆ
2/
&&
ꢈꢆ +LJKꢇ=ꢀWRꢀ/RZꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢈꢍꢆꢈꢆꢀ7KHꢀ/RZꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢇP9ꢀWUDQVLWLRQꢀDZD\ꢀIURPꢀWKHꢀ
+LJKꢇ=ꢀꢂ9 4ꢒꢈꢃꢀOHYHOꢀWRZDUGꢀHLWKHUꢀ9 ꢀRUꢀ9
ꢆ
2/
&&
2+
132
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
Table 24.6 Burst Write Cycle Timing Requirements
70ns/80 MHz
70ns/66 MHz
Parameter
&(ꢔꢀ+LJKꢀEHWZHHQꢀ6XEVHTXHQWꢀ0L[HGꢅ0RGHꢀ2SHUDWLRQV
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLG
Symbol
W&%3+
W&(:
W&/.
W&63
W+'
Min
ꢉ
Max
Min
ꢉ
Max
Units
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
V
Notes
ꢈ
ꢇꢃꢉ
ꢊꢏ
ꢊꢏ
ꢈ
ꢇꢃꢉ
ꢊꢏ
ꢊꢏ
&ORFNꢀ3HULRG
ꢈꢊꢃꢉ
ꢓꢃꢉ
ꢊ
ꢈꢉ
ꢉ
&(ꢔꢀ6HWXSꢀWRꢀ&/.ꢀ$FWLYHꢀ(GJH
+ROGꢀ7LPHꢀIURPꢀ$FWLYHꢀ&/.ꢀ(GJH
&KLSꢀ'LVDEOHꢀWRꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXW
&/.ꢀ5LVHꢀRUꢀ)DOOꢀ7LPH
ꢊ
W+=
ꢍ
ꢈꢃꢍ
ꢋ
ꢍ
W.+./
W.+7/
W.3
ꢊꢃꢏ
ꢈꢈ
&ORFNꢀWRꢀ:DLWꢀ9DOLG
&/.ꢀ+LJKꢀRUꢀ/RZꢀ7LPH
ꢓ
ꢐ
ꢉ
ꢐ
6HWXSꢀ7LPHꢀWRꢀ$FWLYDWHꢀ&/.ꢀ(GJH
0LQLPXPꢀ&(ꢔꢀ3XOVHꢀ:LGWK
W63
W&(0
ꢍ
ꢍ
1RWHVꢀ
ꢅꢆ :KHQꢀFRQILJXUHGꢀIRUꢀV\QFKURQRXVꢀPRGHꢀꢂ%&5>ꢅꢌ@ꢀ ꢀꢁꢃꢄꢀDꢀUHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀLVꢀ
&(0
VDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀFRQGLWLRQVꢔꢀDꢃꢀFORFNHGꢀ&(-ꢀ+,*+ꢄꢀRUꢀEꢃꢀ&(-ꢀ+,*+ꢀIRUꢀJUHDWHUꢀWKDQꢀꢅꢌꢀQVꢆ
ꢈꢆ &ORFNꢀUDWHVꢀEHORZꢀꢌꢁꢀ0+]ꢀꢂW
ꢀ!ꢀꢈꢁꢀQVꢃꢀDUHꢀDOORZHGꢀDVꢀORQJꢀDVꢀW
ꢀVSHFLILFDWLRQVꢀDUHꢀPHWꢆ
&/.
&63
24.1 Timing Diagrams
V
(MIN)
CC
Device ready for
normal operation
V
, V Q = 1.7V
CC CC
t
PU
Figure 24.3 Initialization Period
Table 24.7 Initialization Timing Parameters
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
,QLWLDOL]DWLRQꢀ3HULRGꢀꢁUHTXLUHGꢀEHIRUHꢀQRUPDOꢀRSHUDWLRQVꢂ
W38
ꢈꢉꢏ
ꢈꢉꢏ
V
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
133
A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
VALID ADDRESS
A[22:0]
t
AA
V
V
IH
IL
ADV#
CE#
t
t
CBPH
HZ
V
V
IH
IL
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 24.4 Asynchronous Read
134
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AA
t
t
AVH
AVS
t
VPH
V
V
IH
IL
ADV#
t
AADV
t
VP
t
t
CVS
t
CBPH
HZ
V
V
IH
IL
CE#
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 24.5 Asynchronous Read Using ADV#
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
135
A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
A[22:0]
A[3:0]
VALID ADDRESS
V
V
IH
IL
VALID
VALID
VALID
ADDRESS
VALID ADDRESS
ADDRESS
ADDRESS
t
t
PC
AA
V
V
IH
IL
ADV#
t
t
CEM
CBPH
t
t
t
CBPH
CO
HZ
V
V
IH
IL
CE#
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
t
APA
BLZ
t
t
OH
LZ
V
V
OH
OL
High-Z
t
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 24.6 Page Mode Read
136
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
KHKL
t
t
SP
HD
V
V
IH
IL
A[22:0]
ADV#
VALID ADDRESS
t
t
SP
HD
V
V
IH
IL
t
HD
t
t
HZ
t
ABA
CSP
V
V
IH
IL
CE#
OE#
t
t
OHZ
BOE
V
V
IH
IL
t
OLZ
t
t
SP
SP
HD
V
V
IH
IL
WE#
t
t
HD
V
V
IH
IL
LB#/UB#
t
CEW
t
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
t
KOH
ACLK
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
1RWHꢀꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ&ORFNꢀ
UDWHVꢀEHORZꢀꢌꢁ0+]ꢀꢂW
ꢀ!ꢀꢈꢁQVꢃꢀDUHꢀDOORZHGꢀDVꢀORQJꢀDVꢀW
ꢀVSHFLILFDWLRQVꢀDUHꢀPHWꢆ
&/.
&63
Figure 24.7 Single-Access Burst Read Operation—Variable Latency
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
137
A d v a n c e I n f o r m a t i o n
t
CLK
t
t
t
KP
KHKL
KP
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
t
HD
CSP
ABA
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
1RWHꢀꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ&ORFNꢀ
UDWHVꢀEHORZꢀꢌꢁꢀ0+]ꢀꢂW
ꢀ!ꢀꢈꢁꢀQVꢃꢀDUHꢀDOORZHGꢀDVꢀORQJꢀDVꢀW
ꢀVSHFLILFDWLRQVꢀDUHꢀPHWꢆ
&/.
&63
Figure 24.8 Four-word Burst Read Operation—Variable Latency
138
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
HD
CSP
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
t
t
t
KHTL
KHTL
KHTL
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
High-Z
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
1RWHꢀꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
Figure 24.9 Four-word Burst Read Operation (with LB#/UB#)
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
139
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
HD
SP
V
V
IH
IL
ADV#
t
CBPH
t
t
t
CSP
HZ
V
V
IH
IL
CE#
OE#
t
OHZ
OHZ
(Note 2)
V
V
IH
IL
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
BOE
t
OLZ
High-Z
V
V
High-Z
IH
IL
WAIT
t
KOH
t
BOE
t
ACLK
t
OLZ
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ 2(-ꢀFDQꢀVWD\ꢀ/RZꢀGXULQJꢀEXUVWꢀVXVSHQGꢆꢀ,Iꢀ2(-ꢀLVꢀ/RZꢄꢀ'4>ꢅꢌꢔꢁ@ꢀFRQWLQXHVꢀWRꢀRXWSXWꢀYDOLGꢀGDWDꢆ
Figure 24.10 Refresh Collision During Write Operation
140
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
t
CLK
V
V
IH
IL
A[22:0]
ADV#
V
V
IH
IL
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
OE#
WE#
V
V
IH
IL
V
V
IH
IL
t
t
KHTL
KHTL
V
V
OH
OL
(Note 2)
WAIT
t
t
KOH
ACLK
V
V
OH
OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :DLWꢀDVVHUWVꢀ/&ꢀꢉꢀꢅꢀRUꢀꢈ/&ꢀꢉꢀꢅꢀF\FOHVꢀIRUꢀYDULDEOHꢀODWHQF\ꢀꢂGHSHQGLQJꢀXSRQꢀUHIUHVKꢀVWDWXVꢃꢆ
Figure 24.11 Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
141
A d v a n c e I n f o r m a t i o n
t
AA
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 24.12 CE#-Controlled Asynchronous Write
142
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 24.13 LB#/UB#-Controlled Asynchronous Write
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
143
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
AS
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 24.14 WE#-Controlled Asynchronous Write
144
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
t
AVH
AVS
t
VS
t
t
VP
VPH
t
AS
V
V
IH
IL
ADV#
t
AS
t
AW
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WPH
WP
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 24.15 Asynchronous Write Using ADV#
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
145
A d v a n c e I n f o r m a t i o n
t
KHKL
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
t
t
SP
HD
V
V
IH
IL
t
SP
t
HD
V
V
IH
IL
LB#/UB#
t
t
CSP
t
HD
CBPH
V
V
IH
IL
CE#
OE#
V
V
IH
IL
t
t
SP
HD
V
V
IH
IL
WE#
t
HZ
t
t
CEW
KHTL
High-Z
V
V
(Note 2)
IH
IL
High-Z
WAIT
t
t
HD
SP
V
V
OH
OL
DQ[15:0]
D[1]
D[2]
D[3]
D[0]
Legend:
READ Burst Identified
(WE# = LOW)
Don't Care
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢓꢀEXUVWꢀOHQJWKꢀIRXUꢓꢀEXUVWꢀZUDSꢀ
HQDEOHGꢆ
Figure 24.16 Burst Write Operation
146
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
t
CLK
V
V
IH
IL
A[22:0]
ADV#
V
V
IH
IL
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
V
V
IH
IL
WE#
V
V
IH
IL
OE#
t
t
KHTL
KHTL
(Note 2)
V
V
OH
OL
WAIT
t
t
HD
SP
V
V
OH
OL
Valid Input
D[n+3]
Valid Input
D[n+2]
Valid Input Valid Input
DQ[15:0]
D[n]
D[n+1]
Legend:
Don't Care
END OF ROW
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :DLWꢀDVVHUWVꢀ/&ꢀꢉꢀꢅꢀRUꢀꢈ/&ꢀꢉꢀꢅꢀF\FOHVꢀIRUꢀYDULDEOHꢀODWHQF\ꢀꢂGHSHQGLQJꢀXSRQꢀUHIUHVKꢀVWDWXVꢃꢆ
Figure 24.17 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
147
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
t
HD
SP
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
SP
t
t
HD
SP
HD
V
V
IH
IL
ADV#
t
t
HD
SP
V
V
IH
IL
LB#/UB#
CE#
t
t
t
HD
CSP
CBPH
V
V
IH
IL
(Note 2)
t
CSP
t
OHZ
V
V
IH
IL
OE#
t
SP
t
t
HD
t
SP
HD
V
V
IH
IL
WE#
t
BOE
V
V
High-Z
High-Z
OH
OL
WAIT
t
t
KOH
t
t
HD
ACLK
SP
V
V
V
High-Z
IH
IL
High-Z
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
V
Legend:
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ 7RꢀDOORZꢀVHOIꢇUHIUHVKꢀRSHUDWLRQVꢀWRꢀRFFXUꢀEHWZHHQꢀWUDQVDFWLRQVꢄꢀ&(-ꢀPXVWꢀUHPDLQꢀ+LJKꢀIRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW
LQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀEHWZHHQꢀEXUVWꢀ5HDGꢀDQGꢀEXUVWꢀ:ULWHꢀRSHUDWLRQVꢆ
ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀ
&%3+
Figure 24.18 Burst Write Followed by Burst Read
148
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
WR
AVS
AVH
AW
t
t
HD
t
SP
VPH
V
V
IH
IL
ADV#
t
t
t
VP
VS
t
t
t
BW
SP
HD
CVS
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CBPH
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
t
t
HD
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
WHZ
t
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
t
t
DH
DW
KOH
Legend:
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ,Iꢀ&(-ꢀJRHVꢀ+LJKꢄꢀLWꢀPXVWꢀUHPDLQꢀ+LJKꢀ
IRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW
ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀLQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆ
&%3+
Figure 24.19 Asynchronous Write Followed by Burst Read
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
149
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
WR
AW
t
t
HD
SP
V
V
IH
IL
ADV#
t
t
SP
t
BW
HD
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CSP
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
t
t
HD
WP
WPH
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
t
WHZ
t
t
KOH
DW
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
DH
Legend:
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ,Iꢀ&(-ꢀJRHVꢀ+LJKꢄꢀLWꢀPXVWꢀUHPDLQꢀ+LJKꢀ
IRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀLQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆ
&%3+
Figure 24.20 Asynchronous Write (ADV# Low) Followed By Burst Read
150
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
WC
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AW
SP
t
WR
t
HD
V
V
IH
IL
ADV#
t
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
IH
IL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ,Iꢀ&(-ꢀJRHVꢀ+LJKꢄꢀLWꢀPXVWꢀUHPDLQꢀ+LJKꢀ
IRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀLQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆ
&%3+
Figure 24.21 Burst Read Followed by Asynchronous Write (WE#-Controlled)
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
151
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
HD
SP
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AVS
AVH
t
t
t
VPH
VS
SP
t
t
HD
VP
V
V
IH
IL
ADV#
t
AW
t
t
AS
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
OH
OL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ,Iꢀ&(-ꢀJRHVꢀ+LJKꢄꢀLWꢀPXVWꢀUHPDLQꢀ+LJKꢀ
IRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀLQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆ
&%3+
Figure 24.22 Burst Read Followed by Asynchronous Write Using ADV#
152
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Valid
Address
A[22:0]
ADV#
Address
t
t
t
AW
WR
AA
V
V
IH
IL
t
BHZ
t
t
BW
BLZ
V
V
IH
IL
LB#/UB#
CE#
t
t
CEM
t
CBPH
t
HZ
CW
V
V
IH
IL
(Note)
t
LZ
t
t
OHZ
OE
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
V
V
IH
IL
WE#
t
t
HZ
HZ
V
V
OH
OL
WAIT
t
WHZ
t
OLZ
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
1RWHꢀꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀZKHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀRSHUDWLRQVꢆꢀ,Iꢀ&(-ꢀJRHVꢀ+LJKꢄꢀLWꢀPXVWꢀUHPDLQꢀ+LJKꢀ
IRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀLQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆ
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Figure 24.23 Asynchronous Write Followed by Asynchronous Read—ADV# Low
March 9, 2005 CellRam_03_A0
64Mb CellularRAM Type 2
153
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
t
AA
AVS
AVH
AW
WR
t
t
t
VPH VP
VS
V
V
IH
IL
ADV#
t
t
t
BHZ
t
BW
BLZ
CVS
V
V
IH
IL
LB#/UB#
t
t
t
CBPH
CEM
t
HZ
CW
V
V
IH
IL
CE#
OE#
(Note)
t
t
LZ
AS
t
OHZ
V
V
IH
IL
t
WC
t
t
WP
t
AS
WPH
t
OLZ
V
V
IH
IL
WE#
V
V
OH
OL
WAIT
t
WHZ
t
OE
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
1RWHꢀꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀZKHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀRSHUDWLRQVꢆꢀ,Iꢀ&(-ꢀJRHVꢀ+LJKꢄꢀLWꢀPXVWꢀUHPDLQꢀ+LJKꢀ
IRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW
ꢃꢀWRꢀVFKHGXOHꢀWKHꢀDSSURSULDWHꢀLQWHUQDOꢀUHIUHVKꢀRSHUDWLRQꢆ
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Figure 24.24 Asynchronous Write Followed by Asynchronous Read
154
64Mb CellularRAM Type 2
CellRam_03_A0 March 9, 2005
1.8V 128Mb CellularRAM Type 2
(8M x 16 bit)
Burst CellularRAM
ADVANCE
INFORMATION
Features
²
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General Description
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FUHDVHVꢀUHDGꢑ:ULWHꢀEDQGZLGWKꢀFRPSDUHGꢀZLWKꢀRWKHUꢀORZꢅSRZHUꢀ65$0ꢀRUꢀ3VHXGRꢀ65$0ꢀRIIHULQJVꢃ
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WHUꢀꢁ','5ꢂꢃ
Publication Number cellram_04 Revision A Amendment 0 Issue Date May 16, 2005
A d v a n c e I n f o r m a t i o n
25 Functional Block Diagram
A[22:0]
Address Decode
Logic
Input/
Output
MUX
and
Buffers
8,192K
x 16
DRAM
Memory
Array
DQ[7:0]
DQ[15:8]
Refresh Configuration
Register (RCR)
Device ID Register
(DIDR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
ADV#
CRE
Control
Logic
WAIT
LB#
UB#
1RWHꢀꢁꢀ)XQFWLRQDOꢀEORFNꢀGLDJUDPVꢀLOOXVWUDWHꢀVLPSOLILHGꢀGHYLFHꢀRSHUDWLRQꢆꢀ6HHꢀ7DEOHꢀꢈꢌꢆꢅꢄꢀ³6LJQDOꢀ'HVFULSWLRQVꢄ´ꢀRQꢀSDJHꢀꢅꢌꢋꢄꢀ
7DEOHꢀꢈꢌꢆꢈꢄꢀ³%XVꢀ2SHUDWLRQVꢀ±ꢀ$V\QFKURQRXVꢀ0RGHꢄ´ꢀRQꢀSDJHꢀꢅꢌꢎꢄꢀ7DEOHꢀꢈꢌꢆꢊꢄꢀ³%XVꢀ2SHUDWLRQVꢀ±ꢀ%XUVWꢀ0RGHꢄ´ꢀRQꢀSDJHꢀꢅꢌꢎꢄꢀ
DQGꢀWLPLQJꢀGLDJUDPVꢀIRUꢀGHWDLOHGꢀLQIRUPDWLRQ
Figure 25.1 Functional Block Diagram
156
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
Table 25.1 Signal Descriptions
Symbol
Type
Description
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May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
157
A d v a n c e I n f o r m a t i o n
Table 25.2 Bus Operations – Asynchronous Mode
Clk
(Note 1)
LB#/
UB#
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cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
26 Functional Description
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27 Bus Operating Modes
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May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
159
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OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
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tRC = Read Cycle Time
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Figure 27.1 Read Operation (ADV# Low)
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WE#
ADDRESS
Address Valid
Data Valid
DATA
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Figure 27.2 Write Operation (ADV# Low)
27.2 Page Mode Read Operation
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160
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cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
< tCEM
CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1] ADD[2] ADD[3]
tAA
tAPA
tAPA
tAPA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
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Figure 27.3 Page Mode Read Operation (ADV# Low)
27.3 Burst Mode Operation
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May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
161
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Latency Code 2 (3 clocks)
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WAIT
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LB#/UB#
D[0]
D[1]
D[2]
D[3]
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(WE# = HIGH)
Legend:
Don't care
Undefined
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CLK
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Latency Code 2 (3 clocks)
CE#
OE#
WE#
WAIT
DQ[15:0]
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D[2]
D[3]
Write Burst Identified (WE# = Low)
Legend:
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Figure 27.5 Burst Mode Write (Four-Word Burst)
162
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
27.4 Mixed-Mode Operation
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27.5 Wait Operation
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External
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Other
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Figure 27.6 Wired or Wait Configuration
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May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
163
A d v a n c e I n f o r m a t i o n
27.6 LB#/UB# Operation
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Address
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VOL
Wait
High-Z
VOH
VOL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional Wait states inserted to allow refresh completion.
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Undefined
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Figure 27.7 Refresh Collision During Variable-Latency Read Operation
164
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
28 Low-Power Operation
28.1 Standby Mode Operation
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28.3 Partial Array Refresh
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28.4 Deep Power-Down Operation
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May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
165
A d v a n c e I n f o r m a t i o n
29 Configuration Registers
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29.1 Access Using Control Register Enable (CRE)
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RQꢀWKHꢀULVLQJꢀHGJHꢀRIꢀ$'9ꢔꢄꢀ&(ꢔꢄꢀRUꢀ:(ꢔꢄꢀZKLFKHYHUꢀRFFXUVꢀILUVWꢕꢀ/%ꢔꢀDQGꢀ8%ꢔꢀDUHꢀ'RQ¶Wꢀ&DUHꢃꢀ
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','5ꢀLVꢀUHDGꢀZKHQꢀ$>ꢈꢋꢆꢈꢍ@ꢀDUHꢀꢏꢈEꢃꢀ)RUꢀUHDGVꢄꢀDGGUHVVꢀLQSXWVꢀRWKHUꢀWKDQꢀ$>ꢈꢋꢆꢈꢍ@ꢀDUHꢀ'RQ¶Wꢀ
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A[22:0]
(except
A[19:18])
OPCODE
tAVS
ADDRESS
ADDRESS
tAVH
Select Control Register
A[19:18]
ꢁ6HHꢀ1RWHꢂ
tAVS
CRE
ADV#
CE#
tVPH
tAVH
tVP
tCPH
Initiate Control Register Access
tCW
OE#
tWP
Write Address Bus Value
to Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
Don't Care
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Figure 29.1 Configuration Register Write, Asynchronous Mode Followed by Read Array Operation
166
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
CLK
Latch Control Register Value
A[22:0]
(except
A[19:18])
Address
Address
OPCODE
tHD
tSP
Latch Control Register Address
A[19:18]
ꢁ1RWHꢀꢊꢂ
tSP
CRE
tHD
tSP
ꢁ1RWHꢀꢐꢂ
tHD
ADV#
tCBPH
tCSP
CE#
OE#
tSP
tHD
WE#
LB#/UB#
tCEW
WAIT
High-Z
High-Z
Data
Valid
DQ[15:0]
Don't Care
1RWHVꢀ
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FRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
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UHIUHVKꢀFROOLVLRQVꢀUHTXLUHꢀDꢀFRUUHVSRQGLQJꢀQXPEHUꢀRIꢀDGGLWLRQDOꢀ&(-ꢀ/RZꢀF\FOHVꢆ
Figure 29.2 Configuration Register Write, Synchronous Mode Followed by Read Array Operation
A[22:0]
Address
(except A[19:18])
tAVH
tAVS
Select Register
A[19:18]
ꢁ6HHꢀ1RWHꢂ
Address
tAA
tAVH
tAVS
CRE
tAA
tVPH
ADV#
tVP
tAAVD
tCPH
Initiate Register Access
tCO
CE#
OE#
tHZ
tOHZ
tOE
tBA
WE#
tOLZ
tLZ
tBHZ
LB#/UB#
DQ[15:0]
tLZ
CR Valid
Data Valid
Don't Care
Undefined
1RWHꢀꢁꢀ$>ꢅꢏꢔꢅꢎ@ꢀ ꢀꢁꢁEꢀWRꢀUHDGꢀ5&5ꢄꢀꢅꢁEꢀWRꢀUHDGꢀ%&5ꢄꢀDQGꢀꢁꢅEꢀWRꢀUHDGꢀ','5ꢆ
Figure 29.3 Register Read, Asynchronous Mode Followed by Read Array Operation
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
167
A d v a n c e I n f o r m a t i o n
CLK
A[22:0]
(except
A[19:18])
Latch Control Register Value
Address
Address
tSP
tSP
tSP
Latch Control Register Address
A[19:18]
ꢁ1RWHꢀꢊꢂ
tHD
CRE
tHD
ADV#
tHD
tABA
ꢁ1RWHꢀꢐꢂ
tCBPH
tCSP
CE#
OE#
tHZ
tOHZ
WE#
tBOE
tHD
t
SP
LB#/UB#
tOLZ
tACLK
tCW
High-Z
High-Z
WAIT
CR
Valid
Data
Valid
DQ[15:0]
tKOH
Don't Care
Undefined
1RWHVꢀ
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FORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ
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ꢊꢆ &(-ꢀPXVWꢀUHPDLQꢀ/RZꢀWRꢀFRPSOHWHꢀDꢀEXUVWꢇRIꢇRQHꢀ:ULWHꢆꢀ:DLWꢀPXVWꢀEHꢀPRQLWRUHGꢄꢀDGGLWLRQDOꢀ:DLWꢀF\FOHVꢀFDXVHGꢀE\ꢀ
UHIUHVKꢀFROOLVLRQVꢀUHTXLUHꢀDꢀFRUUHVSRQGLQJꢀQXPEHUꢀRIꢀDGGLWLRQDOꢀ&(-ꢀ/RZꢀF\FOHVꢆ
Figure 29.4 Register Read, Synchronous Mode Followed by Read Array Operation
29.2 Software Access
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UHDGꢀXVLQJꢀWKHꢀVRIWZDUHꢀVHTXHQFHꢃ
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WKHꢀ&HOOXODU5$0ꢀGHYLFHꢀEHLQJꢀDFFHVVHGꢀꢁꢇ)))))KꢀIRUꢀꢈꢊꢍꢀ0EꢂꢕꢀWKHꢀFRQWHQWVꢀRIꢀWKLVꢀDGGUHVVꢀDUHꢀQRWꢀ
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%&5ꢄꢀ5&5ꢄꢀRUꢀWKHꢀ','5ꢀLVꢀWRꢀEHꢀDFFHVVHGꢃꢀ,IꢀWKHꢀGDWDꢀLVꢀꢏꢏꢏꢏKꢄꢀWKHꢀVHTXHQFHꢀDFFHVVHVꢀWKHꢀ5&5ꢕꢀ
LIꢀWKHꢀGDWDꢀLVꢀꢏꢏꢏꢈKꢄꢀWKHꢀVHTXHQFHꢀDFFHVVHVꢀWKHꢀ%&5ꢕꢀLIꢀWKHꢀGDWDꢀLVꢀꢏꢏꢏꢊKꢄꢀWKHꢀVHTXHQFHꢀDFFHVVHVꢀ
WKHꢀ','5ꢃꢀ'XULQJꢀWKHꢀIRXUWKꢀRSHUDWLRQꢄꢀ'4>ꢈꢉꢆꢏ@ꢀWUDQVIHUꢀGDWDꢀLQꢀWRꢀRUꢀRXWꢀRIꢀELWVꢀꢈꢉꢀ±ꢀꢏꢀRIꢀWKHꢀ
UHJLVWHUVꢃ
168
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
7KHꢀXVHꢀRIꢀWKHꢀVRIWZDUHꢀVHTXHQFHꢀGRHVꢀQRWꢀDIIHFWꢀWKHꢀDELOLW\ꢀWRꢀSHUIRUPꢀWKHꢀVWDQGDUGꢀꢁ&5(ꢅFRQꢅ
WUROOHGꢂꢀPHWKRGꢀRIꢀORDGLQJꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUVꢃꢀ+RZHYHUꢄꢀWKHꢀVRIWZDUHꢀQDWXUHꢀRIꢀWKLVꢀDFFHVVꢀ
PHFKDQLVPꢀHOLPLQDWHVꢀWKHꢀQHHGꢀIRUꢀ&5(ꢃꢀ,IꢀWKHꢀVRIWZDUHꢀPHFKDQLVPꢀLVꢀXVHGꢄꢀ&5(ꢀFDQꢀVLPSO\ꢀEHꢀ
WLHGꢀWRꢀ966ꢃꢀ7KHꢀSRUWꢀOLQHꢀRIWHQꢀXVHGꢀIRUꢀ&5(ꢀFRQWUROꢀSXUSRVHVꢀLVꢀQRꢀORQJHUꢀUHTXLUHGꢃ
Read
Read
Write
Write
Address
(Max)
Address
(Max)
Address
(Max)
Address
(Max)
Address
CE#
OE#
WE#
LB#/UB#
CR
Value In
XXXXh
Data
RCR:0000h
BCR:0001h
Don't Care
Figure 29.5 Load Configuration Register
Read
Read
Write
Write
Address
(Max)
Address
(Max)
Address
(Max)
Address
(Max)
Address
CE#
OE#
WE#
LB#/UB#
CR
Data
XXXXh
XXXXh
Value Out
RCR:0000h
BCR:0001h
DIDR:0002h
Don't Care
Figure 29.6 Read Configuration Register
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
169
A d v a n c e I n f o r m a t i o n
29.3 Bus Configuration Register
7KHꢀ%&5ꢀGHILQHVꢀKRZꢀWKHꢀ&HOOXODU5$0ꢀGHYLFHꢀLQWHUDFWVꢀZLWKꢀWKHꢀV\VWHPꢀPHPRU\ꢀEXVꢃꢀ3DJHꢀPRGHꢀ
RSHUDWLRQꢀLVꢀHQDEOHGꢀE\ꢀDꢀELWꢀFRQWDLQHGꢀLQꢀWKHꢀ5&5ꢃꢀ7DEOHꢀꢊꢋꢃꢈꢀGHVFULEHVꢀWKHꢀFRQWUROꢀELWVꢀLQꢀWKHꢀ
%&5ꢃꢀ$WꢀSRZHUꢅXSꢄꢀWKHꢀ%&5ꢀLVꢀVHWꢀWRꢀꢋ'ꢈ)Kꢃ
7KHꢀ%&5ꢀLVꢀDFFHVVHGꢀZLWKꢀ&5(ꢀ+LJKꢀDQGꢀ$>ꢈꢋꢆꢈꢍ@ꢀ ꢀꢈꢏEꢄꢀRUꢀWKURXJKꢀWKHꢀUHJLVWHUꢀDFFHVVꢀVRIWZDUHꢀ
VHTXHQFHꢀZLWKꢀ'4ꢀ ꢀꢏꢏꢏꢈKꢀRQꢀWKHꢀWKLUGꢀF\FOHꢃ
A[22:20] A[19:18] A[17:16] A15
A14 A13A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2 A1 A0
22–20
19–18
17–16
15
14 13 12 11
10
WAIT
Polarity
9
8
7
6
5
4
3
2
1
0
Operating
Mode
Initial
Latency
Latency
Counter
WAIT
Configuration (WC)
Burst
Burst
Wrap (BW)* Length (BL)*
Register
Select
Reserved
Reserved
Reserved
Reserved
Reserved
Drive Strength
Must be set to 0
Must be set to 0
Must be set to 0
Setting is ignored
(Default to 0)
All must be set to 0
Initial Access Latency
BCR[14]
Variable (default)
Fixed
0
1
BCR[3]
Burst Wrap (Note 1)
0
1
Burst wraps within the burst length
Burst no wrap (default)
BCR[12] BCR[11]
BCR[13]
0
Latency Counter
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 0–Reserved
Code 1–Reserved
Code2
Drive Strength
Full
BCR[5]
BCR[4]
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1/2 (default)
1/4
Code 3 (Default)
Code4
Reserved
Code5
Code6
BCR[8]
WAIT Configuration
Asserted during delay
Asserted one data cycle before delay (default)
Code 7–Reserved
0
1
BCR[10]
0
WAIT Polarity
Active LOW
Active HIGH (default)
Burst Length (Note 1)
4 words
BCR[2] BCR[1]BCR[0]
1
0
0
0
1
1
0
1
0
1
0
1
1
8 words
BCR[15]
Operating Mode
0
1
1
16 words
Synchronous burst access mode
Asynchronous access mode (default)
0
1
32 words
Continuous burst (default)
Reserved
Register Select
BCR[19] BCR[18]
Others
0
1
0
0
0
1
Select RCR
Select BCR
Select DIDR
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170
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
Table 29.1 Sequence and Burst Length
Burst
Wrap
Starting
Address
4-Word
Burst Length
8-Word
Burst Length
16-Word
Burst Length
32-Word
Burst Length
Continuous
Burst
BCR[3]
WRAP
(DECIMAL)
LINEAR
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Table 29.2 Drive Strength
BCR[5]
BCR[4]
Drive Strength
)XOOꢀ
Impedance Typ (Ω)
ꢊꢉ±ꢐꢏꢀ
Use Recommendation
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172
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
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CLK
Wait
High-Z
DQ[15:0]
Data[0]
Data[1]
Data immediately valid (or invalid)
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Figure 29.7 Wait Configuration (BCR[8] = 0)
CLK
Wait
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
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Figure 29.8 Wait Configuration (BCR[8] = 1)
CLK
Wait
Wait
BCR[8] = 0
Data valid in
current cycle.
BCR[8] = 1
Data valid in
next cycle.
DQ[15:0]
D[1]
D[2]
D[0]
D[3]
Don't Care
1RWHꢀꢁꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJꢔꢀ:DLWꢀDFWLYHꢀ/RZ
Figure 29.9 Wait Configuration During Burst Operation
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May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
173
A d v a n c e I n f o r m a t i o n
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UHIUHVKꢀFROOLVLRQVꢃꢀ7KHꢀODWHQF\ꢀFRXQWHUꢀPXVWꢀEHꢀFRQILJXUHGꢀWRꢀPDWFKꢀWKHꢀLQLWLDOꢀODWHQF\ꢀDQGꢀWKHꢀ
FORFNꢀIUHTXHQF\ꢃꢀ,WꢀLVꢀQRWꢀQHFHVVDU\ꢀWRꢀPRQLWRUꢀ:DLWꢀZLWKꢀIL[HGꢀLQLWLDOꢀODWHQF\ꢃꢀ7KHꢀEXUVWꢀEHJLQVꢀ
DIWHUꢀWKHꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀFRQILJXUHGꢀE\ꢀWKHꢀODWHQF\ꢀFRXQWHUꢃꢀ7KHꢀEXUVWꢀSDXVHVꢀꢁDQGꢀ:DLWꢀLVꢀ
DVVHUWHGꢂꢀDWꢀWKHꢀERXQGDU\ꢀRIꢀDꢀꢈꢊꢍꢅZRUGꢀURZꢃꢀꢁ6HHꢀ7DEOHꢀꢊꢋꢃꢓꢀDQGꢀ7DEOHꢀꢊꢋꢃꢈꢈꢂꢃ
ꢎꢇꢅꢐꢅꢌ 2SHUDWLQJꢀ0RGHꢀꢂ%&5>ꢄꢈ@ꢃꢁ'HIDXOWꢀ ꢀ$V\QFKURQRXVꢀ2SHUDWLRQ
7KHꢀRSHUDWLQJꢀPRGHꢀELWꢀVHOHFWVꢀHLWKHUꢀV\QFKURQRXVꢀEXUVWꢀRSHUDWLRQꢀRUꢀWKHꢀGHIDXOWꢀDV\QFKURQRXVꢀ
PRGHꢀRIꢀRSHUDWLRQꢃ
Table 29.3 Variable Latency Configuration Codes
Latency (See Note)
Latency
Configuration Code
Max Input Clk Frequency
(MHz)
BCR[13:11]
Normal
Refresh Collision
ꢏꢈꢏ
ꢏꢈꢈ
ꢊꢀꢁꢐꢀFORFNVꢂ
ꢐꢀꢁꢓꢀFORFNVꢂꢀ±ꢀGHIDXOW
5HVHUYHG
ꢊ
ꢓ
ꢉꢓꢀꢁꢈꢍꢃꢉꢀQVꢂ
ꢍꢏꢀꢁꢈꢊꢃꢉꢀQVꢂ
ꢀ±ꢀ
ꢐ
ꢌ
2WKHUVꢀ
ꢀ±ꢀ
ꢀ±ꢀ
1RWHꢀꢁꢀ/DWHQF\ꢀLVꢀWKHꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀIURPꢀWKHꢀLQLWLDWLRQꢀRIꢀDꢀEXUVWꢀRSHUDWLRQꢀXQWLOꢀGDWDꢀDSSHDUVꢆꢀ'DWDꢀLVꢀWUDQVIHUUHGꢀ
RQꢀWKHꢀQH[WꢀFORFNꢀF\FOHꢆ
VIH
CLK
VIL
VIH
Valid
Address
VIL
A[22:0]
VIH
ADV#
VIL
Code2
VOH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DQ[15:0]
VOL
Code 3
(Default)
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Don't Care
Undefined
Figure 29.10 Latency Counter (Variable Initial Latency, No Refresh Collision)
Table 29.4 Fixed Latency Configuration Codes
Latency Configuration
Code
Latency
Count (N)
Max Input CLK
Frequency (MHz)
BCR[13:11]
ꢏꢈꢏꢀ
ꢏꢈꢈꢀ
ꢊꢀꢁꢐꢀFORFNVꢂꢀ
ꢐꢀꢁꢓꢀFORFNVꢂꢀ±ꢀGHIDXOWꢀ
ꢓꢀꢁꢉꢀFORFNVꢂꢀ
ꢊꢀ
ꢐꢀ
ꢓꢀ
ꢉꢀ
ꢌꢀ
ꢀ±ꢀ
ꢐꢐꢀꢁꢐꢏQVꢂꢀ
ꢉꢊꢀꢁꢈꢋꢃꢊQVꢂꢀ
ꢌꢌꢀꢁꢈꢉQVꢂꢀ
ꢇꢉꢀꢁꢈꢐꢃꢐQVꢂꢀ
ꢍꢏꢀꢁꢈꢊꢃꢉQVꢂꢀ
ꢀ±ꢀꢀ
ꢈꢏꢏꢀ
ꢈꢏꢈꢀ
ꢉꢀꢁꢌꢀFORFNVꢂꢀ
ꢈꢈꢏꢀ
ꢌꢀꢁꢇꢀFORFNVꢂꢀ
2WKHUVꢀ
5HVHUYHGꢀ
174
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
N-1 Cycles
CycleN
VIH
VIL
CLK
A[22:0]
ADV#
tAA
VIH
VIL
Valid
Address
tAADV
VIH
VIL
tCO
VIH
VIL
CE#
tACLK
Valid
Output
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
(Read)
t
t
HD
SP
VOH
VOL
Valid
Input
Valid
Input
Valid
Input
Valid
Input
Valid
Input
DQ[15:0]
(Write)
Burst Identified
(ADV# = Low)
Don't Care
Undefined
Figure 29.11 Latency Counter (Fixed Latency)
29.4 Refresh Configuration Register
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SDUHQWꢀVHOIꢀUHIUHVKꢃꢀ$OWHULQJꢀWKHꢀUHIUHVKꢀSDUDPHWHUVꢀFDQꢀGUDPDWLFDOO\ꢀUHGXFHꢀFXUUHQWꢀFRQVXPSWLRQꢀ
GXULQJꢀVWDQGE\ꢀPRGHꢃꢀ3DJHꢀPRGHꢀFRQWUROꢀLVꢀDOVRꢀHPEHGGHGꢀLQWRꢀWKHꢀ5&5ꢃꢀ7DEOHꢀꢊꢋꢃꢉꢀEHORZꢀGHꢅ
VFULEHVꢀWKHꢀFRQWUROꢀELWVꢀXVHGꢀLQꢀWKHꢀ5&5ꢃꢀ$WꢀSRZHUꢅXSꢄꢀWKHꢀ5&5ꢀLVꢀVHWꢀWRꢀꢏꢏꢇꢏKꢃꢀ7KHꢀ5&5ꢀLVꢀ
DFFHVVHGꢀXVLQJꢀ&5(ꢀDQGꢀ$>ꢈꢋ@ꢀ/RZꢃ
A[22:20] A[19:18]
A[17:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address
Bus
Read
Configuration
Register
22–20
19–18
17–8
Reserved
7
6
5
4
3
2
1
0
Register
Select
Reserved
Page
Reserved
DPD
Reserved
PAR
All must be set to 0 All must be set to 0
Setting is ignored
(Default 00b)
Must be set to 0
RCR[2] RCR[1] RCR[0]
Refresh Coverage
0
0
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
RCR[19] RCR[18]
Register Select
0
1
0
0
0
Select RCR
Select BCR
Select DIDR
0
1
0
0
0
1
0
1
1
0
0
1
1
1
1
0
1
1
Top 1/2 array
1
0
1
Top 1/4 array
RCR[7]
Page Mode Enable/Disable
Top 1/8 array
0
1
Page Mode Disabled (default)
Page Mode Enable
RCR[4]
Deep Power-Down
DPD Enable
0
1
DPD Disable (default)
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
175
A d v a n c e I n f o r m a t i o n
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WKHꢀGHYLFHꢀWRꢀUHGXFHꢀVWDQGE\ꢀFXUUHQWꢀE\ꢀUHIUHVKLQJꢀRQO\ꢀWKDWꢀSDUWꢀRIꢀWKHꢀPHPRU\ꢀDUUD\ꢀUHTXLUHGꢀ
E\ꢀWKHꢀKRVWꢀV\VWHPꢃꢀ7KHꢀUHIUHVKꢀRSWLRQVꢀDUHꢀIXOOꢀDUUD\ꢄꢀRQHꢅKDOIꢀDUUD\ꢄꢀRQHꢅTXDUWHUꢀDUUD\ꢄꢀWKUHHꢅ
TXDUWHUVꢀDUUD\ꢄꢀRUꢀQRQHꢀRIꢀWKHꢀDUUD\ꢃꢀ7KHꢀPDSSLQJꢀRIꢀWKHVHꢀSDUWLWLRQVꢀFDQꢀVWDUWꢀDWꢀHLWKHUꢀWKHꢀEHꢅ
JLQQLQJꢀRUꢀWKHꢀHQGꢀRIꢀWKHꢀDGGUHVVꢀPDSꢀꢁVHHꢀ7DEOHꢀꢊꢋꢃꢉꢂꢃ
Table 29.5 128Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
)XOOꢀGLH
Address Space
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ꢏꢏꢏꢏꢏꢏK±ꢐ)))))K
ꢏꢏꢏꢏꢏꢏK±ꢈ)))))K
ꢏꢏꢏꢏꢏꢏK±ꢏ)))))K
ꢏ
Size
Density
ꢈꢊꢍ0E
ꢌꢓ0E
ꢐꢊ0E
ꢈꢌ0E
ꢏ0E
ꢏ
ꢏ
ꢏ
ꢏ
ꢈ
ꢈ
ꢈ
ꢈ
ꢏ
ꢏ
ꢈ
ꢈ
ꢏ
ꢏ
ꢈ
ꢈ
ꢏ
ꢈ
ꢏ
ꢈ
ꢏ
ꢈ
ꢏ
ꢈ
ꢍꢀ0HJꢀ[ꢀꢈꢌ
ꢓꢀ0HJꢀ[ꢀꢈꢌ
ꢊꢀ0HJꢀ[ꢀꢈꢌ
ꢈꢀ0HJꢀ[ꢀꢈꢌ
ꢏꢀ0HJꢀ[ꢀꢈꢌ
ꢓꢀ0HJꢀ[ꢀꢈꢌ
ꢊꢀ0HJꢀ[ꢀꢈꢌ
ꢈꢀ0HJꢀ[ꢀꢈꢌ
2QHꢅKDOIꢀRIꢀGLH
2QHꢅTXDUWHUꢀRIꢀGLH
2QHꢅHLJKWKꢀRIꢀGLH
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2QHꢅTXDUWHUꢀRIꢀGLH
2QHꢅHLJKWKꢀRIꢀGLH
ꢓꢏꢏꢏꢏꢏK±ꢇ)))))K
ꢌꢏꢏꢏꢏꢏK±ꢇ)))))K
ꢇꢏꢏꢏꢏꢏK±ꢇ)))))K
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WKHꢀV\VWHPꢀGRHVꢀQRWꢀUHTXLUHꢀWKHꢀVWRUDJHꢀSURYLGHGꢀE\ꢀWKHꢀ&HOOXODU5$0ꢀGHYLFHꢃꢀ$Q\ꢀVWRUHGꢀGDWDꢀEHꢅ
FRPHVꢀFRUUXSWHGꢀZKHQꢀ'3'ꢀLVꢀHQDEOHGꢃꢀ:KHQꢀUHIUHVKꢀDFWLYLW\ꢀKDVꢀEHHQꢀUHꢅHQDEOHGꢄꢀWKHꢀ
&HOOXODU5$0ꢀGHYLFHꢀUHTXLUHVꢀꢈꢉꢏVꢀWRꢀSHUIRUPꢀDQꢀLQLWLDOL]DWLRQꢀSURFHGXUHꢀEHIRUHꢀQRUPDOꢀRSHUDꢅ
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'HHSꢀSRZHUꢅGRZQꢀLVꢀHQDEOHGꢀE\ꢀVHWWLQJꢀ5&5>ꢓ@ꢀ ꢀꢏꢀDQGꢀWDNLQJꢀ&(ꢔꢀ+LJKꢃꢀ'3'ꢀFDQꢀEHꢀHQDEOHGꢀ
XVLQJꢀ&5(ꢀRUꢀWKHꢀVRIWZDUHꢀVHTXHQFHꢀWRꢀDFFHVVꢀWKHꢀ5&5ꢃꢀ7DNLQJꢀ&(ꢔꢀ/RZꢀIRUꢀDWꢀOHDVWꢀꢈꢏꢀVꢀGLVDEOHVꢀ
'3'ꢀDQGꢀVHWVꢀ5&5>ꢓ@ꢀ ꢀꢈꢕꢀLWꢀLVꢀQRWꢀQHFHVVDU\ꢀWRꢀZULWHꢀWRꢀWKHꢀ5&5ꢀWRꢀGLVDEOHꢀ'3'ꢃ
ꢎꢇꢅꢉꢅꢐ 3DJHꢀ0RGHꢀ2SHUDWLRQꢀꢂ5&5>ꢆ@ꢃꢁꢀ'HIDXOWꢀ ꢀ'LVDEOHG
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RSHUDWLRQVꢃꢀ,QꢀWKHꢀSRZHUꢅXSꢀGHIDXOWꢀVWDWHꢄꢀSDJHꢀPRGHꢀLVꢀGLVDEOHGꢃ
ꢎꢇꢅꢉꢅꢉ 'HYLFHꢀ,GHQWLILFDWLRQꢀ5HJLVWHU
7KHꢀ','5ꢀSURYLGHVꢀLQIRUPDWLRQꢀRQꢀWKHꢀGHYLFHꢀPDQXIDFWXUHUꢄꢀ&HOOXODU5$0ꢀJHQHUDWLRQꢄꢀDQGꢀWKHꢀVSHꢅ
FLILFꢀGHYLFHꢀFRQILJXUDWLRQꢃ7DEOHꢀꢊꢋꢃꢌꢀGHVFULEHVꢀWKHꢀELWꢀILHOGVꢀLQꢀWKHꢀ','5ꢃꢀ7KLVꢀUHJLVWHUꢀLVꢀUHDGꢅRQO\ꢃ
7KHꢀ','5ꢀLVꢀDFFHVVHGꢀZLWKꢀ&5(ꢀ+LJKꢀDQGꢀ$>ꢈꢋꢆꢈꢍ@ꢀ ꢀꢏꢈEꢄꢀRUꢀWKURXJKꢀWKHꢀUHJLVWHUꢀDFFHVVꢀVRIWZDUHꢀ
VHTXHQFHꢀZLWKꢀ'4ꢀ ꢀꢏꢏꢏꢊKꢀRQꢀWKHꢀWKLUGꢀF\FOHꢃ
Table 29.6 Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
DIDR[7:5]
DIDR[4:0]
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)LHOGꢀ1DPHꢀ
5HVHUYHGꢀ
'HYLFHꢀ'HQVLW\ꢀ
9HQGRUꢀ,'ꢀ
Bit Setting
Version
ꢈVWꢀ
ꢏꢏꢏꢏEꢀ
ꢏꢏꢏꢈEꢀ
ꢏEꢀ
±ꢀ
ꢊQG
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0HDQLQJꢀ
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ꢈꢊꢍ0Eꢀ
&HOOXODU5$0ꢀꢈꢃꢉꢀ
&HOOXODU5$0ꢀ7\SHꢀꢊ
176
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
30 Absolute Maximum Ratings
9ROWDJHꢀWRꢀ$Q\ꢀ%DOOꢀ([FHSWꢀ9&&ꢄꢀ9&&4
ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ5HODWLYHꢀWRꢀ966ꢅꢏꢃꢉꢏ9ꢀWRꢀꢁꢓꢃꢏꢀ9ꢀRUꢀ9&&4ꢀꢎꢀꢏꢃꢐꢀ9ꢄꢀZKLFKHYHUꢀLVꢀOHVVꢂ
9ROWDJHꢀRQꢀ9&&ꢀ6XSSO\ꢀ5HODWLYHꢀWRꢀ966 ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ ꢀꢅꢏꢃꢊꢀ9ꢀWRꢀꢎꢊꢃꢓꢉꢀ9
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6WRUDJHꢀ7HPSHUDWXUHꢀꢁSODVWLFꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ±ꢉꢉꢀ&ꢀWRꢀꢎꢈꢉꢏꢀ&
2SHUDWLQJꢀ7HPSHUDWXUHꢀꢁFDVHꢂ
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ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ,QGXVWULDO±ꢓꢏ&ꢀWRꢀꢎꢍꢉꢀ&
6ROGHULQJꢀ7HPSHUDWXUHꢀDQGꢀ7LPH
ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢈꢏꢀVꢀꢁVROGHUꢀEDOOꢀRQO\ꢂꢎꢊꢌꢏꢀ&
1RWHꢀꢁꢀ6WUHVVHVꢀJUHDWHUꢀWKDQꢀWKRVHꢀOLVWHGꢀPD\ꢀFDXVHꢀSHUPDQHQWꢀGDPDJHꢀWRꢀWKHꢀGHYLFHꢆꢀ7KLVꢀLVꢀDꢀVWUHVVꢀUDWLQJꢀRQO\ꢄꢀDQGꢀ
IXQFWLRQDOꢀRSHUDWLRQꢀRIꢀWKHꢀGHYLFHꢀDWꢀWKHVHꢀRUꢀDQ\ꢀRWKHUꢀFRQGLWLRQVꢀDERYHꢀWKRVHꢀLQGLFDWHGꢀLQꢀWKHꢀRSHUDWLRQDOꢀVHFWLRQVꢀRIꢀWKLVꢀ
VSHFLILFDWLRQꢀLVꢀQRWꢀLPSOLHGꢆꢀ([SRVXUHꢀWRꢀDEVROXWHꢀPD[LPXPꢀUDWLQJꢀFRQGLWLRQVꢀIRUꢀH[WHQGHGꢀSHULRGVꢀPD\ꢀDIIHFWꢀUHOLDELOLW\ꢆ
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
177
A d v a n c e I n f o r m a t i o n
31 DC Characteristics
Table 31.1 Electrical Characteristics and Operating Conditions
'HVFULSWLRQ
Conditions
Symbol
Min
ꢈꢃꢇꢏ
ꢈꢃꢇꢏ
Max
ꢈꢃꢋꢉ
ꢈꢃꢋꢉ
Units
Notes
6XSSO\ꢀ9ROWDJH
9
&&
,ꢑ2ꢀ6XSSO\ꢀ9ROWDJH
,QSXWꢀ+LJKꢀ9ROWDJH
,QSXWꢀ/RZꢀ9ROWDJH
2XWSXWꢀ+LJKꢀ9ROWDJH
2XWSXWꢀ/RZꢀ9ROWDJH
,QSXWꢀ/HDNDJHꢀ&XUUHQW
9
&&4
9
9
ꢀ±ꢀꢏꢃꢓ
9 ꢀꢎꢀꢏꢃꢊ
&&4
ꢊ
ꢐ
,+
&&4
9
9
±ꢏꢃꢊꢏ
ꢏꢃꢓ
,/
,
ꢀ ꢀꢅꢏꢃꢊꢀP$
9
ꢏꢃꢍꢏꢀ9
&&4
2+
2+
ꢓ
,
ꢀ ꢀꢎꢏꢃꢊꢀP$
9
,
ꢏꢃꢊꢏꢀ9
ꢈ
2/
2/
&&4
9
ꢀ ꢀꢏꢀWRꢀ9
&&4
,1
/,
$
2(ꢔꢀ ꢀ9 ꢀRUꢀ
,+
&KLSꢀ'LVDEOHG
2XWSXWꢀ/HDNDJHꢀ&XUUHQW
,
ꢈ
/2
Operating Current
ꢅꢇꢏ
ꢅꢍꢉ
ꢅꢇꢏ
ꢅꢍꢉ
ꢊꢉ
ꢊꢊ
ꢈꢉ
ꢈꢊ
ꢐꢏ
ꢊꢉ
ꢊꢉ
ꢊꢏ
ꢐꢏ
ꢊꢉ
$V\QFKURQRXVꢀ5DQGRPꢀ5HDGꢑ:ULWH
$V\QFKURQRXVꢀ3DJHꢀ5HDG
,QLWLDOꢀ$FFHVVꢄꢀ%XUVWꢀ5HDGꢑ:ULWH
&RQWLQXRXVꢀ%XUVWꢀ5HDG
,
&&ꢈ
,
&&ꢈ3
ꢍꢏꢀ0+]
ꢌꢌꢀ0+]
ꢍꢏꢀ0+]
ꢌꢌꢀ0+]
ꢍꢏꢀ0+]
ꢌꢌꢀ0+]
9
ꢀ ꢀ9
ꢀRUꢀꢏꢀ9ꢀ
&&4
,1
,
P$
ꢉ
ꢌ
&&ꢊ
&KLSꢀ(QDEOHGꢄꢀ,
ꢀ ꢀꢏ
287
,
&&ꢐ5
&RQWLQXRXVꢀ%XUVWꢀ:ULWH
,
&&ꢐ:
9
ꢀ ꢀ9
&(ꢔꢀ ꢀ9
ꢀRUꢀꢏ9ꢀ
&&4
,1
&&4
6WDQGE\ꢀ&XUUHQW
,
6WDQGDUG
ꢊꢏꢏ
$
6%
1RWHVꢀ
ꢅꢆ :LUHOHVVꢀ7HPSHUDWXUHꢀꢂꢇꢊꢁ&ꢀꢕꢀ7&ꢀꢕꢀꢉꢎꢌ&ꢃꢓꢀ,QGXVWULDOꢀ7HPSHUDWXUHꢀꢂꢇꢍꢁ&ꢀꢕꢀ7&ꢀꢕꢀꢉꢎꢌ&ꢃꢆ
ꢈꢆ ,QSXWꢀVLJQDOVꢀPD\ꢀRYHUVKRRWꢀWRꢀ9 ꢀꢉꢀꢅꢆꢁ9ꢀIRUꢀSHULRGVꢀOHVVꢀWKDQꢀꢈQVꢀGXULQJꢀWUDQVLWLRQVꢆ
&&4
ꢊꢆ ,QSXWꢀVLJQDOVꢀPD\ꢀXQGHUVKRRWꢀWRꢀ9 ꢀꢇꢀꢅꢆꢁ9ꢀIRUꢀSHULRGVꢀOHVVꢀWKDQꢀꢈQVꢀGXULQJꢀWUDQVLWLRQVꢆ
66
ꢍꢆ %&5>ꢌꢔꢍ@ꢀ ꢀꢁꢅEꢀꢂGHIDXOWꢀVHWWLQJꢀRIꢀRQHꢇKDOIꢀGULYHꢀVWUHQJWKꢃꢆ
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6%
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VWDQGE\ꢀPRGHꢆ
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66 6%
&&4
Table 31.2 Partial Array Refresh Specifications and Conditions
Standard Power
(No Desig.)
Description
Conditions
Symbol
Array Partition
Units
)XOO
ꢈꢑꢊ
ꢈꢑꢓ
ꢈꢑꢍ
ꢏ
ꢊꢏꢏ
ꢈꢇꢏ
ꢈꢉꢉ
ꢈꢉꢏ
ꢈꢓꢏ
3DUWLDOꢀ$UUD\ꢀ5HIUHVK
6WDQGE\ꢀ&XUUHQW
9
ꢀ ꢀ9
ꢀRU
&&4
,1
,
$
3$5
ꢏꢀ9ꢄꢀ&(ꢔꢀ ꢀ9
&&4
1RWHꢀꢁꢀ,
ꢀꢂPD[ꢃꢀYDOXHVꢀPHDVXUHGꢀZLWKꢀ7&5ꢀVHWꢀWRꢀꢎꢌ&ꢆ
3$5
178
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
140
PAR = Full Array
130
120
110
100
90
PAR = 1/2 of Array
PAR = 1/4 of Array
PAR = 1/8 of Array
PAR = None of Array
80
70
60
50
40
30
20
10
0
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
Figure 31.1 Refresh Current vs. Temperature (I
)
TCR
Table 31.3 Deep Power-Down Specifications
Description
Conditions
ꢀ ꢀ9 ꢀRUꢀꢏꢀ9ꢕ
Symbol
Typ
Max
Units
9
ꢄꢀ9
,1
&&4
'HHSꢀ3RZHUꢅ'RZQ
,
ꢐ
ꢊꢉ
$
==
9
ꢀ ꢀꢈꢃꢋꢉꢀ9ꢄꢀꢎꢍꢉ&
&&
&&4
Table 31.4 Capacitance
Description
Conditions
Symbol
Min.
ꢊꢃꢏ
ꢐꢃꢉ
Max
Units
S)ꢀ
Notes
ꢈꢀ
,QSXWꢀ&DSDFLWDQFHꢀ
&
&
ꢌꢀ
ꢌꢀ
,1
,2
7&ꢀ ꢀꢎꢊꢉ&ꢕꢀIꢀ ꢀꢈꢀ0+]ꢕꢀ
9
ꢀ ꢀꢏ9ꢀ
,1
,QSXWꢑ2XWSXWꢀ&DSDFLWDQFHꢀꢁ'4ꢂꢀ
S)ꢀ
ꢈꢀ
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
179
A d v a n c e I n f o r m a t i o n
32 AC Characteristics
VCCQ
Input
(Note 1)
VSSQ
VCCQ/2
VCCQ/2
Output
Test Points
(Note 2)
(Note 3)
1RWHVꢀ
ꢅꢆ $&ꢀWHVWꢀLQSXWVꢀDUHꢀGULYHQꢀDWꢀ9
ꢀIRUꢀDꢀORJLFꢀꢅꢀDQGꢀ9
ꢀIRUꢀDꢀORJLFꢀꢁꢆꢀ,QSXWꢀULVHꢀDQGꢀIDOOꢀWLPHVꢀꢂꢅꢁꢖꢀWRꢀꢏꢁꢖꢃꢀꢕꢀꢅꢆꢐꢀQVꢆ
&&4
664
ꢈꢆ ,QSXWꢀWLPLQJꢀEHJLQVꢀDWꢀ9
ꢒꢈꢆ
&&4
ꢊꢆ 2XWSXWꢀWLPLQJꢀHQGVꢀDWꢀ9
ꢒꢈ
&&4
Figure 32.1 AC Input/Output Reference Waveform
Test Point
50Ω
VCCQ/2
DUT
30pF
1RWHꢀꢁꢀ$OOꢀWHVWVꢀDUHꢀSHUIRUPHGꢀZLWKꢀWKHꢀRXWSXWVꢀFRQILJXUHGꢀIRUꢀGHIDXOWꢀVHWWLQJꢀRIꢀKDOIꢀGULYHꢀVWUHQJWKꢀꢂ%&5>ꢌꢔꢍ@ꢀ ꢀꢁꢅEꢃꢆ
Figure 32.2 Output Load Circuit
180
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
Table 32.1 Asynchronous Read Cycle Timing Requirements
Parameter
$GGUHVVꢀ$FFHVVꢀ7LPH
Symbol
Min
Max
ꢇꢏꢀ
ꢇꢏꢀ
ꢊꢏꢀ
Units
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
Vꢀ
QVꢀ
QVꢀ
QVꢀ
Notes
W
$$
$'9ꢔꢀ$FFHVVꢀ7LPH
W
$$'9
3DJHꢀ$FFHVVꢀ7LPH
W
$3$
$9+
$GGUHVVꢀ+ROGꢀIURPꢀ$'9ꢔꢀ+LJK
$GGUHVVꢀ6HWXSꢀWRꢀ$'9ꢔꢀ+LJK
/%ꢔꢑ8%ꢔꢀ$FFHVVꢀ7LPH
W
ꢊꢀ
ꢉꢀ
W
$96
W
ꢇꢏꢀ
ꢍꢀ
%$
/%ꢔꢑ8%ꢔꢀ'LVDEOHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
/%ꢔꢑ8%ꢔꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
0D[LPXPꢀ&(ꢔꢀ3XOVHꢀ:LGWK
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLG
W
ꢀ
ꢈꢀ
ꢊꢀ
ꢐꢀ
%+=
W
ꢈꢏꢀ
ꢈꢀ
%/=
W
ꢓꢀ
&(0
&(:
W
ꢇꢃꢉꢀ
ꢇꢏꢀ
&KLSꢀ6HOHFWꢀ$FFHVVꢀ7LPH
&(ꢔꢀ/RZꢀWRꢀ$'9ꢔꢀ+LJK
W
&2
W
ꢇꢀ
&96
&KLSꢀ'LVDEOHꢀWRꢀ'4ꢀDQG
:DLWꢀ+LJKꢅ=ꢀ2XWSXW
W
ꢍꢀ
QVꢀ
ꢈꢀ
ꢊꢀ
+=
&KLSꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
2XWSXWꢀ(QDEOHꢀWRꢀ9DOLGꢀ2XWSXW
2XWSXWꢀ+ROGꢀIURPꢀ$GGUHVVꢀ&KDQJH
2XWSXWꢀ'LVDEOHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXW
2XWSXWꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXW
3DJHꢀ&\FOHꢀ7LPH
W
ꢈꢏꢀ
ꢉꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
/=
2(
2+
W
ꢊꢏꢀ
ꢍꢀ
W
W
ꢈꢀ
ꢊꢀ
2+=
W
ꢐꢀ
2/=
W
ꢊꢏꢀ
ꢇꢏꢀ
ꢉꢀ
3&
5HDGꢀ&\FOHꢀ7LPH
W
5&
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ/RZ
W
93
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ+LJK
W
ꢈꢏꢀ
93+
1RWHVꢀ
ꢅꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ )LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁP9ꢀWUDQVLWLRQꢀ
IURPꢀHLWKHUꢀ9 ꢀRUꢀ9 ꢀWRZDUGꢀ9 ꢒꢈꢆ
2+
2/
&&4
ꢈꢆ +LJKꢇ=ꢀWRꢀ/RZꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ/RZꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁP9ꢀWUDQVLWLRQꢀ
DZD\ꢀIURPꢀWKHꢀ+LJKꢇ=ꢀꢂ9 ꢒꢈꢃꢀOHYHOꢀWRZDUGꢀHLWKHUꢀ9 ꢀRUꢀ9
ꢆ
2/
&&4
2+
ꢊꢆ 3DJHꢀPRGHꢀHQDEOHGꢀRQO\ꢆ
ꢍꢆ $OOꢀWHVWVꢀDUHꢀSHUIRUPHGꢀZLWKꢀWKHꢀRXWSXWVꢀFRQILJXUHGꢀIRUꢀIXOOꢀGULYHꢀVWUHQJWKꢀꢂ%&5>ꢌ@ꢀ ꢀꢁꢃꢆ
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
181
A d v a n c e I n f o r m a t i o n
Table 32.2 Burst Read Cycle Timing Requirements
Parameter
Symbol
Min.
Max
ꢇꢏꢀ
ꢇꢏꢀ
ꢓꢌꢀ
ꢋꢀ
Units
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
Notes
$GGUHVVꢀ$FFHVVꢀ7LPHꢀꢁ)L[HGꢀ/DWHQF\ꢂꢀ
$'9ꢔꢀ$FFHVVꢀ7LPHꢀꢁ)L[HGꢀ/DWHQF\ꢂꢀ
%XUVWꢀWRꢀ5HDGꢀ$FFHVVꢀ7LPHꢀꢁ9DULDEOHꢀ/DWHQF\ꢂꢀ
&/.ꢀWRꢀ2XWSXWꢀ'HOD\ꢀ
W
$$
W
ꢀ
$$'9
W
$%$
W
$&/.
$GGUHVVꢀ+ROGꢀIURPꢀ$'9ꢔꢀ+LJKꢀꢁ)L[HGꢀ/DWHQF\ꢂꢀ
%XUVWꢀ2(ꢔꢀ/RZꢀWRꢀ2XWSXWꢀ'HOD\ꢀ
W
ꢊꢀ
ꢌꢀ
$9+
W
ꢀꢊꢏꢀ
%2(
&(ꢔꢀ+LJKꢀEHWZHHQꢀ6XEVHTXHQWꢀ%XUVWꢀRU
0L[HGꢅ0RGHꢀ2SHUDWLRQVꢀ
W
QVꢀ
ꢈꢀ
ꢈꢀ
&%3+
0D[LPXPꢀ&(ꢔꢀ3XOVHꢀ:LGWKꢀ
&(ꢔꢀRUꢀ$'9ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLGꢀ
&/.ꢀ3HULRGꢀ
W
ꢓꢀ
Vꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QV
&(0
W
ꢈꢀ
ꢇꢃꢉꢀ
&(:
W
ꢀꢈꢊꢃꢉꢀ
&/.
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&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ$FWLYHꢀ&/.ꢀ(GJHꢀ
+ROGꢀ7LPHꢀIURPꢀ$FWLYHꢀ&/.ꢀ(GJHꢀ
&KLSꢀ'LVDEOHꢀWRꢀ'4ꢀDQGꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXWꢀ
&/.ꢀ5LVHꢀRUꢀ)DOOꢀ7LPHꢀ
W
ꢇꢏꢀ
&2
W
ꢓꢀ
ꢊꢀ
&63
W
+'
W
ꢍꢀ
ꢈꢃꢍꢀ
ꢋꢀ
ꢊꢀ
+=
W
.+./
&/.ꢀWRꢀ:DLWꢀ9DOLGꢀ
W
.+7/
2XWSXWꢀ+2/'ꢀIURPꢀ&/.ꢀ
W
ꢊꢀ
ꢓꢀ
.2+
&/.ꢀ+LJKꢀRUꢀ/RZꢀ7LPHꢀ
W
.3
2XWSXWꢀ'LVDEOHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXWꢀ
2XWSXWꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXWꢀ
6HWXSꢀ7LPHꢀWRꢀ$FWLYHꢀ&/.ꢀ(GJHꢀ
W
ꢍꢀ
ꢊꢀ
2+=
W
ꢐꢀ
ꢐꢀ
ꢀꢐꢀ
2/=
W
QVꢀ
63
1RWHVꢀ
ꢅꢆ $ꢀUHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀ
&(0
FRQGLWLRQVꢔꢀDꢃꢀ&ORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀEꢃꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀꢅꢌꢀQVꢆ
ꢈꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢀP9ꢀ
WUDQVLWLRQꢀIURPꢀHLWKHUꢀ9 ꢀRUꢀ9 ꢀWRZDUGꢀꢂ9 ꢒꢈꢃꢆ
2+
2/
&&4
ꢊꢆ +LJKꢇ=ꢀWRꢀ/RZꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ/RZꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢀP9ꢀ
WUDQVLWLRQꢀDZD\ꢀIURPꢀWKHꢀ+LJKꢇ=ꢀꢂ9 ꢒꢈꢃꢀOHYHOꢀWRZDUGꢀHLWKHUꢀ9 ꢀRUꢀ9
ꢆ
2/
&&4
2+
ꢍꢆ $OOꢀWHVWVꢀDUHꢀSHUIRUPHGꢀZLWKꢀWKHꢀRXWSXWVꢀFRQILJXUHGꢀIRUꢀIXOOꢀGULYHꢀVWUHQJWKꢀꢂ%&5>ꢌ@ꢀ ꢀꢁꢃꢆ
182
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
Table 32.3 Asynchronous Write Cycle Timing Requirements
Parameter
$GGUHVVꢀDQGꢀ$'9ꢔꢀ/RZꢀ6HWXSꢀ7LPHꢀ
$GGUHVVꢀ+ROGꢀIURPꢀ$'9ꢔꢀ*RLQJꢀ+LJKꢀ
$GGUHVVꢀ6HWXSꢀWRꢀ$'9ꢔꢀ*RLQJꢀ+LJKꢀ
$GGUHVVꢀ9DOLGꢀWRꢀ(QGꢀRIꢀ:ULWHꢀ
/%ꢔꢑ8%ꢔꢀ6HOHFWꢀWRꢀ(QGꢀRIꢀ:ULWHꢀ
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLGꢀ
Symbol
Min.
ꢏꢀ
Max
ꢇꢃꢉꢀ
ꢍꢀ
Units
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QV
Notes
W
$6
W
ꢊꢀ
$9+
W
ꢉꢀ
$96
W
ꢇꢏꢀ
ꢇꢏꢀ
ꢈꢀ
$:
W
%:
W
&(:
&(ꢔꢀ+LJKꢀEHWZHHQꢀ6XEVHTXHQWꢀ$V\QFꢀ2SHUDWLRQVꢀ
&(ꢔꢀ/RZꢀWRꢀ$'9ꢔꢀ+LJKꢀ
W
ꢉꢀ
&(+
W
ꢇꢀ
&96
&KLSꢀ(QDEOHꢀWRꢀ(QGꢀRIꢀ:ULWHꢀ
'DWDꢀ+ROGꢀIURPꢀ:ULWHꢀ7LPHꢀ
'DWDꢀ:ULWHꢀ6HWXSꢀ7LPHꢀ
W
ꢇꢏꢀ
ꢏꢀ
&:
W
'+
W
ꢊꢏꢀ
':
&KLSꢀ'LVDEOHꢀWRꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXWꢀ
&KLSꢀ(QDEOHꢀWRꢀ/RZꢅ=ꢀ2XWSXWꢀ
(QGꢀ:ULWHꢀWRꢀ/RZꢅ=ꢀ2XWSXWꢀ
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ
W
ꢈꢀ
ꢊꢀ
+=
W
ꢈꢏꢀ
ꢉꢀ
/=
W
ꢀꢊꢀ
2:
W
ꢉꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QV
93
$'9ꢔꢀ3XOVHꢀ:LGWKꢀ+LJKꢀ
W
ꢈꢏꢀ
ꢇꢏꢀ
ꢇꢏꢀ
93+
$'9ꢔꢀ6HWXSꢀWRꢀ(QGꢀRIꢀ:ULWHꢀ
:ULWHꢀ&\FOHꢀ7LPHꢀ
W
96
W
:&
:ULWHꢀWRꢀ'4ꢀ+LJKꢅ=ꢀ2XWSXWꢀ
:ULWHꢀ3XOVHꢀ:LGWKꢀ
W
ꢍꢀ
ꢀꢈꢀ
ꢐꢀ
:+=
W
ꢓꢉꢀ
ꢈꢏꢀ
ꢏꢀ
QVꢀ
QVꢀ
QVꢀ
:3
:ULWHꢀ3XOVHꢀ:LGWKꢀ+LJKꢀ
W
:3+
:ULWHꢀ5HFRYHU\ꢀ7LPHꢀ
W
:5
1RWHVꢀ
ꢅꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ )LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁP9ꢀWUDQVLWLRQꢀ
IURPꢀHLWKHUꢀ9 ꢀRUꢀ9 ꢀWRZDUGꢀ9 ꢒꢈꢆ
2+
2/
&&4
ꢈꢆ +LJKꢇ=ꢀWRꢀ/RZꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ/RZꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁP9ꢀWUDQVLWLRQꢀ
DZD\ꢀIURPꢀWKHꢀ+LJKꢇ=ꢀꢂ9 ꢒꢈꢃꢀOHYHOꢀWRZDUGꢀHLWKHUꢀ9 ꢀRUꢀ9
ꢆ
2/
&&4
2+
ꢊꢆ :(-ꢀ/RZꢀWLPHꢀPXVWꢀEHꢀOLPLWHGꢀWRꢀW
ꢀꢂꢍVꢃꢆ
&(0
Table 32.4 Burst Write Cycle Timing Requirements
Parameter
Symbol
Min
ꢏꢀ
Max
Units
QVꢀ
Notes
$GGUHVVꢀDQGꢀ$'9ꢔꢀ/RZꢀVHWXSꢀWLPHꢀ
$GGUHVVꢀ+ROGꢀIURPꢀ$'9ꢔꢀ+LJKꢀꢁ)L[HGꢀ/DWHQF\ꢂꢀ
W
ꢈꢀ
$6
W
ꢊꢀ
QVꢀ
$9+
&(ꢔꢀ+LJKꢀEHWZHHQꢀ6XEVHTXHQW
0L[HGꢅ0RGHꢀ2SHUDWLRQV
W
ꢌꢀ
QVꢀ
ꢊꢀ
ꢊꢀ
&%3+
0D[LPXPꢀ&(ꢔꢀ3XOVHꢀ:LGWKꢀ
&(ꢔꢀ/RZꢀWRꢀ:DLWꢀ9DOLG
W
ꢓꢀ
Vꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
QVꢀ
&(0
W
ꢈꢀ
ꢀꢈꢊꢃꢉꢀ
ꢓꢀ
ꢇꢃꢉꢀ
&(:
&ORFNꢀ3HULRG
W
&/.
&(ꢔꢀ6HWXSꢀWRꢀ&/.ꢀ$FWLYHꢀ(GJH
+ROGꢀ7LPHꢀIURPꢀ$FWLYHꢀ&/.ꢀ(GJH
&KLSꢀ'LVDEOHꢀWRꢀ:DLWꢀ+LJKꢅ=ꢀ2XWSXW
/DVWꢀ&ORFNꢀWRꢀ$'9ꢔꢀ/RZꢀꢁ)L[HGꢀ/DWHQF\ꢂ
&/.ꢀ5LVHꢀRUꢀ)DOOꢀ7LPH
W
&63
W
ꢊꢀ
+'
W
ꢍꢀ
ꢐꢀ
+=
W
ꢌꢀ
.$'9
W
ꢈꢃꢍꢀ
ꢋꢀ
.+./
&ORFNꢀWRꢀ:DLWꢀ9DOLG
W
.+7/
&/.ꢀ+LJKꢀRUꢀ/RZꢀ7LPH
W
W
ꢓꢀ
ꢐꢀ
.3
63
6HWXSꢀ7LPHꢀWRꢀ$FWLYDWHꢀ&/.ꢀ(GJH
1RWHVꢀ
ꢅꢆ
W
UHTXLUHGꢀLIꢀW
ꢀ!ꢀꢈꢁQVꢆ
$6ꢀ
&63
ꢈꢆ $ꢀUHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀ
&(0
FRQGLWLRQVꢔꢀ&ORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀꢅꢌꢀQVꢆ
ꢊꢆ /RZꢇ=ꢀWRꢀ+LJKꢇ=ꢀWLPLQJVꢀDUHꢀWHVWHGꢀZLWKꢀWKHꢀFLUFXLWꢀVKRZQꢀLQꢀ)LJXUHꢀꢊꢈꢆꢈꢆꢀ7KHꢀ+LJKꢇ=ꢀWLPLQJVꢀPHDVXUHꢀDꢀꢅꢁꢁꢀP9ꢀ
WUDQVLWLRQꢀIURPꢀHLWKHUꢀ9 ꢀRUꢀ9 ꢀWRZDUGꢀ9 ꢒꢈꢆ
2+
2/
&&4
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
183
A d v a n c e I n f o r m a t i o n
32.1 Timing Diagrams
VCC (Min)
Device ready for normal operation
VCC, VCCQ = 1.7 V
tPU
Figure 32.1 Initialization Period
tDPD
tDPDX
tPU
CE#
Write
RCR[4] = 0
DPD Enabled
DPD Exit
Device Initialization Device ready for
normal operation
Figure 32.2 DPD Entry and Exit Timing Parameters
Table 32.5 Initialization Timing Parameters
Parameter
Symbol
Min
Max
Units
Notes
,QLWLDOL]DWLRQꢀ3HULRGꢀ
ꢁUHTXLUHGꢀEHIRUHꢀQRUPDOꢀRSHUDWLRQVꢂ
W
ꢈꢉꢏ
V
38
7LPHꢀIURPꢀ'3'ꢀHQWU\ꢀWRꢀ'3'ꢀH[LW
&(ꢔꢀ/RZꢀWLPHꢀWRꢀH[LWꢀ'3'
W
ꢈꢏ
ꢈꢏ
'3'
W
'3';
184
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
tRC
VIH
A[22:0]
ADV#
Valid Address
VIL
tAA
V
IH
VIL
tHZ
VIH
VIL
CE#
tCO
tBHZ
t
BA
VIH
VIL
LB#/UB#
tOE
tOHZ
VIH
VIL
OE#
WE#
VIH
VIL
tOLZ
tBLZ
tLZ
VOH
VOL
High-Z
DQ[15:0]
Wait
Valid Output
tCEW
High-Z
tHZ
VIH
VIL
High-Z
Don't Care
Undefined
Figure 32.3 Asynchronous Read
Table 32.6 Asynchronous Read Timing Parameters
Symbol
Min
Max
ꢇꢏ
ꢇꢏ
ꢍ
Units
QV
Symbol
Min
Max
ꢇꢃꢉ
ꢇꢏ
ꢍ
Units
QV
Symbol
Min
Max
ꢊꢏ
ꢍ
Units
QV
W
W
W
ꢈ
W
2(
$$
%$
&(:
QV
W
QV
W
QV
&2
2+=
W
QV
W
QV
W
2/=
ꢐ
QV
%+=
+=
W
ꢈꢏ
QV
W
ꢈꢏ
QV
W
5&
ꢇꢏ
QV
%/=
/=
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
185
A d v a n c e I n f o r m a t i o n
VIH
VIL
A[22:0]
Valid Address
tAA
tAVS
tAVH
tVPH
VIH
VIL
ADV#
tAADV
tVP
tHZ
tCVS
VIH
VIL
CE#
tCO
tBA
tBHZ
VIH
VIL
LB#/UB#
tOE
tOHZ
VIH
VIL
VIH
VIL
OE#
WE#
tOLZ
tBLZ
tLZ
VOH
VOL
High-Z
DQ[15:0]
Valid Output
tHZ
tCEW
V
IH
High-Z
High-Z
Wait
V
IL
Don't Care
Undefined
Figure 32.4 Asynchronous Read Using ADV#
Table 32.7 Asynchronous Read Timing Parameters Using ADV#
Symbol
Min
Max
ꢇꢏ
Units
QV
Symbol
Min
ꢈꢏ
ꢈ
Max
Units
QV
Symbol
Min
Max
ꢊꢏ
ꢍ
Units
QV
W
W
W
2(
$$
%/=
W
ꢇꢏ
QV
W
ꢇꢃꢉ
ꢇꢏ
QV
W
2+=
QV
$$'9
&(:
W
ꢊ
ꢉ
QV
W
QV
W
2/=
ꢐ
ꢉ
QV
$9+
&2
W
QV
W
ꢇ
QV
W
93
QV
$96
&96
W
ꢇꢏ
ꢍ
QV
W
ꢍ
QV
W
93+
ꢈꢏ
QV
%$
+=
W
QV
W
ꢈꢏ
QV
%+=
/=
186
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
tRC
VIH
Valid
Address
A[22:4]
VIL
VIH
Valid
Valid
Valid
Address Address Address
Valid
Address
A[3:0]
VIL
tPC
tAA
VIH
VIL
ADV#
tCEM
tCO
tHZ
VIH
VIL
CE#
tBA
tBHZ
VIH
VIL
LB#/UB#
tOHZ
tOE
VIH
VIL
OE#
WE#
VIH
VIL
tOLZ
tBLZ
tLZ
tAPA
tOH
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
High-Z
tCEW
High-Z
DQ[15:0]
Wait
tHZ
VIH
VIL
High-Z
Undefined
Don't Care
Figure 32.5 Page Mode Read
Table 32.8 Asynchronous Read Timing Parameters – Page Mode Operation
Symbol
Min
Max
ꢇꢏ
ꢊꢏ
ꢇꢏ
ꢍ
Units
QV
Symbol
Min
Max
ꢇꢃꢉ
ꢇꢏ
ꢍ
Units
QV
Symbol
Min
Max
Units
QV
W
W
ꢈ
W
2+
ꢉ
$$
&(:
W
QV
W
QV
W
2+=
ꢍ
QV
$3$
&2
W
QV
W
QV
W
2/=
ꢐ
QV
%$
+=
W
QV
W
ꢈꢏ
QV
W
ꢊꢏ
ꢇꢏ
QV
%+=
/=
3&
5&
W
ꢈꢏ
QV
W
ꢊꢏ
QV
W
QV
%/=
2(
W
ꢓ
V
&(0
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
187
A d v a n c e I n f o r m a t i o n
tKP
tCLK
tKP
VIH
VIL
CLK
tKHKL
tSP
tHD
VIH
VIL
Valid
Address
A[22:0]
ADV#
tSP
tHD
VIH
VIL
tHD
tCEM
tCSP
tHZ
tABA
VIH
VIL
CE#
OE#
tBOE
tOHZ
VIH
VIL
tOLZ
tSP
tHD
VIH
VIL
WE#
tSP
tHD
VIH
VIL
LB#/UB#
tCEW
High-Z
tKHTL
VOH
VOL
Wait
High-Z
tACLK
tKOH
VOH
VOL
Valid
Output
DQ[15:0]
High-Z
READ Burst Identified
(WE# = High)
Don't Care
Undefined
1RWHꢀꢁꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
Figure 32.6 Single-Access Burst Read Operation – Variable Latency
Table 32.9 Burst Read Timing Parameters – Single Access, Variable Latency
Symbol
Min
Max
ꢓꢌ
ꢋ
Units
QV
Symbol
Min
ꢓ
Max
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
W
.2+
$%$
&63
W
QV
W
ꢊ
QV
W
.3
ꢓ
QV
$&/.
+'
W
ꢊꢏ
ꢓ
QV
W
ꢍ
ꢈꢃꢍ
ꢋ
QV
W
2+=
ꢍ
QV
%2(
&(0
&(:
+=
W
W
QV
W
ꢐ
ꢐ
QV
.+./
2/=
W
ꢈ
ꢇꢃꢉ
QV
QV
W
QV
W
QV
.+7/
63
W
ꢈꢊꢃꢉ
&/.
188
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
tKP
tKP
tKHKL
tCLK
VIH
VIL
CLK
tHD
tSP
VIH
VIL
Valid
Address
A[22:0]
tHD
tSP
VIH
VIL
ADV#
CE#
tCEM
tCSP
tABA
tHD
tCBPH
VIH
VIL
tHZ
tBOE
VIH
VIL
OE#
WE#
tOHZ
tSP
tHD
tOLZ
VIH
VIL
t
SP
t
HD
VIH
VIL
LB#/UB#
Wait
tCEW
tKHTL
VOH
VOL
High-Z
High-Z
tACLK
tKOH
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
High-Z
OUTPUT
Read Burst Identified
(WE# = High)
Don't Care
Undefined
1RWHꢀꢁꢀ1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
Figure 32.7 4-Word Burst Read Operation – Variable Latency
Table 32.10 Burst Read Timing Parameters – 4-Word Burst
Symbol
Min
Max
ꢓꢌ
ꢋ
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
W
W
.2+
$%$
&/.
&63
W
QV
QV
W
ꢓ
QV
$&/.
.3
W
ꢊꢏ
QV
W
ꢊ
QV
W
2+=
ꢍ
QV
%2(
+'
W
ꢌ
ꢈ
QV
W
ꢍ
ꢈꢃꢍ
ꢋ
QV
W
2/=
ꢐ
ꢐ
QV
&%3+
+=
W
ꢓ
W
QV
W
63
QV
&(0
&(:
.+./
W
ꢇꢃꢉ
QV
W
QV
.+7/
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
189
A d v a n c e I n f o r m a t i o n
t
t
t
KP
KP
CLK
VIH
VIL
CLK
t
KHKL
t
SP
VIH
VIL
Valid
Address
A[22:0]
t
AVH
HD
t
AA
t
t
SP
VIH
VIL
ADV#
CE#
t
AADV
t
HD
t
CEM
t
t
HZ
CSP
VIH
VIL
t
CO
t
t
OHZ
BOE
VIH
VIL
OE#
WE#
t
t
OLZ
t
SP
HD
VIH
VIL
t
t
HD
SP
VIH
VIL
LB#/UB#
Wait
t
t
KHTL
CEW
VOH
High-Z
High-Z
VOL
t
t
ACLK
KOH
VOH
VOL
Valid
Output
DQ[15:0]
High-Z
Read Burst Identified
(WE# = High)
Don't Care
Undefined
Figure 32.8 Single-Access Burst Read Operation – Fixed Latency
Table 32.11 Burst Read Timing Parameters – Parameters – Single Access, Fixed Latency
Symbol
Min
Max
ꢇꢏ
ꢇꢏ
ꢋ
Units
QV
Symbol
Min
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
ꢈꢊꢃꢉ
W
.+7/
ꢋ
$$
&/.
W
QV
W
ꢇꢏ
QV
W
.2+
ꢊ
ꢓ
QV
$$'9
&2
W
QV
W
ꢓ
ꢊ
QV
W
.3
QV
$&/.
&63
W
ꢊ
ꢈ
QV
W
QV
W
2+=
ꢍ
QV
$9+
%2(
&(0
&(:
+'
W
ꢊꢏ
ꢓ
QV
W
ꢍ
QV
W
ꢐ
ꢐ
QV
+=
2/=
W
V
W
ꢈꢃꢍ
QV
W
QV
.+./
63
W
ꢇꢃꢉ
QV
190
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
191
A d v a n c e I n f o r m a t i o n
tCLK
Note 2
VIH
VIL
CLK
tSP
tHD
VIH
VIL
Valid
Address
Valid
A[22:0]
Address
tHD
tSP
VIH
VIL
ADV#
CE#
tCEM
tCBPH
tHZ
tCSP
VIH
VIL
tOHZ
tOHZ
Note 3
VIH
VIL
OE#
WE#
tSP tHD
VIH
VIL
tSP
tHD
VIH
VIL
LB#/UB#
Wait
tBOE
VOH
VOL
tOLZ
High-Z
tKOH
High-Z
tBOE
tOLZ
VOH
VOL
Valid
Valid
Output
Valid
Output
Valid
Valid
Valid
High-Z
DQ[15:0]
Output
Output
Output
Output
tACLK
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀ5HDGꢀEXUVWꢀVXVSHQGꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢓꢀODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ
/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ &/.ꢀFDQꢀEHꢀVWRSSHGꢀ/RZꢀRUꢀ+LJKꢄꢀEXWꢀPXVWꢀEHꢀVWDWLFꢄꢀZLWKꢀQRꢀ/RZꢇWRꢇ+LJKꢀWUDQVLWLRQVꢀGXULQJꢀEXUVWꢀVXVSHQGꢆ
ꢊꢆ 2(-ꢀFDQꢀVWD\ꢀ/RZꢀGXULQJꢀEXUVWꢀVXVSHQGꢆꢀ,Iꢀ2(-ꢀLVꢀ/RZꢄꢀ'4>ꢅꢌꢔꢁ@ꢀFRQWLQXHVꢀWRꢀRXWSXWꢀYDOLGꢀGDWDꢆ
Figure 32.10 Read Burst Suspend
Table 32.13 Burst Read Timing Parameters – Burst Suspend
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
W
W
ꢊ
$&/.
&/.
&63
.2+
2+=
W
ꢊꢏ
QV
QV
ꢍ
QV
%2(
W
ꢌ
QV
W
ꢊ
QV
W
2/=
ꢐ
ꢐ
QV
&%3+
+'
W
ꢓ
V
W
ꢍ
QV
W
63
QV
&(0
+=
192
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
VIH
VIL
CLK
tCLK
VIH
VIL
A[22:0]
ADV#
VIH
VIL
VIH
VIL
LB#/UB#
CE#
VIH
VIL
Note 2
VIH
VIL
OE#
WE#
VIH
VIL
tKHTL
tKHTL
VOH
VOL
Wait
Note 3
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
tKOH
tACLK
End of Row
Don't Care
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀFRQWLQXRXVꢀEXUVWꢀ5HDGꢄꢀ%&5>ꢎ@ꢀ ꢀꢁꢔꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ'RꢀQRWꢀ
FURVVꢀURZꢀERXQGDULHVꢀZLWKꢀIL[HGꢀODWHQF\ꢆ
ꢈꢆ &(-ꢀPXVWꢀQRWꢀUHPDLQꢀ/RZꢀORQJHUꢀWKDQꢀW
ꢆ
&(0
ꢊꢆ :DLWꢀDVVHUWVꢀIRUꢀDQ\ZKHUHꢀIURPꢀ/&ꢀWRꢀꢈ/&ꢀF\FOHVꢆꢀ/&ꢀ ꢀ/DWHQF\ꢀ&RGHꢀꢂ%&5>ꢅꢊꢔꢅꢅ@ꢃꢆ
Figure 32.11 Continuous Burst Read Showing an Output Delay
with BCR[8] = 0 for Variable Latency End-of-Row Condition
Table 32.14 Burst Read Timing Parameters – BCR[8] = 0
Symbol
Min
Max
Units
QV
Symbol
Min
Max
Units
QV
W
ꢋ
W
ꢋ
$&/.
.+7/
W
ꢈꢊꢃꢉ
QV
W
ꢊ
QV
&/.
.2+
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
193
A d v a n c e I n f o r m a t i o n
tWC
VIH
VIL
A[22:0]
Valid Address
tAW
tAS
tWR
VIH
VIL
ADV#
CE#
tCW
tCPH
VIH
VIL
t
BW
VIH
VIL
LB#/UB#
OE#
VIH
VIL
tWPH
tWP
VIH
VIL
WE#
tDW
tDH
VIH
VIL
DQ[15:0]
In
High-Z
Valid Input
tWHZ
tLZ
VOH
VOL
DQ[15:0]
Out
tCEW
High-Z
tHZ
VIH
VIL
High-Z
Wait
Don't Care
Figure 32.12 CE#-Controlled Asynchronous Write
Table 32.15 Asynchronous Write Timing Parameters – CE#-Controlled
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢇꢏ
ꢏ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
:&
ꢇꢏ
$6
&:
W
W
ꢇꢏ
ꢇꢏ
ꢈ
QV
W
QV
W
:+=
ꢍ
QV
$:
%:
'+
QV
W
ꢊꢏ
QV
W
ꢓꢉ
ꢈꢏ
ꢏ
QV
':
:3
W
ꢇꢃꢉ
QV
W
ꢍ
QV
W
:3+
QV
&(:
+=
W
ꢉ
QV
W
ꢈꢏ
QV
W
:5
QV
&3+
/=
194
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
tWC
VIH
A[22:0]
Valid Address
tAW
VIL
tWR
tAS
VIH
VIL
ADV#
CE#
tCW
tCPH
VIH
VIL
tBW
VIH
VIL
LB#/UB#
OE#
VIH
VIL
tWPH
tWP
VIH
VIL
WE#
tDW
tDH
VIH
VIL
DQ[15:0]
In
High-Z
Valid Input
tLZ
tWHZ
VOH
VOL
DQ[15:0]
Out
tCEW
High-Z
tHZ
VIH
VIL
Wait
High-Z
Don't Care
Figure 32.13 LB#/UB#-Controlled Asynchronous Write
Table 32.16 Asynchronous Write Timing Parameters – LB#/UB#-Controlled
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
:+=
ꢍ
$6
'+
W
W
ꢇꢏ
ꢇꢏ
ꢈ
QV
W
ꢊꢏ
QV
W
:3
ꢓꢉ
ꢈꢏ
ꢏ
QV
$:
%:
':
QV
W
ꢍ
QV
W
QV
+=
:3+
W
ꢇꢃꢉ
QV
W
ꢈꢏ
ꢇꢏ
QV
W
:5
QV
&(:
/=
W
ꢇꢏ
QV
W
QV
&:
:&
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
195
A d v a n c e I n f o r m a t i o n
tWC
VIH
VIL
A[22:0]
ADV#
Valid Address
tAW
tWR
VIH
VIL
tCW
VIH
VIL
CE#
tBW
VIH
VIL
LB#/UB#
OE#
VIH
VIL
tAS
tWPH
tWP
VIH
VIL
WE#
tDH
tDW
VIH
VIL
DQ[15:0]
In
High-Z
Valid Input
tOW
tWHZ
tLZ
VOH
VOL
DQ[15:0]
Out
tCEW
High-Z
tHZ
VIH
VIL
High-Z
Wait
Don't Care
Figure 32.14 WE#-Controlled Asynchronous Write
Table 32.17 Asynchronous Write Timing Parameters – WE#-Controlled
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
:&
ꢇꢏ
$6
'+
W
ꢇꢏ
ꢇꢏ
ꢈ
QV
W
ꢊꢏ
QV
W
:+=
ꢍ
QV
$:
%:
':
W
QV
W
ꢍ
QV
W
ꢓꢉ
ꢈꢏ
ꢏ
QV
+=
:3
W
ꢇꢃꢉ
QV
W
ꢈꢏ
ꢉ
QV
W
:3+
QV
&(:
/=
W
ꢇꢏ
QV
W
QV
W
:5
QV
&:
2:
196
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
VIH
A[22:0]
Valid Address
tAVH
VIL
tAVS
tVS
tVPH
tVP
tAS
VIH
VIL
ADV#
CE#
tAS
tAW
tCW
VIH
VIL
tBW
VIH
VIL
LB#/UB#
OE#
VIH
VIL
tWPH
tWP
VIH
VIL
WE#
tDW
Valid Input
tOW
tDH
VIH
VIL
DQ[15:0]
IN
High-Z
tWHZ
tLZ
VOH
VOL
DQ[15:0]
OUT
tCEW
High-Z
tHZ
VIH
VIL
Wait
High-Z
Don't Care
Figure 32.15 Asynchronous Write Using ADV#
Table 32.18 Asynchronous Write Timing Parameters Using ADV#
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢇꢏ
ꢏ
Max
Units
QV
Symbol
Min
ꢈꢏ
ꢈꢏ
ꢇꢏ
Max
Units
QV
W
W
W
93
$6
&:
W
ꢊ
QV
W
QV
W
93+
QV
$9+
'+
W
ꢉ
QV
W
ꢊꢏ
QV
W
QV
$96
':
96
W
ꢇꢏ
ꢇꢏ
ꢈ
QV
W
ꢍ
QV
W
ꢍ
QV
$:
+=
:+=
W
QV
W
ꢈꢏ
ꢉ
QV
W
ꢓꢉ
ꢈꢏ
QV
%:
/=
:3
W
ꢇꢃꢉ
QV
W
QV
W
:3+
QV
&(:
2:
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
197
A d v a n c e I n f o r m a t i o n
tCLK
tKP
tKP
tKHKL
VIH
VIL
CLK
tSP
tHD
VIH
VIL
A[22:0]
Valid
Address
3
tAS
tKADV
tSP
tHD
VIH
VIL
ADV#
3
tAS
tSP tHD
VIH
VIL
LB#/UB#
tCEM
tCSP
tHD
tCBPH
VIH
VIL
CE#
OE#
WE#
VIH
VIL
tSP tHD
VIH
VIL
tKHTL
tCEW
tHZ
VOH
VOL
Wait
High-Z
High-Z
Note 2
t
t
HD
SP
VIH
VIL
DQ[15:0]
D[1]
D[2]
D[3]
D[0]
Write Burst Identified
(WE# = Low)
Don't Care
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ:ULWHꢀRSHUDWLRQꢀLQꢀYDULDEOHꢀODWHQF\ꢀPRGHꢔꢀ/DWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ
/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢓꢀEXUVWꢀOHQJWKꢀIRXUꢓꢀEXUVWꢀZUDSꢀHQDEOHGꢆ
ꢈꢆ :DLWꢀDVVHUWVꢀIRUꢀ/&ꢀF\FOHVꢀIRUꢀERWKꢀIL[HGꢀDQGꢀYDULDEOHꢀODWHQF\ꢆꢀ/&ꢀ ꢀ/DWHQF\ꢀ&RGHꢀꢂ%&5>ꢅꢊꢔꢅꢅ@ꢃꢆ
ꢊꢆ
W
ꢀUHTXLUHGꢀLIꢀW
ꢀ!ꢀꢈꢁꢀQVꢆ
$6
&63
Figure 32.16 Burst Write Operation – Variable Latency Mode
Table 32.19 Burst Write Timing Parameters – Variable Latency Mode
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢓ
Max
Units
QV
Symbol
Min
Max
ꢈꢃꢍ
ꢋ
Units
QV
W
W
W
.+./
$6
&63
W
ꢌ
QV
W
ꢊ
QV
W
.+7/
QV
&%3+
+'
W
ꢓ
V
W
ꢍ
QV
W
W
ꢓ
ꢐ
QV
&(0
+=
.3
63
W
ꢈ
ꢇꢃꢉ
QV
W
ꢌ
QV
QV
&(:
.$'9
W
ꢈꢊꢃꢉ
QV
&/.
198
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
tCLK
tKP
tKP
tKHKL
VIH
VIL
CLK
tSP
VIH
VIL
A[22:0]
Valid
Address
3
tAS
tAVH
tKADV
tSP tHD
VIH
VIL
ADV#
3
tAS
tSP tHD
VIH
VIL
LB#/UB#
tCEM
tCSP
tHD
tCBPH
VIH
VIL
CE#
OE#
VIH
VIL
tSP tHD
VIH
VIL
WE#
Wait
tKHTL
tCEW
tHZ
VOH
VOL
High-Z
High-Z
NOTE2
tSP
tHD
D[1]
VIH
VIL
DQ[15:0]
D[2]
D[3]
D[0]
Write Burst Identified
(WE# = Low)
Don't Care
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ:ULWHꢀRSHUDWLRQꢀLQꢀIL[HGꢀODWHQF\ꢀPRGHꢔꢀ)L[HGꢀODWHQF\ꢓꢀODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ
:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢓꢀEXUVWꢀOHQJWKꢀIRXUꢓꢀEXUVWꢀZUDSꢀHQDEOHGꢆ
ꢈꢆ :DLWꢀDVVHUWVꢀIRUꢀ/&ꢀF\FOHVꢀIRUꢀERWKꢀIL[HGꢀDQGꢀYDULDEOHꢀODWHQF\ꢆꢀ/&ꢀ ꢀ/DWHQF\ꢀ&RGHꢀꢂ%&5>ꢅꢊꢔꢅꢅ@ꢃꢆ
ꢊꢆ
W
ꢀUHTXLUHGꢀLIꢀW
ꢀ!ꢀꢈꢁQVꢆ
$6
&63
Figure 32.17 Burst Write Operation – Fixed Latency Mode
Table 32.20 Burst Write Timing Parameters – Fixed Latency Mode
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
Max
ꢈꢃꢍ
ꢋ
Units
QV
W
W
W
W
W
.+./
$6
$6
&/.
&63
ꢊ
QV
QV
W
QV
.+7/
W
ꢌ
QV
W
ꢊ
QV
W
W
ꢓ
ꢐ
QV
&%3+
+'
.3
W
ꢓ
V
W
ꢍ
QV
QV
&(0
&(:
+=
63
W
ꢈ
ꢇꢃꢉ
QV
W
ꢌ
QV
.$'9
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
199
A d v a n c e I n f o r m a t i o n
VIH
VIL
CLK
t
CLK
VIH
VIL
A[22:0]
VIH
VIL
ADV#
VIH
VIL
LB#/UB#
VIH
VIL
CE#
Note 2
VIH
VIL
WE#
VIH
VIL
OE#
Wait
t
t
KHTL
KHTL
VOH
VOL
Note 3
t
t
HD
SP
VIH
VIL
DQ[15:0]
Valid Input Valid Input
Valid Input
Valid Input
End of Row
Start of Row
(A[6:0] = 7Fh) (A[6:0] = 00h)
(Note 4)
Don't Care
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀFRQWLQXRXVꢀEXUVWꢀ:ULWHꢄꢀ%&5>ꢎ@ꢀ ꢀꢁꢔꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ'RꢀQRWꢀ
FURVVꢀURZꢀERXQGDULHVꢀZLWKꢀIL[HGꢀODWHQF\ꢆ
ꢈꢆ &(-ꢀPXVWꢀQRWꢀUHPDLQꢀ/RZꢀORQJHUꢀWKDQꢀW
ꢆ
&(0
ꢊꢆ :DLWꢀDVVHUWVꢀIRUꢀDQ\ZKHUHꢀIURPꢀ/&ꢀWRꢀꢈ/&ꢀF\FOHVꢆꢀ/&ꢀ ꢀ/DWHQF\ꢀ&RGHꢀꢂ%&5>ꢅꢊꢔꢅꢅ@ꢃꢆ
ꢍꢆ 7DNLQJꢀ&(-ꢀ+LJKꢀRUꢀ$'9-ꢀ/RZꢀRQꢀWKHꢀVWDUWꢇRIꢇURZꢀF\FOHꢀDERUWVꢀWKHꢀEXUVWꢀDQGꢀQRWꢀZULWHꢀWKHꢀVWDUWꢇRIꢇURZꢀGDWDꢆꢀ'HYLFHVꢀ
IURPꢀGLIIHUHQWꢀ&HOOXODU5$0ꢀYHQGRUVꢀFDQꢀDVVHUWꢀ:DLWꢀVRꢀWKDWꢀWKHꢀVWDUWꢇRIꢇURZꢀGDWDꢀLVꢀLQSXWꢀMXVWꢀEHIRUHꢀꢂDVꢀVKRZQꢃꢄꢀRUꢀMXVWꢀ
DIWHUꢀ:DLWꢀDVVHUWVꢆꢀ7KLVꢀGLIIHUHQFHꢀLQꢀEHKDYLRUꢀLVꢀQRWꢀQRWLFHGꢀE\ꢀFRQWUROOHUVꢀWKDWꢀPRQLWRUꢀ:DLWꢄꢀRUꢀWKDWꢀXVHꢀ:DLWꢀWRꢀDERUWꢀ
RQꢀWKHꢀVWDUWꢇRIꢇURZꢀLQSXWꢀF\FOHꢆ
Figure 32.18 Continuous Burst Write Showing an Output Delay
with BCR[8] = 0 for Variable Latency End-of-Row Condition
Table 32.21 Burst Write Timing Parameters – BCR[8] = 0
Symbol
Min
ꢈꢊꢃꢉ
ꢊ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
ꢍ
&/.
.+7/
W
QV
W
ꢐ
QV
+'
63
200
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
VIH
VIL
CLK
t
t
t
HD
t
t
t
SP
SP HD
VIH
VIL
A[22:0]
Valid
Address
Valid
Address
t
t
t
HD
SP HD
KADV
SP
VIH
VIL
ADV#
(Note 3)
t t
SP HD
VIH
VIL
LB#/UB#
t
CSP
t
CBPH
t
HD
VIH
VIL
CE#
OE#
WE#
(Note 2)
t
t
CSP
OHZ
VIH
VIL
t
t
SP HD
VIH
VIL
t
t
SP HD
VOH
VOL
t
BOE
Wait
High-Z
High-Z
t
t
SP HD
t
KOH
t
ACLK
DQ[15:0] VIH
In/Out
VIL
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
High-Z
High-Z
D[0]
D[1]
D[2]
D[3]
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ:ULWHꢀIROORZHGꢀE\ꢀEXUVWꢀ5HDGꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢓꢀODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀ
FORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ $ꢀUHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀ
&(0
FRQGLWLRQVꢔꢀDꢃꢀFORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀEꢃꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀꢅꢌQVꢆꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀEHWZHHQꢀEXUVWꢀ5HDGꢀDQGꢀEXUVWꢀ
:ULWHꢀRSHUDWLRQVꢄꢀEXWꢀ&(-ꢀPXVWꢀQRWꢀUHPDLQꢀ/RZꢀORQJHUꢀWKDQꢀW ꢆꢀ6HHꢀEXUVWꢀLQWHUUXSWꢀGLDJUDPVꢀꢂ)LJXUHꢀꢊꢈꢆꢈꢅꢄꢀ
&(0
)LJXUHꢀꢊꢈꢆꢈꢈꢄꢀDQGꢀ)LJXUHꢀꢊꢈꢆꢈꢊꢃꢀIRUꢀFDVHVꢀZKHUHꢀ&(-ꢀVWD\Vꢀ/RZꢀEHWZHHQꢀEXUVWVꢆ
ꢊꢆ 2QO\ꢀIL[HGꢀODWHQF\ꢀUHTXLUHVꢀW
ꢆ
.$'9
Figure 32.19 Burst Write Followed by Burst Read
Table 32.22 Write Timing Parameters – Burst Write Followed by Burst Read
Symbol
Min
ꢌ
Max
Units
QV
Symbol
Min
ꢊ
Max
Units
W
W
QV
&%3+
+'
W
W
ꢈꢊꢃꢉ
ꢓ
ꢊꢏ
ꢊꢏ
QV
W
ꢌ
&/.
.$'9
QV
W
ꢐ
QV
&63
63
Table 32.23 Read Timing Parameters – Burst Write Followed by Burst Read
Symbol
Min
Max
ꢋ
Units
Symbol
Min
ꢊ
Max
Units
QV
W
W
+'
$&/.
W
ꢊꢏ
QV
QV
QV
W
W
ꢊ
QV
%2(
.2+
2+=
W
ꢈꢊꢃꢉ
ꢓ
ꢍ
QV
&/.
W
W
ꢐ
QV
&63
63
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
201
A d v a n c e I n f o r m a t i o n
t
CLK
Read Burst interrupted with new Read or Write. See Note 2.
VIH
VIL
CLK
t
SP
t
HD
t
SP
t
HD
VIH
VIL
Valid
Address
Valid
Address
A[22:0]
ADV#
CE#
t
t
HD
t
t
HD
SP
SP
VIH
VIL
t
CEM (Note3)
t
CSP
t
HD
VIH
VIL
t t
SP HD
t
t
SP HD
VIH
VIL
WE#
t
KHTL
VOH
VOL
t
t
BOE
BOE
WAIT
Note 4
t
High-Z
t
OHZ
OHZ
V
OE#
2nd Cycle Read
t
CEW
IH
VIL
VIH
VIL
LB#/UB#
2nd Cycle Read
t
t
KOH
KOH
t
ACLK
VOH
DQ[15:0] Out
2nd Cycle Read
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
High-Z
High-Z
OL
t
ACLK
VIH
OE#
2nd Cycle Write VIL
VIH
VIL
LB#/UB#
2nd Cycle Write
t
SP
t
HD
VIH
VIL
DQ[15:0] In
2nd Cycle Write
High-Z
D[0]
D[1]
D[2]
D[3]
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ5HDGꢀLQWHUUXSWHGꢀE\ꢀEXUVWꢀ5HDGꢀRUꢀ:ULWHꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀ
FORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/2:ꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ$OOꢀEXUVWVꢀVKRZQꢀIRUꢀYDULDEOHꢀODWHQF\ꢓꢀQRꢀUHIUHVKꢀFROOLVLRQꢆ
ꢈꢆ %XUVWꢀLQWHUUXSWꢀVKRZQꢀRQꢀILUVWꢀDOORZDEOHꢀFORFNꢀꢂIRUꢀH[DPSOHꢄꢀDIWHUꢀWKHꢀILUVWꢀGDWDꢀUHFHLYHGꢀE\ꢀFRQWUROOHUꢃꢆ
ꢊꢆ &(-ꢀFDQꢀVWD\ꢀ/2:ꢀEHWZHHQꢀEXUVWꢀRSHUDWLRQVꢄꢀEXWꢀ&(-ꢀPXVWꢀQRWꢀUHPDLQꢀ/RZꢀORQJHUꢀWKDQꢀW
ꢆ
&(0
ꢍꢆ )RUꢀYDULDEOHꢀODWHQF\ꢄꢀ:DLWꢀDVVHUWVꢀWNKWOꢀDIWHUꢀ$'9-ꢀLVꢀFORFNHGꢀ/RZꢆꢀ)RUꢀIL[HGꢀODWHQF\ꢄꢀ:DLWꢀDVVHUWVꢀW
WUDQVLWLRQVꢀ/RZꢆ
ꢀDIWHUꢀ$'9-ꢀ
&(:
Figure 32.20 Burst Read Interrupted by Burst Read or Write
Table 32.24 Read Timing Parameters – Burst Write Interrupted
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
Max
Units
W
W
ꢊ
QV
$&/.
+'
W
ꢊꢏ
ꢇꢃꢉ
QV
W
.+7/
ꢋ
%2(
W
ꢈ
ꢈꢊꢃꢉ
ꢓ
QV
W
ꢊ
ꢐ
QV
QV
QV
&(:
.2+
2+=
W
QV
W
ꢍ
&/.
&63
W
QV
W
63
Table 32.25 Write Timing Parameters – Burst Write Interrupted
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
ꢊꢏ
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
W
+'
&/.
&63
ꢊꢏ
QV
W
ꢐ
QV
63
202
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
Write Burst interrupted with new Write or Read. See Note 2.
t
CLK
VIH
VIL
CLK
t
t
t
HD
t
t
t
SP
SP HD
VIH
VIL
A[22:0]
Valid
Address
Valid
Address
t
HD
t
HD
SP
SP
VIH
VIL
ADV#
CE#
t
CEM
(Note 3)
t
t
HD
VIH
VIL
CSP
t
t
SP HD
t
t
SP HD
VIH
VIL
WE#
t
KHTL
VOH
VOL
WAIT
High-Z
High-Z
OE# VIH
2nd Cycle Write
VIL
t t
SP HD
VIH
VIL
LB#/UB#
2nd Cycle Write
t
t
SP HD
t
SP
t
HD
VIH
VIL
DQ[15:0] IN
2nd Cycle Write
High-Z
D[0]
D[0]
D[1]
D[2]
D[3]
t
OHZ
t
BOE
V
OE#
2nd Cycle Read
IH
VIL
t
SP
t
HD
V
LB#/UB#
2nd Cycle Read
IH
VIL
t
KOH
t
ACLK
V
V
DQ[15:0] OUT
2nd Cycle Read
OH
OHHigh-Z
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
VOL
Don’t Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ:ULWHꢀLQWHUUXSWHGꢀE\ꢀEXUVWꢀ:ULWHꢀRUꢀ5HDGꢀLQꢀYDULDEOHꢀODWHQF\ꢀPRGHꢔꢀ9DULDEOHꢀODWHQF\ꢓꢀ
ODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆꢀ$OOꢀEXUVWVꢀVKRZQꢀIRUꢀYDULDEOHꢀODWHQF\ꢓꢀQRꢀ
UHIUHVKꢀFROOLVLRQꢆ
ꢈꢆ %XUVWꢀLQWHUUXSWꢀVKRZQꢀRQꢀILUVWꢀDOORZDEOHꢀFORFNꢀꢂVXFKꢀDVꢄꢀDIWHUꢀILUVWꢀGDWDꢀZRUGꢀZULWWHQꢃꢆ
ꢊꢆ &(-ꢀFDQꢀVWD\ꢀ/RZꢀEHWZHHQꢀEXUVWꢀRSHUDWLRQVꢄꢀEXWꢀ&(-ꢀPXVWꢀQRWꢀUHPDLQꢀ/RZꢀORQJHUꢀWKDQꢀW
ꢆ
&(0
Figure 32.21 Burst Write Interrupted by Burst Write or Read – Variable Latency Mode
Table 32.26 Write Timing Parameters – Burst Read Interrupted – Variable Latency Mode
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
ꢊꢏ
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
ꢋ
&/.
&63
.+7/
ꢊꢏ
QV
W
ꢐ
QV
63
W
ꢊ
QV
+'
Table 32.27 Read Timing Parameters – Burst Read Interrupted – Variable Latency Mode
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
+'
$&/.
W
ꢊꢏ
QV
W
W
ꢊ
QV
%2(
.2+
2+=
W
ꢈꢊꢃꢉ
ꢓ
QV
ꢍ
QV
&/.
W
QV
W
ꢐ
QV
&63
63
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
203
A d v a n c e I n f o r m a t i o n
Write Burst interrupted with new Write or Read See Note 2.
t
CLK
VIH
VIL
CLK
t
SP
t
HD
t
t
SP HD
VIH
VIL
A[22:0]
Valid Address
Valid Address
t
SP
t
HD
t
SP
t
HD
VIH
VIL
ADV#
CE#
t
CEM
(Note 3)
t
t
HD
VIH
VIL
CSP
t
t
SP HD
t
t
SP HD
VIH
VIL
WE#
Wait
t
KHTL
VOH
VOL
High-Z
High-Z
OE# VIH
2nd Cycle Write
VIL
t t
SP HD
VIH
VIL
LB#/UB#
2nd Cycle Write
t
t
t
SP
t
HD
SP HD
VIH
VIL
DQ[15:0] In
2nd Cycle Write
High-Z
D[0]
D[0]
D[1]
D[2]
D[3]
t
OHZ
t
BOE
VIH
VIL
OE#
2nd Cycle Read
t
SP
t
HD
VIH
VIL
LB#/UB#
2nd Cycle Read
t
KOH
t
ACLK
VOH
VOL
V
DQ[15:0] Out
2nd Cycle Read
OHHigh-Z
VOL
Valid Output
Valid Output
Valid Output
Valid Output
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ:ULWHꢀLQWHUUXSWHGꢀE\ꢀEXUVWꢀ:ULWHꢀRUꢀ5HDGꢀLQꢀIL[HGꢀODWHQF\ꢀPRGHꢔꢀ)L[HGꢀODWHQF\ꢓꢀODWHQF\ꢀ
FRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ %XUVWꢀLQWHUUXSWꢀVKRZQꢀRQꢀILUVWꢀDOORZDEOHꢀFORFNꢀꢂLꢆHꢆꢄꢀDIWHUꢀILUVWꢀGDWDꢀZRUGꢀZULWWHQꢃꢆ
ꢊꢆ &(-ꢀFDQꢀVWD\ꢀ/RZꢀEHWZHHQꢀEXUVWꢀRSHUDWLRQVꢄꢀEXWꢀ&(-ꢀPXVWꢀQRWꢀUHPDLQꢀ/RZꢀORQJHUꢀWKDQꢀW
ꢆ
&(0
Figure 32.22 Burst Write Interrupted by Burst Write or Read – Fixed Latency Mode
Table 32.28 Write Timing Parameters – Burst Read Interrupted – Fixed Latency Mode
Symbol
Min
ꢊ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
ꢌ
$9+
.$'9
W
ꢈꢊꢃꢉ
ꢓ
ꢊꢏ
QV
W
ꢋ
QV
&/.
&63
.+7/
W
ꢊꢏꢀ
QV
W
ꢐ
QV
63
W
ꢊ
QV
+'
Table 32.29 Read Timing Parameters – Burst Read Interrupted – Fixed Latency Mode
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
+'
$&/.
W
ꢊꢏ
QV
W
W
ꢊ
QV
%2(
.2+
2+=
W
ꢈꢊꢃꢉ
ꢓ
QV
ꢍ
QV
&/.
W
QV
W
ꢐ
QV
&63
63
204
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
VIH
VIL
CLK
A[22:0]
ADV#
t
t
t
t
SP
WC
WC
HD
VIH
VIL
Valid Address
Valid Address
Valid Address
t
t
t
t
WR
AVS
AVH
AW
t
t
t
HD
VPH
SP
VIH
VIL
t
t
VP
VS
t
t
SP
VIH
VIL
HD
t
BW
LB#/UB#
CE#
t
CVS
t
t
CSP
CBPH
t
VIH
VIL
CW
Note 2
t
AS
t
OHZ
VIH
VIL
OE#
t
t
WC
t
t
t
t
WP
SP HD
AS
WPH
VIH
VIL
WE#
t
CEW
VOH
VOL
High-Z
t
BOE
WAIT
t
KOH
t
ACLK
DQ[15:0] VIH
IN/OUT VIL
VOH
VOL
High-Z
Data
t
Data
High-Z
Valid Output Valid Output Valid Output Valid Output
t
DH
DW
Don’t Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀDV\QFKURQRXVꢀ:ULWHꢀIROORZHGꢀE\ꢀEXUVWꢀ5HDGꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢓꢀODWHQF\ꢀFRGHꢀWZRꢀ
ꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀ
ZKHQꢀWUDQVLWLRQLQJꢀWRꢀIL[HGꢇODWHQF\ꢀEXUVWꢀ5HDGVꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀ
&(0
RSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀFRQGLWLRQVꢔꢀDꢃꢀFORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀEꢃꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀ
ꢅꢌQVꢆ
Figure 32.23 Asynchronous Write Followed by Burst Read
Table 32.30 Write Timing Parameters – Asynchronous Write Followed by Burst Read
Symbol
Min
ꢊ
Max
Units
QV
Symbol
Min
ꢇꢏ
ꢏ
Max
Units
QV
Symbol
Min
ꢇꢏ
ꢇꢏ
ꢓꢉ
ꢈꢏ
ꢏ
Max
Units
QV
W
W
W
96
$9+
&:
W
ꢏ
QV
W
QV
W
:&
QV
$6
'+
W
ꢉ
QV
W
ꢊꢏ
ꢉ
QV
W
:3
QV
$96
':
W
ꢇꢏ
ꢇꢏ
ꢇ
QV
W
QV
W
:3+
QV
$:
%:
93
W
QV
W
ꢈꢏ
ꢍ
QV
W
QV
93+
:5
W
QV
&96
Table 32.31 Read Timing Parameters – Asynchronous Write Followed by Burst Read
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
W
W
ꢊ
$&/.
&/.
&63
.2+
2+=
W
ꢊꢏ
QV
QV
ꢍ
QV
%2(
W
ꢌ
ꢈ
QV
W
ꢊ
QV
W
63
ꢐ
QV
&%3+
+'
W
ꢇꢃꢉ
QV
&(:
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
205
A d v a n c e I n f o r m a t i o n
t
CLK
VIH
VIL
CLK
t
t
t
t
HD
WC
WC
SP
VIH
VIL
A[22:0]
Valid Address
Valid Address
Valid Address
t
t
WR
AW
t
t
HD
SP
VIH
VIL
ADV#
t
HD
t
t
BW
SP
VIH
VIL
LB#/UB#
t
t
CSP
t
CW
CBPH
VIH
VIL
CE#
OE#
Note 2
t
OHZ
VIH
VIL
t
WC
t
t
t t
SP HD
WP
WPH
VIH
VIL
WE#
Wait
t
VOH
VOL
t
BOE
CEW
High-Z
t
KOH
t
ACLK
VIH
VIL
DQ[15:0]
IN/OUT
VOH
VOL
High-Z
Data
Data
High-Z
Valid Output Valid Output Valid Output Valid Output
t
t
DH
DW
Don’t Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀDV\QFKURQRXVꢀ:ULWHꢄꢀZLWKꢀ$'9-ꢀ/RZꢄꢀIROORZHGꢀE\ꢀEXUVWꢀ5HDGꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢓꢀ
ODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀ
ZKHQꢀWUDQVLWLRQLQJꢀWRꢀIL[HGꢇODWHQF\ꢀEXUVWꢀ5HDGVꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀ
&(0
RSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀFRQGLWLRQVꢔꢀDꢃꢀFORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀEꢃꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀ
ꢅꢌꢀQVꢆ
Figure 32.24 Asynchronous Write (ADV# Low) Followed By Burst Read
Table 32.32 Asynchronous Write Timing Parameters – ADV# Low
Symbol
Min
ꢇꢏ
ꢇꢏ
ꢇꢏ
Max
Units
QV
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢓꢉ
ꢈꢏ
ꢏ
Max
Units
QV
W
W
W
W
W
:3
$:
%:
&:
'+
QV
W
ꢊꢏ
ꢇꢏ
QV
W
QV
':
:3+
:35
QV
W
QV
W
QV
:&
Table 32.33 Burst Read Timing Parameters
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
W
W
ꢊ
$&/.
&/.
&63
.2+
2+=
W
ꢊꢏ
QV
QV
ꢍ
QV
%2(
W
ꢌ
ꢈ
QV
W
ꢊ
QV
W
63
ꢐ
QV
&%3+
+'
W
ꢇꢃꢉ
QV
&(:
206
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
VIH
CLK
VIL
t
t
WC
t
SP
HD
VIH
A[22:0]
Valid Address
Valid Address
VIL
t
t
WR
t
t
HD
AW
SP
VIH
ADV#
CE#
VIL
t
t
CBPH
HD
t
t
HZ
CSP
VIH
VIL
t
CW
Note 2
t
OHZ
t
BOE
VIH
OE#
WE#
t
AS
VIL
t
t
HD
t
t
t
WPH
SP
OLZ
WP
VIH
VIL
t
t
t
BW
SP
HD
VIH
LB#/UB#
Wait
VIL
t
t
t
CEW
CEW
KHTL
t
HZ
VOH
VOL
High-Z
t
DH
t
t
DW
KOH
t
ACLK
VOH
VOL
VIH
VIL
Valid
Output
DQ[15:0]
High-Z
Valid Output
Read Burst Identified
(WE# = High)
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ5HDGꢀIROORZHGꢀE\ꢀDV\QFKURQRXVꢀ:(-ꢇFRQWUROOHGꢀ:ULWHꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢓꢀ
ODWHQF\ꢀFRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ :KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ&(-ꢀFDQꢀVWD\ꢀ/RZꢀ
ZKHQꢀWUDQVLWLRQLQJꢀIURPꢀIL[HGꢇODWHQF\ꢀEXUVWꢀ5HDGVꢓꢀDV\QFKURQRXVꢀRSHUDWLRQꢀEHJLQVꢀDWꢀWKHꢀIDOOLQJꢀHGJHꢀRIꢀ$'9-ꢆꢀ$ꢀUHIUHVKꢀ
RSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
FORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀEꢃꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀꢅꢌꢀQVꢆ
ꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀFRQGLWLRQVꢔꢀDꢃꢀ
&(0
Figure 32.25 Burst Read Followed by Asynchronous Write (WE#-Controlled)
Table 32.34 Burst Read Timing Parameters
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
W
W
.+7/
ꢋ
$&/.
&/.
&63
W
ꢊꢏ
QV
QV
W
QV
%2(
.2+
2+=
W
ꢌ
ꢈ
QV
W
ꢊ
QV
W
ꢍ
QV
&%3+
+'
W
ꢇꢃꢉ
QV
W
ꢍ
W
63
ꢐ
&(:
+'=
Table 32.35 Asynchronous Write Timing Parameters – WE#-Controlled
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢓꢉ
ꢈꢏ
ꢏ
Max
Units
QV
W
W
W
:3
$6
'+
W
W
W
ꢇꢏ
ꢇꢏ
ꢇꢏ
QV
W
ꢊꢏ
QV
W
QV
$:
%:
&:
':
:3+
:35
QV
W
ꢍ
QV
W
QV
+=
QV
W
ꢇꢏ
QV
:&
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
207
A d v a n c e I n f o r m a t i o n
t
CLK
VIH
CLK
VIL
t
t
HD
SP
VIH
A[22:0]
Valid Address
Valid Address
VIL
t
t
AVH
AVS
t
t
t
t
VS
SP
HD
VPH
t
VIH
VIL
VP
ADV#
CE#
t
AW
t
t
t
AS
HD
CBPH
t
t
CSP
t
CW
HZ
VIH
Note
OHZ
2
VIL
t
t
BOE
VIH
OE#
WE#
VIL
t
AS
t
SP
t
t
t
t
WPH
HD
OLZ
WP
VIH
VIL
VIH
t
t
BW
t
HD
SP
LB#/UB#
VIL
t
t
KHTL
t
CEW
CEW
t
HZ
VOH
VOL
Wait
High-Z
t
t
DH
t
t
DW
ACLK
KOH
VOH
VOL
VIH
VIL
Valid
Output
DQ[15:0]
High-Z
Valid Output
Read Burst Identified
(WE# = High)
Don't Care
Undefined
1RWHVꢀ
ꢅꢆ 1RQꢇGHIDXOWꢀ%&5ꢀVHWWLQJVꢀIRUꢀEXUVWꢀ5HDGꢀIROORZHGꢀE\ꢀDV\QFKURQRXVꢀ:ULWHꢀXVLQJꢀ$'9-ꢔꢀ)L[HGꢀRUꢀYDULDEOHꢀODWHQF\ꢓꢀODWHQF\ꢀ
FRGHꢀWZRꢀꢂWKUHHꢀFORFNVꢃꢓꢀ:DLWꢀDFWLYHꢀ/RZꢓꢀ:DLWꢀDVVHUWHGꢀGXULQJꢀGHOD\ꢆ
ꢈꢆ ꢈꢆꢀ:KHQꢀWUDQVLWLRQLQJꢀEHWZHHQꢀDV\QFKURQRXVꢀDQGꢀYDULDEOHꢇODWHQF\ꢀEXUVWꢀRSHUDWLRQVꢄꢀ&(-ꢀPXVWꢀJRꢀ+LJKꢆꢀ&(-ꢀFDQꢀVWD\ꢀ
/RZꢀZKHQꢀWUDQVLWLRQLQJꢀIURPꢀIL[HGꢇODWHQF\ꢀEXUVWꢀ5HDGVꢓꢀDV\QFKURQRXVꢀRSHUDWLRQꢀEHJLQVꢀDWꢀWKHꢀIDOOLQJꢀHGJHꢀRIꢀ$'9-ꢆꢀ$ꢀ
UHIUHVKꢀRSSRUWXQLW\ꢀPXVWꢀEHꢀSURYLGHGꢀHYHU\ꢀW
ꢆꢀ$ꢀUHIUHVKꢀRSSRUWXQLW\ꢀLVꢀVDWLVILHGꢀE\ꢀHLWKHUꢀRIꢀWKHꢀIROORZLQJꢀWZRꢀ
&(0
FRQGLWLRQVꢔꢀDꢃꢀFORFNHGꢀ&(-ꢀ+LJKꢄꢀRUꢀEꢃꢀ&(-ꢀ+LJKꢀIRUꢀORQJHUꢀWKDQꢀꢅꢌQVꢆ
Figure 32.26 Burst Read Followed by Asynchronous Write Using ADV#
Table 32.36 Burst Read Timing Parameters
Symbol
Min
Max
ꢋ
Units
QV
Symbol
Min
ꢈꢊꢃꢉ
ꢓ
Max
Units
QV
Symbol
Min
ꢊ
Max
Units
QV
W
W
W
W
.+7/
ꢋ
$&/.
&/.
&63
W
ꢊꢏ
QV
QV
W
QV
%2(
.2+
2+=
W
ꢌ
ꢈ
QV
W
ꢊ
QV
W
ꢍ
QV
&%3+
+'
W
ꢇꢃꢉ
QV
W
ꢍ
QV
W
63
ꢐ
QV
&(:
+'=
Table 32.37 Asynchronous Write Timing Parameters Using ADV#
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢈ
Max
Units
QV
Symbol
Min
ꢉ
Max
Units
QV
W
W
ꢇꢃꢉ
W
93
$6
&(:
W
ꢊ
QV
W
ꢇꢏ
ꢏ
QV
W
93+
ꢈꢏ
ꢇꢏ
ꢓꢉ
ꢈꢏ
QV
$9+
&:
W
ꢉ
QV
W
QV
W
QV
$96
'+
96
W
ꢇꢏ
ꢇꢏ
QV
W
ꢊꢏ
QV
W
QV
$:
':
:3
W
QV
W
ꢍ
W
QV
%:
+=
:3+
208
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
VIH
VIL
A[22:0]
Valid Address
Valid Address
Valid Address
t
t
t
AA
WR
AW
VIH
VIL
VIH
VIL
ADV#
t
t
BHZ
t
BLZ
BW
LB#/UB#
t
t
t
HZ
CW
CPH
VIH
VIL
CE#
OE#
NOTE1
t
t
OHZ
LZ
t
OE
VIH
VIL
t
WC
t
t
t
WPH
AS
WP
VIH
VIL
WE#
t
t
HZ
HZ
VOH
VOL
WAIT
t
t
OLZ
WHZ
VIH
VIL
DQ[15:0]
IN/OUT
VOH
VOL
High-Z
High-Z
Data
t
Data
Valid Output
t
DH
DW
Don't Care
Undecided
1RWHꢀꢁꢀ:KHQꢀFRQILJXUHGꢀIRUꢀV\QFKURQRXVꢀPRGHꢀꢂ%&5>ꢅꢌ@ꢀ ꢀꢁꢃꢄꢀ&(-ꢀPXVWꢀUHPDLQꢀ+LJKꢀIRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW
ꢃꢀWRꢀVFKHGXOHꢀ
&3+
WKHꢀDSSURSULDWHꢀUHIUHVKꢀLQWHUYDOꢆꢀ2WKHUZLVHꢄꢀW
ꢀLVꢀRQO\ꢀUHTXLUHGꢀDIWHUꢀ&(-ꢇFRQWUROOHGꢀ:ULWHVꢆ
&3+
Figure 32.27 Asynchronous Write Followed by Asynchronous Read – ADV# Low
Table 32.38 Write Timing Parameters – ADV# Low
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
W
:+=
ꢍ
$6
'+
W
W
ꢇꢏ
ꢇꢏ
ꢉ
QV
W
ꢊꢏ
QV
W
:3
ꢓꢉ
ꢈꢏ
ꢏ
QV
$:
%:
':
QV
W
ꢍ
QV
W
QV
+=
:3+
W
QV
W
ꢇꢏ
QV
W
95
QV
&3+
:&
W
ꢇꢏ
QV
&:
Table 32.39 Read Timing Parameters – ADV# Low
Symbol
Min
Max
ꢇꢏ
ꢍ
Units
QV
Symbol
Min
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
ꢍ
W
2+=
ꢍ
$$
+=
W
QV
W
ꢈꢏ
QV
W
2/=
ꢐ
QV
%+=
/=
W
ꢈꢏ
QV
W
ꢊꢏ
QV
%/=
2(
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
209
A d v a n c e I n f o r m a t i o n
VIH
VIL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
t
AA
AVS
AVH
AW
t
WR
t
t
VPH
VS
VP
VIH
VIL
ADV#
LB#/UB#
CE#
t
BHZ
t
t
t
BLZ
BW
CVS
VIH
VIL
t
t
t
CW
HZ
CPH
VIH
VIL
Note
1
t
t
t
OH Z
AS
LZ
VIH
VIL
OE#
t
WC
t
t
t
t
WP
WPH
OL Z
AS
VIH
VIL
WE#
Wait
VOH
VOL
t
t
WHZ
OE
VIH
VIL
DQ[15:0]
IN/OUT
VOH
VOL
Valid
Output
High-Z
Data
t
Data
High-Z
t
DH
DW
Don't Care
Undefined
1RWHꢀꢁꢀ:KHQꢀFRQILJXUHGꢀIRUꢀV\QFKURQRXVꢀPRGHꢀꢂ%&5>ꢅꢌ@ꢀ ꢀꢁꢃꢄꢀ&(-ꢀPXVWꢀUHPDLQꢀ+LJKꢀIRUꢀDWꢀOHDVWꢀꢌQVꢀꢂW
ꢃꢀWRꢀVFKHGXOHꢀ
&3+
WKHꢀDSSURSULDWHꢀUHIUHVKꢀLQWHUYDOꢆꢀ2WKHUZLVHꢄꢀW
ꢀLVꢀRQO\ꢀUHTXLUHGꢀDIWHUꢀ&(-ꢇFRQWUROOHGꢀ:ULWHVꢆ
&3+
Figure 32.28 Asynchronous Write Followed by Asynchronous Read
Table 32.40 Write Timing Parameters –
Asynchronous Write Followed by Asynchronous Read
Symbol
Min
ꢏ
Max
Units
QV
Symbol
Min
ꢇ
Max
Units
QV
Symbol
Min
ꢇꢏ
Max
Units
QV
W
W
W
96
$6
&96
W
ꢊ
QV
W
ꢇꢏ
ꢏ
QV
W
:&
ꢇꢏ
QV
$9+
&:
W
ꢉ
QV
W
QV
W
:+=
ꢍ
QV
$96
'+
W
ꢇꢏ
ꢇꢏ
ꢉ
QV
W
ꢊꢏ
ꢉ
QV
W
:3
ꢓꢉ
ꢈꢏ
ꢏ
QV
$:
':
W
QV
W
W
:3+
%:
93
W
W
ꢈꢏ
W
95
&3+
93+
Table 32.41 Read Timing Parameters –
Asynchronous Write Followed by Asynchronous Read
Symbol
Min
Max
ꢇꢏ
ꢍ
Units
QV
Symbol
Min
Max
Units
QV
Symbol
Min
Max
Units
QV
W
W
ꢍ
W
2+=
ꢍ
$$
+=
W
QV
W
ꢈꢏ
QV
W
2/=
ꢐ
QV
%+=
/=
W
ꢈꢏ
QV
W
ꢊꢏ
QV
%/=
2(
210
1.8V 128Mb CellularRAM Type 2
cellram_04_A0 May 16, 2005
A d v a n c e I n f o r m a t i o n
33 CellularRAM Type 2 Revision Summary
33.1 Revision A (May 16, 2005)
,QLWLDOꢀUHOHDVHꢃ
May 16, 2005 cellram_04_A0
1.8V 128Mb CellularRAM Type 2
211
A d v a n c e I n f o r m a t i o n
34 MCP Revision Summary
Revision A0 (February 1, 2004)
,QLWLDOꢀ5HOHDVH
Revision A1 (February 9, 2005)
8SGDWHGꢀGRFXPHQWꢀWRꢀLQFOXGHꢀ%XUVWꢀ6SHHGꢀRIꢀꢌꢌꢀ0K]
8SGDWHGꢀ3XEOLFDWLRQꢀ1XPEHU
Revision A2 (March 31, 2005)
8SGDWHGꢀ3URGXFWꢀ6HOHFWRUꢀ*XLGHꢀDQGꢀ2UGHULQJꢀ,QIRUPDWLRQꢀWDEOHV
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Revision A5 (February 7, 2006)
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2006 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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S71WS-N
S71WS-N_00_A5 February 7, 2006
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