S71WS256ND0BAWE3 [SPANSION]
Memory Circuit, 16MX16, CMOS, PBGA84, 12 X 9 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84;
| 型号： | S71WS256ND0BAWE3 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 16MX16, CMOS, PBGA84, 12 X 9 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84 |
| 文件： | 总288页 (文件大小：7324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71WS512Nx0/S71WS256Nx0 Based MCPs
Stacked Multi-chip Product (MCP)
256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with 128/64Megabit (8M/4M x 16-Bit)
pSRAM
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Burst Speed: 54MHz
Packages: 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
-25°C to +85°C
-40°C to +85°C
General Description
The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
One or more flash memory die
pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheet for
further details.
Flash Density
512Mb
256Mb
128Mb
64Mb
128Mb
64Mb
32Mb
S71WS512ND0
S71WS512NC0
S71WS256ND0
S71WS256NC0
16Mb
Publication Number S71WS512/256Nx0_00 Revision A Amendment 0 Issue Date October 26, 2004
A d v a n c e I n f o r m a t i o n
8-, 16-, and 32-Word Linear Burst with Wrap Around ......................36
S71WS512Nx0/S71WS256Nx0 Based MCPs
Table 9. Burst Address Groups ............................................ 37
8-, 16-, and 32-Word Linear Burst without Wrap Around ............... 37
Configuration Register ...................................................................................... 37
RDY: Ready ...........................................................................................................37
Handshaking ......................................................................................................... 37
Simultaneous Read/Write Operations with Zero Latency ...................38
Writing Commands/Command Sequences ................................................38
Unlock Bypass Mode .....................................................................................38
Accelerated Program/Chip Erase Operations ...........................................38
Write Buffer Programming Operation ........................................................39
Autoselect Mode ................................................................................................40
Advanced Sector Protection and Unprotection ........................................41
Persistent Mode Lock Bit ..............................................................................41
Password Mode Lock Bit ..............................................................................41
Sector Protection ...............................................................................................42
Persistent Sector Protection ...........................................................................42
Persistent Protection Bit (PPB) ..................................................................43
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ............................................................................................43
Dynamic Protection Bit (DYB) ..................................................................43
Table 10. Sector Protection Schemes ................................... 44
Password Sector Protection ...........................................................................45
64-bit Password ..............................................................................................45
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode ............................................................................................45
Lock Register .......................................................................................................46
Table 11. WS256N Lock Register ......................................... 46
Table 12. WS128N/064N Lock Register ................................. 46
Hardware Data Protection Mode .................................................................46
Write Protect (WP#) ...................................................................................46
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ................................................................................................... 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .8
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 10
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 11
CellularRAM Based Pinout . . . . . . . . . . . . . . . . . . 11
CosmoRAM Based Pinout ................................................................................ 12
Type 4 - based Pinout .........................................................................................13
MCP Look-ahead Connection Diagram ....................................................... 14
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 15
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 16
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 17
256Mb WS256N Flash + 64Mb pSRAM .........................................................17
256Mb - WS256N Flash + 128 pSRAM ..........................................................18
2x 256Mb—WS512N Flash + 64Mb pSRAM ................................................19
2x256Mb—WS256N Flash + 128Mb pSRAM .............................................20
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 21
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ........................................................................................... 21
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package .......................................................................................... 22
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm
MCP Compatible Package ...............................................................................23
S29WSxxxN MirrorBit™ Flash Family
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 24
Architectural Advantages ........................................................................... 24
Performance Characteristics ..................................................................... 24
Hardware Features ...................................................................................... 24
Security Features .......................................................................................... 24
Software Features ......................................................................................... 25
Additional Features ...................................................................................... 25
Low V Write Inhibit .................................................................................47
CC
Write Pulse “Glitch” Protection ...............................................................47
Logical Inhibit ...................................................................................................47
Power-Up Write Inhibit ...............................................................................47
Standby Mode ......................................................................................................47
Automatic Sleep Mode .....................................................................................47
RESET#: Hardware Reset Input .....................................................................47
Output Disable Mode .......................................................................................48
SecSi™ (Secured Silicon) Sector Flash
Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Factory Locked: Factor SecSi Sector Programmed and Protected At
the Factory .......................................................................................................49
Table 13. SecSiTM Sector Addresses ...................................... 49
Customer SecSi Sector .................................................................................49
Common Flash Memory Interface (CFI) . . . . . . 49
Table 14. CFI Query Identification String .............................. 51
Table 15. System Interface String ........................................ 51
Table 17. Primary Vendor-Specific Extended Query ................ 52
Table 18. WS256N Sector & Memory Address Map ................. 54
Table 19. WS128N Sector & Memory Address Map ................. 62
Table 20. WS064N Sector & Memory Address Map ................. 66
Command Definitions . . . . . . . . . . . . . . . . . . . . . .68
Reading Array Data ...........................................................................................68
Set Configuration Register Command Sequence .....................................68
Read Configuration Register Command Sequence ..................................69
Figure 1. Synchronous/Asynchronous State Diagram.............. 69
Read Mode Setting .........................................................................................69
Programmable Wait State Configuration ...............................................69
Table 21. Programmable Wait State Settings ......................... 70
Programmable Wait State ...........................................................................70
General Description 26
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 29
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . .30
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 31
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 33
Table 1. Device Bus Operations ........................................... 33
VersatileIO™ (V ) Control .............................................................................33
IO
Requirements for Asynchronous (Non-Burst)
Read Operation ...................................................................................................33
Requirements for Synchronous (Burst) Read Operation .......................34
Table 2. Address Dependent Additional Latency ..................... 34
Table 3. Address Latency for 5 Wait States (
Table 4. Address Latency for 4 Wait States (
Table 5. Address Latency for 3 Wait States (
≤
≤
≤
68 MHz) ........... 35
54 MHz) ........... 35
40 MHz) ........... 35
Table 6. Address/Boundary Crossing Latency for 5 Wait States
(< 68 MHz) ...................................................................... 35
Table 7. Address/Boundary Crossing Latency for 4 Wait States
(< 54 MHz) ...................................................................... 35
Table 8. Address/Boundary Crossing Latency for 3 Wait States
(< 40 MHz) ...................................................................... 36
Continuous Burst ............................................................................................36
October 26, 2004 S71WS512/256Nx0_00A0
S71WS512Nx0/S71WS256Nx0
2
A d v a n c e I n f o r m a t i o n
Figure 12. CLK Characterization........................................... 98
Synchronous/Burst Read ..................................................................................99
Timing Diagrams ...............................................................................................100
Figure 13. CLK Synchronous Burst Mode Read..................... 100
Figure 14. 8-word Linear Burst with Wrap Around................ 101
Figure 15. 8-word Linear Burst without Wrap Around ........... 101
Figure 16. Linear Burst with RDY Set One Cycle Before Data . 102
Boundary Crossing Latency ........................................................................ 70
Table 22. Wait States for Handshaking ................................. 70
Handshaking .................................................................................................... 70
Burst Length Configuration ........................................................................ 70
Table 23. Burst Length Configuration ................................... 71
Burst Wrap Around ........................................................................................71
RDY Configuration ..........................................................................................71
RDY Polarity .....................................................................................................71
Configuration Register ......................................................................................72
Table 24. Configuration Register ......................................... 72
Reset Command ..................................................................................................72
Autoselect Command Sequence ....................................................................73
Table 25. Autoselect Addresses ........................................... 74
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .................74
Word Program Command Sequence ...........................................................74
Figure 2. Word Program Operation ....................................... 75
Write Buffer Programming Command Sequence .....................................75
Table 26. Write Buffer Command Sequence .......................... 76
Figure 3. Write Buffer Programming Operation....................... 77
Unlock Bypass Command Sequence ........................................................ 78
Chip Erase Command Sequence ................................................................... 78
Sector Erase Command Sequence ................................................................ 78
Figure 4. Erase Operation.................................................... 79
Erase Suspend/Erase Resume Commands ..................................................80
Program Suspend/Program Resume Commands .....................................80
Lock Register Command Set Definitions ....................................................81
Password Protection Command Set Definitions ...................................... 81
Non-Volatile Sector Protection Command Set Definitions ................. 82
Figure 5. PPB Program/Erase Algorithm................................. 84
Global Volatile Sector Protection Freeze Command Set ..................... 85
Volatile Sector Protection Command Set .................................................. 85
SecSi Sector Entry Command ........................................................................86
AC Characteristics—Asynchronous . . . . . . . . . . 103
Asynchronous Mode Read .............................................................................103
Timing Diagrams ................................................................................................103
Figure 17. Asynchronous Mode Read with Latched Addresses 103
Figure 18. Asynchronous Mode Read.................................. 104
Hardware Reset (RESET#) .............................................................................104
Figure 19. Reset Timings.................................................. 104
Erase/Program Timing ......................................................................................105
Figure 20. Asynchronous Program Operation Timings: WE#
Latched Addresses........................................................... 106
Figure 21. Synchronous Program Operation Timings:
CLK Latched Addresses .................................................... 107
Figure 22. Accelerated Unlock Bypass Programming Timing... 108
Figure 23. Data# Polling Timings
(During Embedded Algorithm)........................................... 108
Figure 24. Toggle Bit Timings
(During Embedded Algorithm)........................................... 109
Figure 25. Synchronous Data Polling Timings/
Toggle Bit Timings........................................................... 109
Figure 26. DQ2 vs. DQ6 ................................................... 110
Figure 27. Latency with Boundary Crossing when
Frequency > 66 MHz........................................................ 110
Figure 28. Latency with Boundary Crossing into Program/
Erase Bank..................................................................... 111
Figure 29. Example of Wait States Insertion........................ 112
Figure 30. Back-to-Back Read/Write Cycle Timings .............. 113
Erase and Programming Performance . . . . . . . . 114
Command Definition Summary ..................................................................... 87
Table 27. Memory Array Commands ................................... 87
Table 28. Sector Protection Commands ................................ 88
CellularRAM
Write Operation Status . . . . . . . . . . . . . . . . . . . . .89
Figure 6. Polling Flow Chart ................................................. 89
DQ7: Data# Polling ...........................................................................................90
DQ6: Toggle Bit I ...............................................................................................90
DQ2: Toggle Bit II ............................................................................................... 91
Table 29. DQ6 and DQ2 Indications ..................................... 91
Reading Toggle Bits DQ6/DQ2 ..................................................................... 92
DQ5: Exceeded Timing Limits ....................................................................... 92
DQ3: Sector Erase Start Timeout State Indicator ................................... 92
DQ1: Write to Buffer Abort ............................................................................93
Table 30. Write Operation Status ......................................... 93
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .94
Figure 7. Maximum Negative Overshoot Waveform................. 94
Figure 8. Maximum Positive Overshoot Waveform .................. 94
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 94
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .95
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
General Description . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 31. Functional Block Diagram .................................. 117
Table 32. Signal Descriptions ............................................ 118
Table 33. Bus Operations—Asynchronous Mode ................... 119
Table 34. Bus Operations—Burst Mode ............................... 120
Functional Description . . . . . . . . . . . . . . . . . . . . 120
Power-Up Initialization ....................................................................................120
Figure 32. Power-Up Initialization Timing............................ 121
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . 121
Asynchronous Mode .........................................................................................121
Figure 33. READ Operation (ADV# LOW) ............................ 121
Figure 34. WRITE Operation (ADV# LOW)........................... 122
Page Mode READ Operation ........................................................................122
Figure 35. Page Mode READ Operation (ADV# LOW)............ 123
Burst Mode Operation ....................................................................................123
Figure 36. Burst Mode READ (4-word burst)........................ 124
Figure 37. Burst Mode WRITE (4-word burst) ...................... 124
Mixed-Mode Operation ...................................................................................125
WAIT Operation ...............................................................................................125
Figure 38. Wired or WAIT Configuration.............................. 125
LB#/UB# Operation .........................................................................................126
Figure 39. Refresh Collision During READ Operation............. 126
Figure 40. Refresh Collision During WRITE Operation............ 127
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 9. Test Setup ........................................................... 96
Table 31. Test Specifications ............................................... 96
Key to Switching Waveforms . . . . . . . . . . . . . . . 96
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 96
Figure 10. Input Waveforms and Measurement Levels............. 96
VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 11. VCC Power-up Diagram ........................................ 97
AC Characteristics—Synchronous . . . . . . . . . . . 98
CLK Characterization .......................................................................................98
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 127
Standby Mode Operation ................................................................................127
3
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 October 26, 2004
A d v a n c e I n f o r m a t i o n
Operation ....................................................................... 150
Figure 53. Single-Access Burst READ
Operation—Variable Latency ............................................. 152
Table 56. Burst READ Timing Parameters—Single Access, Variable
Latency .......................................................................... 152
Figure 54. Four-word Burst READ
Temperature Compensated Refresh .......................................................... 127
Partial Array Refresh .......................................................................................128
Deep Power-Down Operation .....................................................................128
Configuration Registers . . . . . . . . . . . . . . . . . . . 128
Access Using CRE .............................................................................................128
Figure 41. Configuration Register WRITE, Asynchronous Mode
Followed by READ ............................................................ 129
Figure 42. Configuration Register WRITE, Synchronous Mode
Followed by READ0........................................................... 130
Bus Configuration Register ............................................................................130
Table 35. Bus Configuration Register Definition ....................131
Table 36. Sequence and Burst Length .................................132
Burst Length (BCR[2:0]): Default = Continuous Burst ..................... 132
Burst Wrap (BCR[3]): Default = No Wrap ......................................... 132
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength .............................................................................................................133
Table 37. Output Impedance .............................................133
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid ................................................................133
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ................133
Figure 43. WAIT Configuration (BCR[8] = 0)........................ 133
Figure 44. WAIT Configuration (BCR[8] = 1)........................ 134
Figure 45. WAIT Configuration During Burst Operation.......... 134
Latency Counter (BCR[13:11]): Default = Three-Clock Latency ..... 134
Table 38. Variable Latency Configuration Codes ...................134
Figure 46. Latency Counter (Variable Initial Latency, No Refresh
Collision)......................................................................... 135
Operating Mode (BCR[15]): Default = Asynchronous Operation ..135
Refresh Configuration Register .....................................................................135
Table 39. Refresh Configuration Register Mapping ................136
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh .... 136
Table 40. 128Mb Address Patterns for PAR (RCR[4] = 1) .......136
Table 41. 64Mb Address Patterns for PAR (RCR[4] = 1) .........137
Table 42. 32Mb Address Patterns for PAR (RCR[4] = 1) .........137
Deep Power-Down (RCR[4]): Default = DPD Disabled ..................137
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation .........................................................................................................137
Page Mode Operation (RCR[7]): Default = Disabled .........................137
Operation—Variable Latency ............................................. 154
Table 57. Burst READ Timing Parameters—4-word Burst ....... 155
Figure 55. Four-word Burst READ Operation (with LB#/UB#) 156
Table 58. Burst READ Timing Parameters—4-word Burst with LB#/
UB# ............................................................................... 157
Figure 56. READ Burst Suspend......................................... 158
Table 59. Burst READ Timing Parameters—Burst Suspend ..... 158
Figure 57. Continuous Burst READ Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 159
Table 60. Burst READ Timing Parameters—BCR[8] = 0 ......... 159
Figure 58. CE#-Controlled Asynchronous WRITE.................. 160
Table 61. Asynchronous WRITE Timing Parameters—CE#-
Controlled ....................................................................... 160
Figure 59. LB#/UB#-Controlled Asynchronous WRITE .......... 162
Table 62. Asynchronous WRITE Timing Parameters—LB#/UB#-
Controlled ....................................................................... 162
Figure 60. WE#-Controlled Asynchronous WRITE................. 164
Table 63. Asynchronous WRITE Timing Parameters—WE#-
Controlled ....................................................................... 164
Figure 61. Asynchronous WRITE Using ADV# ...................... 166
Table 64. Asynchronous WRITE Timing
Parameters Using ADV# ................................................... 167
Figure 62. Burst WRITE Operation ..................................... 168
Table 65. Burst WRITE Timing Parameters .......................... 169
Figure 63. Continuous Burst WRITE Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 170
Table 66. Burst WRITE Timing Parameters—BCR[8] = 0 ....... 170
Figure 64. Burst WRITE Followed by Burst READ.................. 171
Table 67. WRITE Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 171
Table 68. READ Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 171
Figure 65. Asynchronous WRITE Followed by Burst READ...... 172
Table 69. WRITE Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 173
Table 70. READ Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 173
Figure 66. Asynchronous WRITE (ADV# LOW) Followed By Burst
READ............................................................................. 174
Table 71. Asynchronous WRITE Timing
Parameters—ADV# LOW .................................................. 174
Table 72. Burst READ Timing Parameters ............................ 175
Figure 67. Burst READ Followed by Asynchronous WRITE (WE#-
Controlled) ..................................................................... 176
Table 73. Burst READ Timing Parameters ............................ 177
Table 74. Asynchronous WRITE Timing Parameters—WE#
Controlled ....................................................................... 177
Figure 68. Burst READ Followed by Asynchronous WRITE Using
ADV#............................................................................. 178
Table 75. Burst READ Timing Parameters ............................ 179
Table 76. Asynchronous WRITE Timing Parameters
Using ADV# .................................................................... 179
Figure 69. Asynchronous WRITE Followed by Asynchronous READ—
ADV# LOW..................................................................... 180
Table 77. WRITE Timing Parameters—ADV# LOW ................ 180
Table 78. READ Timing Parameters—ADV# LOW .................. 181
Figure 70. Asynchronous WRITE Followed by
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 138
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 139
Table 43. Electrical Characteristics and Operating Conditions .139
Table 44. Temperature Compensated Refresh Specifications and
Conditions .......................................................................140
Table 45. Partial Array Refresh Specifications and Conditions .140
Table 46. Deep Power-Down Specifications ..........................140
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 47. AC Input/Output Reference Waveform................. 141
Figure 48. Output Load Circuit ........................................... 141
Table 47. Output Load Circuit ............................................141
Table 48. Asynchronous READ Cycle Timing Requirements .....142
Table 49. Burst READ Cycle Timing Requirements .................143
Table 50. Asynchronous WRITE Cycle Timing Requirements ...144
Table 51. Burst WRITE Cycle Timing Requirements ...............144
Timing Diagrams ................................................................................................ 145
Figure 49. Initialization Period............................................ 145
Table 52. Initialization Timing Parameters ...........................145
Figure 50. Asynchronous READ .......................................... 146
Table 53. Asynchronous READ Timing Parameters ................146
Figure 51. Asynchronous READ Using ADV# ........................ 148
Table 54. Asynchronous READ Timing
Parameters Using ADV# ....................................................148
Figure 52. Page Mode READ............................................... 150
Table 55. Asynchronous READ Timing Parameters—Page Mode
Asynchronous READ......................................................... 182
Table 79. WRITE Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 182
October 26, 2004 S71WS512/256Nx0_00A0
S71WS512Nx0/S71WS256Nx0
4
A d v a n c e I n f o r m a t i o n
Table 80. READ Timing Parameters—Asynchronous WRITE
Burst Type ...........................................................................................................199
Table 90. Burst Sequence ................................................. 199
Low Power Features . . . . . . . . . . . . . . . . . . . . . 200
Internal TCSR ................................................................................................... 200
Figure 83. PAR Mode Execution and Exit............................. 200
Table 91. PAR Mode Characteristics .................................... 200
Driver Strength Optimization ..................................................................... 200
Partial Array Refresh (PAR) mode ............................................................. 200
Absolute Maximum Ratings . . . . . . . . . . . . . . . 201
DC Recommended Operating Conditions . . . . 201
Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . 201
DC and Operating Characteristics . . . . . . . . . . 202
Common .............................................................................................................202
AC Operating Conditions . . . . . . . . . . . . . . . . . 203
Test Conditions (Test Load and Test Input/Output Reference) .......203
Figure 84. Output Load .................................................... 203
Asynchronous AC Characteristics ..............................................................204
Followed by Asynchronous READ ........................................183
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Introduction ........................................................................................................183
Asynchronous WRITE Operation ...............................................................184
Figure 71. Extended Timing for tCEM.............................................. 184
Figure 72. Extended Timing for tTM................................................ 184
Table 81. Extended Cycle Impact on READ and WRITE Cycles 184
Extended WRITE Timing— Asynchronous WRITE Operation .....184
Figure 73. Extended WRITE Operation ................................ 185
Page Mode READ Operation ........................................................................185
Burst-Mode Operation ....................................................................................185
Summary ..............................................................................................................185
1.8V pSRAM Type 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 187
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 188
Power Up ............................................................................................................188
Figure 74. Power Up Timing............................................... 188
Standby Mode .....................................................................................................188
Figure 75. Standby Mode State Machines ............................ 188
Functional Description . . . . . . . . . . . . . . . . . . . . 189
Table 82. Asynchronous 4 Page Read & Asynchronous Write Mode
(A15/A14=0/0) ................................................................189
Table 83. Synchronous Burst Read & Asynchronous Write Mode
(A15/A14=0/1) ................................................................190
Table 84. Synchronous Burst Read & Synchronous Burst Write
Mode(A15/A14=1/0) ........................................................191
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 205
Asynchronous Read Timing Waveform ....................................................205
Figure 85. Timing Waveform Of Asynchronous Read Cycle .... 205
Table 92. Asynchronous Read AC Characteristics ................. 205
Page Read .......................................................................................................206
Figure 86. Timing Waveform Of Page Read Cycle................. 206
Table 93. Asynchronous Page Read AC Characteristics .......... 206
Asynchronous Write Timing Waveform ..................................................207
Figure 87. Timing Waveform Of Write Cycle........................ 207
Table 94. Asynchronous Write AC Characteristics ................. 207
Write Cycle 2 ............................................................................................... 208
Figure 88. Timing Waveform of Write Cycle(2) .................... 208
Table 95. Asynchronous Write AC Characteristics (UB# & LB#
Controlled) ..................................................................... 208
Write Cycle (Address Latch Type) ........................................................209
Figure 89. Timing Waveform Of Write Cycle
Mode Register Setting Operation . . . . . . . . . . . . 191
Mode Register Set (MRS) ...............................................................................192
Table 85. Mode Register Setting According to
(Address Latch Type)....................................................... 209
Table 96. Asynchronous Write in Synchronous Mode AC
Field of Function ...............................................................192
Table 86. Mode Register Set ..............................................193
MRS Pin Control Type Mode Register Setting Timing .......................... 193
Figure 76. Mode Register Setting Timing (OE# = VIH)........... 194
Table 87. MRS AC Characteristics .......................................194
Characteristics ................................................................ 209
Asynchronous Write Timing Waveform in Synchronous Mode ........210
Write Cycle (Low ADV# Type) ...............................................................210
Figure 90. Timing Waveform Of Write Cycle (Low ADV# Type) 210
Table 97. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 210
Write Cycle (Low ADV# Type) ................................................................211
Figure 91. Timing Waveform Of Write Cycle (Low ADV# Type) 211
Table 98. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 211
Multiple Write Cycle (Low ADV# Type) ..............................................212
Figure 92. Timing Waveform Of Multiple Write Cycle (Low ADV#
Type)............................................................................. 212
Table 99. Asynchronous Write in Synchronous Mode AC
Asynchronous Operation . . . . . . . . . . . . . . . . . . 195
Asynchronous 4 Page Read Operation ......................................................195
Asynchronous Write Operation .................................................................. 195
Asynchronous Write Operation in Synchronous Mode .......................195
Figure 77. Asynchronous 4-Page Read ................................ 195
Figure 78. Asynchronous Write........................................... 195
Synchronous Burst Operation . . . . . . . . . . . . . . 196
Synchronous Burst Read Operation ...........................................................196
Synchronous Burst Write Operation .........................................................196
Figure 79. Synchronous Burst Read.................................... 196
Figure 80. Synchronous Burst Write.................................... 197
Characteristics ................................................................ 213
AC Operating Conditions . . . . . . . . . . . . . . . . . . 214
Test Conditions (Test Load and Test Input/Output Reference) ........214
Figure 93. AC Output Load Circuit...................................... 214
Table 100. Synchronous AC Characteristics ........................ 215
Synchronous Burst Operation Terminology . . 197
Clock (CLK) ........................................................................................................197
Latency Count ....................................................................................................197
Table 88. Latency Count Support ........................................197
Table 89. Number of CLocks for 1st Data .............................197
Figure 81. Latency Configuration (Read) ............................. 198
Burst Length .......................................................................................................198
Synchronous Burst Operation Timing
Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 94. Timing Waveform Of Basic Burst Operation.......... 216
Table 101. Burst Operation AC Characteristics ..................... 216
Synchronous Burst Read Timing Waveform . . . 217
Burst Stop ............................................................................................................198
Read Timings .......................................................................................................217
Figure 95. Timing Waveform of Burst Read Cycle (1)............ 217
Table 102. Burst Read AC Characteristics ............................ 218
Synchronous Burst Operation Terminology . . 198
Wait Control (WAIT#) ..................................................................................198
Figure 82. WAIT# and Read/Write Latency Control............... 199
5
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 October 26, 2004
A d v a n c e I n f o r m a t i o n
Figure 96. Timing Waveform of Burst Read Cycle (2) ............ 218
Figure 111. Synchronous Operation Diagram....................... 239
Table 103. Burst Read AC Characteristics ............................219
Figure 97. Timing Waveform of Burst Read Cycle (3) ............ 219
Table 104. Burst Read AC Characteristics ............................220
Write Timings ....................................................................................................221
Figure 98. Timing Waveform of Burst Write Cycle (1)............ 221
Table 105. Burst Write AC Characteristics ............................222
Figure 99. Timing Waveform of Burst Write Cycle (2)............ 223
Table 106. Burst Write AC Characteristics ............................223
Functional Description . . . . . . . . . . . . . . . . . . . . 239
Power-up .............................................................................................................239
Configuration Register ....................................................................................239
CR Set Sequence ..............................................................................................239
Address Key ........................................................................................................241
Power Down ......................................................................................................242
Burst Read/Write Operation ........................................................................242
Figure 112. Burst Read Operation...................................... 243
Figure 113. Burst Write Operation...................................... 243
CLK Input Function .........................................................................................243
ADV# Input Function ......................................................................................244
WAIT# Output Function ...............................................................................244
Latency .................................................................................................................245
Figure 114. Read Latency Diagram .................................... 245
Address Latch by ADV# ................................................................................246
Burst Length .......................................................................................................246
Single Write ........................................................................................................246
Write Control ...................................................................................................247
Figure 115. Write Controls................................................ 247
Burst Read Suspend .........................................................................................247
Figure 116. Burst Read Suspend Diagram........................... 248
Burst Write Suspend .......................................................................................248
Figure 117. Burst Write Suspend Diagram .......................... 248
Burst Read Termination .................................................................................248
Figure 118. Burst Read Termination Diagram...................... 249
Burst Write Termination ...............................................................................249
Figure 119. Burst Write Termination Diagram...................... 249
Absolute Maximum Ratings . . . . . . . . . . . . . . . 250
Recommended Operating Conditions (See
Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . 250
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 250
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 251
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 252
Read Operation ................................................................................................252
Write Operation ..............................................................................................254
Synchronous Operation - Clock Input (Burst Mode) ...........................255
Synchronous Operation - Address Latch (Burst Mode) ......................255
Synchronous Read Operation (Burst Mode) ...........................................256
Synchronous Write Operation (Burst Mode) .........................................257
Power Down Parameters ..............................................................................258
Other Timing Parameters ..............................................................................258
AC Test Conditions ........................................................................................258
AC Measurement Output Load Circuit ....................................................259
Figure 120. Output Load Circuit......................................... 259
Synchronous Burst Read Stop Timing
Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 100. Timing Waveform of Burst Read Stop by CS# ..... 224
Table 107. Burst Read Stop AC Characteristics .....................224
Synchronous Burst Write Stop Timing
Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 101. Timing Waveform of Burst Write Stop by CS#..... 225
Table 108. Burst Write Stop AC Characteristics ....................225
Synchronous Burst Read Suspend Timing
Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 102. Timing Waveform of Burst Read
Suspend Cycle (1)............................................................ 226
Table 109. Burst Read Suspend AC Characteristics ...............226
Transition Timing Waveform Between Read And
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 103. Synchronous Burst Read to Asynchronous Write
(Address Latch Type)........................................................ 227
Table 110. Burst Read to Asynchronous Write (Address Latch Type)
AC Characteristics ............................................................227
Figure 104. Synchronous Burst Read to Asynchronous Write (Low
ADV# Type) .................................................................... 228
Table 111. Burst Read to Asynchronous Write (Low ADV# Type) AC
Characteristics .................................................................228
Figure 105. Asynchronous Write (Address Latch Type) to
Synchronous Burst Read Timing......................................... 229
Table 112. Asynchronous Write (Address Latch Type) to Burst Read
AC Characteristics ............................................................229
Figure 106. Asynchronous Write (Low ADV# Type) to Synchronous
Burst Read Timing............................................................ 230
Table 113. Asynchronous Write (Low ADV# Type) to Burst Read AC
Characteristics .................................................................230
Figure 107. Synchronous Burst Read to Synchronous Burst Write
Timing............................................................................ 231
Table 114. Asynchronous Write (Low ADV# Type) to Burst Read AC
Characteristics .................................................................231
Figure 108. Synchronous Burst Write to Synchronous Burst Read
Timing............................................................................ 232
Table 115. Asynchronous Write (Low ADV# Type) to Burst Read AC
Characteristics .................................................................232
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 121. Asynchronous Read Timing #1-1 (Basic Timing) . 260
Figure 122. Asynchronous Read Timing #1-2 (Basic Timing) . 260
Figure 123. Asynchronous Read Timing #2
CosmoRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . 235
Functional Description . . . . . . . . . . . . . . . . . . . . 236
Asynchronous Operation (Page Mode) .................................................... 236
Functional Description . . . . . . . . . . . . . . . . . . . . 237
Synchronous Operation (Burst Mode) .......................................................237
State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Initial/Standby State .........................................................................................238
Figure 109. Initial Standby State Diagram........................... 238
Asynchronous Operation State ...................................................................238
Figure 110. Asynchronous Operation State Diagram ............. 238
Synchronous Operation State ...................................................................... 239
(OE# & Address Access)................................................... 261
Figure 124. Asynchronous Read Timing #3 (LB# / UB# Byte
Access) .......................................................................... 261
Figure 125. Asynchronous Read Timing #4 (Page Address Access
after CE1# Control Access)............................................... 262
Figure 126. Asynchronous Read Timing #5 (Random and Page
Address Access) .............................................................. 262
Figure 127. Asynchronous Write Timing #1-1 (Basic Timing). 263
Figure 128. Asynchronous Write Timing #1-2 (Basic Timing). 263
Figure 129. Asynchronous Write Timing #2 (WE# Control).... 264
Figure 130. Asynchronous Write Timing #3-1 (WE# / LB# / UB#
Byte Write Control).......................................................... 264
Figure 131. Asynchronous Write Timing #3-2 (WE# / LB# / UB#
October 26, 2004 S71WS512/256Nx0_00A0
S71WS512Nx0/S71WS256Nx0
6
A d v a n c e I n f o r m a t i o n
Byte Write Control) .......................................................... 265
Figure 147. Synchronous Write Timing #1
Figure 132. Asynchronous Write Timing #3-3 (WE# / LB# / UB#
Byte Write Control) .......................................................... 265
Figure 133. Asynchronous Write Timing #3-4 (WE# / LB# / UB#
Byte Write Control) .......................................................... 266
Figure 134. Asynchronous Read / Write Timing #1-1 (CE1#
Control).......................................................................... 266
Figure 135. Asynchronous Read / Write Timing #1-2 (CE1# / WE#
/ OE# Control)................................................................. 267
Figure 136. Asynchronous Read / Write Timing #2 (OE#, WE#
Control).......................................................................... 267
Figure 137. Asynchronous Read / Write Timing #3 (OE,# WE#,
LB#, UB# Control) ........................................................... 268
Figure 138. Clock Input Timing .......................................... 268
Figure 139. Address Latch Timing (Synchronous Mode)......... 269
Figure 140. 32M Synchronous Read Timing #1 (OE# Control) 270
Figure 141. 32M Synchronous Read Timing #2
(WE# Level Control) ........................................................ 277
Figure 148. Synchronous Write Timing #2 (WE# Single Clock Pulse
Control) ......................................................................... 278
Figure 149. Synchronous Write Timing #3 (ADV# Control).... 279
Figure 150. Synchronous Write Timing #4 (WE# Level Control,
Single Write)................................................................... 280
Figure 151. 32M Synchronous Read to Write Timing #1(CE1#
Control) ......................................................................... 281
Figure 152. 32M Synchronous Read to Write Timing #2(ADV#
Control) ......................................................................... 282
Figure 153. 64M Synchronous Read to Write Timing #1(CE1#
Control) ......................................................................... 283
Figure 154. 64M Synchronous Read to Write Timing #2(ADV#
Control) ......................................................................... 284
Figure 155. Synchronous Write to Read Timing #1
(CE1# Control) ............................................................... 285
Figure 156. Synchronous Write to Read Timing #2
(CE1# Control) ................................................................ 271
Figure 142. 32M Synchronous Read Timing #3
(ADV# Control)............................................................... 286
Figure 157. Power-up Timing #1 ....................................... 287
Figure 158. Power-up Timing #2 ...................................... 287
Figure 159. Power Down Entry and Exit Timing.................... 287
Figure 160. Standby Entry Timing after Read or Write.......... 288
Figure 161. Configuration Register Set Timing #1 (Asynchronous
Operation)...................................................................... 288
Figure 162. Configuration Register Set Timing #2 (Synchronous
Operation)...................................................................... 289
(ADV# Control)................................................................ 272
Figure 143. Synchronous Read - WAIT# Output Timing (Continuous
Read) ............................................................................. 273
Figure 144. 64M Synchronous Read Timing #1 (OE# Control) 274
Figure 145. 64M Synchronous Read Timing #2
(CE1# Control) ................................................................ 275
Figure 146. 64M Synchronous Read Timing #3
(ADV# Control)................................................................ 276
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . .290
7
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 October 26, 2004
Product Selector Guide
WS256N + 64 pSRAM
pSRAM Flash Speed
pSRAM
Device-Model
density
MHz
speed MHz
DYB Bits - Power Up
Supplier
Package
S71WS256NC0-AK
0 (Protected)
CellularRAM 2
1(Unprotected [Default
State])
S71WS256NC0-AP
S71WS256NC0-AB
S71WS256NC0-AF
S71WS256NC0-AU
S71WS256NC0-AZ
0 (Protected)
64M
54
54
CellularRAM 1
COSMORAM 1
TLA084
1(Unprotected [Default
State])
0 (Protected)
1(Unprotected [Default
State])
WS256N + 128 pSRAM
pSRAM Flash Speed
pSRAM
Device-Model
density
MHz
speed MHz
DYB Bits - Power Up
0 (Protected)
Supplier
Package
S71WS256ND0-EK
S71WS256ND0-EP
S71WS256ND0-EU
S71WS256ND0-EZ
S71WS256ND0-E3
S71WS256ND0-E7
128M
54
54
54
54
CellularRAM 2
1 (Unprotected [Default state])
0 (Protected)
TSD084
9x12x1.2
128M
128M
54
54
COSMORAM 1
1 (Unprotected [Default state])
0 (Protected)
Type 4
1 (Unprotected [Default state])
WS512N + 64 pSRAM
pSRAM
speed
MHz
pSRAM Flash Speed
Device-Model
density
MHz
DYB Bits - Power Up
Supplier
Package
S71WS512NC0-AK
0 (Protected)
CellularRAM 2
1(Unprotected [Default
State])
S71WS512NC0-AP
S71WS512NC0-AB
S71WS512NC0-AF
S71WS512NC0-AU
S71WS512NC0-AZ
0 (Protected)
64Mb
54
54
CellularRAM 1
COSMORAM 1
TLA084
1(Unprotected [Default
State])
0 (Protected)
1(Unprotected [Default
State])
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
8
WS512N + 128 pSRAM
pSRAM
speed
MHz
pSRAM Flash Speed
Device-Model
density
MHz
DYB Bits - Power Up
Supplier
Package
S71WS512ND0-YK
S71WS512ND0-YP
S71WS512ND0-Y3
S71WS512ND0-Y7
0
1
0
1
CellularRAM 2
FEA084
9x12x1.4
128Mb
54
54
1.8V RAM
Type 4
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
9
MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
22
16
DQ15 to DQ0
CLK
WP#
ACC
ACC
CE#
OE#
Flash 1
(Note 3) F1-CE#
OE#
Flash 2
(Note 4)
WE#
F-RST#
AVD#
WE#
RESET#
AVD#
RDY
RDY
(Note 3) F2-CE#
R-VCC
V
SS
22
V
CCQ
V
CC
16
I/O15 to I/O0
CLK
R-CE1#
CE#
WE#
OE#
pSRAM
WAIT#
R-UB#
R-LB#
UB#
LB#
V
SSQ
(Note 1) R-CE2
AVD#
MRS
(Note 2) R-CRE
(Note 6) R-MRS
Notes:
1. R-CRE is only present in CellularRAM-compatible pSRAM.
2. R-CE2 is only present in Cosmoram-compatible pSRAM.
3. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash.
4. Only needed for S71WS512N.
5. For the 128M pSRAM devices, there are 23 shared addresses.
6. R-MRS is only present in the 1.8V RAM Type 4
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
10
Connection Diagrams
CellularRAM Based Pinout
84-ball Fine-Pitch Ball Grid Array
CellularRAM-based Pinout (Top View, Balls Facing Down)
Legend
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
Shared
AVD#
C2
F-WP#
D2
Flash Shared only
RFU
D9
R-LB#
D4
ACC
D5
WE#
D6
A8
A11
D8
D7
1st Flash only
2nd Flash only
A3
R-UB# F-RST#
RFU
E6
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
A2
F2
A1
G2
A0
A5
F3
A20
F6
A9
A13
F8
A21
F9
F7
RAM only
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE# OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
L2
L3
L4
L5
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
1. In MCP's based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two
S29WS256N (S71WS512), ball B5 is F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A21-A0
S71WS256NC0
S71WS256ND0
S71WS512NC0
S71WS512ND0
A23-A22
A23
A22-A0
A23-A22
A23
A21-A0
A22-A0
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
11
CosmoRAM Based Pinout
84-ball Fine-Pitch Ball Grid Array
CosmoRAM-based Pinout (Top View, Balls Facing Down)
Legend
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
Shared
AVD#
C2
F-WP#
D2
1st Flash Only
RFU
D9
R-LB#
D4
ACC
D5
WE#
A8
A11
D8
D7
D6
2nd Flash Only
1st RAM Only
A3
R-UB# F-RST# R-CE2
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
E6
A20
F6
A2
F2
A1
G2
A0
A5
F3
A9
A13
F8
A21
F9
F7
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE# OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
L2
L3
L4
L5
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
Notes:
1. In MCP's based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two
S29WS256N (S71WS512), ball B5 is F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A21-A0
S71WS256NC0
S71WS256ND0
S71WS512NC0
S71WS512ND0
A23-A22
A23
A22-A0
A23-A22
A23
A21-A0
A22-A0
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
12
Type 4 - based Pinout
84-ball Fine-Pitch Ball Grid Array
Type 4-based Pinout (Top View, Balls Facing Down)
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
AVD#
C2
F-WP#
D2
Legend
RFU
D9
R-LB#
D4
F-ACC
D5
WE#
D6
A8
A11
D8
D7
Shared
A3
R-UB# F-RST#
RFU
E6
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
Flash XIP only
A2
F2
A1
G2
A0
A5
F3
A20
F6
A9
A13
F8
A21
F9
F7
RAM only
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
1st Flash
Only
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-MRS
2nd Flash
Only
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
RFU
L9
Reserved for
Future Use
DQ2
DQ5
DQ14
DQ8
DQ11
RFU
L3
L4
L5
L7
L8
L2
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
Notes:
1. In MCP's based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two
S29WS256N (S71WS512), ball B5 is or F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A21-A0
S71WS256NC0
S71WS256ND0
S71WS512NC0
S71WS512ND0
A23-A22
A23
A22-A0
A23-A22
A23
A21-A0
A22-A0
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
13
MCP Look-ahead Connection Diagram
96-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend:
A2
A10
A9
A1
DNU
DNU
DNU
DNU
(Do Not Use)
DNU
B1
B9
B2
B10
DNU
DNU
DNU
DNU
Code Flash Only
pSRAM Only
C4
C5
C6
C7
C8
C9
C2
C3
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK#
R-OE# F2-OE#
D4
D2
D3
A7
D5
D6
D7
A8
D8
D9
D-DM0/
D1, D#
See Table
See Table WE#
E5 E6
F-RST# R1-CE2
A11
F3-CE#
E2
A3
E3
A6
E4
E7
E8
E9
Flash/xRAM
Shared
D-DM1/
D11, D#
A19
A12
A15
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
A18 See Table
A20
A13
A21
MirrorBit Data
Only
G6
G8
G2
A1
G4
G7
G9
G3
A4
G5
A17
R2-CE1
A23
A10
A14
A22
xRAM Shared
H2
A0
H3
H4
H5
H6
H7
H8
H9
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
Flash/Data
Shared
J2
J3
J4
J5
J6
J7
J8
J9
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
F1-CE#
OE#
K2
K5
K3
K4
K6
K7
K8
K9
DQ12
VSS
R1-CE1#
DQ0
DQ10
F-VCC
R1-VCC
DQ7
L2
L9
L4
L5
L6
L7
L8
L3
DQ2
DQ11
A25
DQ5
DQ14
F-WP#
R-VCC
DQ8
DNU
M5
M2
M3
M4
M6
M7
M8
M9
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ
DNU
N1
N2
N10
N9
DNU
DNU
DNU
DNU
P1
P2
P10
P9
DNU
DNU
DNU
DNU
Table
BALL
1.8V
Vcc
3.0V
Vcc
FASL Standard
MCP Packages
D2
NC
F-WP#
ACC
7.0 x 9.0mm
8.0 x 11.6mm
9.0 x 12.0mm
11.0 x 13.0mm
WP#/
ACC
D5
F5
RY/
BY#
F-RDY/
R-WAIT#
Notes:
1. In a 3.0V system, the GL device used as Data has to have WP tied to VCC.
2. F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash.
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
14
Input/Output Descriptions
A23-A0
DQ15-DQ0
OE#
=
=
=
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
=
=
=
=
Write Enable input.
Ground
V
SS
NC
RDY
No Connect; not connected internally
Ready output. Indicates the status of the Burst read.
The WAIT# pin of the pSRAM is tied to RDY.
CLK
=
Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at V or V
IL
IH
while in asynchronous mode
AVD#
=
Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
F-RST#
F-WP#
=
=
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At V , disables
IL
program and erase functions in the four outermost
sectors. Should be at V for all other conditions.
IH
F-ACC
=
Accelerated input. At V , accelerates
HH
programming; automatically places device in unlock
bypass mode. At V , disables all program and erase
IL
functions. Should be at V for all other conditions.
IH
R-CE1#
R-CE2
F1-CE#
=
=
=
Chip-enable input for pSRAM.
Chip-enable 2 for CosmoRAM only.
Chip-enable input for Flash 1. Asynchronous relative
to CLK for Burst Mode.
F2-CE#
=
Chip-enable input for Flash 2. Asynchronous relative
to CLK for Burst Mode. This applies to the 512Mb
MCP only.
R-MRS
R-CRE
=
=
Mode register select for Type 4.
Control Register Enable (pSRAM). For CellularRAM
only.
F-VCC
R-VCC
R-UB#
R-LB#
DNU
=
=
=
=
=
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Do Not Use.
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
15
Ordering Information
The order number (Valid Combination) is formed by the following:
S71WS 256
N
C
0
BA
W
A
K
SUPPLIER, DYB, SPEED COMBINATION
K = 2
P = 2
B = 1
F = 1
U = 1
Z = 1
3
=
=
=
=
=
=
=
=
CellularRAM 2, 0, 54MHz
CellularRAM 2, 1, 54MHz
CellularRAM 1, 0, 54MHz/RAM Type 4,0, 54MHz
CellularRAM 1, 1, 54MHz/RAM Type 4,1, 54MHz
COSMORAM 1, 0, 54MHz
COSMORAM 1, 1, 54MHz
RAM Type 4, 0, 54MHz
RAM Type 4, 1, 54MHz
7
PACKAGE MODIFIER
A
Y
E
=
=
=
1.2mm, 8 x 11.6, 84-ball FBGA
1.4mm, 9 x 12, 84-ball FBGA
1.2mm, 9 x 12, 84-ball FBGA
TEMPERATURE RANGE
W
I
=
=
Wireless (-25
°
C to +85
°
C)
Industrial (–40
°
C to +85
°C)
PACKAGE TYPE
BA
=
Very Thin Fine-Pitch BGA
Lead (Pb)-free Compliant Package
Very Thin Fine-Pitch BGA
Lead (Pb)-free Package
BF
=
CHIP CONTENTS—2
No second content
CHIP CONTENTS—1
C = 64Mb
D = 128Mb
PROCESS TECHNOLOGY
N
=
110nm MirrorBit™ Technology
FLASH DENSITY
512
256
=
=
512Mb (2x256Mb)
256Mb
DEVICE FAMILY
S71WS= Multi-Chip Product
1.8 Volt-only Simultaneous Read/Write Burst Mode
Flash Memory + xRAM
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
16
Valid Combinations
256Mb WS256N Flash + 64Mb pSRAM
Temperature
Range °C
Burst
Speed
Material
Set
Order Number
Package Marking
DYB Power-up State
Supplier
S71WS256NC0BAWAK
71WS256NC0BAWAK
0(Protected)
CellularRAM 2
1(Unprotected[Default
State])
S71WS256NC0BAWAP
S71WS256NC0BAWAB
S71WS256NC0BAWAF
S71WS256NC0BAWAU
S71WS256NC0BAWAZ
S71WS256NC0BAIAK
S71WS256NC0BAIAP
S71WS256NC0BAIAB
S71WS256NC0BAIAF
S71WS256NC0BAIAU
S71WS256NC0BAIAZ
S71WS256NC0BFWAK
S71WS256NC0BFWAP
S71WS256NC0BFWAB
S71WS256NC0BFWAF
S71WS256NC0BFWAU
S71WS256NC0BFWAZ
S71WS256NC0BFIAK
S71WS256NC0BFIAP
S71WS256NC0BFIAB
S71WS256NC0BFIAF
S71WS256NC0BFIAU
S71WS256NC0BFIAZ
71WS256NC0BAWAP
71WS256NC0BAWAB
71WS256NC0BAWAF
71WS256NC0BAWAU
71WS256NC0BAWAZ
71WS256NC0BAIAK
71WS256NC0BAIAP
71WS256NC0BAIAB
71WS256NC0BAIAF
71WS256NC0BAIAU
71WS256NC0BAIAZ
71WS256NC0BFWAK
71WS256NC0BFWAP
71WS256NC0BFWAB
71WS256NC0BFWAF
71WS256NC0BFWAU
71WS256NC0BFWAZ
71WS256NC0BFIAK
71WS256NC0BFIAP
71WS256NC0BFIAB
71WS256NC0BFIAF
71WS256NC0BFIAU
71WS256NC0BFIAZ
0(Protected)
-25° to +85°C
CellularRAM 1
CosmoRAM 1
CellularRAM 2
CellularRAM 1
CosmoRAM 1
CellularRAM 2
CellularRAM 1
CosmoRAM 1
CellularRAM 2
CellularRAM 1
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
Pb-free
compliant
0(Protected)
1(Unprotected[Default
State])
0(Protected)
-40° to +85°C
-25° to +85°C
-40° to +85°C
1(Unprotected[Default
State])
0(Sectors Protected)
1(Unprotected[Default
State])
54MHz
0(Protected)
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
Pb-free
0(Protected)
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
17
256Mb - WS256N Flash + 128 pSRAM
Temperature
Range °C
Burst
Speed
Material
Set
Order Number
Package Marking
DYB Power-up State
Supplier
S71WS256ND0BAWEK
71WS256ND0BAWEK
0(Protected)
CellularRAM 2
1(Unprotected[Default
State])
S71WS256ND0BAWEP
S71WS256ND0BAWEU
S71WS256ND0BAWEZ
S71WS256ND0BAWE3
S71WS256ND0BAWE7
S71WS256ND0BAIEK
S71WS256ND0BAIEP
S71WS256ND0BAIEU
S71WS256ND0BAIEZ
S71WS256ND0BAIE3
S71WS256ND0BAIE7
S71WS256ND0BFWEK
S71WS256ND0BFWEP
S71WS256ND0BFWEU
S71WS256ND0BFWEZ
S71WS256ND0BFWE3
S71WS256ND0BFWE7
S71WS256ND0BFIEK
S71WS256ND0BFIEP
S71WS256ND0BFIEU
S71WS256ND0BFIEZ
S71WS256ND0BFIE3
S71WS256ND0BFIE7
71WS256ND0BAWEP
71WS256ND0BAWEU
71WS256ND0BAWEZ
71WS256ND0BAWE3
71WS256ND0BAWE7
71WS256ND0BAIEK
71WS256ND0BAIEP
71WS256ND0BAIEU
71WS256ND0BAIEZ
71WS256ND0BAIE3
71WS256ND0BAIE7
71WS256ND0BFWEK
71WS256ND0BFWEP
71WS256ND0BFWEU
71WS256ND0BFWEZ
71WS256ND0BFWE3
71WS256ND0BFWE7
71WS256ND0BFIEK
71WS256ND0BFIEP
71WS256ND0BFIEU
71WS256ND0BFIEZ
71WS256ND0BFIE3
71WS256ND0BFIE7
0(Protected)
CosmoRAM 1
-25° to +85°C
1(Unprotected[Default
State])
0(Protected)
1.8V RAM
Type 4
1(Unprotected[Default
State])
Pb-free
compliant
0(Protected)
CellularRAM 2
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
-40° to +85°C
-25° to +85°C
-40° to +85°C
1(Unprotected[Default
State])
0(Sectors Protected)
1.8V RAM
Type 4
1(Unprotected[Default
State])
54MHz
0(Protected)
CellularRAM 2
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Protected)
1.8V RAM
Type 4
1(Unprotected[Default
State])
Pb-free
0(Protected)
CellularRAM 2
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Protected)
1.8V RAM
Type 4
1(Unprotected[Default
State])
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
18
2x 256Mb—WS512N Flash + 64Mb pSRAM
Temperature
Range °C
Burst
Speed
Material
Set
Order Number
Package Marking
DYB Power-up State
Supplier
S71WS512NC0BAWAK
71WS512NC0BAWAK
0(Protected)
CellularRAM 2
1(Unprotected[Default
State])
S71WS512NC0BAWAP
S71WS512NC0BAWAU
S71WS512NC0BAWAZ
S71WS512NC0BAWAB
S71WS512NC0BAWAF
S71WS512NC0BAIAK
S71WS512NC0BAIAP
S71WS512NC0BAIAU
S71WS512NC0BAIAZ
S71WS512NC0BAIAB
S71WS512NC0BAIAF
S71WS512NC0BFWAK
S71WS512NC0BFWAP
S71WS512NC0BFWAU
S71WS512NC0BFWAZ
S71WS512NC0BFWAB
S71WS512NC0BFWAF
S71WS512NC0BFIAK
S71WS512NC0BFIAP
S71WS512NC0BFIAU
S71WS512NC0BFIAZ
S71WS512NC0BFIAB
S71WS512NC0BFIAF
71WS512NC0BAWAP
71WS512NC0BAWAU
71WS512NC0BAWAZ
71WS512NC0BAWAB
71WS512NC0BAWAF
71WS512NC0BAIAK
71WS512NC0BAIAP
71WS512NC0BAIAU
71WS512NC0BAIAZ
71WS512NC0BAIAB
71WS512NC0BAIAF
71WS512NC0BFWAK
71WS512NC0BFWAP
71WS512NC0BFWAU
71WS512NC0BFWAZ
71WS512NC0BFWAB
71WS512NC0BFWAF
71WS512NC0BFIAK
71WS512NC0BFIAP
71WS512NC0BFIAU
71WS512NC0BFIAZ
71WS512NC0BFIAB
71WS512NC0BFIAF
0(Protected)
CosmoRAM 1
CellularRAM 1
-25° to +85°C
-40° to +85°C
-25° to +85°C
-40° to +85°C
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
Pb-free
compliant
0(Protected)
CellularRAM 2
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Sectors Protected)
CellularRAM 1
1(Unprotected[Default
State])
54MHz
0(Protected)
CellularRAM 2
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Protected)
CellularRAM 1
1(Unprotected[Default
State])
Pb-free
0(Protected)
CellularRAM 2
CosmoRAM 1
1(Unprotected[Default
State])
0(Protected)
1(Unprotected[Default
State])
0(Protected)
CellularRAM 1
1(Unprotected[Default
State])
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
19
2x256Mb—WS256N Flash + 128Mb pSRAM
Te m p e r a t u re
Range °C
Burst
Speed
Material
Set
Order Number
Package Marking
DYB Power-up State
Supplier
S71WS512ND0BAWEK
71WS512ND0BAWEK
0(Protected)
CellularRAM 2
1(Unprotected [Default
State])
S71WS512ND0BAWEP
S71WS512ND0BAWE3
S71WS512ND0BAWE7
S71WS512ND0BAIEK
S71WS512ND0BAIEP
S71WS512ND0BAIE3
S71WS512ND0BAIE7
S71WS512ND0BFWEK
S71WS512ND0BFWEP
S71WS512ND0BFWE3
S71WS512ND0BFWE7
S71WS512ND0BFIEK
S71WS512ND0BFIEP
71WS512ND0BAWEP
71WS512ND0BAWE3
71WS512ND0BAWE7
71WS512ND0BAIEK
71WS512ND0BAIEP
71WS512ND0BAIE3
71WS512ND0BAIE7
71WS512ND0BFWEK
71WS512ND0BFWEP
71WS512ND0BFWE3
71WS512ND0BFWE7
71WS512ND0BFIEK
71WS512ND0BFIEP
-25° to +85°C
0(Protected)
1.8V RAM
Type 4
1(Unprotected [Default
State])
Pb-free
compliant
0(Protected)
CellularRAM 2
1(Unprotected [Default
State])
-40° to +85°C
0(Protected)
1.8V RAM
Type 4
1(Unprotected [Default
State])
54MHz
0(Protected)
CellularRAM 2
1(Unprotected [Default
State])
-25° to +85°C
0(Protected)
1.8V RAM
Type 4
1(Unprotected [Default
State])
Pb-free
0(Protected)
CellularRAM 2
1(Unprotected [Default
State])
-40° to +85°C
S71WS512ND0BFIE3
S71WS512ND0BFIE7
71WS512ND0BFIE3
71WS512ND0BFIE7
0(Protected)
0(Protected)
1.8V RAM
Type 4
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
20
Physical Dimensions
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
0.15
b
M
C
C
A B
0.08
M
NOTES:
PACKAGE
JEDEC
FEA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.10
1.11
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.26
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
21
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TSD 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.94
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
A2,A3,A4,A5,A6,7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3426\ 16-038.22
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
22
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm MCP
Compatible Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
Note: BSC is an ANSI standard for Basic Space Centering
October 26, 2004 S71WS512/256Nx0_00
S71WS512Nx0/S71WS256Nx0
23
S29WSxxxN MirrorBit™ Flash Family
For Multi-chip Products
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Distinctive Characteristics
—
—
—
Burst access times of 11.2/13.5 ns
Synchronous initial latency of 69/69 ns
Asynchronous random access times of 70/70 ns
Architectural Advantages
Single 1.8 volt read, program and erase (1.70 to
1.95 volt)
Manufactured on 110 nm MirrorBitTM process
technology
Program and Erase Performance
—
—
Typical word programming time of 40 µs
Typical effective word programming time of 9.4 µs
utilizing a 32-Word Write Buffer at VCC Level
Typical effective word programming time of 6 µs
utilizing a 32-Word Write Buffer at ACC Level
Typical sector erase time of 150 ms for 16 Kword
sectors and 600 ms sector erase time for 64 Kword
sectors
VersatileIO™ (VIO) Feature
—
Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
—
—
—
VIO options available for 1.8 V (1.70 V – 1.95 V)
Simultaneous Read/Write operation
Power dissipation (typical values @ 66 MHz)
—
Data can be continuously read from one bank while
executing erase/program functions in another bank
Zero latency between read and write operations
Sixteen bank architecture: Each bank consists of
16Mb (WS256N) / 8Mb (WS128N) / 4Mb (WS064N)
—
—
—
—
—
Continuous Burst Mode Read: 35 mA
Simultaneous Operation: 50 mA
Program: 19 mA
Erase: 19 mA
Standby mode: 20 µA
—
—
Programable Burst Interface
—
—
2 Modes of Burst Read Operation
Linear Burst: 32, 16, and 8 words with or without
wrap-around
Hardware Features
Sector Protection
—
—
Continuous Sequential Burst
Write protect (WP#) function allows protection of
eight outermost boot sectors, four at top and four at
bottom of memory, regardless of sector protect
status
SecSiTM (Secured Silicon) Sector region
—
256 words accessible through a command
sequence, 128 words for the Factory SecSi Sector
and 128 words for the Customer SecSi Sector.
Non-erasable region
Handshaking feature available
—
—
Provides host system with minimum possible latency
by monitoring RDY
Sector Architecture
Boot Option
Dual Boot
Low VCC write inhibit
—
—
—
—
S29WS256N: Eight 16 Kword sectors and two-
hundred-fifty-four 64 Kword sectors
S29WS128N: Eight 16 Kword sectors and one-
hundred-twenty-six 64 Kword sectors
S29WS064N: Eight 16 Kword sectors and sixty-two
64 Kword sectors
Banks 0 and 15 each contain 16 Kword sectors and
64 Kword sectors; Other banks each contain 64
Kword sectors
—
Security Features
Advanced Sector Protection consists of the two
following modes of operation
Persistent Sector Protection
—
A command sector protection method to lock
combinations of individual sectors to prevent
program or erase operations within that sector
—
Eight 16 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
—
Sectors can be locked and unlocked in-system at VCC
level
Cycling Endurance: 100,000 cycles per sector
typical
Password Sector Protection
—
Data Retention: 20 years typical
A sophisticated sector protection method to lock
combinations of individual sectors to prevent
program or erase operations within that sector using
a user-defined 64-bit password
Performance Characteristics
Read access times at 80/66/54 MHz
Publication Number S29WSxxxN_MCP00 Revision A Amendment 3 Issue Date August 31, 2004
Software Features
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4 standards
Data# Polling and toggle bits
—
Provides a software method of detecting program and erase operation completion
Erase Suspend/Resume
—
Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes
the erase operation
Program Suspend/Resume
—
Suspends a programming operation to read data from a sector other than the one being programmed, then resume the
programming operation
Unlock Bypass Program command
Reduces overall programming time when issuing multiple program command sequences
—
Additional Features
Program Operation
Ability to perform synchronous and asynchronous program operation independent of burst control register setting
ACC input
Acceleration function reduces programming and erase time in a factory setting.
—
—
25
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
General Description
The WSxxxN family consists of 256, 128, and 64 Mbit, 1.8 Volt-only, simultaneous
Read/Write, Burst Mode Flash memory devices, organized as 16, 8, or 4 Mwords
of 16 bits. These devices use a single V of 1.70 to 1.95 V to read, program, and
CC
erase the memory array. A 9.0-volt V
on ACC may be used for faster program
HH
performance in a factory setting. These devices can be programmed in standard
EPROM programmers.
At 66 MHz and 1.8V V , the device provides a burst access of 11.2 ns at 30 pF
IO
with an initial latency of 69 ns at 30 pF. At 54 MHz and 1.8V V , the device pro-
IO
vides a burst access of 13.5 ns at 30 pF with an initial latency of 69 ns at 30 pF.
The device operates within the industrial temperature range of -40°C to +85°C
or wireless temperature range of -25°C to +85°C. These devices are offered in
MCP compatible FBGA packages. See the product selector guide for details
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into sixteen banks. The device can improve over-
all system performance by allowing a host system to program or erase in one
bank, then immediately and simultaneously read from another bank, with zero
latency. This releases the system from waiting for the completion of program or
erase operations.
The devices are divided into banks and sectors as shown in the following table:
Quantity of Sectors
Bank
(WS256N/WS128N/WS064N)
Sector Size
16 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
16 Kwords
4/4/4
0
15/7/3
1
2
16/8/4
16/8/4
3
16/8/4
4
16/8/4
5
16/8/4
6
16/8/4
7
16/8/4
8
16/8/4
9
16/8/4
10
11
12
13
14
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
15/7/3
15
4/4/4
The VersatileIO™ (V ) control allows the host system to set the voltage levels
IO
that the device generates at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted on the V pin.
IO
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#)
and Output Enable (OE#) to control asynchronous read and write operations.
For burst operations, the device additionally requires Ready (RDY), and Clock
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
26
(CLK). This implementation allows easy interface with minimal glue logic to a
wide range of microprocessors/microcontrollers for high performance read
operations.
The burst read mode feature gives system designers flexibility in the interface to
the device. The user can preset the burst length and then wrap or non-wrap
through the same memory space, or read the flash array in continuous mode.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as
inputs to an internal state-machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the Embedded Program Algorithm — an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster program times by requiring only two
write cycles to program data instead of four. The additional Write Buffer Pro-
gramming feature provides superior programming performance by grouping
locations being programmed.
Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase Algorithm — an internal algorithm that automatically pre-
programs the array (if it is not already fully programmed) before executing the
erase operation. During erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
The Program Suspend/Program Resume feature enables the user to put
program on hold to read data from any sector that is not selected for program-
ming. If a read is needed from the SecSi Sector area, Persistent Protection area,
Dynamic Protection area, or the CFI area, after an program suspend, then the
user must use the proper command sequence to enter and exit this region. The
program suspend/resume functionality is also available when programming in
erase suspend (1 level depth only).
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a read is needed from
the SecSi Sector area, Persistent Protection area, Dynamic Protection area, or
the CFI area, after an erase suspend, then the user must use the proper com-
mand sequence to enter and exit this region.
The hardware RESET# pin terminates any operation in progress and resets
the internal state machine to reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus also reset the device, en-
abling the system microprocessor to read boot-up firmware from the Flash
memory device.
The host system can detect whether a memory array program or erase opera-
tion is complete by using the device status bit DQ7 (Data# Polling), DQ6/DQ2
(toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase start timeout state
indicator), and DQ1 (write to buffer abort). After a program or erase cycle has
been completed, the device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is
fully erased when shipped from the factory.
27
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Hardware data protection measures include a low V detector that automat-
CC
ically inhibits write operations during power transitions. The device also offers
two types of data protection at the sector level. When at V , WP# locks the
IL
four outermost boot sectors at the top of memory and the four outermost boot
sectors at the bottom of memory.
When the ACC pin = V , the entire flash memory array is protected.
IL
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is greatly reduced in both modes.
SpansionTM Flash memory products combine years of Flash memory manufactur-
ing experience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector. The data is
programmed using hot electron injection.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
28
Product Selector Guide
Part Number
S29WS256N, S29WS128N, S29WS064N
Speed Option (Burst Frequency) (See Note)
66 MHz
69
54 MHz
69
Max Synchronous Latency, ns (tIACC
)
Max Synchronous Burst Access Time, ns (tBACC
Max Asynchronous Access Time tCE), ns
Max CE# Access Time, ns (tCE), ns
)
11.2
70
13.5
70
70
70
Max OE# Access Time, ns (tOE
)
11.2
13.5
Note: 80 MHz available for standalone applications only, 66 MHz and 54 MHz available for both multi-chip and standalone applications.
Block Diagram
DQ15–DQ0
VCC
VSS
VIO
RDY
Buffer
RDY
Erase Voltage
Generator
Input/Output
Buffers
WE#
RESET#
WP#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0*
* WS256N: A23-A0
WS128N: A22-A0
WS064N: A21-A0
29
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Block Diagram of
Simultaneous Operation Circuit
V
CC
V
SS
V
IO
Bank Address
DQ15–DQ0
Bank 0
Amax–A0
X-Decoder
OE#
Bank Address
DQ15–DQ0
Bank 1
WP#
ACC
X-Decoder
Amax–A0
STATE
CONTROL
&
COMMAND
REGISTER
RESET#
WE#
DQ15–DQ0
Status
CE#
AVD#
RDY
Control
DQ15–DQ0
Amax–A0
X-Decoder
Bank 14
DQ15–DQ0
Bank Address
Amax–A0
Amax–A0
X-Decoder
Bank 15
Bank Address
DQ15–DQ0
Note: Amax=A23 for the WS256N, A22 for the WS128N, and A21 for the WS064N.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
30
Input/Output Descriptions
A23-A0
=
Address inputs for WS256N (A22-A0 for WS128 and
A21-A0 for WS064N).
DQ15-DQ0
CE#f1
=
=
Data input/output.
Chip Enable input. Asynchronous relative to CLK for
the Burst mode.
OE#
WE#
=
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
Write Enable input.
=
=
=
=
=
=
V
V
Device Power Supply.
CC
Ground.
SS
NC
RDY
CLK
No Connect; not connected internally.
Ready output. Indicates the status of the Burst read.
Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at V or V
IL
IH
while in asynchronous mode.
AVD#
=
Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs.
RESET#
WP#
=
=
Hardware reset input. Low = device resets and
returns to reading array data.
Hardware write protect input. At V , disables
IL
program and erase functions in the four outermost
sectors. Should be at V for all other conditions.
IH
ACC
RFU
=
=
Accelerated input. At V , accelerates.
programming; automatically places device in unlock
HH
bypass mode. At V , disables all program and erase
IL
functions. Should be at V for all other conditions.
IH
Reserved for future use (see MCP look-ahead pinout
for use with MCP).
31
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Logic Symbol
Max*+1
Amax*–A0
16
DQ15–DQ0
CLK
WP#
ACC
CE#
OE#
WE#
RDY
RESET#
AVD#
* max = 23 for the WS256N, 22 for the WS128N, and
21 for the WS064N.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
32
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Device Bus Operations
Operation
CE#
L
OE#
L
WE#
Addresses
Addr In
Addr In
Addr In
Addr In
X
DQ15–0
I/O
RESET#
CLK
X
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
H
H
L
H
H
H
H
H
L
L
L
I/O
X
L
L
L
H
I/O
X
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
L
X
L
H
H
Addr In
X
X
H
H
Advance Burst to next address with
appropriate Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
X
X
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
Addr In
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care.
VersatileIO™ (VIO) Control
The VersatileIO (V ) control allows the host system to set the voltage levels that
IO
the device generates at its data outputs and the voltages tolerated at its data in-
puts to the same voltage level that is asserted on the V pin.
IO
Requirements for Asynchronous (Non-Burst)
Read Operation
To read data from the memory array, the system must first assert a valid address
on A23–A0 for WS256N (A22–A0 for the WS128N, A21–A0 for WS064N), while
driving AVD# and CE# to V . WE# should remain at V . The rising edge of AVD#
IL
IH
latches the address. The data will appear on DQ15–DQ0.
Address access time (t ) is equal to the delay from stable addresses to valid
ACC
output data. The chip enable access time (t ) is the delay from the stable CE#
CE
to valid data at the outputs. The output enable access time (t ) is the delay from
OE
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data in asynchronous mode
upon device power-up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power transition.
33
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst read and linear burst read
of a preset length. When the device first powers up, it is enabled for asynchro-
nous read operation.
Prior to entering burst mode, the system should determine how many wait states
are desired for the initial word (t
) of each burst access, what mode of burst
IACC
operation is desired, and how the RDY signal will transition with valid data. The
system would then write the configuration register command sequence. See Set
Configuration Register Command Sequence for further details.
The initial word is output t
after the active edge of the first CLK cycle. Sub-
IACC
sequent words are output t
after the active edge of each successive clock
BACC
cycle at which point the internal address counter is automatically incremented.
Note that the device has a fixed internal address boundary that occurs every 128
words, starting at address 00007Fh. No boundary crossing latency is required
when the device operates at or below 66 MHz to reach address 000080h. When
the device operates above 66 MHz, a boundary crossing of one additional wait
state is required. The timing diagram can be found in Figure 27.
When the starting burst address is not divisible by four, additional waits are re-
quired. For example, if the starting burst address is divisible by four A1:0 = 00,
no additional wait state is required, but if the starting burst address is at address
A1:0 = 01, 10, or 11, one, two or three wait states are required, respectively,
until data D4 is read. The RDY output indicates this condition to the system by
deasserting (see Table 2).
Table 2. Address Dependent Additional Latency
Initial
Address
A[10]
Cycle
X+3
X
X+1
X+2
X+4
X+5
X+6
00
01
10
11
D0
D1
D2
D3
D1
D2
D3
—
D2
D3
—
D3
—
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
—
—
—
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
34
Tables 3–5 show the address latency for variable wait state scheme, as imple-
mented in WS128N and WS064N.
Table 3. Address Latency for 5 Wait States (≤ 68 MHz)
Wait
Word
Cycle
States
5 ws
5 ws
5 ws
5 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D3
1 ws
1 ws
1 ws
Table 4. Address Latency for 4 Wait States (≤ 54 MHz)
Wait
Cycle
States
Word
0
1
2
3
4 ws
4 ws
4 ws
4 ws
D0
D1
D2
D3
D1
D2
D2
D3
D4
D4
D3
D4
D5
D5
D4
D5
D6
D6
D5
D6
D7
D7
D6
D7
D8
D8
D7
D8
D9
D9
D8
D9
D3
D10
D10
1 ws
Table 5. Address Latency for 3 Wait States (≤ 40 MHz)
Wait
Cycle
States
Word
0
1
2
3
3 ws
3 ws
3 ws
3 ws
D0
D1
D2
D3
D1
D2
D3
D4
D2
D3
D4
D5
D3
D4
D5
D6
D4
D5
D6
D7
D5
D6
D7
D8
D6
D7
D8
D9
D7
D8
D8
D9
D9
D10
D11
D10
Tables 6-8 show the address/boundary crossing latency for variable wait state if
a boundary crossing occurs during initial access as implemented in WS128N and
WS064N.
Table 6. Address/Boundary Crossing Latency for 5 Wait States (< 68 MHz)
Wait
Word
Cycle
D4
States
5 ws
5 ws
5 ws
5 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
1 ws
1 ws
1 ws
D4
D4
D4
D3
1 ws
1 ws
1 ws
Table 7. Address/Boundary Crossing Latency for 4 Wait States (< 54 MHz)
Wait
Word
Cycle
States
4 ws
4 ws
4 ws
4 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D3
1 ws
1 ws
1 ws
35
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 8. Address/Boundary Crossing Latency for 3 Wait States (< 40 MHz)
Wait
Word
Cycle
States
3 ws
3 ws
3 ws
3 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D4
D4
D3
D4
D5
D5
D4
D5
D6
D6
D5
D6
D7
D7
D6
D7
D8
D8
D7
D8
D9
D9
D8
D9
D3
D10
D10
1 ws
Continuous Burst
The device will continue to output sequential burst data, wrapping around to ad-
dress 000000h after it reaches the highest addressable memory location, until
the system drives CE# high, RESET# low, or AVD# low in conjunction with a new
address. See Table 1.
If the host system crosses a 128-word line boundary while reading in burst mode,
and the subsequent word line is not programming or erasing, a one-cycle latency
is required as described above if the device is operating above 66 MHz. If the de-
vice is operating at or below 66 MHz, no boundary crossing latency is required. If
the host system crosses the bank boundary while the subsequent bank is pro-
gramming or erasing, the device will provide read status information. The clock
will be ignored. After the host has completed status reads, or the device has com-
pleted the program or erase operation, the host can restart a burst operation
using a new address and AVD# pulse.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The next three burst read modes are of the linear wrap around design, in which
a fixed number of words are read from consecutive addresses. In each of these
modes, the burst addresses read are determined by the group within which the
starting address falls. The groups are sized according to the number of words
read in a single burst sequence for a given mode (see Table 9.)
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
36
Table 9. Burst Address Groups
Mode
Group Size
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
8 words
16 words
32 words
For example, if the starting address in the 8-word mode is 3Ch, the address range
to be read would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-
39-3A-3Bh if wrap around is enabled. The burst sequence begins with the starting
address written to the device, but wraps back to the first address in the selected
group and stops at the group size, terminating the burst read. In a similar fash-
ion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on
the starting address written to the device, and then wrap back to the first address
in the selected address group. Note that in these three burst read modes the
address pointer does not cross the boundary that occurs every 128
words; thus, no wait states are inserted (except during the initial ac-
cess). (See Figure 14.)
8-, 16-, and 32-Word Linear Burst without Wrap Around
If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute
linearly up to the maximum memory address of the selected number of words.
The burst will stop after 8, 16, or 32 addresses and will not wrap around to the
first address of the selected group. For example: if the starting address in the 8-
word mode is 3Ch, the address range to be read would be 39-40h, and the burst
sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled.
The next address to be read will require a new address and AVD# pulse. Note
that in this burst read mode, the address pointer may cross the boundary that
occurs every 128 words.
Configuration Register
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, RDY configuration, and synchronous
mode active. For more information, see Table 24.
RDY: Ready
The RDY is a dedicated output, controlled by CE#. When the device is configured
in the Synchronous mode and RDY is at logic low, the system should wait 1 clock
cycle before expecting the next word of data.
Handshaking
The device is equipped with a handshaking feature that allows the host system
to simply monitor the RDY signal from the device to determine when the burst
data is ready to be read. The host system should use the programmable wait
state configuration to set the number of wait states for optimal burst mode oper-
ation. The initial word of burst data is indicated by the rising edge of RDY after
OE# goes low.
For optimal burst mode performance, the host system must set the appropriate
number of wait states in the flash device depending on clock frequency. See Set
Configuration Register Command Sequence and Requirements for Synchronous
(Burst) Read Operation for more information.
37
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while program-
ming or erasing in another bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank (ex-
cept the sector being erased). Figure 30 shows how read and write cycles may be
initiated for simultaneous operation with zero latency. Refer to the DC Character-
istics table for read-while-program and read-while-erase current specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous
write operation. While the device is configured in Asynchronous read it is able to
perform Asynchronous write operations only. CLK is ignored when the device is
configured in the Asynchronous mode. When in the Synchronous read mode con-
figuration, the device is able to perform both Asynchronous and Synchronous
write operations. CLK- and AVD#-induced address latches are supported in the
Synchronous programming mode. During a synchronous write operation, to write
a command or command sequence (which includes programming data to the de-
vice and erasing sectors of memory), the system must drive AVD# and CE# to
V , and OE# to V when providing an address to the device, and drive WE# and
IL
IH
CE# to V , and OE# to V when writing commands or data. During an asynchro-
IL
IH
nous write operation, the system must drive CE# and WE# to V and OE# to V
IL
IH
when providing an address, command, and data. Addresses are latched on the
last falling edge of WE# or CE#, while data is latched on the 1st rising edge of
WE# or CE# (see Table 24).
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 18–20 indicate the address space that each sector occupies. The device
address space is divided into sixteen banks: Banks 1 through 14 contain only 64
Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in ad-
dition to 64 Kword sectors. A “bank address” is the set of address bits required
to uniquely select a bank. Similarly, a “sector address” is the address bits re-
quired to uniquely select a sector.
I
in “DC Characteristics” represents the active current specification for the
CC2
write mode. “AC Characteristics—Synchronous” and “AC Characteristics—Asyn-
chronous” contain timing specification tables and timing diagrams for write
operations.
Unlock Bypass Mode
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a set of words, instead of four. See Unlock Bypass Command
Sequence for more details.
Accelerated Program/Chip Erase Operations
The device offers accelerated chip program and erase operations through the A
CC
function. This method is faster than the standard chip program and erase com-
mand sequences. The accelerated chip program and erase functions must
not be used more than 10 times per sector. In addition, accelerated chip pro-
gram and erase should be performed at room temperature (25°C 10°C).
The system can use the Write Buffer Load command sequence. Note that if a
“Write-to-Buffer-Abort Reset” is required, the full 3-cycle RESET command se-
quence must be used to reset the device. Removing V
from the ACC input,
HH
upon completion of the embedded program or erase operation, returns the device
August 31, 2004 S29WSxxxN_MCP00_A3 S29WSxxxN MirrorBit™ Flash Family
38
to normal operation. Note that sectors must be unlocked prior to raising ACC to
. Note that the ACC pin must not be at V for operations other than acceler-
V
HH
HH
ated programming and accelerated chip erase, or device damage may result. In
addition, the ACC pin must not be left floating or unconnected; inconsistent be-
havior of the device may result.
When at V , ACC locks all sectors. ACC should be at V for all other conditions.
IL
IH
Write Buffer Programming Operation
Write Buffer Programming allows the system to write a maximum of 32 words
in one programming operation. This results in a faster effective word program-
ming time than the standard “word” programming algorithms. The Write Buffer
Programming command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing the Write Buffer Load command
written at the starting address in which programming will occur. At this point, the
system writes the number of “word locations minus 1” that will be loaded into
the page buffer at the starting address in which programming will occur. This tells
the device how many write buffer addresses will be loaded with data and there-
fore when to expect the “Program Buffer to Flash” confirm command. The number
of locations to program cannot exceed the size of the write buffer or the operation
will abort. (NOTE: the number loaded = the number of locations to program
minus 1. For example, if the system will program 6 address locations, then 05h
should be written to the device.)
The system then writes the starting address/data combination. This starting ad-
dress is the first address/data pair to be programmed, and selects the “write-
buffer-page” address. All subsequent address/data pairs must fall within the “se-
lected-write-buffer-page”.
The “write-buffer-page” is selected by using the addresses A
- A5 where A
MAX
MAX
is A23 for WS256N, A22 for WS128N, and A21 for WS064N.
The “write-buffer-page” addresses must be the same for all address/data
pairs loaded into the write buffer. (This means Write Buffer Programming
cannot be performed across multiple “write-buffer-pages”. This also means that
Write Buffer Programming cannot be performed across multiple sectors. If the
system attempts to load programming data outside of the selected “write-buffer-
page”, the operation will ABORT.)
After writing the Starting Address/Data pair, the system then writes the remain-
ing address/data pairs into the write buffer. Write buffer locations may be loaded
in any order.
Note that if a Write Buffer address location is loaded multiple times, the “address/
data pair” counter will be decremented for every data load operation. Also,
the last data loaded at a location before the “Program Buffer to Flash” confirm
command will be programmed into the device. It is the software’s responsibility
to comprehend ramifications of loading a write-buffer location more than once.
The counter decrements for each data load operation, NOT for each unique
write-buffer-address location.
Once the specified number of write buffer locations have been loaded, the system
must then write the “Program Buffer to Flash” command at the Sector Address.
Any other address/data write combinations will abort the Write Buffer Program-
ming operation. The device will then “go busy.” The Data Bar polling techniques
should be used while monitoring the last address location loaded into the
write buffer. This eliminates the need to store an address in memory because
39
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
the system can load the last address location, issue the program confirm com-
mand at the last loaded address location, and then data bar poll at that same
address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the
device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using
the standard suspend/resume commands. Upon successful completion of the
Write Buffer Programming operation, the device will return to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following
conditions:
Load a value that is greater than the page buffer size during the “Number of
Locations to Program” step.
Write to an address in a sector different than the one specified during the
“Write-Buffer-Load” command.
Write an Address/Data pair to a different write-buffer-page than the one se-
lected by the “Starting Address” during the “write buffer data loading” stage
of the operation.
Write data other than the “Confirm Command” after the specified number of
“data load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last ad-
dress location loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write
Buffer Programming Operation was ABORTED. A “Write-to-Buffer-Abort reset”
command sequence is required when using the Write-Buffer-Programming fea-
tures in Unlock Bypass mode. Note that the SecSiTM sector, autoselect, and CFI
functions are unavailable when a program operation is in progress.
Use of the write buffer is strongly recommended for programming when
multiple words are to be programmed. Write buffer programming is allowed
in any sequence of memory (or address) locations. These flash devices are capa-
ble of handling multiple write buffer programming operations on the same write
buffer address range without intervening erases. However, programming the
same word address multiple times without intervening erases requires a modified
programming method. Please contact your local SpansionTM representative for
details.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output from the internal register
(separate from the memory array) on DQ15–DQ0. This mode is primarily in-
tended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. The autoselect
codes can also be accessed in-system.
When verifying sector protection, the sector address must appear on the appro-
priate highest order address bits (see Tables 18–20). The remaining address bits
are don’t care. When all necessary bits have been set as required, the program-
ming equipment may then read the corresponding identifier code on DQ15–DQ0.
The autoselect codes can also be accessed in-system through the command reg-
ister. See Command Definition Summary for command sequence requirements.
Note that if a Bank Address (BA) on the four uppermost address bits is asserted
during the third write cycle of the autoselect command, the host system can read
autoselect data from that bank and then immediately read array data from the
other bank, without exiting the autoselect mode.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
40
To access the autoselect codes, the host system must issue the autoselect com-
mand via the command register, as shown in the Command Definition Summary
section. See Autoselect Command Sequence for more information.
Advanced Sector Protection and Unprotection
This advanced security feature provides an additional level of protection to all
sectors against inadvertant program or erase operations.
The advanced sector protection feature disables both programming and erase op-
erations in a sector while the advanced sector unprotection feature re-enables
both program and erase operations in previously protected sectors. Sector pro-
tection/unprotection can be implemented using either or both of the two methods
Hardware method
Software method
Persistent/Password Sector Protection is achieved by using the software method
while the sector protection with WP# pin is achieved by using the hardware
method.
All parts default to operate in the Persistent Sector Protection mode. The cus-
tomer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method will be used.
Persistent Mode Lock Bit
Password Mode Lock Bit
If the customer decides to continue using the Persistent Sector Protection
method, they must set the Persistent Mode Lock Bit. This will permanently set
the part to operate using only Persistent Sector Protection. However, if the cus-
tomer decides to use the Password Sector Protection method, they must set the
Password Mode Lock Bit. This will permanently set the part to operate using
only Password Sector Protection.
It is important to remember that setting either the Persistent Mode Lock Bit
or the Password Mode Lock Bit permanently selects the protection mode. It is
not possible to switch between the two methods once a locking bit has been set.
It is important that one mode is explicitly selected when the device is
first programmed, rather than relying on the default mode alone. If both
are selected to be set at the same time, the operation will abort. This is
done so that it is not possible for a system program or virus to later set the Pass-
word Mode Locking Bit, which would cause an unexpected shift from the default
Persistent Sector Protection Mode into the Password Sector Protection Mode.
The device is shipped with all sectors unprotected. Optional SpansionTM program-
ming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for more details.
Persistent Mode Lock Bit
A Persistent Mode Lock Bit exists to guarantee that the device remain in software
sector protection. Once programmed (set to “0”), the Persistent Mode Lock Bit
prevents programming of the Password Mode Lock Bit. This allows protection
from potential hackers locking the device by placing the device in password sec-
tor protection mode and then changing the password accordingly.
Password Mode Lock Bit
In order to select the Password Sector Protection scheme, the customer must first
program the password. It is recommended that the password be somehow cor-
41
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
related to the unique Electronic Serial Number (ESN) of the particular flash
device. Each ESN is different for every flash device; therefore each password
should be different for every flash device. While programming in the password
region, the customer may perform Password Verify operations.
Once the desired password is programmed in, the customer must then set the
Password Mode Locking Bit. This operation achieves two objectives:
1.It permanently sets the device to operate using the Password Sector Protection
Mode. It is not possible to reverse this function.
2.It also disables all further commands to the password region. All program and
read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Sector Protec-
tion method is desired when setting the Password Mode Locking Bit. More
importantly, the user must be sure that the password is correct when the Pass-
word Mode Locking Bit is set. Due to the fact that read operations are disabled,
there is no means to verify what the password is after it is set. If the password
is lost after setting the Password Mode Lock Bit, there will be no way to clear the
PPB Lock Bit.
The Password Mode Lock Bit, once set, prevents reading the 64-bit password on
the DQ bus and further password programming. The Password Mode Lock Bit
is not erasable. Once the Password Mode Lock Bit is programmed, the Persistent
Mode Lock Bit is disabled from programming, guaranteeing that no changes to
the protection scheme are allowed.
Sector Protection
The device features several levels of sector protection, which can disable both the
program and erase operations in certain sectors.
Persistent Sector Protection
A software enabled command sector protection method that replaces the old 12
V controlled protection method.
Password Sector Protection
A highly sophisticated software enabled protection method that requires a pass-
word before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin (WP#) can prevent program or erase operations in the outer-
most sectors.The WP# Hardware Protection feature is always available,
independent of the software managed protection method chosen.
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protec-
tion method while at the same time enhancing flexibility by providing three
different sector protection states:
Persistently Locked—A sector is protected and cannot be changed.
Dynamically Locked—The sector is protected and can be changed by a simple
command
Unlocked—The sector is unprotected and can be changed by a simple com-
mand
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
42
In order to achieve these states, three types of “bits” namely Persistent Protec-
tion Bit (PPB), Dynamic Protection Bit (DYB), and Persistent Protection Bit Lock
(PPB Lock) are used to achieve the desired sector protection scheme
Persistent Protection Bit (PPB)
PPB is used to as an advanced security feature to protect individual sectors from
being programmed or erased thereby providing additional level of protection.
Every sector is assigned a Persistent Protection Bit.
Each PPB is individually programmed through the PPB Program Command.
However all PPBs are erased in parallel through the All PPB Erase Command.
Prior to erasing, these bits don’t have to be preprogrammed. The Embedded
Erase algorithm automatically preprograms and verifies prior to an electrical
erase. The system is not required to provide any controls or timings during these
operations.
The PPBs retain their state across power cycles because they are Non-Volatile.
The PPBs have the same endurance as the flash memory.
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode
PPB Lock Bit is a global volatile bit and provides an additional level of protection
to the sectors. When programmed (set to “0”), all the PPBs are locked and
hence none of them can be changed. When erased (cleared to “1”), the PPBs
are changeable. There is only one PPB Lock Bit in every device. Only a hardware
reset or a power-up clears the PPB Lock Bit. Note that there is no software solu-
tion; that is, there is no command sequence that would unlock the PPB Lock Bit.
Once all PPBs are configured to the desired settings, the PPB Lock Bit may be set
(programmed to “0”). The PPB Lock Bit is set by issuing the PPB Lock Bit Set Com-
mand. Programming or setting the PPB Lock Bit disables program and erase
commands to all the PPBs. In effect, the PPB Lock Bit locks the PPBs into their
current state. The only way to clear the PPB Lock Bit is to go through a hardware
or power-up reset. System boot code can determine if any changes to the PPB
are needed e.g. to allow new system code to be downloaded. If no changes are
needed then the boot code can disable the PPB Lock Bit to prevent any further
changes to the PPBs during system operation.
Dynamic Protection Bit (DYB)
DYB is another security feature used to protect individual sectors from being pro-
grammed or erased inadvertently. It is a volatile protection bit and is assigned to
each sector. Each DYB can be individually modified through the DYB Set Com-
mand or the DYB Clear Command.
The Protection Status for a particular sector is determined by the status of the
PPB and the DYB relative to that sector. For the sectors that have the PPBs cleared
(erased to “1”), the DYBs control whether or not the sector is protected or unpro-
tected. By issuing the DYB Set or Clear command sequences, the DYBs will be set
(programmed to “0”) or cleared (erased to “1”), thus placing each sector in the
protected or unprotected state respectively. These states are the so-called Dy-
namic Locked or Unlocked states due to the fact that they can switch back and
forth between the protected and unprotected states. This feature allows software
to easily protect sectors against inadvertent changes yet does not prevent the
easy removal of protection when changes are needed. The DYBs maybe set (pro-
grammed to “0”) or cleared (erased to “1”) as often as needed.
43
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon
power up or reset, the DYBs are set or cleared depending upon the ordering op-
tion chosen. If the option to clear the DYBs after power up is chosen, (erased to
“1”), then the sectors may be modified depending upon the PPB state of that sec-
tor. (See Table 10) If the option to set the DYBs after power up is chosen
(programmed to “0”), then the sectors would be in the protected state. The PPB
Lock Bit defaults to the cleared state (erased to “1”) after power up and the PPBs
retain their previous state as they are non-volatile.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Set command sequence
is all that is necessary. The DYB Set or Clear command for the dynamic sectors
signify protected or unprotected state of the sectors respectively. However, if
there is a need to change the status of the persistently locked sectors, a few more
steps are required. First, the PPB Lock Bit must be cleared by either putting the
device through a power-cycle, or hardware reset. The PPBs can then be changed
to reflect the desired settings. Setting the PPB Lock Bit once again will lock the
PPBs, and the device operates normally again.
To achieve the best protection, execute the PPB Lock Bit Set command early in
the boot code and protect the boot code by holding WP# = V . Note that the PPB
IL
and DYB bits have the same function when ACC = V
as they do when ACC =
HH
V .
IH
Table 10. Sector Protection Schemes
DYB
1
PPB
1
PPB Lock
Sector State
1
1
1
Sector Unprotected
0
1
Sector Protected through DYB
Sector Protected through PPB
1
0
Sector Protected through PPB
and DYB
0
0
1
1
0
1
1
1
0
0
0
0
Sector Unprotected
Sector Protected through DYB
Sector Protected through PPB
Sector Protected through PPB
and DYB
0
0
0
Table 10 contains all possible combinations of the DYB, PPB, and PPB Lock relating
to the status of the sector.
In summary, if the PPB is set (programmed to “0”), and the PPB Lock is set (pro-
grammed to “0”), the sector is protected and the protection can not be removed
until the next power cycle clears (erase to “1”) the PPB Lock Bit. Once the PPB
Lock Bit is cleared (erased to “1”), the sector can be persistently locked or un-
locked. Likewise, if both PPB Lock Bit or PPB is cleared (erased to “1”) the sector
can then be dynamically locked or unlocked. The DYB then controls whether or
not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program or erase command to a pro-
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
44
tected sector enables status polling and returns to read mode without having
modified the contents of the protected sector.
The programming of the DYB, PPB, and PPB Lock for a given sector can be verified
by writing individual status read commands DYB Status, PPB Status, and PPB
Lock Status to the device.
Password Sector Protection
The Password Sector Protection Mode method allows an even higher level of se-
curity than the Persistent Sector Protection Mode. There are two main differences
between the Persistent Sector Protection Mode and the Password Sector Protec-
tion Mode:
When the device is first powered up, or comes out of a reset cycle, the PPB
Lock Bit is set to the locked state, rather than cleared to the unlocked
state.
The only means to clear the PPB Lock Bit is by writing a unique 64-bit Pass-
word to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a non-erasable region of the flash memory. Once the
Password Mode Lock Bit is set, the password is permanently set with no means
to read, program, or erase it. The password is used to clear the PPB Lock Bit. The
Password Unlock command must be written to the flash, along with a password.
The flash device internally compares the given password with the pre-pro-
grammed password. If they match, the PPB Lock Bit is cleared, and the PPBs can
be altered. If they do not match, the flash device does nothing. There is a built-
in 1 µs delay for each “password check.” This delay is intended to thwart any ef-
forts to run a program that tries all possible combinations in order to crack the
password.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Verify commands. The password function
works in conjunction with the Password Mode Locking Bit, which when set, pre-
vents the Password Verify command from reading the contents of the password
on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode
The Persistent Protection Bit Lock (PPB Lock Bit) is a volatile bit that reflects the
state of the Password Mode Lock Bit after power-up reset. If the Password Mode
Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up re-
set, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is
to issue the Password Unlock command. Successful execution of the Password
Unlock command to enter the entire password clears the PPB Lock Bit, allowing
for sector PPBs modifications. Asserting RESET# or taking the device through a
power-on reset, resets the PPB Lock Bit to a “1”.
If the Password Mode Lock Bit is not set (device is operating in the default Per-
sistent Protection Mode). The Password Unlock command is ignored in Persistent
Sector Protection Mode.
45
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Lock Register
The Lock Register consists of 3 bits. The Customer SecSi Sector Protection Bit is
DQ0, Persistent Protection Mode Lock Bit is DQ1, and the Password Protection
Mode Lock Bit is DQ2. Each of these bits are non-volatile. DQ15-DQ3 are reserved
and will be 1’s.
Table 11. WS256N Lock Register
DQ15-3
DQ2
DQ1
DQ0
Password Protection Mode
Lock Bit
Persistent Protection Mode
Lock Bit
Customer SecSi Sector
Protection Bit
1’s
Table 12. WS128N/064N Lock Register
DQ15-5
DQ4
DQ3
DQ2
DQ1
DQ0
DYB Lock Boot Bit
0 = DYB bits, power up
protected
1 = DYB bits, power up
unprotected
PPB One-Time Programmable Bit
0 = All PPB erase command
disabled
1 = All PPB Erase command
enabled
Password
Protection
Mode Lock
Bit
Persistent
Protection
Mode Lock Protection Bit
Bit
SecSi Sector
Undefined
Hardware Data Protection Mode
The device offers two types of data protection at the sector level:
When WP# is at V , the four outermost sectors are locked (device specific).
IL
When ACC is at V , all sectors are locked.
IL
The write protect pin (WP#) adds a final level of hardware program and erase
protection to the outermost boot sectors. The outermost boot sectors are the sec-
tors containing both the lower and upper set of outermost sectors in a dual-boot-
configured device. When this pin is low it is not possible to change the con-
tents of these outermost sectors. These sectors generally hold system boot
code. So, the WP# pin can prevent any changes to the boot code that could over-
ride the choices made while setting up sector protection during system
initialization.
The following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals
during V power-up and power-down transitions, or from system noise.
CC
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the four out-
ermost sectors. This function is provided by the WP# pin and overrides the
previously discussed Sector Protection/Unprotection method.
If the system asserts V on the WP# pin during the command sequence, the de-
IL
vice disables program and erase functions in the “outermost” boot sectors. The
outermost boot sectors are the sectors containing both the lower and upper set
of sectors in a dual-boot-configured device.
If the system asserts V on the WP# pin, the device reverts to whether the boot
IH
sectors were last set to be protected or unprotected after the embedded opera-
tion. That is, sector protection or unprotection for these sectors depends on
whether they were last protected or unprotected.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
46
Note that the WP# pin must not be left floating or unconnected; inconsistent be-
havior of the device may result. The WP# pin must be held stable during a
command sequence.
Low VCC Write Inhibit
When V is less than V
, the device does not accept any write cycles. This pro-
CC
LKO
tects data during V power-up and power-down. The command register and all
CC
internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V is greater than V
. The sys-
CC
LKO
tem must provide the proper signals to the control inputs to prevent unintentional
writes when V is greater than V
.
LKO
CC
Write Pulse “Glitch” Protection
Noise pulses of less than t
on WE# do not initiate a write cycle.
WEP
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# =
IL
IH
V . To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
IH
logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = V and OE# = V during power up, the device does
IL
IH
not accept commands on the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the standby mode when the CE# and RESET# inputs are both
held at V . The device requires standard access time (t ) for read access, be-
CC
CE
fore it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
in “DC Characteristics” represents the standby current specification.
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. While in
asynchronous mode, the device automatically enables this mode when addresses
remain stable for t
+ 20 ns. The automatic sleep mode is independent of the
ACC
CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. While in synchronous mode, the au-
tomatic sleep mode is disabled. Note that a new burst operation is required to
provide new data.
I
in “DC Characteristics” represents the automatic sleep mode current
CC6
specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading
array data. When RESET# is driven low for at least a period of t , the device im-
RP
47
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
mediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V , the device draws CMOS standby current (I
). If RESET# is held at V ,
IL
SS
CC4
but not at V , the standby current will be greater.
SS
RESET# may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from
the Flash memory.
See Hardware Reset (RESET#) for RESET# parameters and to Figure 19 for the
timing diagram.
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The outputs are
IH
placed in the high impedance state.
SecSi™ (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides an extra Flash memory re-
gion that enables permanent part identification through an Electronic Serial
Number (ESN). The SecSi Sector is 256 words in length. All reads outside of the
256 word address range will return non-valid data. The Factory Indicator Bit,
DQ7, (at Autoselect address (BAS) + 03h) is used to indicate whether or not the
Factory SecSi Sector is locked when shipped from the factory. The Customer In-
dicator Bit (DQ6) is used to indicate whether or not the Customer SecSi Sector is
locked when shipped from the factory. The Factory SecSi bits are permanently set
at the factory and cannot be changed, which prevents cloning of a factory locked
part. This ensures the security of the ESN and customer code once the product is
shipped to the field.
The Factory portion of the SecSi Sector is locked when shipped and the Customer
SecSi Sector that is either locked or is lockable. The Factory SecSi Sector is al-
ways protected when shipped from the factory, and has the Factory Indicator Bit
(DQ7) permanently set to a “1”. The Customer SecSi Sector is typically shipped
unprotected (set to “0”), allowing customers to utilize that sector in any manner
they choose. Once the Customer SecSi Sector area is protected, the Customer
Indicator Bit will be permanently set to “1.”
The system accesses the SecSi Sector through a command sequence (see Enter
SecSi™ Sector/Exit SecSi Sector Command Sequence). After the system has
written the Enter SecSi Sector command sequence, it may read the SecSi Sector
by using the addresses normally occupied by sector SA0 within the memory ar-
ray. This mode of operation continues until the system issues the Exit SecSi
Sector command sequence, or until power is removed from the device. While
SecSi Sector access is enabled, Memory Array read access, program operations,
and erase operations to all sectors other than SA0 are also available. On power-
up, or following a hardware reset, the device reverts to sending commands to the
normal address space.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
48
Factory Locked: Factor SecSi Sector Programmed and Protected
At the Factory
In a factory sector locked device, the Factory SecSi Sector is protected when the
device is shipped from the factory. The Factory SecSi Sector cannot be modified
in any way. The device is pre programmed with both a random number and a se-
cure ESN. The Factory SecSi Sector is located at addresses 000000h–00007Fh.
The device is available pre programmed with one of the following:
A random, secure ESN only within the Factor SecSi Sector
Customer code within the Customer SecSi Sector through the SpansionTM pro-
gramming service
Both a random, secure ESN and customer code through the SpansionTM pro-
gramming service.
Table 13. SecSiTM Sector Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
Customers may opt to have their code programmed through the SpansionTM pro-
gramming services. Spansion programs the customer’s code, with or without the
random ESN. The devices are then shipped from the Spansion factory with the
Factory SecSi Sector and Customer SecSi Sector permanently locked. Contact
your local representative for details on using SpansionTM programming services.
Customer SecSi Sector
If the security feature is not required, the Customer SecSi Sector can be treated
as an additional Flash memory space. The Customer SecSi Sector can be read
any number of times, but can be programmed and locked only once. Note that
the accelerated programming (ACC) and unlock bypass functions are not avail-
able when programming the Customer SecSi Sector, but reading in Banks 1
through 15 is available. The Customer SecSi Sector is located at addresses
000080h–0000FFh.
The Customer SecSi Sector area can be protected by writing the SecSi Sector
Protection Bit Lock command sequence.
Once the Customer SecSi Sector is locked and verified, the system must write the
Exit SecSi Sector Region command sequence to return to reading and writing the
memory array. The device returns to the memory array at sector 0.
The Customer SecSi Sector lock must be used with caution since, once locked,
there is no procedure available for unlocking the Customer SecSi Sector area and
none of the bits in the Customer SecSi Sector memory space can be modified in
any way.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address (BA)555h any time the device is ready to read array
49
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
data. The system can read CFI information at valid addresses within that bank
(see Tables 14– 17). All reads outside of the CFI address range, within the bank,
will return non-valid data. Reads from other banks are allowed, writes are not. To
terminate reading CFI data, the system must write the reset command.
For further information, please refer to the CFI Specification and CFI Publication
100. Please contact your sales office for copies of these documents.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
50
Table 14. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 15. System Interface String
Addresses
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0017h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0019h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0006h
0009h
000Ah
0000h
0003h
004h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
003h
0000h
Table 16. Device Geometry Definition
Addresses
Data
Description
0019h (WS256N)
0018h (WS128N)
0017h (WS064N)
Device Size = 2N byte
27h
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ah
2Bh
0006h
0000h
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
51
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 16. Device Geometry Definition (Continued)
Addresses
Data
Description
00FDh (WS256N)
007Dh (WS128N)
003Dh (WS064N)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0002h
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Table 17. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0034h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0100h
Silicon Technology (Bits 5-2) 0100 = 0.11 µm
Erase Suspend
46h
47h
48h
49h
0002h
0001h
0000h
0008h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
00DFh (WS256N)
006Fh (WS128N)
0037h (WS064N)
Simultaneous Operation
Number of Sectors in all banks except boot bank
4Ah
Burst Mode Type
00 = Not Supported, 01 = Supported
4Bh
4Ch
0001h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
0085h
0095h
0001h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0001h = Dual Boot Device
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
52
Table 17. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
50h
0001h
Program Suspend. 00h = not supported
Unlock Bypass
51h
0001h
00 = Not Supported, 01=Supported
SecSi Sector (Customer OTP Area) Size 2N bytes
52h
53h
0007h
0014h
Hardware Reset Low Time-out during an embedded algorithm to read mode
Maximum 2N ns
Hardware Reset Low Time-out not during an embedded algorithm to read mode
Maximum 2N ns
54h
0014h
55h
56h
57h
0005h
0005h
0010h
Erase Suspend Time-out Maximum 2N ns
Program Suspend Time-out Maximum 2N ns
Bank Organization: X = Number of banks
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
Bank 0 Region Information. X = Number of sectors in bank
Bank 1 Region Information. X = Number of sectors in bank
Bank 2 Region Information. X = Number of sectors in bank
Bank 3 Region Information. X = Number of sectors in bank
Bank 4 Region Information. X = Number of sectors in bank
Bank 5 Region Information. X = Number of sectors in bank
Bank 6 Region Information. X = Number of sectors in bank
Bank 7 Region Information. X = Number of sectors in bank
Bank 8 Region Information. X = Number of sectors in bank
Bank 9 Region Information. X = Number of sectors in bank
Bank 10 Region Information. X = Number of sectors in bank
Bank 11 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
53
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 17. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
64h
Bank 12 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
65h
66h
67h
Bank 13 Region Information. X = Number of sectors in bank
Bank 14 Region Information. X = Number of sectors in bank
Bank 15 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
Table 18. WS256N Sector & Memory Address Map
Bank
Sector
SA0
Sector Size
16 Kwords
16 Kwords
16 Kwords
16 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
000000h-003FFFh
004000h-007FFFh
008000h-00BFFFh
00C000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
0000000000
0000000001
0000000010
0000000011
00000001XX
00000010XX
00000011XX
00000100XX
00000101XX
00000110XX
00000111XX
00001000XX
00001001XX
00001010XX
00001011XX
00001100XX
00001101XX
00001110XX
00001111XX
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
Bank 0
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
54
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
00010000XX
00010001XX
00010010XX
00010011XX
00010100XX
00010101XX
00010110XX
00010111XX
00011000XX
00011001XX
00011010XX
00011011XX
00011100XX
00011101XX
00011110XX
00011111XX
00100000XX
00100001XX
00100010XX
00100011XX
00100100XX
00100101XX
00100110XX
00100111XX
00101000XX
00101001XX
00101010XX
00101011XX
00101100XX
00101101XX
00101110XX
00101111XX
Bank 1
Bank 2
55
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
00110000XX
00110001XX
00110010XX
00110011XX
00110100XX
00110101XX
00110110XX
00110111XX
00111000XX
00111001XX
00111010XX
00111011XX
00111100XX
00111101XX
00111110XX
00111111XX
01000000XX
01000001XX
01000010XX
01000011XX
01000100XX
01000101XX
01000110XX
01000111XX
01001000XX
01001001XX
01001010XX
01001011XX
01001100XX
01001101XX
01001110XX
01001111XX
Bank 3
Bank 4
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
56
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA83
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
550000h-55FFFFh
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
640000h-64FFFFh
650000h-65FFFFh
660000h-66FFFFh
670000h-67FFFFh
680000h-68FFFFh
690000h-69FFFFh
6A0000h-6AFFFFh
6B0000h-6BFFFFh
6C0000h-6CFFFFh
6D0000h-6DFFFFh
6E0000h-6EFFFFh
6F0000h-6FFFFFh
01010000XX
01010001XX
01010010XX
01010011XX
01010100XX
01010101XX
01010110XX
01010111XX
01011000XX
01011001XX
01011010XX
01011011XX
01011100XX
01011101XX
01011110XX
01011111XX
01100000XX
01100001XX
01100010XX
01100011XX
01100100XX
01100101XX
01100110XX
01100111XX
01101000XX
01101001XX
01101010XX
01101011XX
01101100XX
01101101XX
01101110XX
01101111XX
SA84
SA85
SA86
SA87
SA88
SA89
SA90
Bank 5
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
Bank 6
57
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
700000h-70FFFFh
710000h-71FFFFh
720000h-72FFFFh
730000h-73FFFFh
740000h-74FFFFh
750000h-75FFFFh
760000h-76FFFFh
770000h-77FFFFh
780000h-78FFFFh
790000h-79FFFFh
7A0000h-7AFFFFh
7B0000h-7BFFFFh
7C0000h-7CFFFFh
7D0000h-7DFFFFh
7E0000h-7EFFFFh
7F0000h-7FFFFFh
800000h-80FFFFh
810000h-81FFFFh
820000h-82FFFFh
830000h-83FFFFh
840000h-84FFFFh
850000h-85FFFFh
860000h-86FFFFh
870000h-87FFFFh
880000h-88FFFFh
890000h-89FFFFh
8A0000h-8AFFFFh
8B0000h-8BFFFFh
8C0000h-8CFFFFh
8D0000h-8DFFFFh
8E0000h-8EFFFFh
8F0000h-8FFFFFh
01110000XX
01110001XX
01110010XX
01110011XX
01110100XX
01110101XX
01110110XX
01110111XX
01111000XX
01111001XX
01111010XX
01111011XX
01111100XX
01111101XX
01111110XX
01111111XX
10000000XX
10000001XX
10000010XX
10000011XX
10000100XX
10000101XX
10000110XX
10000111XX
10001000XX
10001001XX
10001010XX
10001011XX
10001100XX
10001101XX
10001110XX
10001111XX
Bank 7
Bank 8
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
58
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
900000h-90FFFFh
910000h-91FFFFh
920000h-92FFFFh
930000h-93FFFFh
940000h-94FFFFh
950000h-95FFFFh
960000h-96FFFFh
970000h-97FFFFh
980000h-98FFFFh
990000h-99FFFFh
9A0000h-9AFFFFh
9B0000h-9BFFFFh
9C0000h-9CFFFFh
9D0000h-9DFFFFh
9E0000h-9EFFFFh
9F0000h-9FFFFFh
A00000h-A0FFFFh
A10000h-A1FFFFh
A20000h-A2FFFFh
A30000h-A3FFFFh
A40000h-A4FFFFh
A50000h-A5FFFFh
A60000h-A6FFFFh
A70000h-A7FFFFh
A80000h-A8FFFFh
A90000h-A9FFFFh
AA0000h-AAFFFFh
AB0000h-ABFFFFh
AC0000h-ACFFFFh
AD0000h-ADFFFFh
AE0000h-AEFFFFh
AF0000h-AFFFFFh
10010000XX
10010001XX
10010010XX
10010011XX
10010100XX
10010101XX
10010110XX
10010111XX
10011000XX
10011001XX
10011010XX
10011011XX
10011100XX
10011101XX
10011110XX
10011111XX
10100000XX
10100001XX
10100010XX
10100011XX
10100100XX
10100101XX
10100110XX
10100111XX
10101000XX
10101001XX
10101010XX
10101011XX
10101100XX
10101101XX
10101110XX
10101111XX
Bank 9
Bank 10
59
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
B00000h-B0FFFFh
B10000h-B1FFFFh
B20000h-B2FFFFh
B30000h-B3FFFFh
B40000h-B4FFFFh
B50000h-B5FFFFh
B60000h-B6FFFFh
B70000h-B7FFFFh
B80000h-B8FFFFh
B90000h-B9FFFFh
BA0000h-BAFFFFh
BB0000h-BBFFFFh
BC0000h-BCFFFFh
BD0000h-BDFFFFh
BE0000h-BEFFFFh
BF0000h-BFFFFFh
C00000h-C0FFFFh
C10000h-C1FFFFh
C20000h-C2FFFFh
C30000h-C3FFFFh
C40000h-C4FFFFh
C50000h-C5FFFFh
C60000h-C6FFFFh
C70000h-C7FFFFh
C80000h-C8FFFFh
C90000h-C9FFFFh
CA0000h-CAFFFFh
CB0000h-CBFFFFh
CC0000h-CCFFFFh
CD0000h-CDFFFFh
CE0000h-CEFFFFh
CF0000h-CFFFFFh
10110000XX
10110001XX
10110010XX
10110011XX
10110100XX
10110101XX
10110110XX
10110111XX
10111000XX
10111001XX
10111010XX
10111011XX
10111100XX
10111101XX
10111110XX
10111111XX
11000000XX
11000001XX
11000010XX
11000011XX
11000100XX
11000101XX
11000110XX
11000111XX
11001000XX
11001001XX
11001010XX
11001011XX
11001100XX
11001101XX
11001110XX
11001111XX
Bank 11
Bank 12
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
60
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A23–A14
(x16) Address Range
D00000h-D0FFFFh
D10000h-D1FFFFh
D20000h-D2FFFFh
D30000h-D3FFFFh
D40000h-D4FFFFh
D50000h-D5FFFFh
D60000h-D6FFFFh
D70000h-D7FFFFh
D80000h-D8FFFFh
D90000h-D9FFFFh
DA0000h-DAFFFFh
DB0000h-DBFFFFh
DC0000h-DCFFFFh
DD0000h-DDFFFFh
DE0000h-DEFFFFh
DF0000h-DFFFFFh
E00000h-E0FFFFh
E10000h-E1FFFFh
E20000h-E2FFFFh
E30000h-E3FFFFh
E40000h-E4FFFFh
E50000h-E5FFFFh
E60000h-E6FFFFh
E70000h-E7FFFFh
E80000h-E8FFFFh
E90000h-E9FFFFh
EA0000h-EAFFFFh
EB0000h-EBFFFFh
EC0000h-ECFFFFh
ED0000h-EDFFFFh
EE0000h-EEFFFFh
EF0000h-EFFFFFh
11010000XX
11010001XX
11010010XX
11010011XX
11010100XX
11010101XX
11010110XX
11010111XX
11011000XX
11011001XX
11011010XX
11011011XX
11011100XX
11011101XX
11011110XX
11011111XX
11100000XX
11100001XX
11100010XX
11100011XX
11100100XX
11100101XX
11100110XX
11100111XX
11101000XX
11101001XX
11101010XX
11101011XX
11101100XX
11101101XX
11101110XX
11101111XX
Bank 13
Bank 14
61
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 18. WS256N Sector & Memory Address Map (Continued)
Bank
Sector
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
16 Kwords
16 Kwords
16 Kwords
16 Kwords
A23–A14
(x16) Address Range
F00000h-F0FFFFh
F10000h-F1FFFFh
F20000h-F2FFFFh
F30000h-F3FFFFh
F40000h-F4FFFFh
F50000h-F5FFFFh
F60000h-F6FFFFh
F70000h-F7FFFFh
F80000h-F8FFFFh
F90000h-F9FFFFh
FA0000h-FAFFFFh
FB0000h-FBFFFFh
FC0000h-FCFFFFh
FD0000h-FDFFFFh
FE0000h-FEFFFFh
FF0000h-FF3FFFh
FF4000h-FF7FFFh
FF8000h-FFBFFFh
FFC000h-FFFFFFh
11110000XX
11110001XX
11110010XX
11110011XX
11110100XX
11110101XX
11110110XX
11110111XX
11111000XX
11111001XX
11111010XX
11111011XX
11111100XX
11111101XX
11111110XX
1111111100
1111111101
1111111110
1111111111
Bank 15
Table 19. WS128N Sector & Memory Address Map
Bank
Sector
SA0
Sector Size
16 Kwords
16 Kwords
16 Kwords
16 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A22–A14
(x16) Address Range
000000h-003FFFh
004000h-007FFFh
008000h-00BFFFh
00C000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
000000000
000000001
000000010
000000011
0000001XX
0000010XX
0000011XX
0000100XX
0000101XX
0000110XX
0000111XX
0001000XX
0001001XX
0001010XX
0001011XX
0001100XX
0001101XX
0001110XX
0001111XX
SA1
SA2
SA3
SA4
Bank 0
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Bank 1
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
62
Table 19. WS128N Sector & Memory Address Map (Continued)
Bank
Sector
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A22–A14
(x16) Address Range
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
0010000XX
0010001XX
0010010XX
0010011XX
0010100XX
0010101XX
0010110XX
0010111XX
0011000XX
0011001XX
0011010XX
0011011XX
0011100XX
0011101XX
0011110XX
0011111XX
0100000XX
0100001XX
0100010XX
0100011XX
0100100XX
0100101XX
0100110XX
0100111XX
0101000XX
0101001XX
0101010XX
0101011XX
0101100XX
0101101XX
0101110XX
0101111XX
0110000XX
0110001XX
0110010XX
0110011XX
0110100XX
0110101XX
0110110XX
0110111XX
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
63
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 19. WS128N Sector & Memory Address Map (Continued)
Bank
Sector
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A22–A14
(x16) Address Range
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
550000h-55FFFFh
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
0111000XX
0111001XX
0111010XX
0111011XX
0111100XX
0111101XX
0111110XX
0111111XX
1000000XX
1000001XX
1000010XX
1000011XX
1000100XX
1000101XX
1000110XX
1000111XX
1001000XX
1001001XX
1001010XX
1001011XX
1001100XX
1001101XX
1001110XX
1001111XX
1010000XX
1010001XX
1010010XX
1010011XX
1010100XX
1010101XX
1010110XX
1010111XX
1011000XX
1011001XX
1011010XX
1011011XX
1011100XX
1011101XX
1011110XX
1011111XX
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
64
Table 19. WS128N Sector & Memory Address Map (Continued)
Bank
Sector
SA99
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
16 Kwords
16 Kwords
16 Kwords
16 Kwords
A22–A14
(x16) Address Range
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
640000h-64FFFFh
650000h-65FFFFh
660000h-66FFFFh
670000h-67FFFFh
680000h-68FFFFh
690000h-69FFFFh
6A0000h-6AFFFFh
6B0000h-6BFFFFh
6C0000h-6CFFFFh
6D0000h-6DFFFFh
6E0000h-6EFFFFh
6F0000h-6FFFFFh
700000h-70FFFFh
710000h-71FFFFh
720000h-72FFFFh
730000h-73FFFFh
740000h-74FFFFh
750000h-75FFFFh
760000h-76FFFFh
770000h-77FFFFh
780000h-78FFFFh
790000h-79FFFFh
7A0000h-7AFFFFh
7B0000h-7BFFFFh
7C0000h-7CFFFFh
7D0000h-7DFFFFh
7E0000h-7EFFFFh
7F0000h-7F3FFFh
7F4000h-7F7FFFh
7F8000h-7FBFFFh
7FC000h-7FFFFFh
1100000XX
1100001XX
1100010XX
1100011XX
1100100XX
1100101XX
1100110XX
1100111XX
1101000XX
1101001XX
1101010XX
1101011XX
1101100XX
1101101XX
1101110XX
1101111XX
1110000XX
1110001XX
1110010XX
1110011XX
1110100XX
1110101XX
1110110XX
1110111XX
1111000XX
1111001XX
1111010XX
1111011XX
1111100XX
1111101XX
1111110XX
111111100
111111101
111111110
111111111
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
Bank 12
Bank 13
Bank 14
Bank 15
65
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 20. WS064N Sector & Memory Address Map
Bank
Sector
SA0
Sector Size
16 Kwords
16 Kwords
16 Kwords
16 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
A21–A14
(x16) Address Range
000000h-003FFFh
004000h-007FFFh
008000h-00BFFFh
00C000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
00000000
00000001
00000010
00000011
000001XX
000010XX
000011XX
000100XX
000101XX
000110XX
000111XX
001000XX
001001XX
001010XX
001011XX
001100XX
001101XX
001110XX
001111XX
010000XX
010001XX
010010XX
010011XX
010100XX
010101XX
010110XX
010111XX
011000XX
011001XX
011010XX
011011XX
011100XX
011101XX
011110XX
011111XX
100000XX
100001XX
100010XX
100011XX
SA1
SA2
Bank 0
SA3
SA4
SA5
SA6
SA7
SA8
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
66
Table 20. WS064N Sector & Memory Address Map (Continued)
Bank
Sector
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
16 Kwords
16 Kwords
16 Kwords
16 Kwords
A21–A14
(x16) Address Range
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F3FFFh
3F4000h-3F7FFFh
3F8000h-3FBFFFh
3FC000h-3FFFFFh
100100XX
100101XX
100110XX
100111XX
101000XX
101001XX
101010XX
101011XX
101100XX
101101XX
101110XX
101111XX
110000XX
110001XX
110010XX
110011XX
110100XX
110101XX
110110XX
110111XX
111000XX
111001XX
111010XX
111011XX
111100XX
111101XX
111110XX
11111100
11111101
11111110
11111111
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
67
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. The Command Definition Summary section
defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence may place the device in an
unknown state. The system must write the reset command to return the device
to reading array data. See “AC Characteristics—Synchronous” and “AC Charac-
teristics—Asynchronous” for timing diagrams.
Reading Array Data
The device is automatically set to reading asynchronous array data after device
power-up. No commands are required to retrieve data in asynchronous mode.
Each bank is ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. After completing a pro-
gramming operation in the Erase Suspend mode, the system may once again
read array data from any non-erase-suspended sector within the same bank. See
Erase Suspend/Erase Resume Commands for more information.
After the device accepts a Program Suspend command, the corresponding bank
enters the program-suspend-read mode, after which the system can read data
from any non-program-suspended sector within the same bank. See Program
Suspend/Program Resume Commands for more information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See Reset Command for more
information. If DQ1 goes high during Write Buffer Programming, the system must
issue the Write Buffer Abort Reset command.
See also Requirements for Asynchronous (Non-Burst) Read Operation and Re-
quirements for Synchronous (Burst) Read Operation for more information. The
Asynchronous Read and Synchronous/Burst Read tables provide the read param-
eters, and Figure 13, and Figure 17 show the timings.
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, RDY configuration, and synchronous
mode active (see Figure 24 for details). The configuration register must be set
before the device will enter burst mode. On power up or reset, the device is set
in asynchronous read mode and the configuration register is reset. The configu-
ration register is not reset after deasserting CE#.
The configuration register is loaded with a four-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be D0h and address bits should be 555h. During the fourth cycle, the con-
figuration code should be entered onto the data bus with the address bus set to
address 000h. Once the data has been programmed into the configuration regis-
ter, a software reset command is required to set the device into the correct state.
The device will power up or after a hardware reset with the default setting, which
is in asynchronous mode. The register must be set before the device can enter
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
68
synchronous mode. The configuration register can not be changed during device
operations (program, erase, or sector lock).
Read Configuration Register Command Sequence
The configuration register can be read with a four-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be C6h and address bits should be 555h. During the fourth cycle, the con-
figuration code should be read out of the data bus with the address bus set to
address 000h. Once the data has been read from the configuration register, a
software reset command is required to set the device into the array read mode.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Asynchronous Mode
(D15 = 1)
Synchronous Read
Mode Only
Figure 1. Synchronous/Asynchronous State Diagram
Read Mode Setting
This setting allows the system to enable or disable burst mode during system op-
erations. Configuration Bit CR15 determines this setting: “1’ for asynchronous
mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock
cycles that must elapse after AVD# is driven active before data will be available.
This value is determined by the input frequency of the device. Configuration Bit
CR13–CR11 determine the setting (see Table 21).
The wait state command sequence instructs the device to set a particular number
of clock cycles for the initial access in burst mode. The number of wait states that
should be programmed into the device is directly related to the clock frequency.
69
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 21. Programmable Wait State Settings
CR13
0
CR12
0
CR11
0
Total Initial Access Cycles
2
0
0
1
3
0
1
0
4
5
0
1
1
1
0
0
6
1
0
1
7 (default)
Reserved
Reserved
1
1
0
1
1
1
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set
to a total initial access cycle of 2.
It is recommended that the wait state command sequence be written, even if the
default wait state value is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default setting.
Programmable Wait State
If the device is equipped with the handshaking option, the host system should set
CR13-CR11 to 010 for a clock frequency of 54 MHz, to 011 for a clock frequency
of 66 MHz, or to 100 for a clock frequency of 80 MHz for the system/device to
execute at maximum speed.
Table 22 describes the typical number of clock cycles (wait states) for various
conditions.
Boundary Crossing Latency
If the device is operating above 66 MHz, an additional wait state must be inserted
to account for boundary crossing latency. This is done by setting CR14 to a ‘1’
(default). If the device is operating at or below 66 MHz, the additional wait state
for boundary crossing is not needed. Therefore the CR14 can be changed to a ‘0’
to remove boundary crossing latency.
Table 22. Wait States for Handshaking
Typical No. of Clock Cycles after AVD#
Low
Conditions at Address
54 MHz
66 MHz
80 MHz
Initial address (VIO = 1.8 V)
4
5
6
Handshaking
For optimal burst mode performance, the host system must set the appropriate
number of wait states in the flash device depending on the clock frequency.
The autoselect function allows the host system to determine whether the flash
device is enabled for handshaking. See Autoselect Command Sequence for more
information.
Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and
32 word linear with or without wrap around modes. A continuous sequence (de-
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
70
fault) begins at the starting address and advances the address pointer until the
burst operation is complete. If the highest address in the device is reached during
the continuous burst read mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap around begins on the starting
address written to the device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after the previous eight word
boundary, wrapping through the starting location. The sixteen- and thirty-two lin-
ear wrap around modes operate in a fashion similar to the eight-word mode.
Table 23 shows the CR2-CR0 and settings for the four read modes.
Table 23. Burst Length Configuration
Address Bits
Burst Modes
Continuous
CR2
0
CR1
0
CR0
0
8-word linear
16-word linear
32-word linear
0
1
0
0
1
1
1
0
0
Note: Upon power-up or hardware reset the default setting is continuous.
Burst Wrap Around
By default, the device will perform burst wrap around with CR3 set to a ‘1’.
Changing the CR3 to a ‘0’ disables burst wrap around.
RDY Configuration
By default, the device is set so that the RDY pin will output V
whenever there
OH
is valid data on the outputs. The device can be set so that RDY goes active one
data cycle before active data. CR8 determines this setting; “1” for RDY active
(default) with data, “0” for RDY active one clock cycle before valid data.
RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a
new transaction with CR10 set to a ‘1’. In this case, the RDY pin is active high.
Changing the CR10 to a ‘0’ sets the RDY pin to be active low. In this case, the
RDY pin will always indicate that the device is ready to handle a new transaction
when low.
71
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Configuration Register
Table 24 shows the address bits that determine the configuration register settings
for various device functions.
Table 24. Configuration Register
CR Bit
Function
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
CR15
Set Device Read Mode
0 = No extra boundary crossing latency
CR14
CR13
Boundary Crossing
1 = With extra boundary crossing latency (default)
000 = Data is valid on the 2nd active CLK edge after addresses are latched
001 = Data is valid on the 3rd active CLK edge after addresses are latched
010 = Data is valid on the 4th active CLK edge after addresses are latched
011 = Data is valid on the 5th active CLK edge after addresses are latched
100 = Data is valid on the 6th active CLK edge after addresses are latched
101 = Data is valid on the 7th active CLK edge after addresses are latched (default)
110 = Reserved
CR12
Programmable
Wait State
CR11
CR10
111 = Reserved
0 = RDY signal is active low
RDY Polarity
1 = RDY signal is active high (default)
CR9
CR8
Reserved
RDY
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
CR7
CR6
CR5
CR4
Reserved
Reserved
Reserved
Reserved
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR3
CR2
Burst Wrap Around
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR1
CR0
Burst Length
Note:
1. Device will be in the default state upon power-up or hardware reset.
2. If CR2 is set to ‘0’, then the CR3 bit will automatically revert to 1 regardless of the user setting.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins (prior to the third cycle). This re-
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
72
sets the bank to which the system was writing to the read mode. If the program
command sequence is written to a bank that is in the Erase Suspend mode, writ-
ing the reset command returns that bank to the erase-suspend-read mode. Once
programming begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend and program-suspend-read mode if that bank was in Pro-
gram Suspend).
Note: If DQ1 goes high during a Write Buffer Programming operation, the system
must write the “Write to Buffer Abort Reset” command sequence to RESET the
device to reading array data. The standard RESET command will not work. See
Table 17 for details on this command sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
The Command Definition Summary shows the address and data requirements.
The autoselect command sequence may be written to an address within a bank
that is either in the read or erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in the
other bank. Autoselect does not support simultaneous operations nor burst
mode.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the bank address and the au-
toselect command. The bank then enters the autoselect mode. The system may
read at any address within the same bank any number of times without initiating
another autoselect command sequence. Read commands to other banks will re-
turn data from the array. Writes to other banks is not allowed. The following table
describes the address requirements for the various autoselect functions, and the
resulting data. BA represents the bank address. The device ID is read in three
cycles.
73
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 25. Autoselect Addresses
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data
(BA) + 00h
(BA) + 01h
0001h
227Eh
2230 (WS256N)
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh
(BA) + 0Fh
2232 (WS064N)
2231 (WS128N)
2200
DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
Indicator Bits
(See Note)
(BA) + 03h
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option), 0 =
Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed, 0 = Erase
disabled
Sector Block Lock/
Unlock
(SA) + 02h
0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 will be reserved.
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight
word electronic serial number (ESN). The system can access the SecSi Sector re-
gion by issuing the three-cycle Enter SecSi Sector command sequence. The
device continues to access the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command
sequence returns the device to normal operation. The SecSi Sector is not acces-
sible when the device is executing an Embedded Program or embedded Erase
algorithm. See Command Definition Summary for address and data requirements
for both command sequences.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin (see Figure 2).
When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Op-
eration Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored except the Program Suspend command. Note that the SecSi Sec-
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
74
tor, autoselect, and CFI functions are unavailable when a program
operation is in progress. Note that a hardware reset immediately terminates
the program operation. The program command sequence should be reinitiated
once the device has returned to the read mode, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. Program-
ming to the same word address multiple times without intervening erases is
limited. For such application requirements, please contact your local Spansion
representative. A “0” cannot be programmed back to a “1.” Attempting to
do so will cause the device to set DQ5 = 1 (halting any further operation and re-
quiring a reset command). A succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.” See Figure 2.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Command Definition Summary for program command sequence.
Figure 2. Word Program Operation
Write Buffer Programming Command Sequence
Write Buffer Programming Command Sequence allows for faster programming
compared to the standard Program Command Sequence. Write Buffer Program-
ming allows the system to write up to 32 words in one programming operation.
See Write Buffer Programming Operation section for the program command
sequence.
75
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 26. Write Buffer Command Sequence
Sequence
Address
555
Data
00AA
0055
Comment
Not required in the Unlock Bypass mode
Same as above
Unlock Command 1
Unlock Command 2
Write Buffer Load
2AA
Starting Address
0025h
Specify the Number of Program
Locations
Starting Address
Starting Address
Word Count
Number of locations to program minus 1
All addresses must be within write-buffer-page
boundaries, but do not have to be loaded in any order
Load 1st data word
Program Data
Write Buffer
Location
Load next data word
...
Program Data
...
Same as above
Same as above
Same as above
...
Write Buffer
Location
Load last data word
Program Data
This command must follow the last write buffer location
loaded, or the operation will ABORT
Write Buffer Program Confirm
Device goes busy
Sector Address
0029h
Status monitoring through DQ pins
(Perform Data Bar Polling on the Last
Loaded Address)
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
76
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Yes
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ15 - DQ0 at
Last Loaded Address
Yes
DQ7 = Data?
No
No
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
Yes
DQ7 = Data?
No
FAIL or ABORT
PASS
Figure 3. Write Buffer Programming Operation
77
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Unlock Bypass Command Sequence
The unlock bypass feature allows faster programming than the standard word
program command sequence. The unlock bypass command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command sequence is all that is re-
quired to program in this mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. See Command
Definition Summary for the unlock bypass command sequences requirements.
During the unlock bypass mode, only the Read, Unlock Bypass Program, and Un-
lock Bypass Reset commands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset command sequence. The
first cycle must contain the bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns to the read mode.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. See Command Definition Summary for chip erase
command sequence address and data requirements.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7 or DQ6/DQ2. See Write Operation Status for
information on these status bits.
Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once that bank
has returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. See Erase/Program
Timing for parameters and timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. See Command Definition
Summary for sector erase command sequence address and data requirements.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
78
After the command sequence is written, a sector erase time-out of no less than
occurs. During the time-out period, additional sector addresses and sector
t
SEA
erase commands may be written. Loading the sector erase buffer may be done
in any sequence, and the number of sectors may be from one sector to all sectors.
The time between these additional cycles must be less than t
. Any sector erase
SEA
address and command following the exceeded time-out (t
) may or may not be
SEA
accepted. Any command other than Sector Erase or Erase Suspend during the
time-out period resets that bank to the read mode.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See DQ3: Sector Erase Start Timeout State Indicator.) The time-out begins from
the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
banks. The system can determine the status of the erase operation by reading
DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for information
on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. See Erase/Program
Timing for parameters and timing diagrams.
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Command Definition Summary for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Figure 4. Erase Operation
79
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase oper-
ation and then read data from, or program data to, any sector not selected for
erasure. The bank address is required when writing this command. This com-
mand is valid only during the sector erase operation, including the t
time-out
SEA
period during the sector erase command sequence. The Erase Suspend command
is ignored if written during the chip erase operation.
When the Erase Suspend command is written during the sector erase operation,
the device requires t
(erase suspend latency) to suspend the erase operation.
ESL
However, when the Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out period and suspends
the erase operation.
After the erase operation has been suspended, the bank enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to Table 30 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the
erase-suspend-read mode. The system can determine the status of the program
operation using the DQ7 or DQ6 status bits, just as in the standard program
operation.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. See Write Buffer Programming Operation and the Autoselect
Command Sequence for details.
To resume the sector erase operation, the system must write the Erase Resume
command. The bank address of the erase-suspended bank is required when writ-
ing this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing.
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded
programming operation or a “Write to Buffer” programming operation so that
data can read from any non-suspended sector. When the Program Suspend com-
mand is written during a programming process, the device halts the
programming operation within t
(program suspend latency) and updates the
PSL
status bits. Addresses are “don’t-cares” when writing the Program Suspend
command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command may also
be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the SecSi Sector area, then user must use the
proper command sequences to enter and exit this region.
The system may also write the autoselect command sequence when the device
is in Program Suspend mode. The device allows reading autoselect codes in the
suspended sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to Program Suspend mode,
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
80
and is ready for another valid operation. See “Autoselect Command Sequence”
for more information.
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write
Operation Status” for more information.
The system must write the Program Resume command (address bits are “don’t
care”) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Program Resume command are ignored. Another
Program Suspend command can be written after the device has resumed
programming.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to program the SecSi Sector
Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection Mode
Lock Bit one time. The Lock Command Set also allows for the reading of the SecSi
Sector Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection
Mode Lock Bit.
The Lock Register Command Set Entry command sequence must be issued
prior to any of the following commands to enable proper command execution.
Lock Register Program Command
Lock Register Read Command
Lock Register Exit Command
Note that issuing the Lock Register Command Set Entry command disables reads
and writes for Bank 0. Reads from other banks excluding Bank 0 are allowed.
The Lock Register Command Set Exit command must be issued after the execu-
tion of the commands to reset the device to read mode, and re-enables reads and
writes for Bank 0.
Note that if the Persistent Protection Mode Locking Bit and the Password Protec-
tion Mode Locking Bit are programmed at the same time, neither will be
programmed.
Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit
password, verify the programming of the 64-bit password, and then later unlock
the device by issuing the valid 64-bit password.
The Password Protection Command Set Entry command sequence must be
issued prior to any of the following commands to enable proper command
execution.
Password Program Command
Password Read Command
Password Unlock Command
Note that issuing the Password Protection Command Set Entry command
disables reads and writes for Bank 0. Reads and writes for other banks excluding
Bank 0 are allowed.
The Password Program Command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64 bits
81
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
long. There is no special addressing order required for programming the
password.
Once the Password is written and verified, the Password Mode Locking Bit must
be set in order to prevent verification. The Password Program Command is only
capable of programming “0”s. Programming a “1” after a cell is programmed as
a “0” results in a time-out by the Embedded Program Algorithm with the cell re-
maining as a “0”. The password is all “1”s when shipped from the factory. All 64-
bit password combinations are valid as a password.
The Password Verify Command is used to verify the Password. The Password is
verifiable only when the Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the user attempts to verify the
Password, the device will always drive all “1”s onto the DQ data bus.
The lower two address bits (A1–A0) are valid during the Password Read, Pass-
word Program, and Password Unlock.
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs
can be unlocked for modification, thereby allowing the PPBs to become accessible
for modification. The exact password must be entered in order for the unlocking
function to occur. This command cannot be issued any faster than 1 µs at a time
to prevent a hacker from running through all the 64-bit combinations in an at-
tempt to correctly match a password. If the command is issued before the 1 µs
execution window for each portion of the unlock, the command will be ignored.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit. The
password is 64 bits long. A1 and A0 are used for matching. Writing the Password
Unlock command does not need to be address order specific. An example se-
quence is starting with the lower address A1–A0= 00, followed by A1–A0= 01,
A1–A0= 10, and A1–A0= 11.
Approximately 1 µSec is required for unlocking the device after the valid 64-bit
password is given to the device. It is the responsibility of the microprocessor to
keep track of the 64-bit password as it is entered with the Password Unlock com-
mand, the order, and when to read the PPB Lock bit to confirm successful
password unlock. In order to re-lock the device into the Password Mode, the PPB
Lock Bit Set command can be re-issued.
The Password Protection Command Set Exit command must be issued after
the execution of the commands listed previously to reset the device to read
mode, otherwise the device will hang. Note that issuing the Password Protec-
tion Command Set Exit command re-enables reads and writes for Bank 0.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the
Persistent Protection Bits (PPBs), erase all of the Persistent Protection Bits (PPBs),
and read the logic state of the Persistent Protection Bits (PPBs).
The Non-Volatile Sector Protection Command Set Entry command se-
quence must be issued prior to any of the following commands to enable proper
command execution.
PPB Program Command
All PPB Erase Command
PPB Status Read Command
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
82
Note that issuing the Non-Volatile Sector Protection Command Set Entry
command disables reads and writes for the bank selected. Reads within that bank
will return the PPB status for that sector. Reads from other banks are allowed;
writes are not allowed. All Reads must be performed using the Asynchronous
mode.
The PPB Program command is used to program, or set, a given PPB. Each PPB is
individually programmed (but is bulk erased with the other PPBs). The specific
sector address (A23–A14 WS256N, A22–A14 WS128N, A21–A14 WS064N) are
written at the same time as the program command. If the PPB Lock Bit is set, the
PPB Program command will not execute and the command will time-out without
programming the PPB.
The All PPB Erase command is used to erase all PPBs in bulk. There is no means
for individually erasing a specific PPB. Unlike the PPB program, no specific sector
address is required. However, when the PPB erase command is written, all Sector
PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command
will not execute and the command will time-out without erasing the PPBs.
The device will preprogram all PPBs prior to erasing when issuing the All PPB
Erase command. Also note that the total number of PPB program/erase cycles has
the same endurance as the flash memory array.
The programming state of the PPB for a given sector can be verified by writing a
PPB Status Read Command to the device.
The Non-Volatile Sector Protection Command Set Exit command must be
issued after the execution of the commands listed previously to reset the device
to read mode. Note that issuing the Non-Volatile Sector Protection Com-
mand Set Exit command re-enables reads and writes for Bank 0.
83
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte.
Addr = SA0
Read Byte.
Addr = SA0
No
DQ6 =
Toggle?
Yes
DQ5 = 1?
Yes
Read Byte Twice.
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
Figure 5. PPB Program/Erase Algorithm
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
84
Global Volatile Sector Protection Freeze Command Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set
the PPB Lock Bit and read the logic state of the PPB Lock Bit.
The Volatile Sector Protection Freeze Command Set Entry command se-
quence must be issued prior to any of the commands listed following to enable
proper command execution:
PPB Lock Bit Set Command
PPB Lock Bit Status Read Command
Reads from all non-busy remaining 15 banks are allowed.
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either
at reset or if the Password Unlock command was successfully executed. There is
no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared
unless the device is taken through a power-on clear (for Persistent Sector Protec-
tion Mode) or the Password Unlock command is executed (for Password Sector
Protection Mode). If the Password Mode Locking Bit is set, the PPB Lock Bit status
is reflected as set, even after a power-on reset cycle.
The programming state of the PPB Lock Bit can be verified by executing a PPB
Lock Bit Status Read Command to the device.
The Global Volatile Sector Protection Freeze Command Set Exit command
must be issued after the execution of the commands listed previously to reset the
device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic
Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic
state of the Dynamic Protection Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence
must be issued prior to any of the following commands to enable proper com-
mand execution.
DYB Set Command
DYB Clear Command
DYB Status Read Command
Note that issuing the Volatile Sector Protection Command Set Entry com-
mand disables reads and writes for the bank selected with the command. Reads
within that bank will return the DYB status for that sector. Writes within that bank
will set the DYB for that sector. Reads for other banks excluding that bank are
allowed; writes are not allowed. All Reads must be performed using the Asyn-
chronous mode.
The DYB Set/Clear command is used to set or clear a DYB for a given sector. The
high order address bits (A23–A14 for the WS256N, A22–A14 for the WS128N,
A21–A14 for the WS064N) are issued at the same time as the code 00h or 01h
on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle.
The DYBs are modifiable at any time, regardless of the state of the PPB or PPB
Lock Bit. The DYBs are cleared at power-up or hardware reset.
The programming state of the DYB for a given sector can be verified by writing a
DYB Status Read Command to the device.
The Volatile Sector Protection Command Set Exit command must be issued
after the execution of the commands listed previously to reset the device to read
85
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
mode. Note that issuing the Volatile Sector Protection Command Set Exit
command re-enables reads and writes for Bank 0.
SecSi Sector Entry Command
The SecSi Sector Entry Command allows the following commands to be executed
Read from SecSi Sector
Program to SecSi Sector
Sector 0 is remapped from memory array to SecSi Sector array. Reads can be
performed using the Asynchronous or Synchronous mode. Burst mode reads
within SecSi Sector will wrap from address FFh back to address 00h. Reads out-
side of sector 0 will return memory array data. Continuous burst read past the
maximum address is undefined.
Simultaneous operations are allowed except for Bank 0. Once the SecSi Sector
Entry Command is issued, the SecSi Sector Exit command has to be issued to exit
SecSi Sector Mode.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
86
Command Definition Summary
Table 27. Memory Array Commands
Bus Cycles (Notes 1–5)
Third Fourth
Addr
First
Addr
Second
Fifth
Addr
Sixth
Addr Data
Command Sequence
(Notes)
Data
RD
Addr
Data
Data
Addr
Data
Data
Asynchronous Read (6)
Reset (7)
Manufacturer ID
1
1
4
6
RA
XXX
555
555
F0
AA
2AA
2AA
55
55
[BA]555
[BA]555
90
90
[BA]X00
[BA]X01
0001
227E
Device ID (9)
AA
BA+X0E
PA
Data
PD
BA+X0F 2200
Indicator Bits (10)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
4
6
1
3
6
6
1
1
4
4
1
3
2
1
555
555
SA
AA
AA
29
AA
AA
AA
B0
30
AA
AA
98
AA
A0
98
2AA
2AA
55
55
555
PA
A0
25
PA
PA
PD
Write to Buffer (11)
Program Buffer to Flash
Write to Buffer Abort Reset (12)
Chip Erase
WC
WBL
PD
555
555
555
BA
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase/Program Suspend (13)
Erase/Program Resume (14)
Set Configuration Register (18)
Read Configuration Register
CFI Query (15)
BA
555
555
[BA]555
555
XXX
XXX
2AA
2AA
55
55
555
555
D0
C6
X00
X00
CR
CR
Entry
2AA
PA
55
PD
555
20
Program (16)
CFI (16)
Reset
2
XXX
90
XXX
00
Entry
3
4
1
555
555
00
AA
AA
2AA
2AA
55
55
555
555
88
A0
Program (17)
Read (17)
PA
PD
00
Data
Exit (17)
4
555
AA
2AA
55
555
90
XXX
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
12. Command sequence resets device for next command after write-
to-buffer operation.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address will equal 55h on all
future devices, but 555h for WS256N/128N/064N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
17. Requires Entry command sequence prior to execution. SecSi
Sector Exit Reset command is required to exit this mode; device
may otherwise be placed in an unknown state.
8. The system must provide the bank address. See Autoselect
18. Requires reset command to configure the Configuration Register.
Command Sequence section for more information.
9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231
(WS128N).
10. See Table 25 for indicator bit values.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer. The number
of cycles in the command sequence is 37 for full page
programming (32 words).
87
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Table 28. Sector Protection Commands
Bus Cycles (Notes 1–4)
Third Fourth
Addr Data Addr Data Addr Data Addr Data
First
Second
Fifth
Sixth
Seventh
Command Sequence
(Notes)
Addr
Data
AA
Addr
Data
55
Addr
Data
Command Set Entry (5)
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
555
XX
2AA
77
555
40
Lock
Register
Bits
Program (6)
A0
data
Read (6)
77
data
90
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (9)
XX
XX
2AA
00
00
55
555
XX
AA
555
60
A0
PWD[0-3]
PWD1
03
Password
Protection
0...00 PWD0 0...01
0...02
00
PWD2 0...03 PWD3
Unlock
00
XX
555
XX
XX
SA
25
90
00
XX
PWD0
01
PWD1
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
00
AA
2AA
SA
55
[BA]555
C0
A0
00
Non-Volatile
Sector
Protection (PPB)
80
00
30
RD(0)
90
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XX
555
XX
BA
XX
2AA
XX
00
55
00
Global
Volatile Sector
Protection
Freeze
AA
[BA]555
[BA]555
50
E0
A0
PPB Lock Bit Status Read
RD(0)
Command Set Exit (7)
Command Set Entry (5)
DYB Set
2
3
2
2
1
2
XX
555
XX
XX
SA
90
AA
XX
2AA
SA
00
55
00
01
(PPB Lock)
A0
Volatile Sector
Protection
(DYB)
DYB Clear
A0
SA
DYB Status Read
Command Set Exit (7)
RD(0)
90
XX
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
Notes:
1. All values are in hexadecimal.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation will abort and return the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses will equal 00h, but are
currently 77h for WS256N, WS128N, and WS064N. See Table 11
for explanation of lock bits.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 5 for details.
11. “All PPB Erase” command will pre-program all PPBs before
erasure to prevent over-erasure.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
88
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. Table 30 and the following sub-
sections describe the function of these bits. DQ7 and DQ6 each offers a method
for determining whether a program or erase operation is complete or in progress.
Please see the figure below for the general purpose data polling algorithm.
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
Read 3
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 6. Polling Flow Chart
89
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse
in the command sequence. Note that the Data# Polling is valid only for the
last word being programmed in the write-buffer-page during Write
Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page will return
false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately t , then that bank returns to the read mode.
PSP
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately t , then the
ASP
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may
be still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
Table 30 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data#
Polling algorithm. Figure 23 in “AC Characteristics—Asynchronous” shows the
Data# Polling timing diagram.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address in the same bank, and is valid
after the rising edge of the final WE# pulse in the command sequence (prior to
the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. When the operation is complete, DQ6
stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately t
(all sectors protected toggle
ASP
time), then returns to reading array data. If not all selected sectors are protected,
August 31, 2004 S29WSxxxN_MCP00_A3 S29WSxxxN MirrorBit™ Flash Family
90
the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately t
after the program command sequence is written, then returns to
PSP
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
See the following for additional information: Figure 7, DQ6: Toggle Bit I, Figure
24 (toggle bit timing diagram), and Table 29.
Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted
to show the change in state.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. But DQ2 cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 29 to compare outputs for DQ2 and DQ6.
See the following for additional information: Figure 7; DQ6: Toggle Bit I; and Fig-
ure 24.
Table 29. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
toggles,
toggles,
also toggles.
does not toggle.
toggles.
actively erasing,
erase suspended,
at an address within sectors not
selected for erasure,
at an address within a sector
selected for erasure,
does not toggle,
returns array data,
toggles,
at an address within sectors not
returns array data. The system can read
from any sector not selected for erasure.
selected for erasure,
programming in
erase suspend
at any address,
is not applicable.
91
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–
DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the tog-
gle bit with the first. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation. Refer to Figure 7
for more details.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the operation,
and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Start Timeout State Indicator
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase start timeout state
indicator does not apply to the chip erase command.) If additional sectors are se-
lected for erasure, the entire time-out also applies after each additional sector
erase command. When the time-out period is complete, DQ3 switches from a “0”
to a “1.” If the time between additional sector erase commands from the system
can be assumed to be less than t
, the system need not monitor DQ3. See Sec-
SEA
tor Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept addi-
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
92
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 30 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these con-
ditions DQ1 produces a ‘1’. The system must issue the Write to Buffer Abort Reset
command sequence to return the device to reading array data. See Write Buffer
Programming Operation for more details.
Table 30. Write Operation Status
DQ7
DQ5
DQ2
DQ1
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
(Note 2)
(Note 4)
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
INVALID
0
0
No toggle
Toggle
0
Standard
Mode
1
N/A
INVALID
INVALID
INVALID
INVALID
INVALID
Reading within Program Suspended
Sector
Program
Suspend
Mode
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Reading within Non-Program
Suspended Sector
(Note 3)
Data
1
Data
No toggle
Data
Data
0
Data
N/A
Data
Toggle
Data
Data
N/A
Erase
Suspended Sector
Erase-Suspend-
Erase
Suspend
Mode
Read
Non-Erase
Data
Data
Data
Data
Suspended Sector
Erase-Suspend-Program
BUSY State
DQ7#
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
Toggle
0
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
Write to
Buffer
(Note 5)
Exceeded Timing Limits
ABORT State
0
1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum
timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection
for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7#
during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-
BUFFER ADDRESS location.
93
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or
I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may
overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage
on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
–0.5 V
–2.0 V
VCC
+0.5 V
1.0 V
20 ns
20 ns
20 ns
Figure 7. Maximum Negative Overshoot
Waveform
Figure 8. Maximum Positive Overshoot
Waveform
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
(Contact local sales office for VIO = 1.35 to +1.70 V.)
Notes: Operating ranges define those limits between which the functionality of the device
is guaranteed.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
94
DC Characteristics
CMOS Compatible
Parameter
Description (Notes)
Test Conditions (Notes 1, 2, 9)
= V to V , V = V max
Min
Typ
Max
±1
±1
54
60
48
54
42
48
36
42
30
36
18
4
Unit
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
µA
mA
mA
mA
µA
mA
µA
µA
µA
mA
µA
mA
mA
V
I
Input Load Current
V
V
LI
IN
SS
CC
CC
CC
I
Output Leakage Current (3)
= V to V , V = V max
OUT SS CC CC CC
LO
54 MHz
66 MHz
54 MHz
66 MHz
54 MHz
66 MHz
54 MHz
66 MHz
27
28
28
30
29
32
32
35
20
27
13
3
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 8
IH
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 16
IH
I
V
Active burst Read Current
CCB
CC
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 32
IH
CE# = V , OE# = V , WE#
IL
IH
= V , burst length =
IH
Continuous
I
V
V
Non-active Output
OE# = V
IH
IO1
IO
10 MHz
5 MHz
1 MHz
Active Asynchronous Read Current
CE# = V , OE# = V , WE#
IL IH
CC
I
CC1
(4)
= V
IH
V
1
5
ACC
CE# = V , OE# = V , ACC
IL
IH
I
I
V
V
Active Write Current (5)
CC2
CC3
CC
CC
= V
IH
V
19
1
52.5
5
CC
V
ACC
CE# = RESET# =
± 0.2 V
Standby Current (6, 7)
Reset Current (7)
V
CC
V
20
70
50
2
40
150
60
40
20
20
0.4
CC
I
I
I
V
V
V
RESET# = V CLK = V
IL, IL
CC4
CC5
CC6
CC
CC
CC
Active Current (Read While Write) (7) CE# = V , OE# = V , ACC = V
IL
IH
IH
IH
Sleep Current (7)
CE# = V , OE# = V
IL
V
6
ACC
CE# = V , OE# = V
ACC
IL
IH,
I
Accelerated Program Current (8)
ACC
V
= 9.5 V
V
14
CC
V
Input Low Voltage
V
V
= 1.8 V
= 1.8 V
–0.5
IL
IO
V
Input High Voltage
V
V
– 0.4
V
+ 0.4
V
IH
IO
IO
IO
V
Output Low Voltage
I
I
= 100 µA, V = V
= V
IO
0.1
V
OL
OH
HH
OL
OH
CC
CC min
V
V
Output High Voltage
Voltage for Accelerated Program
= –100 µA, V = V
= V
IO
– 0.1
8.5
1.0
V
CC
CC min
IO
9.5
1.4
V
V
Low V Lock-out Voltage
V
LKO
CC
Notes:
1. Maximum I specifications are tested with V
= V max.
CC
CC
CC
2.
3. CE# must be set high when measuring the RDY pin.
4. The I current listed is typically less than 3 mA/MHz, with OE# at V
V
= V .
CC IO
.
IH
CC
5.
I
active while Embedded Erase or Embedded Program is in progress.
CC
6. Device enters automatic sleep mode when addresses are stable for t
+ 20 ns. Typical sleep mode current is equal to I
.
ACC
CC3
7.
V
= V ± 0.2 V and V > –0.1 V.
IH CC IL
8. Total current during accelerated programming is the sum of V
and V currents.
ACC
CC
9.
V
= V
on ACC input.
ACC
HH
95
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Test Conditions
Device
Under
Test
C
L
Figure 9. Test Setup
Table 31. Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
3.0 @ 54, 66 MHz
0.0–VIO
ns
V
Input timing measurement
reference levels
VIO/2
VIO/2
V
V
Output timing measurement
reference levels
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Switching Waveforms
VIO
All Inputs and Outputs
VIO/2
VIO/2
Input
Measurement Level
Output
0.0 V
Figure 10. Input Waveforms and Measurement Levels
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
96
VCC Power-up
Parameter
Description
Te s t Set up
Speed
Unit
tVCS
VCC Setup Time
Min
1
ms
Note:
1. The ramp rate must be greater than 1 V/200 µs and V
≥ V -100 mV.
IO
CC
2. If the ramp rate is less than 1 V/200 µs, then a Hardware Reset will be required.
t
tVCS
VCC
tVIOS
VIO
RESET#
Figure 11. VCC Power-up Diagram
97
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
AC Characteristics—Synchronous
CLK Characterization
Parameter
fCLK
Description
CLK Frequency
54 MHz
54
66 MHz
66
Unit
MHz
ns
Max
Min
tCLK
tCH
CLK Period
18.5
15.1
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Min
7.4
3
6.1
3
ns
ns
tCL
tCR
Max
tCF
t
CLK
t
t
CH
CL
CLK
t
t
CF
CR
Figure 12. CLK Characterization
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
98
Synchronous/Burst Read
Parameter
JEDEC
Standard
tIACC
tBACC
tACS
tACH
tBDH
tCR
Description
54 MHz
66 MHz Unit
Latency
Max
Max
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
69
ns
Burst Access Time Valid Clock to Output Delay
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
13.5
5
11.2
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6
4
3
13.5
13.5
11.2
11.2
tOE
Output Enable to Output Valid
Chip Enable to High Z (Note 2)
Output Enable to High Z (Note 2)
CE# Setup Time to CLK
tCEZ
10
10
4
tOEZ
tCES
tRDYS
tRACC
tAAS
tAAH
tCAS
tAVC
tAVD
tAOE
RDY Setup Time to CLK
5
13.5
5
4
11.2
4
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
7
6
0
4
8
AVD# Low to CLK
AVD# Pulse
AVD# Low to OE# Low
38.4
Notes:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
2. Not 100% tested.
99
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Timing Diagrams
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCEZ
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Addresses
Aa
tBACC
tACH
Hi-Z
Data (n)
OE#
tIACC
Da
Da + 1
Da + n
Da + 2
Da + 3
tAOE
tOEZ
tBDH
tRACC
tOE
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
RDY (n + 1)
Hi-Z
Hi-Z
Data (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
RDY (n + 2)
Hi-Z
Hi-Z
Data (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
RDY (n + 3)
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of wait states can be
programmed from two cycles to seven cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles
are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Figure 13. CLK Synchronous Burst Mode Read
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
100
7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
tAOE
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure 14. 8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
tCOE
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
Figure 15. 8-word Linear Burst without Wrap Around
101
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tAOE
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one
cycle before valid data.
Figure 16. Linear Burst with RDY Set One Cycle Before Data
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
102
AC Characteristics—Asynchronous
Asynchronous Mode Read
Parameter
JEDEC
Standard
tCE
Description
Access Time from CE# Low
54 MHz
66 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
70
70
8
tACC
Asynchronous Access Time
tAVDP
tAAVDS
tAAVDH
tOE
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
7
6
13.5
11.2
Read
0
10
10
0
tOEH
Output Enable Hold Time
Toggle and Data# Polling
tOEZ
tCAS
Output Enable to High Z (see Note)
CE# Setup Time to AVD#
Note: Not 100% tested.
Timing Diagrams
CE#
Note: RA = Read Address, RD = Read Data.
Figure 17. Asynchronous Mode Read with Latched Addresses
103
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Note: RA = Read Address, RD = Read Data.
Figure 18. Asynchronous Mode Read
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
tRP
Description
All Speed Options
Unit
µs
RESET# Pulse Width
Reset High Time Before Read (See Note)
Min
Min
30
tRH
200
ns
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
Figure 19. Reset Timings
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
104
Erase/Program Timing
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz Unit
t
t
Write Cycle Time (Note 1)
Min
Min
70
5
ns
ns
ns
AVAV
WC
Synchronous
Asynchronous
Synchronous
Asynchronous
t
t
Address Setup Time (Notes 2, 3)
Address Hold Time (Notes 2, 3)
AVWL
WLAX
AS
0
9
t
t
Min
ns
AH
20
8
t
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Typ
Typ
ns
AVDP
t
t
t
Data Setup Time
45
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
DVWH
DS
DH
t
Data Hold Time
0
0
WHDX
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
GHWL
GHWL
t
0
CAS
t
t
0
WHEH
WLWH
WHWL
CH
WP
t
t
t
Write Pulse Width
30
20
0
t
Write Pulse Width High
WPH
t
Latency Between Read and Write Operations
SR/W
t
V
V
V
Rise and Fall Time
500
1
VID
ACC
ACC
t
Setup Time (During Accelerated Programming)
VIDS
t
Setup Time
CC
50
5
VCS
t
t
CE# Setup Time to WE#
ELWL
CS
t
AVD# Setup Time to WE#
5
AVSW
AVHW
t
AVD# Hold Time to WE#
5
t
AVD# Setup Time to CLK
5
AVSC
AVHC
t
AVD# Hold Time to CLK
5
t
Clock Setup Time to WE#
5
CSW
t
Noise Pulse Margin on WE#
Sector Erase Accept Time-out
Erase Suspend Latency
3
WEP
t
50
20
20
100
1
SEA
t
ESL
PSL
ASP
t
Program Suspend Latency
t
Toggle Time During Sector Protection
Toggle Time During Programming Within a Protected Sector
t
PSP
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and
Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,
addresses are latched on the rising edge of CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
105
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
AVD
V
IL
tAVSW
tAVHW
tAVDP
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. CLK can be either V or V
.
IH
IL
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the
Configuration Register.
Figure 20. Asynchronous Program Operation Timings: WE# Latched Addresses
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
106
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
AVD
tAS
tAH
tAVSC
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 21. Synchronous Program Operation Timings: CLK Latched Addresses
107
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
1 ms
V
V
ID
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 22. Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
Data
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data#
Polling will output true data.
Figure 23. Data# Polling Timings
(During Embedded Algorithm)
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
108
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
VA
Data
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
will stop toggling.
Figure 24. Toggle Bit Timings
(During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
will stop toggling.
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before
data.
Figure 25. Synchronous Data Polling Timings/
Toggle Bit Timings
109
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Read
Suspend
Program
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 26. DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
Notes:
1. RDY active with data (D8 = 1 in the Configuration Register).
2. RDY active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the
Boundary Crossing bit (D14) in the Configuration Register is set to 0
Figure 27. Latency with Boundary Crossing when Frequency > 66 MHz
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
110
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY active with data (D8 = 1 in the Configuration Register).
2. RDY active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the
Boundary Crossing bit (D14) in the Configuration Register is set to 0
Figure 28. Latency with Boundary Crossing into Program/Erase Bank
111
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Wait State Configuration Register Setup:
D13, D12, D11 = “111” ⇒ Reserved
D13, D12, D11 = “110” ⇒ Reserved
D13, D12, D11 = “101” ⇒ 5 programmed, 7 total
D13, D12, D11 = “100” ⇒ 4 programmed, 6 total
D13, D12, D11 = “011” ⇒ 3 programmed, 5 total
D13, D12, D11 = “010” ⇒ 2 programmed, 4 total
D13, D12, D11 = “001” ⇒ 1 programmed, 3 total
D13, D12, D11 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Figure 29. Example of Wait States Insertion
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
112
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
Figure 30. Back-to-Back Read/Write Cycle Timings
113
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_MCP00_A3 August 31, 2004
Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
64 Kword
16 Kword
VCC
VCC
0.6
3.5
2
Sector Erase Time
s
<0.15
153.6 (WS256N)
77.4 (WS128N)
39.3 (WS064N)
308 (WS256N)
154 (WS128N)
78 (WS064N)
Excludes 00h
programming prior to
erasure (Note 4)
VCC
Chip Erase Time
s
130.6 (WS256N)
65.8 (WS128N)
33.4 (WS064N)
262 (WS256N)
132 (WS128N)
66 (WS064N)
ACC
VCC
ACC
VCC
ACC
VCC
ACC
40
24
400
240
94
Single Word Programming Time
(Note 8)
µs
µs
µs
9.4
6
Effective Word Programming Time
utilizing Program Write Buffer
60
300
192
3000
1920
Total 32-Word Buffer
Programming Time
157.3 (WS256N)
78.6 (WS128N)
39.3 (WS064N)
314.6 (WS256N)
157.3 (WS128N)
78.6 (WS064N)
VCC
Excludes system level
overhead (Note 5)
Chip Programming Time (Note 3)
s
100.7 (WS256N)
50.3 (WS128N)
25.2 (WS064N)
201.3 (WS256N)
100.7 (WS128N)
50.3 (WS064N)
ACC
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 10,000 cycles;
CC
checkerboard data pattern.
2. Under worst case conditions of 90°C, V = 1.70 V, 100,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
Based upon single word programming, not page programming.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before
erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Command Definition Summary for further information on command definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating
conditions.
7. Refer to Application Note “Erase Suspend/Resume Timing” for more details.
8. Word programming specification is based upon a single word programming operation not utilizing the write
buffer.
August 31, 2004 S29WSxxxN_MCP00_A3
S29WSxxxN MirrorBit™ Flash Family
114
A d v a n c e I n f o r m a t i o n
CellularRAM
128/64/32 Megabit
Burst CellularRAM
Features
Single device supports asynchronous, page, and burst operations
VCC Voltages
—
1.70V–1.95V VCC
Random Access Time: 70ns
Burst Mode Write Access
—
Continuous burst
Burst Mode Read Access
4, 8, or 16 words, or continuous burst
Page Mode Read Access
—
—
—
—
Sixteen-word page size
Interpage read access: 70ns
Intrapage read access: 20ns
Low Power Consumption
—
—
—
—
—
—
Asynchronous READ < 25mA
Intrapage READ < 15mA
Initial access, burst READ < 35mA
Continuous burst READ < 11mA
Standby: 180µA
Deep power-down < 10µA
Low-Power Features
—
—
—
Temperature Compensated Refresh (TCR) On-chip sensor control
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
General Description
CellularRAM™ products are high-speed, CMOS dynamic random access memories
developed for low-power, portable applications. These devices include an industry
standard burst mode Flash interface that dramatically increases read/write band-
width compared with other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a
transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on de-
vice read/write performance.
Two user-accessible control registers define device operation. The bus configura-
tion register (BCR) defines how the CellularRAM device interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash de-
vices. The refresh configuration register (RCR) is used to control how refresh is
performed on the DRAM array. These registers are automatically loaded with de-
fault settings during power-up and can be updated anytime during normal
operation.
Special attention has been focused on standby current consumption during self
refresh. CellularRAM products include three mechanisms to minimize standby
current. Partial array refresh (PAR) enables the system to limit refresh to only
that part of the DRAM array that contains essential data. Temperature compen-
October 4, 2004 cellRAM_00_A0
CellularRAM
115
A d v a n c e I n f o r m a t i o n
sated refresh (TCR) adjusts the refresh rate to match the device temperature—
the refresh rate decreases at lower temperatures to minimize current consump-
tion during standby. Deep power-down (DPD) enables the system to halt the
refresh operation altogether when no vital information is stored in the device. The
system-configurable refresh mechanisms are accessed through the RCR.
A[22:0]
Address Decode
Input/
Output
MUX
and
Buffers
DQ[7:0]
Logic
DRAM
MEMORY
ARRAY
DQ[15:8]
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
WAIT
LB#
UB#
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-
agrams for detailed information.
Figure 1. Functional Block Diagram
116
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 1. Signal Descriptions
SYMBOL
TYPE
DESCRIPTION
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are
internally latched during READ and WRITE cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR.
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous
access READ and WRITE operations and during PAGE READ ACCESS operations.
CLK
Input
Input
Address Valid: Indicates that a valid address is present on the address inputs. Addresses
can be latched on the rising edge of ADV# during asynchronous READ and WRITE
operations. ADV# can be held LOW during asynchronous READ and WRITE operations.
ADV#
CRE
CE#
Input
Input
Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output
buffers are disabled.
OE#
WE#
Input
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a
WRITE to either a configuration register or to the memory array.
LB#
UB#
Input
Input
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Input/
Output
DQ[15:0]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is
gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE
operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to
mask the delay associated with opening a new internal page. WAIT is asserted and should
be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is
HIGH.
WAIT
VCC
Output
Supply
Supply
Supply
Supply
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VCC
VSS
VSS
Q
Q
VSSQ must be connected to ground.
Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode.
WAIT will be asserted but should be ignored during asynchronous and page mode operations.
October 4, 2004 cellRAM_00_A0
CellularRAM
117
A d v a n c e I n f o r m a t i o n
Table 2. Bus Operations—Asynchronous Mode
CLK
(Note 1) ADV#
LB#/
UB#
WAIT
(Note 2)
DQ[15:0]
(Note 3)
MODE
Read
POWER
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
NOTES
4
X
X
X
X
L
L
H
L
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
Write
L
X
4
Standby
No Operation
X
X
H
X
X
X
X
X
5, 6
4, 6
L
X
Configuration
Register
Active
X
X
L
L
H
X
L
H
X
X
X
Low-Z
High-Z
High-Z
Deep
Power-down
DPD
X
H
X
High-Z
7
Notes:
1. CLK may be HIGH or LOW, but must be static during synchronous read, synchronous write, burst suspend, and DPD
modes; and to achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
118
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 3. Bus Operations—Burst Mode
CLK
(Note 1) ADV#
LB#/
UB#
WAIT
(Note 2)
DQ[15:0]
(Note 3)
MODE
POWER
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
NOTES
4
Async Read
Async Write
Standby
X
X
X
X
L
L
H
L
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
L
X
4
X
X
H
X
X
X
X
X
5, 6
4, 6
No Operation
L
X
Initial Burst Read
Initial Burst Write
Active
Active
L
L
L
L
X
H
H
L
L
L
L
Low-Z
Low-Z
Data-Out
Data-In
4, 8
4, 8
X
Data-In or
Data-Out
Burst Continue
Burst Suspend
Active
Active
Active
H
X
L
L
L
L
X
H
H
X
X
L
L
L
X
X
X
Low-Z
Low-Z
Low-Z
4, 8
4, 8
8
X
X
High-Z
High-Z
Configuration
Register
H
Deep
Power-Down
DPD
X
H
X
X
X
X
High-Z
High-Z
7
Notes:
1. CLK may be HIGH or LOW, but must be static during asynchronous read, synchronous write, burst suspend, and
DPD modes; and to achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode
transfers. Page mode accesses are also included as a bandwidth-enhancing ex-
tension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the
power-up initialization process. Initialization will configure the BCR and the RCR
with their default settings (see Table 35 and Table 39). V
and V Q must be
CC
CC
applied simultaneously. When they reach a stable level at or above 1.7V, the de-
vice will require 150µs to complete its self-initialization process. During the
initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
October 4, 2004 cellRAM_00_A0
CellularRAM
119
A d v a n c e I n f o r m a t i o n
>
PU
V
= 1.7 V
t
150 µs
CC
Device ready for
normal operation
V
CC
Device Initialization
V
Q
CC
Figure 2. Power-Up Initialization Timing
Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products
targeting low-power, wireless applications. This bus interface supports asynchro-
nous, page mode, and burst mode read and write transfers. The specific interface
supported is defined by the value loaded into the BCR. Page mode is controlled
by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode
uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#).
READ operations (Figure 33) are initiated by bringing CE#, OE#, and LB#/UB#
LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations (Figure 34) occur when
CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE opera-
tions, the OE# level is a “Don't Care,” and WE# will override OE#. The data to be
written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs
first). Asynchronous operations (page mode disabled) can either use the ADV
input to latch the address, or ADV can be driven LOW during the entire READ/
WRITE operation.
During asynchronous operation, the CLK input must be held static (HIGH or LOW,
no transitions). WAIT will be driven while the device is enabled and its state
should be ignored.
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
= READ Cycle Time
RC
Don't Care
Note: ADV must remain LOW for page mode operation.
Figure 3. READ Operation (ADV# LOW)
120
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
= READ Cycle Time
RC
Don't Care
Figure 4. WRITE Operation (ADV# LOW)
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous
READ operation. In page mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be read quickly by simply
changing the low-order address. Addresses A[3:0] are used to determine the
members of the 16-address CellularRAM page. Addresses A[4] and higher must
remain fixed during the entire page mode access. Figure 35 shows the timing for
a page mode access. Page mode takes advantage of the fact that adjacent ad-
dresses can be read in a shorter period of time than random addresses. WRITE
operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW.
CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled and its state should be ignored. Page mode is
enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable
page mode functionality. ADV must be driven LOW during all page mode read
accesses.
October 4, 2004 cellRAM_00_A0
CellularRAM
121
A d v a n c e I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1] ADD[2] ADD[3]
t
t
t
t
AA
APA
APA
APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
Don't Care
Figure 5. Page Mode READ Operation (ADV# LOW)
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE opera-
tions. Burst operations consist of a multi-clock sequence that must be performed
in an ordered fashion. After CE# goes LOW, the address to access is latched on
the rising edge of the next clock that ADV# is LOW. During this first clock rising
edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH,
Figure 36) or WRITE (WE# = LOW, Figure 37).
The size of a burst can be specified in the BCR either as a fixed length or contin-
uous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous
bursts have the ability to start at a specified address and burst through the entire
memory.
The latency count stored in the BCR defines the number of clock cycles that
elapse before the initial data value is transferred between the processor and Cel-
lularRAM device.
The WAIT output asserts as soon as a burst is initiated, and de-asserts to indicate
when data is to be transferred into (or out of) the memory. WAIT will again be
asserted if the burst crosses a row boundary. Once the CellularRAM device has
restored the previous row's data and accessed the next row, WAIT will be deas-
serted and the burst can continue (see Figure 57).
To access other devices on the same bus without the timing penalty of the initial
latency for a new burst, burst mode can be suspended. Bursts are suspended by
stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the
data bus while the burst is suspended, OE# should be taken HIGH to disable the
CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT out-
put will continue to be active, and as a result no other devices should directly
share the WAIT connection to the controller. To continue the burst sequence, OE#
is taken LOW, then CLK is restarted after valid data is available on the bus.
See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on
the maximum CE# LOW time during burst operations. If a burst suspension will
122
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
cause CE# to remain LOW for longer than t
, CE# should be taken HIGH and
CEM
the burst restarted with a new CE# LOW/ADV# LOW cycle.
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
Figure 6. Burst Mode READ (4-word burst)
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
Don't care
WRITE Burst Identified
(WE# = LOW)
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
Figure 7. Burst Mode WRITE (4-word burst)
October 4, 2004 cellRAM_00_A0
CellularRAM
123
A d v a n c e I n f o r m a t i o n
Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous
WRITE operations when the BCR is configured for synchronous operation. The
asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH
or LOW) during the entire sequence. The ADV# signal can be used to latch the
target address, or it can remain LOW during the entire WRITE operation. CE# can
remain LOW when transitioning between mixed-mode operations with fixed la-
tency enabled. Note that the t
period is the same as a READ or WRITE cycle.
CKA
This time is required to ensure adequate refresh. Mixed-mode operation facili-
tates a seamless interface to legacy burst mode Flash memory controllers. See
Figure 65 for the “Asynchronous WRITE Followed by Burst READ” timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, sys-
tem-level WAIT signal (see Figure 38 below). The shared WAIT signal is used by
the processor to coordinate transactions with multiple memories on the synchro-
nous bus.
External
Pull-Up/
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Other
Other
Device
Device
Processor
Figure 8. Wired or WAIT Configuration
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate
that the CellularRAM device requires additional time before data can be trans-
ferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory control-
ler when data will be accepted into the CellularRAM device. When WAIT
transitions to an inactive state, the data burst will progress on successive clock
edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT config-
uration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data
corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after
WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT
signal asserts.)
When using variable initial access latency (BCR[14] = 0), the WAIT output per-
forms an arbitration role for READ or WRITE operations launched while an on-chip
refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional
clock cycles until the refresh has completed (see Figure 39 and Figure 40). When
the refresh operation has completed, the READ or WRITE operation will continue
normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses the
boundary between 128-word rows. The WAIT assertion allows time for the new
row to be accessed, and permits any pending refresh operations to be performed.
WAIT will be asserted but should be ignored during asynchronous READ and
WRITE, and page READ operations.
124
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During
READ operations, the enabled byte(s) are driven onto the DQs. The DQs associ-
ated with a disabled byte are put into a High-Z state during a READ operation.
During WRITE operations, any disabled bytes will not be transferred to the RAM
array and the internal value will remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,
LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
will disable the data bus from receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active mode as long as CE# remains
LOW.
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 9. Refresh Collision During READ Operation
October 4, 2004 cellRAM_00_A0
CellularRAM
125
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 10. Refresh Collision During WRITE Operation
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary
to perform the DRAM refresh operation. Standby operation occurs when CE# is
HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operation, or when the address and control inputs remain static for an extended
period of time. This mode will continue until a change occurs to the address or
control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate de-
pending on the device operating temperature. DRAM technology requires
increasingly frequent refresh operation to maintain data integrity as tempera-
tures increase. More frequent refresh is required due to increased leakage of the
DRAM capacitive storage elements as temperatures rise. A decreased refresh rate
at lower temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C,
+45°C, +70°C, and +85°C). The setting selected must be for a temperature
higher than the case temperature of the CellularRAM device. For example, if the
case temperature is 50°C, the system can minimize self refresh current con-
sumption by selecting the +7°0C setting. The +15°C and +45°C settings would
result in inadequate refreshing and cause data corruption.
126
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total
memory array. This feature enables the device to reduce standby current by re-
freshing only that part of the memory array required by the host system. The
refresh options are full array, one-half array, one-quarter array, three-quarter ar-
ray, or none of the array. The mapping of these partitions can start at either the
beginning or the end of the address map (see Table 40). READ and WRITE oper-
ations to address ranges receiving refresh will not be affected. Data stored in
addresses not receiving refresh will become corrupted. When re-enabling addi-
tional portions of the array, the new portions are available immediately upon
writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode
is used if the system does not require the storage provided by the CellularRAM
device. Any stored data will become corrupted when DPD is enabled. When re-
fresh activity has been re-enabled by rewriting the RCR, the CellularRAM device
will require 150µs to perform an initialization procedure before normal operations
can resume. During this 150µs period, the current consumption will be higher
than the specified standby levels, but considerably lower than the active current
specification.
DPD cannot be enabled or disabled by writing to the RCR using the software ac-
cess sequence; the RCR should be accessed using CRE instead.
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus
configuration register (BCR) defines how the CellularRAM interacts with the sys-
tem memory bus and is nearly identical to its counterpart on burst mode Flash
devices. The refresh configuration register (RCR) is used to control how refresh
is performed on the DRAM array. These registers are automatically loaded with
default settings during power-up, and can be updated any time the devices are
operating in a standby state.
Access Using CRE
The configuration registers can be written to using either a synchronous or an
asynchronous operation when the configuration register enable (CRE) input is
HIGH (see Figure 41 and Figure 42). When CRE is LOW, a READ or WRITE oper-
ation will access the memory array. The register values are written via address
pins A[21:0]. In an asynchronous WRITE, the values are latched into the config-
uration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first;
LB# and UB# are “Don’t Care.” The BCR is accessed when A[19] is HIGH; the
RCR is accessed when A[19] is LOW. For reads, address inputs other than A[19]
are “Don’t Care,” and register bits 15:0 are output on DQ[15:0].
October 4, 2004 cellRAM_00_A0
CellularRAM
127
A d v a n c e I n f o r m a t i o n
A[22:0]
(except A19)
ADDRESS
ADDRESS
OPCODE
t
t
AVH
AVS
Select Control Register
A19
(Note)
CRE
t
AVS
t
AVH
t
VPH
ADV#
t
VP
t
CBPH
Initiate Control Register Access
CE#
OE#
t
CW
t
WP
Write Address
Bus Value to
Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
Legend:
Don't care
Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
Figure 11. Configuration Register WRITE, Asynchronous Mode Followed by READ
128
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
CLK
Latch Control Register Value
OPCODE
A[22:0]
(except A19)
ADDRESS
ADDRESS
t
HD
Latch Control Register Address
t
SP
SP
A19
(Note 2)
t
CRE
t
t
HD
t
SP
ADV#
HD
t
CBPH
(Note 3)
t
CSP
CE#
OE#
t
SP
WE#
t
HD
LB#/UB#
t
CEW
WAIT
High-Z
High-Z
DATA
VALID
DQ[15:0]
Legend:
Don't care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused
by refresh collisions require a corresponding number of additional CE# LOW cycles.
Figure 12. Configuration Register WRITE, Synchronous Mode Followed by READ0
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory
bus. Page mode operation is enabled by a bit contained in the RCR. Table 35
below describes the control bits in the BCR. At powerup, the BCR is set to 9D4Fh.
October 4, 2004 cellRAM_00_A0
CellularRAM
129
A d v a n c e I n f o r m a t i o n
The BCR is accessed using CRE and A[19] HIGH.
Table 4. Bus Configuration Register Definition
A[22:20]
A19
A[18:16]
A15
A14
A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2 A1 A0
22–20
19
18–16
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
Burst
Wrap
Impedance (BW)
(Note)
Burst
Length
(BL)
WAIT
Register
Select
Operating
Mode
Initial
Latency
Latency
Counter
WAIT
Polarity
Output
Reserved
Reserved
Reserved Configuration Reserved Reserved
(WC)
(Note)
All must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Setting is ignored
Output Impedance
BCR[5] BCR[4]
Initial Access Latency
Variable (default)
Fixed
BCR[14]
0
0
1
1
0
1
0
1
Full Drive (default)
1/2 Drive
0
1
1/4 Drive
Reserved
BCR[13] BCR[12] BCR[11]
Latency Counter
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 0–Reserved
Code 1–Reserved
Code 2
BCR[3]
Burst Wrap (Note)
0
1
Burst wraps within the burst length
Burst no wrap (default)
Code 3 (Default)
Code 4
Code 5
Code 6
Code 7–Reserved
BCR[8]
WAIT Configuration
Asserted during delay
0
1
Asserted one data cycle before delay (default)
BCR[10] WAIT Polarity
0
1
Active LOW
Active HIGH (default)
BCR[15]
Operating Mode
Burst Length (Note)
BCR[2] BCR[1] BCR[0]
0
1
Synchronous burst access mode
Asynchronous access mode (default)
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
4 words
8 words
16 words
Register Select
BCR[19]
32 words
0
1
Select RCR
Select BCR
Continuous burst (default)
Others
Reserved
Note: Burst wrap and length apply to READ operations only.
130
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 5. Sequence and Burst Length
4-WORD
STARTING
ADDRESS LENGTH
BURST
8-WORD BURST
LENGTH
CONTINUOUS
BURST
BURST WRAP
16-WORD BURST LENGTH
BCR[3] WRAP (DECIMAL) LINEAR
LINEAR
LINEAR
LINEAR
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11-…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13-…
…
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
…
2
3
4
5
0
Yes
6
7
…
14
15
0
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
5-6-7-8-9-10-11-12-13-…-15-16-17-18-19-20
6-7-8-9-10-11-12-13-14-…-16-17-18-19-20-21
7-8-9-10-11-12-13-14-…-17-18-19-20-21-22
…
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12…
7-8-9-10-11-12-13…
…
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
1
2
2-3-4-5-6-7-8-9
3
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
4
5
1
No
6
7
…
14
15
14-15-16-17-18-19-…-23-24-25-26-27-28-29
5-16-17-18-19-20-…-24-25-26-27-28-29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ
operations. The device supports a burst length of 4, 8, or 16 words. The device
can also be set in continuous burst mode where data is accessed sequentially
without regard to address boundaries. Enabling burst no-wrap with BCR[3] = 1
overrides the burst-length setting.
Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word READ burst wraps within
the burst length or steps through sequential addresses. If the wrap option is not
enabled, the device accesses data from sequential addresses without regard to
burst boundaries. When continuous burst operation is selected, the internal ad-
dress wraps to 000000h if the burst goes past the last address. Enabling burst
nowrap (BCR[3] = 1) overrides the burst-length setting.
October 4, 2004 cellRAM_00_A0
CellularRAM
131
A d v a n c e I n f o r m a t i o n
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter
strength to adjust for different data bus loading scenarios. The reduced-strength
options are intended for stacked chip (Flash + CellularRAM) environments when
there is a dedicated memory bus. The reduced-drive-strength option minimizes
the noise generated on the data bus during READ operations. Normal output drive
strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive
strength during testing.
Table 6. Output Impedance
BCR[5]
BCR[4]
DRIVE STRENGTH
0
0
1
1
0
1
0
1
Full
1/2
1/4
Reserved
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between
the asserted and the de-asserted state with respect to valid data presented on
the data bus. The memory controller will use the WAIT signal to coordinate data
transfer during synchronous READ and WRITE operations. When BCR[8] = 0,
data will be valid or invalid on the clock edge immediately after WAIT transitions
to the de-asserted or asserted state, respectively (Figure 43 and Figure 45).
When A8 = 1, the WAIT signal transitions one clock period prior to the data bus
going valid or invalid (Figure 44).
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH
or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-
down resistor to maintain the de-asserted state.
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 45.
Figure 13. WAIT Configuration (BCR[8] = 0)
132
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 45.
Figure 14. WAIT Configuration (BCR[8] = 1)
CLK
BCR[8]
= 0
WAIT
DATA VALID IN CURRENT CYCLE
BCR[8]
= 1
WAIT
DATA VALID IN NEXT CYCLE
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: WAIT active LOW.
Figure 15. WAIT Configuration During Burst Operation
Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the begin-
ning of a READ or WRITE operation and the first data value transferred. Latency
codes from two (three clocks) to six (seven clocks) are allowed (see Table 38 and
Figure 46 below).
Table 7. Variable Latency Configuration Codes
LATENCY (Note)
REFRESH
MAX INPUT CLK FREQUENCY (MHz)
LATENCY
BCR[13:11]
010
CONFIGURATION CODE
NORMAL
COLLISION
70ns/80 MHz
85ns/66 MHz
2 (3 clocks)
3 (4 clocks)—default
4 (5 clocks)
2
3
4
4
6
8
75 (13.0ns)
44 (22.7ns)
011
80 (12.5ns)
66 (15.2ns)
100
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans-
ferred on the next clock cycle.
October 4, 2004 cellRAM_00_A0
CellularRAM
133
A d v a n c e I n f o r m a t i o n
V
IH
CLK
V
IL
V
IH
A[21:0]
Valid Address
V
IL
V
IH
ADV#
A/DQ[15:0]
A/DQ[15:0]
A/DQ[15:0]
A/DQ[15:0]
V
IL
Code 2
Code 3
Code 4
Code 5
Code 6
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
(Default)
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
V
OH
Valid
Output
Valid
Output
Valid
Output
V
OL
V
V
OH
OL
Valid
Output
Valid
Output
V
V
OH
OL
Valid
Output
A/DQ[15:0]
Legend:
Don't care
Undefined
Figure 16. Latency Counter (Variable Initial Latency, No Refresh Collision)
Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default
asynchronous mode of operation.
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device per-
forms its transparent self refresh. Altering the refresh parameters can
dramatically reduce current consumption during standby mode. Page mode con-
trol is also embedded into the RCR. Table 39 below describes the control bits used
in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE
and A[19] LOW.
134
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 8. Refresh Configuration Register Mapping
A[22:20]
A19
A[18:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
22–20
Reserved
19
18–8
Reserved
7
6
5
4
3
2
1
0
Read Configuration
Register
Register
Select
Page
Reserved
DPD
Reserved
PAR
Setting is ignored
Must be set to "0"
All must be set to "0"
All must be set to "0"
RCR[19] Register Select
RCR[2] RCR[1] RCR[0] Refresh Coverage
0
1
Select RCR
Select BCR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
RCR[7]
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
0
1
Top 1/2 array
Top 1/4 array
RCR[4]
Deep Power-Down
DPD Enable
Top 1/8 array
0
1
DPD Disable (default)
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part
of the memory array required by the host system. The refresh options are full ar-
ray, one-half array, one-quarter array, three-quarters array, or none of the array.
The mapping of these partitions can start at either the beginning or the end of
the address map (see Table 40 through Table 42).
Table 9. 128Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
0
SIZE
DENSITY
128Mb
64Mb
32Mb
16Mb
0Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
400000h–7FFFFFh
600000h–7FFFFFh
700000h–7FFFFFh
64Mb
32Mb
16Mb
October 4, 2004 cellRAM_00_A0
CellularRAM
135
A d v a n c e I n f o r m a t i o n
Table 10. 64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–3FFFFFh
000000h–2FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
0
SIZE
DENSITY
64Mb
48Mb
32Mb
16Mb
0Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
48Mb
32Mb
16Mb
Table 11. 32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–1FFFFFh
000000h–17FFFFh
000000h–0FFFFFh
000000h–07FFFFh
0
SIZE
DENSITY
32Mb
24Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Meg x 16
1.5 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
1.5 Meg x 16
1 Meg x 16
512K x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
0Mb
One-half of die
One-quarter of die
One-eighth of die
080000h–1FFFFFh
100000h–1FFFFFh
180000h–1FFFFFh
24Mb
16Mb
8Mb
Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This
mode is used if the system does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted when DPD is enabled. When
refresh activity has been re-enabled, the CellularRAM device will require 150µs
to perform an initialization procedure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until
RCR[4] is set to “1.”
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation
The TCR bits allow for adequate refresh at four different temperature thresholds
(+15ºC, +45ºC, +70ºC, and +85ºC). The setting selected must be for a temper-
ature higher than the case temperature of the CellurlarRAM device. If the case
temperature is +50ºC, the system can minimize self refresh current consumption
by selecting the +70ºC setting. The +15ºC and +45ºC settings would result in
inadequate refreshing and cause data corruption.
Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asyn-
chronous READ operations. In the power-up default state, page mode is disabled.
136
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Voltage to Any Ball Except V , V
Q
CC
CC
Relative to V . . . . . -0.50V to (4.0V or V Q + 0.3V, whichever is less)
SS
CC
Voltage on V Supply Relative to V
. . . . . . . . . . . . . . . . -0.2V to +2.45V
SS
CC
Voltage on V Q Supply Relative to V
. . . . . . . . . . . . . . . . -0.2V to +2.45V
SS
CC
Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . -55ºC to +150ºC
Operating Temperature (case)
Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25ºC to +85ºC
*Stresses greater than those listed may cause permanent damage to the device. This
is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
October 4, 2004 cellRAM_00_A0
CellularRAM
137
A d v a n c e I n f o r m a t i o n
DC Characteristics
Table 12. Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
1.70
Max
1.95
Units
V
Notes
Supply Voltage
VCC
W: 1.8V
J: 1.5V
1.70
1.95
V
I/O Supply Voltage
VCCQ
1.35
1.65
V
Input High Voltage
Input Low Voltage
VIH
VIL
VCCQ - 0.4
-0.20
VCCQ + 0.2
0.4
V
2
3
4
4
V
Output High Voltage
Output Low Voltage
Input Leakage Current
IOH = -0.2mA
IOL = +0.2mA
VOH
VOL
ILI
0.80 VCC
Q
V
0.20 VCC
Q
V
VIN = 0 to VCC
Q
1
µA
OE# = VIH or
Chip Disabled
Output Leakage Current
ILO
1
µA
Operating Current
-70
-85
25
20
Asynchronous Random READ
Asynchronous Page READ
Initial Access, Burst READ
Continuous Burst READ
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
ICC
1
mA
5
5
-70
-85
15
12
80 MHz
66 MHz
80 MHz
66 MHz
-70
35
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
30
ICC1
mA
18
15
25
VIN = VCCQ or 0V
Chip Enabled
WRITE Operating Current
ICC2
mA
µA
-85
20
128 M
64 M
180
120
110
VIN = VCCQ or 0V
Standby Current
ISB
6
CE# = VCC
Q
32 M
Notes:
1. Wireless Temperature (-25ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC).
2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
3. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
4. BCR[5:4] = 00b.
5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the
current required to drive output capacitance expected in the actual system.
6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. To achieve low standby current,
all inputs must be driven to either VCCQ or VSS
.
138
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 13. Temperature Compensated Refresh Specifications and Conditions
Standard
Power
Tem pe rature (No Desig.)
Max Case
Description
Conditions
Symbol
Density
Units
+85
+70
+45
+15
+85
+70
+45
+15
°
°
°
°
°
°
°
°
C
C
C
C
C
C
C
C
120
105
85
64 Mb
70
Temperature Compensated
Refresh Standby Current
VIN = VCCQ or 0V,
CE# = VCCQ
ITCR
µA
110
95
32 Mb
80
70
Note: IPAR (MAX) values measured with TCR set to 85°C.
Table 14. Partial Array Refresh Specifications and Conditions
Standard
Power
Array
Description
Conditions
Symbol
Density
Partition
Full
1/2
1/4
1/8
0
(No Desig.)
Units
120
115
110
105
70
64 Mb
Full
1/2
1/4
1/8
0
110
105
100
95
Partially Array Refresh Standby
Current
VIN = VCCQ or 0V,
CE# = VCCQ
IPAR
µA
32 Mb
70
Full
0
180
50
128 Mb
Note:IPAR (MAX) values measured with TCR set to 85°C.
Table 15. Deep Power-Down Specifications
Description
Conditions
Symbol
Typ
Units
µA
Deep Power-down
VIN = VCCQ or 0V; +25°C; VCC = 1.8V
IZZ
10
October 4, 2004 cellRAM_00_A0
CellularRAM
139
A d v a n c e I n f o r m a t i o n
AC Characteristics
V
CC
Q
V
Q
/2
V
Q/2
CC
(Note 2)
CC
Input
(Note 1)
Output
Test Points
(Note 3)
V
SS
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
Figure 17. AC Input/Output Reference Waveform
V
Q
CC
R1
Test Point
DUT
30pF
R2
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 18. Output Load Circuit
Table 16. Output Load Circuit
V
Q
R1/R2
2.7K
CC
1.8V
Ω
140
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 17. Asynchronous READ Cycle Timing Requirements
85ns/66 MHz
70ns/80 MHz
Units
Notes
Parameter
Address Access Time
Symbol
tAA
Min
Max
85
Min
Max
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# Access Time
tAADV
tAPA
tAVH
tAVS
tBA
85
70
Page Access Time
25
20
Address Hold from ADV# HIGH
Address Setup to ADV# HIGH
LB#/UB# Access Time
5
5
10
10
85
8
70
8
LB#/UB# Disable to DQ High-Z Output
LB#/UB# Enable to Low-Z Output
CE# HIGH between Subsequent Mixed-Mode Operations
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
tBHZ
tBLZ
tCBPH
tCEM
tCEW
tCO
4
3
10
5
10
5
4
4
2
1
10
10
5
7.5
85
1
10
10
5
7.5
70
Chip Select Access Time
CE# LOW to ADV# HIGH
tCVS
tHZ
Chip Disable to DQ and WAIT High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
8
20
8
8
20
8
4
3
tLZ
tOE
tOH
tOHZ
tOLZ
tPC
4
3
5
5
25
85
10
10
20
70
10
10
READ Cycle Time
tRC
ADV# Pulse Width LOW
tVP
ADV# Pulse Width HIGH
tVPH
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. See “How Extended Timings Impact CellularRAM™ Operation” below.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 48. The Low-Z timings measure a
4. 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
5. Low-Z to High-Z timings are tested with the circuit shown in Figure 48. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
October 4, 2004 cellRAM_00_A0
CellularRAM
141
A d v a n c e I n f o r m a t i o n
Table 18. Burst READ Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Burst to READ Access Time (Variable Latency)
CLK to Output Delay
Symbol
tABA
tACLK
tAVS
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
11
Address Setup to ADV# HIGH
Burst OE# LOW to Output Delay
CE# HIGH between Subsequent Mixed-Mode Operations
CE# LOW to WAIT Valid
10
10
20
20
5
1
5
1
7.5
7.5
CLK Period
12.5
4
15
5
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and WAIT High-Z Output
CLK Rise or Fall Time
2
2
tHZ
8
1.6
9
8
1.6
11
8
2
tKHKL
tKHTL
tKHZ
tKLZ
tKOH
tKP
CLK to WAIT Valid
CLK to DQ High-Z Output
3
2
2
3
8
3
2
2
3
CLK to Low-Z Output
5
5
Output HOLD from CLK
CLK HIGH or LOW Time
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
tOHZ
tOLZ
tSP
8
8
2
3
5
3
5
3
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 48. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 48. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
142
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 19. Asynchronous WRITE Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
Notes
Address and ADV# LOW Setup Time
Address Hold from ADV# Going HIGH
Address Setup to ADV# Going HIGH
Address Valid to End of Write
LB#/UB# Select to End of Write
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
tAVH
tAVS
tAW
5
5
ns
10
70
70
10
85
85
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
tCEM
tCEW
tCKA
tCVS
tCW
tDH
4
4
1
1
7.5
1
7.5
Async Address-to-Burst Transition Time
CE# Low to ADV# HIGH
70
10
70
0
85
10
85
0
Chip Enable to End of Write
Data Hold from Write Time
Data WRITE Setup Time
tDW
tHZ
23
23
1
Chip Disable to WAIT High-Z Output
Chip Enable to Low-Z Output
End WRITE to Low-Z Output
ADV# Pulse Width
8
8
tLZ
10
5
10
5
3
3
tOW
tVP
tVPH
tVS
10
10
70
70
10
10
85
85
ADV# Pulse Width HIGH
ADV# Setup to End of WRITE
WRITE Cycle Time
tWC
tWHZ
tWP
WRITE to DQ High-Z Output
WRITE Pulse Width
8
8
2
1
46
10
0
55
10
0
WRITE Pulse Width HIGH
tWPH
tWR
WRITE Recovery Time
Notes:
1. See “How Extended Timings Impact CellularRAM™ Operation” below.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 48. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 48. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
Table 20. Burst WRITE Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
tCBPH
tCEW
Min
5
Max
Min
5
Max
Units
ns
Notes
CE# HIGH between Subsequent Mixed-Mode Operations
CE# LOW to WAIT Valid
1
7.5
1
7.5
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
143
A d v a n c e I n f o r m a t i o n
Table 20. Burst WRITE Cycle Timing Requirements (Continued)
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
tCLK
tCSP
tHD
Min
12.5
4
Max
Min
15
5
Max
Units
ns
Notes
Clock Period
CE# Setup to CLK Active Edge
Hold Time from Active CLK Edge
Chip Disable to WAIT High-Z Output
CLK Rise or Fall Time
ns
2
2
ns
tHZ
8
1.6
9
8
ns
tKHKL
tKHTL
tKP
1.6
11
ns
Clock to WAIT Valid
ns
CLK HIGH or LOW Time
Setup Time to Activate CLK Edge
3
3
3
3
ns
tSP
ns
Timing Diagrams
V
(MIN)
CC
V
, V Q = 1.7V
CC CC
t
PU
Device ready for
normal operation
Figure 19. Initialization Period
Table 21. Initialization Timing Parameters
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
Initialization Period (required before normal operations)
tPU
150
150
µs
144
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
VALID ADDRESS
A[22:0]
t
AA
V
V
IH
IL
ADV#
CE#
t
t
CBPH
HZ
V
V
IH
IL
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 20. Asynchronous READ
Table 22. Asynchronous READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
70
8
Min
Max
85
85
8
Units
ns
tBA
ns
tBHZ
tBLZ
ns
10
5
10
5
ns
tCBPH
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
145
A d v a n c e I n f o r m a t i o n
Table 22. Asynchronous READ Timing Parameters (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCEW
tCO
Min
Max
7.5
70
8
Min
Max
Units
ns
1
1
7.5
ns
tHZ
8
ns
tLZ
10
10
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
tRC
ns
5
5
ns
70
85
ns
146
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AA
t
t
AVH
AVS
t
VPH
V
V
IH
IL
ADV#
t
AADV
t
VP
t
t
CVS
t
CBPH
HZ
V
V
IH
IL
CE#
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 21. Asynchronous READ Using ADV#
Table 23. Asynchronous READ Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
Min
Max
85
Units
ns
tAADV
70
85
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
147
A d v a n c e I n f o r m a t i o n
Table 23. Asynchronous READ Timing Parameters Using ADV# (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCVS
tAVH
tAVS
tBA
Min
10
5
Max
Min
10
5
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
70
8
85
8
tBHZ
tBLZ
tCBPH
tCEW
tCO
10
5
10
5
1
7.5
70
1
7.5
85
tCVS
tHZ
10
10
10
10
8
8
tLZ
tOE
20
8
20
8
tOHZ
tOLZ
tVP
5
5
10
10
10
10
tVPH
148
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
A[22:0]
A[3:0]
VALID ADDRESS
V
V
IH
IL
VALID
VALID
VALID
ADDRESS
VALID ADDRESS
ADDRESS
ADDRESS
t
t
PC
AA
V
V
IH
IL
ADV#
t
t
CEM
CBPH
t
t
t
CBPH
CO
HZ
V
V
IH
IL
CE#
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
t
APA
BLZ
t
t
OH
LZ
V
V
OH
OL
High-Z
t
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 22. Page Mode READ
Table 24. Asynchronous READ Timing Parameters—Page Mode Operation
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
20
70
8
Min
Max
85
25
85
8
Units
ns
tAPA
tBA
ns
ns
tBHZ
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
149
A d v a n c e I n f o r m a t i o n
Table 24. Asynchronous READ Timing Parameters—Page Mode Operation (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tBLZ
tCBPH
tCEM
tCEW
tCO
Min
10
5
Max
Min
10
5
Max
Units
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
7.5
70
8
4
7.5
85
8
1
1
tHZ
tLZ
10
5
10
5
tOE
20
8
20
8
tOH
tOHZ
tOLZ
tPC
5
5
20
70
25
85
tRC
150
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
KHKL
t
t
SP
HD
V
V
IH
IL
A[22:0]
ADV#
VALID ADDRESS
t
t
SP
HD
V
V
IH
IL
t
HD
t
t
HZ
t
ABA
CSP
V
V
IH
IL
CE#
OE#
t
t
OHZ
BOE
V
V
IH
IL
t
OLZ
t
t
SP
SP
HD
V
V
IH
IL
WE#
t
t
HD
V
V
IH
IL
LB#/UB#
t
CEW
t
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
t
KOH
ACLK
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 23. Single-Access Burst READ Operation—Variable Latency
Table 25. Burst READ Timing Parameters—Single Access, Variable Latency
70ns/80 MHz
85ns/66 MHz
Symbol
tABA
Min
Max
35
9
Min
Max
55
Units
ns
tACLK
11
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
151
A d v a n c e I n f o r m a t i o n
Table 25. Burst READ Timing Parameters—Single Access, Variable Latency (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tBOE
tCEW
tCLK
tCSP
tHD
Min
Max
20
Min
Max
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
12.5
4
7.5
1
15
5
7.5
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
tOLZ
tSP
8
8
5
3
5
3
152
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
CLK
t
t
t
KP
KHKL
KP
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
t
HD
CSP
ABA
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 24. Four-word Burst READ Operation—Variable Latency
October 4, 2004 cellRAM_00_A0
CellularRAM
153
A d v a n c e I n f o r m a t i o n
Table 26. Burst READ Timing Parameters—4-word Burst
70ns/80 MHz
85ns/66 MHz
Symbol
tABA
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
tOLZ
tSP
8
8
5
3
5
3
154
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
HD
CSP
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
t
t
t
KHTL
KHTL
KHTL
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
High-Z
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 25. Four-word Burst READ Operation (with LB#/UB#)
October 4, 2004 cellRAM_00_A0
CellularRAM
155
A d v a n c e I n f o r m a t i o n
Table 27. Burst READ Timing Parameters—4-word Burst with LB#/UB#
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
2
2
tHZ
8
9
8
5
8
11
8
tKHTL
tKHZ
tKLZ
3
2
2
3
2
2
5
tKOH
tOHZ
tOLZ
tSP
8
8
5
3
5
3
156
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
HD
SP
V
V
IH
IL
ADV#
t
CBPH
t
t
t
CSP
HZ
V
V
IH
IL
CE#
OE#
t
OHZ
OHZ
(Note 2)
V
V
IH
IL
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
BOE
t
OLZ
High-Z
V
V
High-Z
IH
IL
WAIT
t
KOH
t
BOE
t
ACLK
t
OLZ
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.
Figure 26. READ Burst Suspend
Table 28. Burst READ Timing Parameters—Burst Suspend
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
12.5
4
5
15
5
ns
ns
tCSP
ns
tHD
2
2
ns
tHZ
8
8
8
8
ns
tKOH
tOHZ
tOLZ
2
5
2
5
ns
ns
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
157
A d v a n c e I n f o r m a t i o n
Table 28. Burst READ Timing Parameters—Burst Suspend (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tSP
3
3
ns
V
CLK
V
IH
IL
t
CLK
V
IH
IL
A[22:0]
V
V
V
IH
IL
ADV#
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
OE#
WE#
V
V
IH
IL
V
V
IH
IL
t
t
KHTL
KHTL
V
V
OH
OL
(Note 2)
WAIT
t
t
KOH
ACLK
V
V
OH
OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 27. Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 29. Burst READ Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tCLK
Min
12.5
2
Max
Min
15
2
Max
Units
ns
9
11
ns
tKHTL
tKOH
9
11
ns
ns
158
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
AA
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 28. CE#-Controlled Asynchronous WRITE
Table 30. Asynchronous WRITE Timing Parameters—CE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAW
70
70
85
85
ns
tBW
ns
tCEM
4
4
µs
October 4, 2004 cellRAM_00_A0
CellularRAM
159
A d v a n c e I n f o r m a t i o n
Table 30. Asynchronous WRITE Timing Parameters—CE#-Controlled (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCEW
tCW
Min
1
Max
Min
1
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.5
7.5
70
0
85
0
tDH
tDW
tHZ
23
23
8
8
8
8
tLZ
10
70
10
85
tWC
tWHZ
tWP
tWPH
tWR
46
10
0
55
10
0
160
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 29. LB#/UB#-Controlled Asynchronous WRITE
Table 31. Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAW
70
70
85
85
ns
tBW
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
161
A d v a n c e I n f o r m a t i o n
Table 31. Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCEM
tCEW
tCW
Min
Max
4
Min
Max
4
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
70
0
7.5
1
85
0
7.5
tDH
tDW
tHZ
23
23
8
8
8
8
tLZ
10
70
10
85
tWC
tWHZ
tWP
tWPH
tWR
46
10
0
55
10
0
162
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
AS
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 30. WE#-Controlled Asynchronous WRITE
Table 32. Asynchronous WRITE Timing Parameters—WE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tAS
0
0
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
163
A d v a n c e I n f o r m a t i o n
Table 32. Asynchronous WRITE Timing Parameters—WE#-Controlled (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tAW
Min
70
Max
Min
85
Max
Units
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
70
85
tCEM
tCEW
tCW
4
4
1
70
0
7.5
1
85
0
7.5
tDH
tDW
tHZ
23
23
8
8
8
8
tLZ
10
5
10
5
tOW
tWC
tWHZ
tWP
tWPH
tWR
70
85
46
10
0
55
10
0
164
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
t
AVH
AVS
t
VS
t
t
VP
VPH
t
AS
V
V
IH
IL
ADV#
t
AS
t
AW
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WPH
WP
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 31. Asynchronous WRITE Using ADV#
October 4, 2004 cellRAM_00_A0
CellularRAM
165
A d v a n c e I n f o r m a t i o n
Table 33. Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
5
5
10
70
70
10
85
85
tBW
tCEM
tCEW
tCW
tDH
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
tLZ
10
5
10
5
tOW
tAS
0
0
tVP
10
10
70
10
10
85
tVPH
tVS
tWHZ
tWP
8
8
46
10
55
10
tWPH
166
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
KHKL
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
t
t
SP
HD
V
V
IH
IL
t
SP
t
HD
V
V
IH
IL
LB#/UB#
t
t
CSP
t
HD
CBPH
V
V
IH
IL
CE#
OE#
V
V
IH
IL
t
t
SP
HD
V
V
IH
IL
WE#
t
HZ
t
t
CEW
KHTL
High-Z
V
V
(Note 2)
IH
IL
High-Z
WAIT
t
t
HD
SP
V
V
OH
OL
DQ[15:0]
D[1]
D[2]
D[3]
D[0]
Legend:
READ Burst Identified
(WE# = LOW)
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst
length four; burst wrap enabled.
Figure 32. Burst WRITE Operation
October 4, 2004 cellRAM_00_A0
CellularRAM
167
A d v a n c e I n f o r m a t i o n
Table 34. Burst WRITE Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tCBPH
tCEW
tCLK
tCSP
tHD
Min
5
Max
Min
5
Max
Units
ns
1
7.5
1
7.5
ns
12.5
4
15
5
ns
ns
2
2
ns
tHZ
8
1.6
9
8
ns
tKHKL
tKHTL
tKP
1.6
11
ns
ns
3
3
3
3
ns
tSP
ns
168
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
t
CLK
V
V
IH
IL
A[22:0]
ADV#
V
V
IH
IL
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
V
V
IH
IL
WE#
V
V
IH
IL
OE#
t
t
KHTL
KHTL
(Note 2)
V
V
OH
OL
WAIT
t
t
HD
SP
V
V
OH
OL
Valid Input
D[n+3]
Valid Input
D[n+2]
Valid Input Valid Input
DQ[15:0]
D[n]
D[n+1]
Legend:
Don't Care
END OF ROW
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 33. Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 35. Burst WRITE Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
tCLK
Min
12.5
2
Max
Min
15
2
Max
Units
ns
tHD
ns
tKHTL
tSP
8
3
11
3
ns
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
169
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
t
HD
SP
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
SP
t
t
HD
SP
HD
V
V
IH
IL
ADV#
t
t
t
HD
KADV
SP
V
V
IH
IL
LB#/UB#
CE#
t
t
t
HD
CSP
CBPH
V
V
IH
IL
(Note 2)
t
CSP
t
OHZ
V
V
IH
IL
OE#
t
SP
t
t
HD
t
SP
HD
V
V
IH
IL
WE#
t
BOE
V
V
High-Z
High-Z
OH
OL
WAIT
t
t
KOH
t
t
HD
ACLK
SP
V
V
V
High-Z
IH
IL
High-Z
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
V
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to
schedule the appropriate internal refresh operation. CE# can stay LOW between burst READ and burst WRITE
operations. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE#
LOW time (tCEM).
Figure 34. Burst WRITE Followed by Burst READ
Table 36. WRITE Timing Parameters—Burst WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tCBPH
tCLK
Min
5
Max
Min
5
Max
Units
ns
12.5
4
20
20
15
5
20
20
ns
tCSP
ns
tHD
2
2
ns
tSP
3
3
ns
Table 37. READ Timing Parameters—Burst WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
Min
Max
Min
Max
ns
Units
9
11
20
20
ns
ns
tCLK
12.5
15
170
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 37. READ Timing Parameters—Burst WRITE Followed by Burst READ (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCSP
tHD
Min
4
Max
Min
5
Max
Units
ns
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
WR
AVS
AVH
AW
t
t
HD
t
SP
VPH
V
V
IH
IL
ADV#
t
t
t
VP
VS
t
t
t
BW
SP
HD
CVS
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CBPH
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
t
t
HD
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
WHZ
t
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
t
t
DH
DW
KOH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 35. Asynchronous WRITE Followed by Burst READ
October 4, 2004 cellRAM_00_A0
CellularRAM
171
A d v a n c e I n f o r m a t i o n
Table 38. WRITE Timing Parameters—Asynchronous WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tAVH
tAS
Min
5
Max
Min
5
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
tAVS
tAW
10
70
70
70
10
70
0
10
85
85
85
10
85
0
tBW
tCKA
tCVS
tCW
tDH
tDW
tVP
tVPH
tVS
20
10
10
70
70
23
10
10
85
85
tWC
tWHZ
tWP
tWPH
tWR
8
8
46
10
0
55
10
0
Table 39. READ Timing Parameters—Asynchronous WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
1
5
1
ns
7.5
7.5
ns
12.5
4
15
5
ns
tCSP
ns
tHD
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
172
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
WR
AW
t
t
HD
SP
V
V
IH
IL
ADV#
t
t
SP
t
BW
HD
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CSP
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
t
t
HD
WP
WPH
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
t
WHZ
t
t
KOH
DW
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
DH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 36. Asynchronous WRITE (ADV# LOW) Followed By Burst READ
Table 40. Asynchronous WRITE Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
tAW
Min
70
70
70
70
0
Max
Min
85
85
85
85
0
Max
Units
ns
tBW
ns
tCKA
tCW
ns
ns
tDH
ns
tDW
23
70
23
85
ns
tWC
ns
tWHZ
8
8
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
173
A d v a n c e I n f o r m a t i o n
Table 40. Asynchronous WRITE Timing Parameters—ADV# LOW (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tWP
Min
46
10
0
Max
Min
55
10
0
Max
Units
ns
tWPH
tWR
ns
ns
Table 41. Burst READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
1
5
1
ns
7.5
7.5
ns
12.5
4
15
5
ns
tCSP
ns
tHD
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
174
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
WC
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AW
SP
t
WR
t
HD
V
V
IH
IL
ADV#
t
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
IH
IL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 37. Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
October 4, 2004 cellRAM_00_A0
CellularRAM
175
A d v a n c e I n f o r m a t i o n
Table 42. Burst READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
tCSP
tHD
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
8
8
Table 43. Asynchronous WRITE Timing Parameters—WE# Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
Max
Units
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
0
tAW
70
70
85
85
tBW
tCEM
tCW
tDH
4
4
8
70
0
85
0
tDW
tHZ
tWC
tWP
tWPH
tWR
23
23
8
70
46
10
0
85
55
10
0
176
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
HD
SP
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AVS
AVH
t
t
t
VPH
VS
SP
t
t
HD
VP
V
V
IH
IL
ADV#
t
AW
t
t
AS
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
OH
OL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 38. Burst READ Followed by Asynchronous WRITE Using ADV#
October 4, 2004 cellRAM_00_A0
CellularRAM
177
A d v a n c e I n f o r m a t i o n
Table 44. Burst READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
tCSP
tHD
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
8
8
Table 45. Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
5
5
10
70
70
10
85
85
tBW
tCEM
tCEW
tCW
4
4
1
70
0
7.5
1
85
0
7.5
tDH
tDW
tHZ
23
23
8
8
tVP
10
10
70
46
10
10
10
85
55
10
tVPH
tVS
tWP
tWPH
178
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Table 45. Asynchronous WRITE Timing Parameters Using ADV# (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tWR
0
0
ns
V
V
IH
IL
Valid
Address
Valid
Valid
Address
A[22:0]
ADV#
Address
t
t
WR
t
AW
AA
V
V
IH
IL
t
t
t
BHZ
BW
BLZ
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CBPH
CEM
t
HZ
CW
V
V
IH
IL
(Note)
t
LZ
t
t
OHZ
OE
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
V
V
IH
IL
WE#
t
t
HZ
HZ
V
V
OH
OL
WAIT
t
WHZ
t
OLZ
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact Cel-
lularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 39. Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW
Table 46. WRITE Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAW
70
70
70
85
85
85
ns
tBW
ns
tCW
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
179
A d v a n c e I n f o r m a t i o n
Table 46. WRITE Timing Parameters—ADV# LOW (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tDH
Min
0
Max
Min
0
Max
Units
ns
tDW
23
23
ns
tHZ
8
8
8
8
ns
tWC
70
85
ns
tWHZ
tWP
tWPH
tWR
ns
46
10
0
55
10
0
ns
ns
ns
Table 47. READ Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
8
Min
Max
85
8
Units
ns
tBHZ
tBLZ
tCBPH
tCEM
tHZ
ns
10
5
10
5
ns
ns
4
8
4
8
µs
ns
tLZ
10
5
10
5
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
ns
ns
180
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
t
AA
AVS
AVH
AW
WR
t
t
t
VPH VP
VS
V
V
IH
IL
ADV#
t
t
t
BHZ
t
BW
BLZ
CVS
V
V
IH
IL
LB#/UB#
t
t
CEM
t
CBPH
t
HZ
CW
V
V
IH
IL
CE#
OE#
(Note)
t
t
LZ
AS
t
OHZ
V
V
IH
IL
t
WC
t
t
WP
t
AS
WPH
t
OLZ
V
V
IH
IL
WE#
V
V
OH
OL
WAIT
t
WHZ
t
OE
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact Cel-
lularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 40. Asynchronous WRITE Followed by Asynchronous READ
Table 48. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAVH
tAVS
tAW
5
5
ns
10
70
70
10
70
0
10
85
85
10
85
0
ns
ns
tBW
ns
tCVS
tCW
ns
ns
tDH
ns
tDW
23
23
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
181
A d v a n c e I n f o r m a t i o n
Table 48. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
tVP
Min
10
10
70
70
Max
Min
10
10
85
85
Max
Units
ns
tVPH
tVS
ns
ns
tWC
ns
tWHZ
tWP
tWPH
tWR
8
8
ns
46
10
0
55
10
0
ns
ns
ns
Table 49. READ Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
8
Min
Max
85
8
Units
ns
tBHZ
tBLZ
tCBPH
tCEM
tHZ
ns
10
5
10
5
ns
ns
4
8
4
8
µs
ns
tLZ
10
10
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
ns
5
5
ns
How Extended Timings Impact CellularRAM™ Operation
Introduction
This section describes CellularRAM™ timing requirements in systems that per-
form extended operations.
CellularRAM products use a DRAM technology that periodically requires refresh to
ensure against data corruption. CellularRAM devices include on-chip circuitry that
performs the required refresh in a manner that is completely transparent in sys-
tems with normal bus timings. The refresh circuitry imposes constraints on
timings in systems that take longer than 4µs to complete an operation. WRITE
operations are affected if the device is configured for asynchronous operation.
Both READ and WRITE operations are affected if the device is configured for page
or burst-mode operation.
182
CellularRAM
cellRAM_00_A0 October 4, 2004
A d v a n c e I n f o r m a t i o n
Asynchronous WRITE Operation
The timing parameters provided in Figure 50 require that all WRITE operations
must be completed within 4µs. After completing a WRITE operation, the device
must either enter standby (by transitioning CE# HIGH), or else perform a second
operation (READ or WRITE) using a new address. Figure 71 and Figure 72 dem-
onstrate these constraints as they apply during an asynchronous (page-mode-
disabled) operation. Either the CE# active period (t
in Figure 71) or the ad-
CEM
dress valid period (t
in Figure 72) must be less than 4µs during any WRITE
TM
operation, otherwise, the extended WRITE timings must be used.
t
< 4 µs
CEM
CE#
ADDRESS
Figure 41. Extended Timing for tCEM
CE#
t
<
TM 4µs
ADDRESS
Figure 42. Extended Timing for tTM
Table 50. Extended Cycle Impact on READ and WRITE Cycles
Page Mode
Timing Constraint
Read Cycle
Write Cycle
Must use extended WRITE
timing.
Asynchronous
Page Mode Disabled
tCEM and tTM > 4µs
(See Figure 71 and Figure 72.)
No impact.
(See Figure 72)
Must use extended WRITE
timing.
Asynchronous
Page Mode Enabled
tCEM > 4µs
(See Figure 71.)
All following intrapage READ
access times are tAA (not tAPA).
(See Figure 73)
Burst
tCEM > 4µs (See Figure 71.)
Burst must cross a row boundary within 4µs.
Extended WRITE Timing— Asynchronous WRITE Operation
Modified timings are required during extended WRITE operations (see Figure 73).
An extended WRITE operation requires that both the write pulse width (t ) and
WP
the data valid period (t ) be lengthened to at least the minimum WRITE cycle
DW
time (t
[MIN]). These increased timings ensure that time is available for both
WC
a refresh operation and a successful completion of the WRITE operation.
October 4, 2004 cellRAM_00_A0
CellularRAM
183
A d v a n c e I n f o r m a t i o n
t
or t
> 4µs
TM
CEM
ADDRESS
CE#
LB#/UB#
t
t
> t
(MIN)
(MIN)
WP
DW
WC
WC
WE#
> t
DATA-IN
Figure 43. Extended WRITE Operation
Page Mode READ Operation
When a CellularRAM device is configured for page mode operation, the address
inputs are used to accelerate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. If CE# is LOW longer than the t
maximum time
CEM
of 4µs during a READ operation, the system must allow t
(not t
, as would
AA
APA
otherwise be expected) for all subsequent intrapage accesses until CE# goes
HIGH.
Burst-Mode Operation
When configured for burst-mode operation, it is necessary to allow the device to
perform a refresh within any 4µs window. One of two conditions will enable the
device to schedule a refresh within 4µs. The first condition is when all burst op-
erations complete within 4µs. A burst completes when the CE# signal is
registered HIGH on a rising clock edge. The second condition that allows a refresh
is when a burst access crosses a row boundary. The row-boundary crossing
causes WAIT to be asserted while the next row is accessed and enables the
scheduling of refresh.
Summary
CellularRAM products are designed to ensure that any possible asynchronous tim-
ings do not cause data corruption due to lack of refresh. Slow bus timings on
asynchronous WRITE operations require that t
and t
be lengthened. Slow
WP
DW
bus timings during asynchronous page READ operations cause the next intrapage
READ data to be delayed to t
.
AA
Burst mode timings must allow the device to perform a refresh within any 4µs
period. A burst operation must either complete (CE# registered HIGH) or cross a
row boundary within 4µs to ensure successful refresh scheduling. These timing
requirements are likely to have little or no impact when interfacing a CellularRAM
device with a low-speed memory bus.
184
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
1.8V pSRAM Type 4
8M x 16-bit Synchronous Burst pSRAM
Features
Process Technology: CMOS
Organization: 8M x16 bit
Power Supply Voltage: 1.7~2.0V
Three State Outputs
Supports MRS (Mode Register Set)
MRS control - MRS Pin Control
Supports Power Saving modes - Partial Array Refresh mode Internal TCSR
Supports Driver Strength Optimization for system environment power saving
Supports Asynchronous 4-Page Read and Asynchronous Write Operation
Supports Synchronous Burst Read and Asynchronous Write Operation (Ad-
dress Latch Type and Low ADV Type)
Supports Synchronous Burst Read and Synchronous Burst Write Operation
Synchronous Burst (Read/Write) Operation
— Supports 4 word / 8 word / 16 word and Full Page(256 word) burst
— Supports Linear Burst type & Interleave Burst type
— Latency support:
Latency 5 @ 66MHz(tCD 10ns)
Latency 4 @ 54MHz(tCD 10ns)
— Supports Burst Read Suspend in No Clock toggling
— Supports Burst Write Data Masking by /UB & /LB pin control
— Supports WAIT pin function for indicating data availability.
Max. Burst Clock Frequency: 66MHz
Pin Description
Pin Name
CLK
Function
Type
Description
Clock
Commands are referenced to CLK
ADV#
MRS#
Address Valid
Valid Address is latched by ADV falling edge
MRS# low enables Mode Register to be set
CS# low enables the chip to be active
Mode Register set
CS#
Chip Select
CS# high disables the chip and puts it into standby
mode
Input
OE#
WE#
LB#
Output Enable
Write Enable
OE# low enables the chip to output the data
WE# low enables the chip to start writing the data
Lower Byte (I/O0~7
)
UB# (LB#) low enables upper byte (lower byte) to
start operating
UB#
Upper Byte (I/O8~15)
Valid addresses input when ADV is low
Mode setting input when MRS is low
A0-A22
Address 0 ~ Address 22
Depending on UB# or LB# status, word (16-bit,
UB# & LB# low) data, upper byte (8-bit, UB# low &
LB# high) data or lower byte (8-bit, LB# low & UB#
high) data is loaded
I/O0-I/O15
Data Inputs / Outputs
Input/Output
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
185
P r e l i m i n a r y
Pin Name
VCC
Function
Voltage Source
Type
Description
Power
Power
GND
Core Power supply
I/O Power supply
Core ground Source
I/O Ground Source
VCCQ
Voltage Source
VSS
Ground Source
VSSQ
I/O Ground Source
Valid Data Indicator
GND
WAIT#
Output
WAIT# indicates whether data is valid or not
Power Up Sequence
After applying V up to minimum operating voltage (1.7V), drive CS# high first
CC
and then drive MRS# high. This gets the device into power up mode. Wait 200 µs
minimum to get into the normal operation mode. During power up mode, the
standby current cannot be guaranteed. To obtain stable standby current levels,
at least one cycle of active operation should be implemented regardless of wait
time duration. To obtain appropriate device operation, be sure to follow the
proper power up sequence.
1. Apply power.
2. Maintain stable power (V min.=1.7V) for a minimum 200 µs with CS# and
CC
MRS# high.
186
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Timing Diagrams
Power Up
200 µs
VCC(Min)
VCC
Min. 0ns
Min. 0ns
MRS#
CS#
Min. 200 µs
PowerUp Mode
Normal Operation
Figure 1. Power Up Timing
Notes:
1. After VCC reaches VCC(Min.), wait 200 µs with CS# and MRS# high. This puts the device into normal operation.
Standby Mode
CS# = V
CS# = UB# = LB# = V
WE# = V , MRS# = V
CS# = V , UB# or LB# = V
IL IL
IH
IL
IH
MRS# = V
MRS# = V
CS# = V
IH
IH
IL
IH
MRS# = V
IH
Initial State
(wait 200µs)
Standby
Mode
PAR
Mode
Power On
MRS Setting
Active
MRS# = V
IL
MRS Setting
CS# = V
IL
WE# = V , MRS#=V
IL IL
Figure 2. Standby Mode State Machines
The default mode after power up is Asynchronous mode (4 Page Read and Asyn-
chronous Write). But this default mode is not 100% guaranteed, so the MRS#
setting sequence is highly recommended after power up.
For entry to PAR mode, drive the MRS# pin into V for over 0.5µs or longer (sus-
IL
pend period) during standby mode after the MRS# setting has been completed
(A4=1, A3=0). If the MRS# pin is driven into V during PAR mode, the device
IH
reverts to standby mode without the wake up sequence.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
187
P r e l i m i n a r y
Functional Description
Table 1. Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0)
Mode
CS#
MRS#
OE#
X
WE#
LB#
X
UB#
X
I/O
I/O
Power
Standby
PAR
0-7
8-15
Deselected
Deselected
H
H
L
L
L
L
L
L
L
L
L
H
L
X
X
H
X
H
H
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
Output Disabled
Outputs Disabled
Lower Byte Read
Upper Byte Read
Word Read
H
H
H
H
H
H
H
H
L
H
X
X
X
Active
Active
Active
Active
Active
Active
Active
Active
Active
H
L
H
H
L
L
D
OUT
L
H
L
High-Z
D
D
OUT
OUT
L
L
D
OUT
Lower Byte Write
Upper Byte Write
Word Write
H
H
H
H
L
H
L
D
High-Z
IN
L
H
L
High-Z
D
D
IN
IN
L
L
D
IN
Mode Register Set
L
L
L
High-Z
High-Z
Legend:X = Don’t care (must be low or high state).
Notes:
1. In asynchronous mode, Clock and ADV# are ignored.
2. The WAIT# pin is High-Z in asynchronous mode.
188
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Table 2. Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1)
Mode
CS# MRS# OE# WE# LB# UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
Deselected
H
H
L
H
L
X
X
H
X
X
X
H
X
X
X
X
H
X
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Standby
(note 2)
(note 2)
X
X
Deselected
PAR
(note 2)
(note 2)
X
Output Disabled
Outputs Disabled
H
H
H
H
Active
Active
(note 2)
X
L
(note 2)
Read Command
Lower Byte Read
Upper Byte Read
L
L
L
H
H
H
X
L
L
H
H
H
X
L
X
H
L
High-Z
High-Z
High-Z
Active
Active
Active
D
H
H
OUT
H
High-Z
D
D
OUT
Word Read
L
H
L
H
L
L
D
H
Active
OUT
OUT
X
Lower Byte Write
Upper Byte Write
Word Write
L
L
L
L
H
H
H
L
H
H
H
H
L
L
L
L
L
H
L
H
L
L
L
D
High-Z
Active
Active
Active
Active
IN
(note 2)
or
or
or
or
X
High-Z
D
D
IN
IN
(note 2)
X
D
IN
(note 2)
X
Mode Register Set
L
High-Z
High-Z
(note 2)
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram
for WAIT# pin function.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
189
P r e l i m i n a r y
Table 3. Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14=1/0)
Mode
CS# MRS#
OE#
WE#
LB#
UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
X
X
X
X
Deselected
H
H
L
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Standby
(note1)
(note1)
(note1) (note1)
(note 2)
(note 2)
X
X
X
X
X
X
Deselected
PAR
(note1)
(note1)
(note1) (note1)
(note 2)
(note 2)
Output
Disabled
X
H
H
H
H
X
H
X
H
H
H
Active
Active
(note 2)
Outputs
Disabled
X
X
X
L
(note1)
(note1)
(note 2)
Read
X
L
L
L
H
H
H
H
H
H
X
L
X
H
L
High-Z
High-Z
High-Z
Active
Active
Active
Command
(note1)
LowerByte
Read
L
L
D
H
H
OUT
UpperByte
Read
H
High-Z
D
D
OUT
OUT
Word Read
L
H
L
H
L
L
D
H
Active
OUT
Write
Command
X
L
L
L
H
H
H
High-Z
High-Z
High-Z
Active
Active
Active
L
(note1)
or
LowerByte
Write
X
H
H
L
H
L
D
H
H
IN
(note1)
UpperByte
Write
X
H
High-Z
D
D
IN
IN
(note1)
X
Word Write
L
L
H
L
H
H
L
L
L
L
D
H
Active
Active
IN
(note1)
Mode
Register
Set
High-Z
High-Z
L
or
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram
for WAIT# pin function.
Mode Register Setting Operation
The device has several modes:
Asynchronous Page Read mode
Asynchronous Write mode
Synchronous Burst Read mode
Synchronous Burst Write mode
Standby mode and Partial Array Refresh (PAR) mode.
Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS)
option. The MRS option also defines burst length, burst type, wait polarity and
latency count at synchronous burst read/write mode.
190
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of
the pSRAM. It programs Partial Array Refresh (PAR), burst length, burst type, la-
tency count and various vendor specific options to make pSRAM useful for a
variety of different applications. The default values of mode register are defined,
therefore when the reserved address is input, the device runs at default modes.
The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS#
to V and driving OE# to V during valid addressing. The mode register is di-
IL
IH
vided into various fields depending on the fields of functions. The PAR field uses
A0~A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses
A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Driver
Strength uses A16~A17.
Refer to the Table below for detailed Mode Register Settings. A18~A22 addresses
are “Don’t care” in the Mode Register Setting.
Table 4. Mode Register Setting According to Field of Function
Address
Function
A17-A16
A15-A14
A13
A12
A11-A19
A8
A7-A5
A4-A3
A2
A1-A0
DS
MS
WP
RFU
Latency
BT
BL
PAR
PARA
PARS
Note: DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Re-
served for Future Use).
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
191
P r e l i m i n a r y
Table 5. Mode Register Set
Driver Strength
A16 DS
Mode Select
A17
0
A15
0
A14
MS
0
1
0
Full Drive (note 1)
1/2 Drive
0
1
0
Async. 4 Page Read / Async. Write (note 1)
Sync. Burst Read / Async. Write
Sync. Burst Read / Sync. Burst Write
0
0
1
1/4 Drive
1
WAIT# Polarity
RFU
RFU
Latency Count
Burst Type
BT
Burst Length
A6 A5
A13
WP
A12
0
A11 A10 A9
Latency
A8
0
A7
BL
Low Enable
(note 1)
Must
(note 1)
Linear
(note 1)
0
1
0
0
0
3
0
1
0
4 word
High Enable
1
—
0
0
0
0
1
1
1
0
1
4
5
6
1
Interleave
0
1
1
1
0
1
1
0
1
8 word
16 word (note 1)
Full (256 word)
Partial Array Refresh
PAR Array
PAR Size
A0
A4
A3
PAR
A2
PARA
A1
PARS
Bottom Array
(note 1)
Full Array
(note 1)
1
0
PAR Enable
0
0
0
1
PAR Disable
(note 1)
1
1
1
Top Array
0
3/4 Array
1
1
0
1
1/2 Array
1/4 Array
Notes:
1. Default mode. The address bits other than those listed in the table above are reserved. For example, Burst Length address
bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then
the mode will be set to the default mode. Each field has its own default mode, but this default mode is not 100% guaranteed,
so the MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as
“0”. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion. The 256 word Full
page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.
MRS Pin Control Type Mode Register Setting Timing
In this device, the MRS pin is used for two purposes. One is to get into the mode
register setting and the other is to execute Partial Array Refresh mode.
To get into the Mode Register Setting, the system must drive the MRS# pin to V
IL
and immediately (within 0.5µs) issue a write command (drive CS#, ADV#, UB#,
LB# and WE# to V and drive OE# to V during valid address). If the subse-
IL
IH
quent write command (WE# signal input) is not issued within 0.5µs, then the
device may get into the PAR mode.
192
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
tWC
Address
CS#
tCW
tAW
tBW
UB#, LB#
WE#
tWP
tAS
tWU
tMW
MRS#
Register Update Complete
Register Write Complete
Register Write Start
(MRS SETTING TIMING)
1. Clock input is ignored.
Figure 3. Mode Register Setting Timing (OE# = VIH
)
Table 6. MRS AC Characteristics
Speed
Parameter List
Symbol
tMW
Min
0
Max
500
—
Units
ns
MRS# Enable to Register Write Start
End of Write to MRS# Disable
MRS
tWU
0
ns
Note: VCC=1.7~2.0V, TA=-40 to 85°C, Maximum Main Clock Frequency=66MHz
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
193
P r e l i m i n a r y
Asynchronous Operation
Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are
driven to V under the valid address without toggling page addresses (A0, A1).
IL
If the page addresses (A0, A1) are toggled under the other valid address, the first
data will be out with the normal read cycle time (tRC) and the second, the third
and the fourth data will be out with the page cycle time (tPC). (MRS# and WE#
should be driven to V during the asynchronous (page) read operation) Clock,
IH
ADV#, WAIT# signals are ignored during the asynchronous (page) read
operation.
Asynchronous Write Operation
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven
to V under the valid address. MRS# and OE# should be driven to V during the
IL
IH
asynchronous write operation. Clock, ADV#, WAIT# signals are ignored during
the asynchronous (page) read operation.
Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS#, WE# and UB# or LB# are driven to V under
IL
the valid address. Clock input does not have any affect to the write operation
(MRS# and OE# should be driven to V during write operation. ADV# can be ei-
IH
ther toggling for address latch or held in V ). Clock, ADV#, WAIT# signals are
IL
ignored during the asynchronous (page) read operation.
A22~A2
A1~A0
CS#
UB#, LB#
OE#
Data Out
Figure 4. Asynchronous 4-Page Read
Address
CS#
UB#, LB#
WE#
High-Z
Data in
High-Z
High-Z
Data out
Figure 5. Asynchronous Write
194
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Operation
Burst mode operations enable the system to get high performance read and write
operation. The address to be accessed is latched on the rising edge of clock or
ADV# (whichever occurs first). CS# should be setup before the address latch.
During this first clock rising edge, WE# indicates whether the operation is going
to be a Read (WE# High) or a Write (WE# Low).
For the optimized Burst Mode of each system, the system should determine how
many clock cycles are required for the first data of each burst access (Latency
Count), how many words the device outputs during an access (Burst Length) and
which type of burst operation (Burst Type: Linear or Interleave) is needed. The
Wait Polarity should also be determined (See Table 86).
Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is
detected during the ADV# low pulse. ADV# and CS# should be set up before the
clock rising. During the Read command, WE# should be held in V . The multiple
IH
clock risings (during the low ADV# period) are allowed, but the burst operation
starts from the first clock rising. The first data will be out with Latency count and
t
.
CD
Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is
detected during the ADV# and WE# low pulse. ADV#, WE# and CS# should be
set up before the clock rising. The multiple clock risings (during the low ADV#
period) are allowed but, the burst operation starts from the first clock rising. The
first data will be written in the Latency clock with t
.
DS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
ADV#
Addr.
CS#
UB#, LB#
OE#
Data Out
WAIT#
Figure 6. Synchronous Burst Read
Note: Latency 5, BL 4, WP: Low Enable
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
195
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10 11 12 13
CLK
ADV#
Addr.
CS#
UB#, LB#
WE#
Data in
WAIT#
Figure 7. Synchronous Burst Write
Note: Latency 5, BL 4, WP: Low Enable
Synchronous Burst Operation Terminology
Clock (CLK)
The clock input is used as the reference for synchronous burst read and write op-
eration of the pSRAM. The synchronous burst read and write operations are
synchronized to the rising edge of the clock. The clock transitions must swing be-
tween V and V .
IL
IH
Latency Count
The Latency Count configuration tells the device how many clocks must elapse
from the burst command before the first data should be available on its data pins.
This value depends on the input clock frequency. Table 88 shows the supported
Latency Count.
Table 7. Latency Count Support
Clock Frequency
Latency Count
Up to 66 MHz
Up to 54 MHz
Up to 40 MHz
5
4
3
Table 8. Number of CLocks for 1st Data
Set Latency
Latency 3
Latency 4
Latency 5
# of Clocks for 1st data (Read)
# of Clocks for 1st data (Write)
4
2
5
3
6
4
196
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
T
Clock
ADV#
Address
Latency 3
Latency 4
Latency 5
Latency 6
DQ1
DQ2
DQ3
DQ2
DQ1
DQ4
DQ3
DQ2
DQ1
DQ5
DQ4
DQ3
DQ2
DQ6
DQ5
DQ4
DQ3
DQ7
DQ6
DQ5
DQ4
DQ8
DQ7
DQ6
DQ5
DQ9
DQ8
DQ7
DQ6
Data out
Data out
Data out
Data out
DQ1
Figure 8. Latency Configuration (Read)
Note: The first data will always keep the Latency. From the second data on, some period of wait time may be caused
by WAIT# pin.
Burst Length
Burst Length identifies how many data the device outputs during an access. The
device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256
word Full page burst mode needs to meet t
2500ns max.
(Burst Cycle time) parameter as
BC
The first data will be output with the set Latency + t . From the second data on,
CD
the data will be output with t
from each clock.
CD
Burst Stop
Burst stop is used when the system wants to stop burst operation on purpose. If
driving CS# to V during the burst read operation, the burst operation is
IH
stopped. During the burst read operation, the new burst operation cannot be is-
sued. The new burst operation can be issued only after the previous burst
operation is finished.
The burst stop feature is very useful because it enables the user to utilize the un-
supported burst length such as 1 burst or 2 burst, used mostly in the mobile
handset application environment.
Synchronous Burst Operation Terminology
Wait Control (WAIT#)
The WAIT# signal is the device’s output signal that indicates to the host system
when it’s data-out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the
WAIT# polarity (WP) can be configured. The polarity can be programmed to be
either low enable or high enable.
For the timing of WAIT# signal, the WAIT# signal should be set active one clock
prior to the data regardless of Read or Write cycle.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
197
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
CS#
Latency 5
Read
Data out
DQ0 DQ1
DQ2
DQ3
High-Z
High-Z
WAIT#
Latency 5
Write
Data in
D0
D1
D2
D3
WAIT#
Figure 9. WAIT# and Read/Write Latency Control
Note: LATENCY: 5, Burst Length: 4, WP: Low Enable
Burst Type
The device supports Linear type burst sequence and Interleave type burst se-
quence. Linear type burst sequentially increments the burst address from the
starting address. The detailed Linear and Interleave type burst address sequence
is shown in Table 90.
Table 9. Burst Sequence
Burst Address Sequence (Decimal)
Wrap (note 1)
Start
Address
4 word Burst
8 word Burst
Linear
16 word Burst
Full Page(256 word)
Linear
Linear
Interleave
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Interleave
0-1-2-...-6-7
1-0-3-...-7-6
2-3-0-...-4-5
3-2-1-...-5-4
4-5-6-...-2-3
5-4-7-...-3-2
6-7-4-...-0-1
7-6-5-...-1-0
Linear
Interleave
0-1-2-3-4...14-15
1-0-3-2-5...15-14
2-3-0-1-6...12-13
3-2-1-0-7...13-12
4-5-6-7-0...10-11
5-4-7-6-1...11-10
6-7-4-5-2...8-9
7-6-5-4-3...9-8
~
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-...-5-6-7
1-2-...-6-7-0
2-3-...-7-0-1
3-4-...-0-1-2
4-5-...-1-2-3
5-6-...-2-3-4
6-7-...-3-4-5
7-0-...-4-5-6
0-1-2-...-14-15
1-2-3-...-15-0
2-3-4-...-0-1
3-4-5-...-1-2
4-5-6-...-2-3
5-6-7-...-3-4
6-7-8-...-4-5
7-8-9-...-5-6
~
0-1-2-...-254-255
1-2-3-...-255-0
2
2-3-4-...-255-0-1
3-4-5-...-255-0-1-2
4-5-6-...-255-0-1-2-3
5-6-7-...-255-...-3-4
6-7-8-...-255-...-4-5
7-8-9-...-255-...-5-6
~
3
4
5
6
7
~
14
15
~
14-15-0-...-12-13
15-0-1-...-13-14
14-15-12-...-0-1
15-14-13-...-1-0
14-15-...-255-...-12-13
15-16-...-255-...-13-14
~
255
255-0-1-...-253-254
198
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Low Power Features
Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very
useful tool for reducing standby current at room temperature (below 40°C).
DRAM cells have weak refresh characteristics in higher temperatures. High tem-
peratures require more refresh cycles, which can lead to standby current
increase.
Without the internal TCSR, the refresh cycle should be set at worst condition so
as to cover the high temperature (85°C) refresh characteristics. But with internal
TCSR, a refresh cycle below 40°C can be optimized, so the standby current at
room temperature can be greatly reduced. This feature is beneficial since most
mobile phones are used at or below 40°C in the phone standby mode.
0.5 µs
MRS#
Normal
Operation
Normal
Operation
Suspend
PAR mode
MODE
CS#
Figure 10. PAR Mode Execution and Exit
Table 10. PAR Mode Characteristics
Address (Bottom Array) Address (Top Array)
Memory Cell
Standby Current
(µA, Max)
Wait
Time (µs)
Power Mode
(note 2)
(note 2)
Data
Standby (Full Array)
Partial Refresh(3/4 Block)
Partial Refresh(1/2 Block)
Partial Refresh(1/4 Block)
000000h ~ 7FFFFFh
000000h ~ 5FFFFFh
000000h ~ 3FFFFFh
000000h ~ 1FFFFFh
000000h ~ 7FFFFFh
200000h ~ 7FFFFFh
400000h ~ 7FFFFFh
600000h ~ 7FFFFFh
200
170
150
140
Valid (note 1)
0
Notes:
1. Only the data in the refreshed block are valid.
2. The PAR Array can be selected through Mode Register Set (see “Mode Register Setting Operation” on page 191).
Driver Strength Optimization
The optimization of output driver strength is possible through the mode register
setting to adjust for the different data loadings. Through this driver strength op-
timization, the device can minimize the noise generated on the data bus during
read operation. The device supports full drive, 1/2 drive and 1/4 drive.
Partial Array Refresh (PAR) mode
The PAR mode enables the user to specify the active memory array size. The
pSRAM consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or
all blocks as active memory arrays through the Mode Register Setting. The active
memory array is periodically refreshed whereas the disabled array is not re-
freshed, so the previously stored data is lost. Even though PAR mode is enabled
through the Mode Register Setting, PAR mode execution by the MRS# pin is still
needed. The normal operation can be executed even in refresh-disabled array as
long as the MRS# pin is not driven to the Low condition for over 0.5µs. Driving
the MRS# pin to the High condition puts the device back to the normal operation
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
199
P r e l i m i n a r y
mode from the PAR executed mode. Refer to Figure 83 and Table 91 for PAR op-
eration and PAR address mapping.
Absolute Maximum Ratings
Item
Symbol
VIN , VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 2.5V
1.0
Unit
V
Voltage on any pin relative to VSS
Power supply voltage relative to VSS
Power Dissipation
V
PD
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" section may cause permanent damage to the device.
Functional operation should be restricted to use under recommended operating conditions only. Exposure to absolute
maximum rating conditions longer than one second may affect reliability.
DC Recommended Operating Conditions
Symbol
VCC
Parameter
Power Supply Voltage
Ground
Min
1.7
Typ
1.85
0
Max
Unit
2.0
VSS
0
0
VCC + 0.2 (note 2)
0.4
V
VIH
Input High Voltage
Input Low Voltage
0.8 x VCC
-0.2 (note 3)
—
VIL
—
Notes:
1. TA=-40 to 85°C, unless otherwise specified.
2. Overshoot: VCC+1.0V in case of pulse width ≤ 20ns.
3. Undershoot: -1.0V in case of pulse width ≤ 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (Ta = 25°C, f = 1 MHz)
Symbol
CIN
Parameter
Test Condition
VIN = 0V
Min
—
Max
8
Unit
pF
Input Capacitance
CIO
Input/Output Capacitance
VOUT = 0V
—
10
pF
Note: This parameter is sampled periodically and is not 100% tested.
200
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
DC and Operating Characteristics
Common
Item
Symbol
Test Conditions
Min
-1
Typ
—
Max
Unit
µA
Input Leakage Current
Output Leakage Current
I
V
=V to V
CC
1
1
LI
IN
SS
I
CS#=V , MRS#=V , OE#=V or WE#=V , V =V to V
CC
-1
—
µA
LO
IH
IH
IH
IL
IO
SS
Average Operating
Current
Cycle time=t +3t , I =0mA, 100% duty, CS#=V , MRS#=V
,
RC
IH
PC IO
IL
IH
I
—
—
40
mA
CC2
V
=V or V
IN
IL
Output Low Voltage
Output High Voltage
V
I
I
=0.1mA
—
1.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.2
—
V
V
OL
OL
V
=-0.1mA
OH
OH
< 40°C
< 85°C
TBD
200
TBD
TBD
TBD
170
150
140
µA
µA
CS# ≥ V -0.2V, MRS# ≥ V -0.2V, Other
inputs = V to V
CC
CC
Standby Current (CMOS)
Partial Refresh Current
Notes:
I
SB1
SS
CC
3/4 Block
1/2 Block
1/4 Block
3/4 Block
1/2 Block
1/4 Block
< 40°C
< 85°C
µA
µA
I
MRS# ≤ 0.2V, CS# ≥ V -0.2V Other inputs =
V
SBP
CC
(note 1)
to V
SS CC
1. Full Array Partial Refresh Current (ISBP) is same as Standby Current (ISB1).
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
201
P r e l i m i n a r y
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to V -0.2V
CC
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x V
Output load (See Figure 84): CL=50pF
CC
Vtt = 0.5 x V
DDQ
50
Dout
Z0=50
30pF
Figure 11. Output Load
202
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Asynchronous AC Characteristics
(V =1.7~2.0V, TA=-40 to 85 °C)
CC
Speed Bins
Symbol
tRC
Parameter
Read Cycle Time
Min
70
25
—
—
—
—
—
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
tPC
Page Read Cycle Time
—
tAA
Address Access Time
70
tPA
Page Access Time
20
tCO
Chip Select to Output
70
tOE
Output Enable to Valid Output
UB#, LB# Access Time
35
tBA
35
tLZ
Chip Select to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#, LB# Disable to High-Z Output
Output Disable to High-Z Output
Output Hold
—
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
—
5
—
0
7
0
7
0
7
3
—
tWC
tCW
tADV
tAS
Write Cycle Time
70
60
7
—
Chip Select to End of Write
ADV# Minimum Low Pulse Width
Address Set-up Time to Beginning of Write
Address Set-up Time to ADV# Falling
Address Hold Time from ADV# Rising
—
—
0
—
tAS(A)
tAH(A)
tCSS(A)
tAW
0
—
7
—
CS# Setup Time to ADV# Rising
Address Valid to End of Write
UB#, LB# Valid to End of Write
Write Pulse Width
10
60
60
—
—
tBW
—
tWP
55 (Note 1)
—
tWHP
tWR
tWLRL
tDW
WE# High Pulse Width
5 ns
0
Latency-1 clock
Write Recovery Time
—
—
—
—
ns
clock
ns
ns
WE# Low to Read Latency
Data to Write Time Overlap
Data Hold from Write Time
1
30
0
tDH
Notes:
1. tWP (min)=70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
203
P r e l i m i n a r y
Timing Diagrams
Asynchronous Read Timing Waveform
MRS# = V , WE# = V , WAIT# = High-Z
IH
IH
tRC
Address
tAA
tOH
tCO
CS#
tCHZ
tBA
UB#, LB#
tBHZ
tOE
OE#
t
OLZ
tLBZLZ
tOHZ
t
Data out
High-Z
Data Valid
Figure 12. Timing Waveform Of Asynchronous Read Cycle
Notes:
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device interconnection.
3. In asynchronous read cycle, Clock, ADV# and WAIT# signals are ignored.
Table 11. Asynchronous Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
—
—
—
3
Max
—
Units
Symbol
tOLZ
tBLZ
Min
5
Max
—
—
—
7
Units
tAA
70
70
35
35
—
5
tCO
tLZ
10
0
ns
ns
tBA
tCHZ
tBHZ
tOHZ
tOE
0
7
tOH
0
7
204
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Page Read
MRS# = V , WE# = V , WAIT# = High-Z
IH
IH
t
RC
Valid
Address
A22~A2
A1~A0
tOH
t
AA
Valid
Valid
Valid
Valid
Address
Address Address Address
tPC
tCO
CS#
tBA
UB#, LB#
tBHZ
tOE
OE#
t
CHZ
t
tBOLZLZ
t
OHZ
t
PA
t
LZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data out
High Z
Figure 13. Timing Waveform Of Page Read Cycle
Notes:
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device interconnection.
3. In asynchronous 4 page read cycle, Clock, ADV# and WAIT# signals are ignored.
Table 12. Asynchronous Page Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
Max
—
Units
Symbol
tOH
Min
3
Max
—
—
—
—
7
Units
tAA
70
—
tOLZ
tBLZ
tLZ
5
tPC
25
—
5
tPA
20
70
35
35
ns
10
0
ns
tCO
—
tCHZ
tBHZ
tOHZ
tBA
—
0
7
tOE
—
0
7
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
205
P r e l i m i n a r y
Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
tWC
Address
tWR
tCW
CS#
tAW
t
BW
UB#, LB#
WE#
tWP
tAS
tDW
tDH
High-Z
High-Z
Data in
Data out
Data Valid
High-Z
High-Z
Figure 14. Timing Waveform Of Write Cycle
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
2. tCW is measured from the CS# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Table 13. Asynchronous Write AC Characteristics
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tAS
Min
0
Max
—
Units
70
tCW
60
60
—
tWR
0
—
ns
tAW
—
ns
tDW
30
0
—
tBW
60
—
tDH
—
tWP
55 (note 1)
—
Notes:
1. tWP(min) = 70ns for continuous write operation over 50 times.
206
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Write Cycle 2
MRS# = V , OE# = V , WAIT# = High-Z, UB# & LB# Controlled
IH
IH
tWC
Address
tWR
tCW
CS#
tAW
tBW
UB#, LB#
tAS
tWP
WE#
tDH
tDW
Data Valid
Data in
Data out
High-Z
High-Z
Figure 15. Timing Waveform of Write Cycle(2)
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
2. tCW is measured from the CS# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Table 14. Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tAS
Min
0
Max
—
Units
70
tCW
60
60
—
tWR
0
—
ns
tAW
—
ns
tDW
30
0
—
tBW
60
—
tDH
—
tWP
55 (note 1)
—
Notes:
1. tWP(min) = 70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
207
P r e l i m i n a r y
Write Cycle (Address Latch Type)
MRS# = V , OE# = V , WAIT# = High-Z, WE# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
tADV
ADV#
tAS(A)
tAH(A)
Address
Valid
tCSS(A)
tCW
CS#
t
tBW
AW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDW
tDH
Data in
Data Valid
Read Latency5
High-Z
High-Z
Data out
Figure 16. Timing Waveform Of Write Cycle (Address Latch Type)
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation. A write ends at
the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of
write.
2.
t
AW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW
.
3. tCW is measured from the CS# going low to the end of write.
4. tBW is measured from the UB# and LB# going low to the end of write.
5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 15. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tADV
Min
7
Max
—
Units
Symbol
tBW
Min
Max
—
Units
ns
60
tAS(A)
tAH(A)
tCSS(A)
tCW
0
—
tWP
55 (note 2)
—
7
—
tWLRL
tAS
1
0
—
clock
ns
10
60
60
—
—
—
tDW
30
0
—
ns
tAW
—
tDH
—
Notes:
1. Address Latch Type, WE# Controlled.
2. WP(min) = 70ns for continuous write operation over 50 times.
t
208
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Asynchronous Write Timing Waveform in Synchronous Mode
Write Cycle (Low ADV# Type)
MRS# = V , OE# = V , WAIT# = High-Z, WE# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
tWR
tCW
tAW
CS#
tBW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDH
tDW
Data in
Data Valid
Read Latency 5
High-Z
Data out
High-Z
Figure 17. Timing Waveform Of Write Cycle (Low ADV# Type)
Notes:
1. Low ADV# type write cycle - WE# Controlled.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
3. tCW is measured from the CS# going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
6. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 16. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Max
—
Units
70
clock
tCW
60
60
—
0
—
tAW
—
ns
tWR
0
—
ns
tBW
60
—
tDW
30
0
—
tWP
55 (note 2)
—
tDH
—
Notes:
1. Low ADV# Type, WE# Controlled.
2. tWP(min) = 70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
209
P r e l i m i n a r y
Write Cycle (Low ADV# Type)
MRS# = V , OE# = V , WAIT# = High-Z, UB# & LB# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
CS#
tWR
tCW
t
AW
tBW
UB#, LB#
WE#
tAS
tWLRL
tWP
tDH
tDW
Data Valid
Data in
Read Latency 5
High-Z
Data out
High-Z
Figure 18. Timing Waveform Of Write Cycle (Low ADV# Type)
Notes:
1. Low ADV# type write cycle - UB# and LB# Controlled.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
3. tCW is measured from the CS# going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
6. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 17. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Max
—
Units
70
clock
tCW
60
60
—
0
—
tAW
—
ns
tWR
0
—
ns
tBW
60
—
tDW
30
0
—
tWP
55 (note 2)
—
tDH
—
Notes:
1. Low ADV# type multiple write, UB#, LB# controlled.
2. tWP(min) = 70ns for continuous write operation over 50 times.
210
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Multiple Write Cycle (Low ADV# Type)
MRSE = V , OE# = V , WAIT# = High-Z, WE# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
Address
tWC
tWC
tWR
tWR
t
AW
tCW
t
AW
tCW
CS#
tBW
tBW
UB#, LB#
tWHP
tWP
tWP
WE#
tAS
tAS
tDH
tDH
tDW
tDW
Data in
Data Valid
DataValid
Data out
High-Z
High-Z
Figure 19. Timing Waveform Of Multiple Write Cycle (Low ADV# Type)
Notes:
1. Low ADV# type multiple write cycle.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
3. tCW is measured from the CS# going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
6. Clock input does not have any affect on the asynchronous multiple write operation if tWHP is shorter than the (Read Latency
- 1) clock duration.
7.
tWP(min) = 70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
211
P r e l i m i n a r y
Table 18. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
—
Min
5ns
0
Max
t
t
t
t
70
t
Latency-1 clock
—
WC
CW
AW
BW
WHP
60
60
—
t
—
—
—
—
AS
—
ns
t
0
WR
DW
ns
60
—
t
30
0
t
55 (note 2)
—
t
DH
WP
Notes:
1. Low ADV# type multiple write, WE# Controlled.
2.
tWP(min) = 70ns for continuous write operation over 50 times.
212
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to V -0.2V
CC
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x V
Output load (See Figure 84): CL = 30pF
CC
Vtt = 0.5 x V
DDQ
50
Ω
Dout
Z0=50
Ω
30pF
Figure 20. AC Output Load Circuit
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
213
P r e l i m i n a r y
Table 19. Synchronous AC Characteristics
Speed
Parameter List
Symbol
Units
Min
15
—
0
Max
200
2500
—
Clock Cycle Time
T
Burst Cycle Time
t
BC
Address Set-up Time to ADV# Falling (Burst)
Address Hold Time from ADV# Rising (Burst)
ADV# Setup Time
t
AS(B)
AH(B)
t
7
—
t
t
5
—
ADVS
ADVH
ADV# Hold Time
7
—
CS# Setup Time to Clock Rising (Burst)
Burst End to New ADV# Falling
Burst Stop to New ADV# Falling
CS# Low Hold Time from Clock
CS# High Pulse Width
t
5
—
CSS(B)
t
7
—
BEADV
Burst Operation
(Common)
ns
t
12
7
—
BSADV
t
—
CSLH
CSHP
ADHP
t
55
—
—
—
—
—
1
—
ADV# High Pulse Width
t
—
Chip Select to WAIT# Low
t
10
10
12
7
WL
ADV# Falling to WAIT# Low
Clock to WAIT# High
t
AWL
t
WH
Chip De-select to WAIT# High-Z
UB#, LB# Enable to End of Latency Clock
Output Enable to End of Latency Clock
UB#, LB# Valid to Low-Z Output
Output Enable to Low-Z Output
Latency Clock Rising Edge to Data Output
Output Hold
t
WZ
BEL
OEL
t
—
clock
clock
t
1
—
t
5
—
BLZ
OLZ
t
5
—
t
—
3
10
—
CD
Burst Read Operation
t
OH
ns
Burst End Clock to Output High-Z
Chip De-select to Output High-Z
Output Disable to Output High-Z
UB#, LB# Disable to Output High-Z
t
—
—
—
—
10
7
HZ
t
CHZ
OHZ
t
7
t
7
BHZ
WE# Set-up Time to Command Clock
WE# Hold Time from Command Clock
WE# High Pulse Width
tWES
tWEH
tWHP
tBS
5
5
5
5
5
7
7
5
3
—
—
—
—
—
—
—
—
—
UB#, LB# Set-up Time to Clock
UB#, LB# Hold Time from Clock
Byte Masking Set-up Time to Clock
Byte Masking Hold Time from Clock
Data Set-up Time to Clock
Burst Write Operation
tBH
ns
tBMS
tBMH
tDS
Data Hold Time from Clock
tDHC
Note: (VCC = 1.7~2.0V, TA=-40 to 85 °C, Maximum Main Clock Frequency = 66MHz.
214
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Operation Timing Waveform
Latency = 5, Burst Length = 4 (MRS# = V )
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
tADVH
tADVS
ADV#
tBEADV
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
Undefined
Data out
Data in
DQ0 DQ1 DQ2 DQ3
D0
D1
D2
D3
D0
Burst Command Clock
Burst Read End Clock
Burst Write End Clock
Figure 21. Timing Waveform Of Basic Burst Operation
Table 20. Burst Operation AC Characteristics
Speed
Speed
Symbol
Min
15
—
5
Max
200
2500
—
Units
Symbol
tAS(B)
Min
0
Max
Units
T
—
—
—
—
tBC
tAH(B)
7
ns
ns
tADVS
tADVH
tCSS(B)
tBEADV
5
7
—
7
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
215
P r e l i m i n a r y
Synchronous Burst Read Timing Waveform
Read Timings
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V , MRS# = V ). CS#
IH
IH
Toggling Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
t
CSHP
tCSS(B)
tBC
tBHZ
tBEL
LB#, UB#
OE#
tBLZ
tOHZ
tOEL
t
t
CHZ
t
OLZ
Latency 5
tCD
tOH
HZ
Undefined
Data out
WAIT#
DQ0 DQ1 DQ2 DQ3
tWZ
t
WL
t
WH
tWH
tWL
High-Z
Figure 22. Timing Waveform of Burst Read Cycle (1)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
216
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Table 21. Burst Read AC Characteristics
Speed
Speed
Symbol
tCSHP
tBEL
Min
5
Max
—
Units
Symbol
tOHZ
tBHZ
tCD
Min
—
—
—
3
Max
7
Units
ns
1
—
7
clock
ns
tOEL
1
—
10
—
10
12
7
tBLZ
5
—
tOH
ns
tOLZ
tHZ
5
—
tWL
—
—
—
—
—
10
7
tWH
tCHZ
tWZ
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V , MRS# = V ).
IH
IH
CS# Low Holding Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tCD
tOH
tHZ
Undefined
Data out
WAIT#
DQ0 DQ1 DQ2 DQ3
tAWL
tWH
t
WL
t
WH
High-Z
Figure 23. Timing Waveform of Burst Read Cycle (2)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
5. Burst Cycle Time (tBC) should not be over 2.5µs.
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
217
P r e l i m i n a r y
Table 22. Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
tBLZ
tOLZ
tHZ
1
—
tOH
5
—
tWL
—
—
—
10
10
12
ns
5
—
ns
tAWL
tWH
—
10
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V , MRS# = V ).
IH
IH
Last data sustaining
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
t
ADVH
ADVS
t
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
t
CSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
tOH
tCD
Latency 5
Undefined
Data out
WAIT#
DQ0 DQ1 DQ2 DQ3
t
WL
t
WH
High-Z
Figure 24. Timing Waveform of Burst Read Cycle (3)
Notes:
1. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge).
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. Burst Cycle Time (tBC) should not be over 2.5µs.
218
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Table 23. Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
1
—
tOH
ns
tBLZ
5
—
tWL
—
—
10
12
ns
tOLZ
5
—
tAWL
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
219
P r e l i m i n a r y
Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V , MRS# = V ).
IH
IH
CS# Toggling Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
tADVH
tADVS
ADV#
tBEADV
tCSHP
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
tBC
tCSS(B)
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
tWH
Latency 5
tWH
Data in
WAIT#
D0
D1
D2
D3
D0
tWZ
tWL
tWL
High-Z
Figure 25. Timing Waveform of Burst Write Cycle (1)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
4. D2 is masked by UB# and LB#.
5. Burst Cycle Time (tBC) should not be over 2.5µs.
220
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Table 24. Burst Write AC Characteristics
Speed
Speed
Symbol
tCSHP
tBS
Min
5
Max
—
Units
Symbol
tWHP
tDS
Min
5
Max
—
Units
5
—
5
—
tBH
5
—
tDHC
tWL
3
—
ns
tBMS
tBMH
tWES
tWEH
7
—
ns
—
—
—
10
12
7
7
—
tWH
5
—
tWZ
5
—
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
221
P r e l i m i n a r y
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V , MRS# = V ).
IH
IH
CS# Low Holding Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
ADV
t
ADVH
ADVS
t
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
t
CSS(B)
tBC
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
Latency 5
Data in
WAIT#
D0
D1
D2
D3
D0
tWL
tAWL
tWH
tWH
High-Z
Figure 26. Timing Waveform of Burst Write Cycle (2)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
4. D2 is masked by UB# and LB#.
5. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
6. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 25. Burst Write AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
5
Max
—
Min
5
Max
—
t
t
t
WHP
BS
5
—
t
5
—
BH
DS
t
7
—
t
3
—
BMS
BMH
WES
WEH
DHC
ns
ns
t
t
7
—
t
—
—
—
10
10
12
WL
5
—
t
AWL
t
5
—
t
WH
222
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= V , MRS# = V ).
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
t
ADVH
ADVS
t
ADV#
tBSADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSHP
tCSS(B)
tCSLH
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
tOH
tCHZ
tCD
Latency 5
Undefined
Data
DQ0
DQ1
tWZ
t
WL
tWL
tWH
High-Z
High-Z
WAIT#
Figure 27. Timing Waveform of Burst Read Stop by CS#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Table 26. Burst Read Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
—
3
Max
10
—
t
t
BSADV
CD
t
t
—
ns
t
CSLH
CSHP
OH
5
—
t
—
—
—
—
7
CHZ
ns
t
1
—
t
10
12
7
BEL
OEL
BLZ
WL
WH
WZ
clock
ns
t
t
1
—
t
5
—
t
t
5
—
OLZ
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
223
P r e l i m i n a r y
Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= V , MRS# = V ).
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
t
ADVH
ADVS
t
ADV#
tBSADV
tAH(B)
tAS(B)
Don’t Care
Address
CS#
Valid
Valid
tCSHP
t
CSS(B)
tCSLH
tBS
tBH
LB#, UB#
WE#
tWHP
t
WEH
t
WES
tDS
tDHC
Latency 5
Latency 5
Data in
WAIT#
D0
D1
D0
D1
D2
tWZ
t
WL
t
WL
tWH
tWH
High-Z
High-Z
Figure 28. Timing Waveform of Burst Write Stop by CS#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Table 27. Burst Write Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
5
Max
—
t
t
WHP
BSADV
t
t
—
t
5
—
CSLH
CSHP
DS
5
—
t
3
—
DHC
ns
t
5
—
t
—
—
—
10
12
7
ns
BS
WL
WH
WZ
t
5
—
t
t
BH
t
5
—
WES
WEH
t
5
—
224
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= V , MRS# = V ).
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
T
CLK
t
ADVH
ADVS
t
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tOHZ
tOLZ
tOH
tCD
tHZ
High-Z
Undefined
Data out
WAIT#
DQ0 DQ1
DQ1 DQ2 DQ3
tWZ
t
WL
t
WH
High-Z
Figure 29. Timing Waveform of Burst Read Suspend Cycle (1)
Notes:
1. If the clock input is halted during burst read operation, the data output will be suspended. During the burst read suspend
period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data will be output first.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during suspend
period, the previous data will be sustained.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 28. Burst Read Suspend AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
1
Max
—
Min
—
Max
10
7
t
t
HZ
BEL
OEL
BLZ
OLZ
clock
t
t
1
—
t
—
OHZ
5
—
t
—
10
12
7
WL
WH
WZ
ns
t
5
—
t
t
—
ns
t
—
3
10
—
—
CD
OH
t
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
225
P r e l i m i n a r y
Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4, WP = Low enable (MRS# = V ).
IH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tADV
tAH(A)
tBEADV
tAS(A)
tAH(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tAW
tCW
tBC
tCSS(A)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
WAIT#
tWL
tWZ
tWH
High-Z
High-Z
Read Latency 5
Figure 30. Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 29. Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
226
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid Adderss
tWR
tAW
tCW
tCSS(B)
tBC
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
WAIT#
tWL
tWZ
tWH
High-Z
High-Z
Read Latency 5
Figure 31. Synchronous Burst Read to Asynchronous Write (Low ADV# Type)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 30. Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
227
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADVS
ADV#
tADV
tAH(A)
tAS(A)
tAS(B)
Address
CS#
Don’t Care
tAW
tCW
Don’t Care
tBC
Valid
Valid
tCSS(A)
tCSS(B)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
Read Latency 5
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
WAIT#
Figure 32. Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 31. Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
WLRL
228
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADtHAPDVS
ADV#
Address
CS#
tAS(B)
tWC
Valid
Valid
Don’t Care
tBC
tAW
tCW
tWR
tCSS(B)
tWLRL
tWP
tBW
WE#
OE#
tAS
tOEL
tBEL
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
Read Latency 5
WAIT#
Figure 33. Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 32. Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
t
—
ns
WLRL
ADHP
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
229
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBEL
tBS
tBH
LB#, UB#
Data in
tDS
Latency 5
tDHC
tWZ
D0 D1 D2 D3
High-Z
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tWZ
tHZ
High-Z
Data out
WAIT#
tWH
tWL
tWH
tWL
High-Z
Figure 34. Synchronous Burst Read to Synchronous Burst Write Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 33. Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
230
1.8V pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBS
tBH
tBEL
LB#, UB#
tDS
Latency 5
tDHC
D0 D1 D2
D3
High-Z
Data in
Data out
WAIT#
Latency 5
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
High-Z
tWL
tWH
tWZ
tWH
tWL
High-Z
Figure 35. Synchronous Burst Write to Synchronous Burst Read Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 34. Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
July 30, 2004 pSRAM_Type04_17A0
1.8V pSRAM Type 4
231
P r e l i m i n a r y
CosmoRAM
32Mbit (2M word x 16-bit)
64Mbit (4M word x 16-bit)
Features
Asynchronous SRAM Interface
Fast Access Time
— t = t = 70ns max
CE
AA
8 words Page Access Capability
— t = 20ns max
PAA
Low Voltage Operating Condition
— V = +1.65V to +1.95V (32M)
DD
— +1.70V to +1.95V (64M)
Wide Operating Temperature
— TA = -30°C to +85°C
Byte Control by LB# and UB#
Low Power Consumption
— I
— I
= 30mA max (32M), TBDmA max (64M)
= 80mA max (32M), TBDmA max (64M)
DDA1
DDS1
Various Power Down mode
— Sleep, 4M-bit Partial or 8M-bit Partial (32M)
— Sleep, 8M-bit Partial or 16M-bit Partial (64M)
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
233
P r e l i m i n a r y
Pin Description (32M)
Pin Name
A21 to A0
CE1#
CE2
Description
Address Input: A20 to A0 for 32M, A21 to A0 for 64M
Chip Enable (Low Active)
Chip Enable (High Active)
Write Enable (Low Active)
Output Enable (Low Active)
Upper Byte Control (Low Active)
Lower Byte Control (Low Active)
Clock Input
WE#
OE#
UB#
LB#
CLK
ADV#
WAIT#
Address Valid Input (Low Active)
Wait Signal Output
DQ16 9
-
Upper Byte Data Input/Output
Lower Byte Data Input/Output
Power Supply
DQ8-1
VDD
VSS
Ground
234
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Functional Description
Asynchronous Operation (Page Mode)
Mode
Standby (Deselect)
Output Disable (Note 1)
Output Disable (No Read)
Read (Upper Byte)
Read (Lower Byte)
Read (Word)
CE2 CE1# CLK
H
ADV#
WE#
OE#
X
LB# UB#
A
DQ
DQ
16-9
WAIT#
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
21-0
8-1
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
H
Note 5
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
X
H
H
L
H
L
High-Z
High-Z
High-Z
Output Valid
High-Z
H
L
H
L
Output Valid
L
Output Valid Output Valid
L
(Note 3)
Page Read
L/H
H
H
L
L/H
H
L
Note 6
Invalid
Note 6
Invalid
No Write
Write (Upper Byte)
Write (Lower Byte)
Write (Word)
Invalid
Input Valid
Invalid
H
L
(Note 4)
H
L
Input Valid
Input Valid
High-Z
L
Input Valid
High-Z
Power Down (Note 2)
X
X
X
X
X
X
Legend:L = V , H = V , X can be either V or V , High-Z = High Impedance.
IL
IH
IL
IH
Notes:
1. Should not be kept at this logic condition longer than 1µs.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of Partial Size. Refer to the "Power Down" section in the Functional Description for details.
3. “L” for address pass through and “H” for address latch on the rising edge of ADV#.
4. OE# can be VIL during Write operation if the following conditions are satisfied:
(1) Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is
satisfied.
(2) OE# stays VIL during Write cycle
5. Can be either VIL or VIH but must be valid before Read or Write.
6. Output is either Valid or High-Z depending on the level of UB# and LB# input.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
235
P r e l i m i n a r y
Functional Description
Synchronous Operation (Burst Mode)
Mode
CE2 CE1#
CLK
ADV#
WE#
OE#
LB#
UB#
A
DQ
DQ
16-9
WAIT#
21-0
8-1
Standby (Deselect)
H
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
Start Address
Latch
(Note 1)
VE
(Note 3)
X
X
Valid
(Note 7)
High-Z
(Note 8)
High-Z
(Note 8) (Note 11)
High-Z
PELP
(Note 4) (Note 4)
Advance Burst
Read to Next
Address (Note 1)
Output
Valid
(Note 9)
Output
Output
Valid
(Note 9)
VE
(Note 3)
L
Valid
H
Burst Read
Suspend
(Note 1)
VE
(Note 3)
High
High-Z
L
H
High-Z
(Note 12)
H
X
X
Input
Advance Burst
Write to Next
Address (Note 1)
(Note 6) (Note 6)
Input
Valid
(Note 10)
VE
(Note 3)
L
(Note 5)
H
Valid
(Note
10)
High
(Note 13)
H
X
Burst Write
Suspend (Note 1)
VE
(Note 3)
H
Iput
Invalid
Iput
Invalid
High
(Note 12)
(Note 5)
Terminate Burst
Read
VE
VE
X
X
X
H
X
X
X
H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Terminate Burst
Write
Power Down
(Note 2)
L
X
X
X
X
X
Legend:L = V , H = V , X can be either V or V , VE = Valid Edge, PELP = Positive Edge of Low Pulse, High-
IL
IH
IL
IH
Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than the specified time of 8µs for 32M and 4µs for 64M.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of Partial Size. Refer to the "Power Down" section for details.F
3. Valid clock edge shall be set on either positive or negative edge through CR Set. CLK must be started and stable prior to
memory access.
4. Can be either VIL or VIH except for the case the both of OE# and WE# are VIL. It is prohibited to bring the both of OE# and
WE# to VIL
.
5. When device is operating in “WE# Single Clock Pulse Control” mode, WE# is don’t care once write operation is determined by
WE# Low Pulse at the beginning of write access together with address latching. Write suspend feature is not supported in
“WE# Single Clock Pulse Control” mode.
6. Can be either VIL or VIH but must be valid before Read or Write is determined. And once UB# and LB# inputs are
determined, they must not be changed until the end of burst.
7. Once valid address is determined, input address must not be changed during ADV#=L.
8. If OE#=L, output is either Invalid or High-Z depending on the level of UB# and LB# input. If WE#=L, Input is Invalid. If
OE#=WE#=H, output is High-Z.
9. Output is either Valid or High-Z depending on the level of UB# and LB# input.
10. Input is either Valid or Invalid depending on the level of UB# and LB# input.
11. Output is either High-Z or Invalid depending on the level of OE# and WE# input.
12. Keep the level from previous cycle except for suspending on last data. Refer to “WAIT# Output Function” for details.
13. WAIT# output is driven in High level during write operation.
236
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
State Diagrams
Initial/Standby State
Asynchronous Operation
(Page Mode)
Power Up
Synchronous Operation
(Burst Mode)
Common State
CR Set
Pause Time
Power
Down
Power
Down
@M=1
@M=0
CE2=H
CE2=L
CE2=L
CE2=H
@RP=1
Standby
Standby
CE2=H
@RP=0
Figure 1. Initial Standby State Diagram
(64M Only)
Asynchronous Operation State
CE2 = CE1# = H
Standby
CE1# = L
CE1# = L &
WE# = L
CE1# = H
CE1# = L &
OE# = L
CE1# = H
Output
Disable
CE1# = H
OE# = L
WE# = H
WE# = L
OE# = H
Address Change
or Byte Control
Read
Write
Byte Control
Byte Control @ OE# = L
Figure 2. Asynchronous Operation State Diagram
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
237
P r e l i m i n a r y
Synchronous Operation State
CE2 = CE1# = H
Standby
CE1# = H
CE1# = H
CE1# = H
Read
CE1# = H
Write
Suspend
Suspend
OE# = H
WE# = H
CE1# = L
CE1# = L
OE# = L
ADV# Low Pulse
& OE# = L
ADV# Low Pulse
& WE# = L
WE# = L
ADV# Low Pulse
ADV# Low Pulse
Read
Write
ADV# Low Pulse
(@BL = 8 or 16, and after burst
operation is completed)
Figure 3. Synchronous Operation Diagram
Notes:
1. Assumes all the parameters specified in the "AC Characteristics" section are satisfied. Refer to the "Functional Description"
section, "AC Characteristics" section, and the "Timing Diagrams" section for details. RP (Reset to Page) mode is available
only for 64M.
Functional Description
This device supports asynchronous page read & normal write operation and syn-
chronous burst read & burst write operation for faster memory access and
features three kinds of power down modes for power saving as a user config-
urable option.
Power-up
It is required to follow the power-up timing to start executing proper device op-
eration. Refer to POWER-UP Timing. After Power-up, the device defaults to
asynchronous page read & normal write operation mode with sleep power down
feature.
Configuration Register
The Configuration Register (CR) is used to configure the type of device function
among optional features. Each selection of features is set through CR Set se-
quence after Power-up. If CR Set sequence is not performed after power-up, the
device is configured for asynchronous operation with sleep power down feature
as default configuration.
CR Set Sequence
The CR Set requires total 6 read/write operations with unique address. Between
each read/write operation requires the device to be in standby mode. The follow-
ing table shows the detail sequence.
Cycle #
1st
Operation
Read
Address
3FFFFFh (MSB)
3FFFFFh
Data
Read Data (RDa)
RDa
2nd
Write
238
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Cycle #
3rd
Operation
Write
Address
3FFFFFh
Data
RDa
4th
Write
3FFFFFh
X
5th
Write
3FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
The first cycle is to read from most significant address (MSB).
The second and third cycle are to write to MSB. If the second or third cycle is writ-
ten into the different address, the CR Set is cancelled and the data written by the
second or third cycle is valid as a normal write operation. It is recommended to
write back the data (RDa) read by first cycle to MSB in order to secure the data.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is
don’t-care. If the forth or fifth cycle is written into different address, the CR Set
is also cancelled but write data may not be written as normal write operation.
The last cycle is to read from specific address key for mode selection. And read
data (RDb) is invalid.
Once this CR Set sequence is performed from an initial CR set to the other new
CR set, the written data stored in memory cell array may be lost. So, CR Set se-
quence should be performed prior to regular read/write operation if necessary to
change from default configuration.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
239
P r e l i m i n a r y
Address Key
The address key has the following format.
Description
Note
Address
Pin
Register
Name
Function
Key
32M
64M
Unused bits muse be 1
16M Partial
A21
—
—
1
—
1
00
01
10
11
8M Partial
4M Partial
8M Partial
A20-A19
PS
Partial Size
Reserved for future use
Sleep [Default]
2
2
000 to 001 Reserved for future use
010
011
8 words
A18-A16
BL
M
Burst Length
16 words
100 to 110 Reserved for future use
2
111
0
Continuous
Synchronous Mode (Burst Read / Write)
3
4
2
A15
Mode
1
Asynchronous Mode [Default] (Page Read / Normal Write)
000
001
010
011
100
Reserved for future use
3 clocks
4 clocks
A14-A12
RL
Read Latency
5 clocks
Reserved for future use
6 clocks
101 to 111 Reserved for future use
2
2
0
1
0
1
0
1
0
1
Reserved for future use
Sequential
Burst
A11
A10
A9
BS
SW
VE
Sequence
Burst Read & Burst Write
Burst Read & Single Write
Falling Clock Edge
Single Write
5
Valid Clock
Edge
Rising Clock Edge
Reset to Page mode
6
5
1
A8
RP
Reset to Page
Unused bits must be 1
Remain the previous mode
WE# Single Clock Pulse Control without Write Suspend
Function
0
A7
WC
—
Write Control
—
1
1
WE# Level Control with Write Suspend Function
Unused bits muse be 1
A6-A0
Notes:
1. A21 and A6 to A0 must be all “1” in any case.
2. It is prohibited to apply this key.
3. If M=0, all the registers must be set with appropriate Key input at the same time.
4. If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must be “1”.
5. Burst Read & Single Write is not supported at WE# Single Clock Pulse Control.
6. Effective only when PS=11. RP (Reset to Page) mode is available only for 64M.
240
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the
device in power down mode and maintains low power idle state as long as CE2 is
kept Low. CE2 High resumes the device from power down mode. These devices
have three power down mode. These can be programmed by series of read/write
operations. Each mode has following features.
32M
Data Retention Size
No
64M
Data Retention Size
No
Mode
Retention Address
N/A
Mode
Retention Address
N/A
Sleep (default)
4M Partial
Sleep (default)
8M Partial
4M bit
000000h to 03FFFFh
000000h to 07FFFFh
8M bit
000000h to 07FFFFh
000000h to 0FFFFFh
8M Partial
8M bit
16M Partial
16M bit
The default state is Sleep and it is the lowest power consumption but all data will
be lost once CE2 is brought to Low for Power Down. It is not required to program
to Sleep mode after power-up.
64M supports Reset to Page (RP) mode. When RP=0, Power Down comprehends
a function to reset the device to default configuration (asynchronous mode). After
resuming from power down mode, the device is back in default configurations.
This is effective only when PS is set on Sleep mode. When Partial mode is se-
lected, RP=0 is not effective.
Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that syn-
chronized to microcontroller or system bus frequency. Configuration Register Set
is required to perform burst read & write operation after power-up. Once CR Set
sequence is performed to select synchronous burst mode, the device is config-
ured to synchronous burst read/write operation mode with corresponding RL and
BL that is set through CR Set sequence together with operation mode. In order
to perform synchronous burst read & write operation, it is required to control new
signals, CLK, ADV# and WAIT# that Low Power SRAMs don’t have.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
241
P r e l i m i n a r y
CLK
ADDRESS
Valid
ADV#
CE1#
OE#
High
WE#
DQ
RL
High-Z
High-Z
Q1
QBL
Q2
BL
WAIT#
Figure 4. Burst Read Operation
CLK
ADDRESS
Valid
ADV#
CE1#
High
OE#
WE#
DQ
RL-1
High-Z
High-Z
D1
DBL
D2
BL
WAIT#
Figure 5. Burst Write Operation
CLK Input Function
The CLK is input signal to synchronize memory to microcontroller or system bus
frequency during synchronous burst read & write operation. The CLK input incre-
ments device internal address counter and the valid edge of CLK is referred for
latency counts from address latch, burst write data latch, and burst read data out.
During synchronous operation mode, CLK input must be supplied except for
standby state and power down state. CLK is don’t care during asynchronous
operation.
242
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
ADV# Input Function
The ADV# is input signal to indicate valid address presence on address inputs. It
is applicable to synchronous operation as well as asynchronous operation. ADV#
input is active during CE1#=L and CE1#=H disables ADV# input. All addresses
are determined on the positive edge of ADV#.
During synchronous burst read/write operation, ADV#=H disables all address in-
puts. Once ADV# is brought to High after valid address latch, it is inhibited to
bring ADV# Low until the end of burst or until burst operation is terminated.
ADV# Low pulse is mandatory for synchronous burst read/write operation mode
to latch the valid address input.
During asynchronous operation, ADV#=H also disables all address inputs. ADV#
can be tied to Low during asynchronous operation and it is not necessary to con-
trol ADV# to High.
WAIT# Output Function
The WAIT# is output signal to indicate data bus status when the device is oper-
ating in synchronous burst mode.
During burst read operation, WAIT# output is enabled after specified time dura-
tion from OE#=L or CE1#=L whichever occurs last. WAIT# output Low indicates
data out at next clock cycle is invalid, and WAIT# output becomes High one clock
cycle prior to valid data out. During OE# read suspend, WAIT# output doesn’t
indicate data bus status but carries the same level from previous clock cycle (kept
High) except for read suspend on the final data output. If final read data out is
suspended, WAIT# output become high impedance after specified time duration
from OE#=H.
In case of continuous burst read operation of 32M, an additional output delay may
occur when a burst sequence crosses it’s device-row boundary. The WAIT# out-
put indicates this delay. Refer to the "Burst Length" section for the additional
delay cycles in details.
During burst write operation, WAIT# output is enabled to High level after speci-
fied time duration from WE#=L or CE1#=L whichever occurs last and kept High
for entire write cycles including WE# write suspend. The actual write data latch-
ing starts on the appropriate clock edge with respect to Valid Clock Edge, Read
Latency and Burst Length. During WE# write suspend, WAIT# output doesn’t in-
dicate data bus status but carries the same level from previous clock cycle (kept
High) except for write suspend on the final data input. If final write data in is sus-
pended, WAIT# output become high impedance after specified time duration
from WE#=H.
The burst write operation of 32M and the both burst read/write operation of 64M
are always started after fixed latency with respect to Read Latency set in CR.
When the device is operating in asynchronous mode, WAIT# output is always in
High Impedance.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
243
P r e l i m i n a r y
Latency
Read Latency (RL) is the number of clock cycles between the address being
latched and first read data becoming available during synchronous burst read op-
eration. It is set through CR Set sequence after power-up. Once specific RL is set
through CR Set sequence, write latency, that is the number of clock cycles be-
tween address being latched and first write data being latched, is automatically
set to RL-1.The burst operation is always started after fixed latency with respect
to Read Latency set in CR. RL=6 is available only for 64M.
CLK
0
3
4
5
6
1
2
ADDRESS
ADV#
Valid
CE1#
OE# or WE#
RL=3
DQ [Out]
WAIT#
Q1
Q2
Q3
Q4
Q5
D5
High-Z
DQ [In]
WAIT#
D1
D2
D3
D4
D5
High-Z
RL=4
DQ [Out]
WAIT#
Q1
D2
Q2
D3
Q3
D4
Q4
D5
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=5
DQ [Out]
WAIT#
Q1
D2
Q2
D3
Q3
D4
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=6
DQ [Out]
WAIT#
Q1
D2
Q2
D3
High-Z
DQ [In]
WAIT#
D1
High-Z
Figure 6. Read Latency Diagram
244
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Address Latch by ADV#
The ADV# indicates valid address presence on address inputs. During synchro-
nous burst read/write operation mode, all the address are determined on the
positive edge of ADV# when CE1#=L. The specified minimum value of ADV#=L
setup time and hold time against valid edge of clock where RL count begin must
be satisfied for appropriate RL counts. Valid address must be determined with
specified setup time against either the negative edge of ADV# or negative edge
of CE1# whichever comes late. And the determined valid address must not be
changed during ADV#=L period.
Burst Length
Burst Length is the number of word to be read or write during synchronous burst
read/write operation as the result of a single address latch cycle. It can be set on
8, 16 words boundary or continuous for entire address through CR Set sequence.
The burst type is sequential that is incremental decoding scheme within a bound-
ary address. Starting from initial address being latched, device internal address
counter assign +1 to the previous address until reaching the end of boundary ad-
dress and then wrap round to least significant address (=0). After completing
read data out or write data latch for the set burst length, operation automatically
ended except for continuous burst length. When continuous burst length is set,
read/write is endless unless it is terminated by the positive edge of CE1#.
During continuous burst read of 32M, an additional output delay may occur when
a burst sequence cross it’s device-row boundary. This is the case when A0 to A6
of starting address is either 7Dh, 7Eh, or 7Fh as shown in the following table. The
WAIT# signal indicates this delay. The 64M device has no additional output delay.
Read Address Sequence
Start Address
(A6-A0)
00h
01h
02h
03h
...
BL = 8
BL = 16
Continuous
00-01-02-03-04-...
01-02-03-04-05-...
02-03-04-05-06-...
03-04-05-06-07-...
...
00-01-02-...-06-07
01-02-03-...-07-00
02-03-...-07-00-01
03-...-07-00-01-02
...
00-01-02-...-0E-0F
01-02-03-...-0F-00
02-03-...-0F-00-01
03-...-0F-00-01-02
...
7Ch
7Dh
7Eh
7Fh
7C-...-7F-78-...-7B
7D-7E-7F-78-...-7C
7E-7F-78-79-...-7D
7F-78-79-7A-...-7E
7C-...-7F-70-...-7B
7D-7E-7F-70-...-7C
7E-7F-70-71-...-7D
7F-70-71-72-...-7E
7C-7D-7E-7F-80-81-...
7D-7E-7F-WAIT-80-81-...
7E-7F-WAIT-WAIT-80-81-...
7F-WAIT WAIT
-
-WAIT-80-81
Note: Read address in Hexadecimal.
Single Write
Single Write is synchronous write operation with Burst Length =1. The device can
be configured either to “Burst Read & Single Write” or to “Burst Read & Burst
Write” through CR set sequence. Once the device is configured to “Burst Read &
Single Write” mode, the burst length for synchronous write operation is always
fixed 1 regardless of BL values set in CR, while burst length for read is in accor-
dance with BL values set in CR.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
245
P r e l i m i n a r y
Write Control
The device has two types of WE# signal control method, “WE# Level Control” and
“WE# Single Clock Pulse Control”, for synchronous write operation. It is config-
ured through CR set sequence.
CLK
0
3
4
5
6
1
2
ADDRESS
Valid
ADV#
CE1#
RL=5
WE# Level Control
WE#
tWLD
DQ [In]
WAIT#
D1
D2
D3
D4
tWLTH
High-Z
WE# Single Clock Pulse Control
tWSCK
WE#
tCKWH
DQ [In]
D1
D2
D3
D4
tCLTH
tWLTH
WAIT#
High-Z
Figure 7. Write Controls
Burst Read Suspend
Burst read operation can be suspended by OE# High pulse. During burst read op-
eration, OE# brought to High suspends burst read operation. Once OE# is
brought to High with the specified set up time against clock where the data being
suspended, the device internal counter is suspended, and the data output be-
come high impedance after specified time duration. It is inhibited to suspend the
first data out at the beginning of burst read.
OE# brought to Low resumes burst read operation. Once OE# is brought to Low,
data output become valid after specified time duration, and internal address
counter is reactivated. The last data out being suspended as the result of OE#=H
and first data out as the result of OE#=L are from the same address.
In order to guarantee to output last data before suspension and first data after
resumption, the specified minimum value of OE#=L hold time and setup time
against clock edge must be satisfied respectively.
246
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
CLK
OE#
t
CKOH
t
OSCK
t
CKOH
tOSCK
t
AC
t
OHZ
t
AC
t
AC
t
AC
Q
1
Q2
Q3
DQ
Q2
Q
4
tCKQX
t
OLZ
t
CKQX
t
CKQX
t
CKTV
WAIT#
Figure 8. Burst Read Suspend Diagram
Burst Write Suspend
Burst write operation can be suspended by WE# High pulse. During burst write
operation, WE# brought to High suspends burst write operation. Once WE# is
brought to High with the specified set up time against clock where the data being
suspended, device internal counter is suspended, data input is ignored. It is in-
hibited to suspend the first data input at the beginning of burst write.
WE# brought to Low resumes burst write operation. Once WE# is brought to Low,
data input become valid after specified time duration, and internal address
counter is reactivated. The write address of the cycle where data being sus-
pended and the first write address as the result of WE#=L are the same address.
In order to guarantee to latch the last data input before suspension and first data
input after resumption, the specified minimum value of WE#=L hold time and
setup time against clock edge must be satisfied respectively. Burst write suspend
function is available when the device is operating in WE# level controlled burst
write only.
CLK
tCKWH
t
WSCK
t
CKWH
t
WSCK
WE#
tDSCK
tDSCK
tDSCK
t
DSCK
DQ
D1
D2
D2
D3
D4
t
DHCK
t
DHCK
t
DHCK
High
Figure 9. Burst Write Suspend Diagram
WAIT#
Burst Read Termination
Burst read operation can be terminated by CE1# brought to High. If BL is set on
Continuous, burst read operation is continued endless unless terminated by
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
247
P r e l i m i n a r y
CE1#=H. It is inhibited to terminate burst read before first data out is completed.
In order to guarantee last data output, the specified minimum value of CE1#=L
hold time from clock edge must be satisfied. After termination, the specified min-
imum recovery time is required to start new access.
CLK
ADDRESS
Valid
ADV#
CE1#
tTRB
tCKCLH
tCKOH
tCHZ
tOHZ
OE#
WAIT#
DQ
High-Z
tCHTZ
tCKQX
tAC
Q1
Q2
Figure 10. Burst Read Termination Diagram
Burst Write Termination
Burst write operation can be terminated by CE1# brought to High. If BL is set on
Continuous, burst write operation is continued endless unless terminated by
CE1#=H. It is inhibited to terminate burst write before first data in is completed.
In order to guarantee last write data being latched, the specified minimum values
of CE1#=L hold time from clock edge must be satisfied. After termination, the
specified minimum recovery time is required to start new access.
CLK
ADDRESS
Valid
ADV#
CE1#
tTRB
tCKCLH
tCKWH
tCHCK
WE#
WAIT#
DQ
tCHTZ
High-Z
tDSCK
tDSCK
D1
D2
tDHCK
tDHCK
Figure 11. Burst Write Termination Diagram
248
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Absolute Maximum Ratings
Item
Voltage of VDD Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Storage temperature
Symbol
VDD
Value
Unit
V
-0.5 to +3.6
-0.5 to +3.6
±50
VIN, VOUT
IOUT
V
mA
°C
TSTG
-55 to +125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions (See Warning Below)
32M
64M
Parameter
Symbol
VDD
VSS
VIH
Min
1.65
0
Max
1.95
Min
1.7
Max
1.95
Unit
V
Supply Voltage
0
0
0
V
High Level Input Voltage (Note 1)
High Level Input Voltage (Note 2)
Ambient Temperature
VDD x 0.8
-0.3
VDD+0.2
VDD x 0.2
85
VDD x 0.8
-0.3
VDD+0.2
VDD x 0.2
85
V
VIL
V
TA
-30
-30
°C
Notes:
1. Maximum DC voltage on input and I/O pins are VDD+0.2V. During voltage transitions, inputs may positive overshoot to
VDD+1.0V for periods of up to 5 ns.
2. Minimum DC voltage on input or I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot VSS to -1.0V
for periods of up to 5ns.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de-
vice’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Package Pin Capacitance
Test conditions: T = 25°C, f = 1.0 MHz
A
Symbol
Description
Te st Se tup
VIN = 0V
VIN = 0V
VIO = 0V
Typ
—
Max
5
Unit
pF
CIN1
CIN2
CIO
Address Input Capacitance
Control Input Capacitance
Data Input/Output Capacitance
—
5
pF
—
8
pF
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
249
P r e l i m i n a r y
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
32M
64M
Parameter
Symbol
Test Conditions
Unit
Min.
Max.
Min.
Max.
Input Leakage
Current
I
V
V
V
= V to V
DD
-1.0
+1.0
-1.0
+1.0
µA
µA
V
LI
IN
SS
Output Leakage
Current
I
= V to V , Output Disable
-1.0
2.4
—
+1.0
—
-1.0
2.4
+1.0
—
LO
OUT
SS
DD
Output High Voltage
Level
V
= V (min), I
= –0.5mA
OH
DD
DD
OH
Output Low Voltage
Level
V
I
= 1mA
OL
0.4
—
—
0.4
V
OL
I
I
I
SLEEP
—
—
—
10
40
50
TBD
µA
µA
µA
DDPS
DDP4
DDP8
4M Partial
8M Partial
16M Partial
N/A
V
V
= V
max.,
DD
DD
IN
V
Power Down
DD
= V or V
,
IH
IL
Current
CE2 ≤ 0.2V
—
—
TBD
TBD
I
N/A
DDP16
V
V
= V
max.,
DD
DD
IN
I
(including CLK)= V or V ,
CE1# = CE2 = V
—
1.5
—
TBD
mA
DDS
IH
IL
IH
V
V
V
= V
max.,
DD
TA ≤ +85°C
TA ≤ +40°C
—
—
80
80
—
—
TBD
TBD
µA
µA
DD
IN
IN
V
Standby
(including CLK) ≤ 0.2V or
(including CLK) ≥ V
DD
I
DDS1
Current
– 0.2V,
DD
CE1# = CE2 ≥ V
– 0.2V
DD
V
V
= V
max., t =min.
DD CK
DD
IN
≤ 0.2V or V ≥ V
– 0.2V,
—
200
—
TBD
µA
IN
DD
– 0.2V
CE1# = CE2 ≥ V
DD
t
t
/ t
=
WC
RC
I
I
—
—
30
3
—
—
35
5
mA
mA
DDA1
V
V
= V
max.,
DD
DD
IN
minimum
= V or V
,
IH
IL
V
V
Active Current
Page Read
DD
DD
CE1# = V and CE2= V
,
IH
IL
/ t
1µs
=
WC
RC
I
=0mA
OUT
DDA2
V
= V
max., V = V or V
,
,
DD
DD
IN
IH
IH
IL
I
CE1# = V and CE2= V ,
—
—
10
15
—
—
TBD
TBD
mA
mA
DDA3
DDA4
IL
Current
I
=0mA, t
= min.
PRC
OUT
V
= V
max., V = V or V
DD IN IH
IL IH
DD
IL
V
Burst Access
CE1# = V and CE2= V ,
DD
I
Current
t
I
= t min., BL = Continuous,
=0mA
CK CK
OUT
Notes:
1. All voltages are referenced to VSS
2. DC Characteristics are measured after following POWER-UP timing.
3. OUT depends on the output load conditions.
.
I
250
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
32M
64M
Parameter
Symbol
tRC
Min.
70
—
Max.
1000
70
40
70
70
30
20
1000
—
Min.
70
—
Max.
1000
70
40
70
70
30
20
1000
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read Cycle Time
CE1# Access Time
OE# Access Time
1, 2
tCE
3
tOE
—
—
3
Address Access Time
tAA
—
—
3, 5
ADV# Access Time
tAV
3
LB# / UB# Access Time
tBA
—
—
20
5
—
—
20
5
3
Page Address Access Time
Page Read Cycle Time
tPAA
tPRC
tOH
3,6
1, 6, 7
Output Data Hold Time
3
4
4
4
3
3
3
CE1# Low to Output Low-Z
OE# Low to Output Low-Z
LB# / UB# Low to Output Low-Z
CE1# High to Output High-Z
OE# High to Output High-Z
LB# / UB# High to Output High-Z
Address Setup Time to CE1# Low
Address Setup Time to OE# Low
ADV# Low Pulse Width
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tASC
tASO
tVPL
tVPH
tASV
tAHV
tAX
5
—
5
—
10
0
—
0
—
—
0
—
—
—
—
–5
10
10
15
5
20
20
20
—
—
—
—
–5
10
10
15
5
20
20
20
—
—
—
—
—
8
8
ADV# High Pulse Width
—
—
Address Setup Time to ADV High
Address Hold Time from ADV# High
Address Invalid Time
—
—
10
—
–5
–5
15
15
—
5
—
10
—
—
–5
–5
25
15
10
—
5, 9
10
Address Hold Time from CE1# High
Address Hold Time from OE# High
WE# High to OE# Low Time for Read
CE1# High Pulse Width
tCHAH
tOHAH
tWHOL
tCP
—
—
10
1000
—
1000
—
11
Notes:
1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21.
2. Address should not be changed within minimum tRC
3. The output load 50pF with 50ohm termination to VDD*0.5 V.
.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
251
P r e l i m i n a r y
4. The output load 5pF without any other load.
5. Applicable to A3 to A21 when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4µs. In other
words, Page Read Cycle must be closed within 4µs.
8. tVPL is specified from the negative edge of either CE1# or ADV# whichever comes late. The sum of tVPL and tVPH must be
equal or greater than tRC for each access.
9. Applicable to address access when at least two of address inputs are switched from previous state.
10. tRC(min) and tPRC(min) must be satisfied.
11. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the
amount of subtracting actual value from specified minimum value.
252
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Write Operation
32M
64M
Parameter
Symbol
tWC
tAS
Min.
70
0
Max.
1000
—
Min.
70
0
Max.
1000
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1, 2
3
Write Cycle Time
Address Setup Time
ADV# Low Pulse Width
tVPL
tVPH
tASV
tAHV
tCW
tWP
10
15
5
—
10
15
5
—
4
ADV# High Pulse Width
Address Setup Time to ADV# High
Address Hold Time from ADV# High
CE1# Write Pulse Width
WE# Write Pulse Width
LB# / UB# Write Pulse Width
LB# / UB# Byte Mask Setup Time
LB# / UB# Byte Mask Hold Time
CE1# Write Recovery Time
Write Recovery Time
—
—
—
—
10
45
45
45
-5
-5
15
15
15
15
15
15
0
—
5
—
—
45
45
45
-5
-5
15
15
15
15
15
15
0
—
3
3
3
5
6
7
7
—
—
tBW
tBS
—
—
—
—
tBH
—
—
tWRC
tWR
tCP
—
—
1000
—
1000
—
CE1# High Pulse Width
WE# High Pulse Width
tWHP
tBHP
tDS
1000
1000
—
1000
1000
—
LB# / UB# High Pulse Width
Data Setup Time
Data Hold Time
tDH
—
—
OE# High to CE1# Low Setup Time for Write
OE# High to Address Setup Time for Write
LB# / UB# Write Pulse Overlap
tOHCL
tOES
-5
0
—
-5
0
—
8
9
—
—
tBWO
30
—
30
—
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB# / UB#, whichever occurs last.
4. tVPL is specified from the negative edge of either CE#1 or ADV# whichever comes late. The sum of tVPL and tVPH must be
equal or greater than tWC for each access.
5. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
6. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
7. Write recovery is defined from Low to High transition of CE1#, WE#, or LB# / UB#, whichever occurs first.
8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data
bus is in High-Z.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
253
P r e l i m i n a r y
Synchronous Operation - Clock Input (Burst Mode)
32M
64M
Parameter
Symbol
Min.
Max.
Min.
13
15
18
30
4
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
RL = 6
RL = 5
RL = 4
RL = 3
N/A
15
20
30
5
—
—
—
—
—
3
—
Clock Period
tCK
1
—
Clock High Time
Clock Low Time
Clock Rise/Fall Time
Notes:
tCKH
tCKL
tCKT
—
—
3
5
4
—
—
2
1. Clock period is defined between valid clock edges.
2. Clock rise/fall time is defined between VIH Min. and VIL Max.
Synchronous Operation - Address Latch (Burst Mode)
32M
64M
Parameter
Symbol
tASVL
tASCL
tAHV
Min.
-5
Max.
—
Min.
-5
-5
5
Max.
Unit
Notes
Address Setup Time to ADV# Low
Address Setup Time to CE1# Low
Address Hold Time from ADV# High
ADV# Low Pulse Width
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
-5
—
10
10
—
tVPL
—
10
5
3
4
4
4
4
4
RL = 6, 5
—
ADV# Low Setup Time to CLK
tVSCK
7
7
RL = 4, 3
RL = 6, 5
RL = 4, 3
—
7
—
5
CE1 Low Setup Time to CLK
tCLCK
—
7
ADV# Low Hold Time from CLK
tCKVH
tVHVL
1
—
1
Burst End ADV# High Hold Time from CLK
15
—
13
Notes:
1. tASCL is applicable if CE1# is brought to Low after ADV# is brought to Low.
2. ASVL is applicable if ADV# is brought to Low after CE1# is brought to Low.
t
3. tVPL is specified from the negative edge of either CE1# or ADV# whichever comes late.
4. Applicable to the 1st valid clock edge.
254
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Synchronous Read Operation (Burst Mode)
32M
64M
Parameter
Burst Read Cycle Time
Symbol
Min.
Max.
Min.
—
—
—
3
Max.
4000
10
12
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tRCB
—
8000
RL = 6, 5
RL = 4, 3
1
1
CLK Access Time
tAC
—
12
Output Hold Time from CLK
CE1# Low to WAIT# Low
tCKQX
tCLTL
tOLTL
tVLTL
tCKTV
tCKTX
tCLZ
3
5
0
—
20
20
1
5
20
20
20
10
—
1
OE# Low to WAIT# Low
0
1, 2
1
ADV# Low to WAIT# Low
N/A
0
CLK to WAIT# Valid Time
—
3
12
—
—
—
—
14
14
14
20
20
—
—
—
—
—
—
—
—
—
3
1, 3
1
WAIT# Valid Hold Time from CLK
CE1# Low to Output Low-Z
OE# Low to Output Low-Z
LB#, UB# Low to Output Low-Z
CE1# High to Output High-Z
OE# High to Output High-Z
LB#, UB# High to Output High-Z
CE1# High to WAIT High-Z
OE# High to WAIT High-Z
OE# Low Setup Time to 1st Data-out
5
5
—
4
tOLZ
10
0
10
0
—
4
tBLZ
—
4
tCHZ
—
—
—
—
—
30
30
5
—
—
—
—
—
30
26
5
20
20
20
20
20
—
1
tOHZ
tBHZ
1
1
tCHTZ
tOHTZ
tOLQ
1
1
UB#, LB# Setup Time to 1st Data-out
OE# Setup Time to CLK
tBLQ
—
5
tOSCK
tCKOH
tCKCLH
tCKBH
—
OE# Hold Time from CLK
5
5
—
Burst End CE1# Low Hold Time from CLK
Burst End UB#, LB# Hold Time from CLK
5
5
—
5
5
—
BL=8, 16
BL=Continuous
30
70
26
70
—
6
6
Burst Terminate Recovery Time
tTRB
—
Notes:
1. The output load 50pF with 50ohm termination to VDD*0.5 V.
2. WAIT# drives High at the beginning depending on OE# falling edge timing.
3. tCKTV is guaranteed after tOLTL (max) from OE# falling edge and tOSCK must be satisfied.
4. The output load is 5pF without any other load.
5. Once they are determined, they must not be changed until the end of burst.
6. Defined from the Low to High transition of CE1# to the High to Low transition of either ADV# or CE1# whichever occurs late.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
255
P r e l i m i n a r y
Synchronous Write Operation (Burst Mode)
32M
64M
Parameter
Burst Write Cycle Time
Symbol
tWCB
Min.
—
7
Max.
8000
—
Min.
—
5
Max.
4000
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Data Setup Time to Clock
tDSCK
tDHCK
tWLD
Data Hold Time from CLK
3
—
3
—
WE# Low Setup Time to 1st Data In
UB#, LB# Setup Time for Write
WE# Setup Time to CLK
30
-5
5
—
30
-5
5
—
tBS
—
—
1
tWSCK
tCKWH
tCLTH
tWLTH
tCHTZ
tWHTZ
tCKCLH
tCHCK
tCKBH
tWRB
—
—
WE# Hold Time from CLK
5
—
5
—
CE1# Low to WAIT# High
5
20
20
20
20
—
5
20
20
20
20
—
2
2
2
2
WE# Low to WAIT# High
0
0
CE1# High to WAIT# High-Z
WE# High to WAIT# High-Z
—
—
5
—
—
5
Burst End CE1# Low Hold Time from CLK
Burst End CE1# High Setup Time to next CLK
Burst End UB#, LB# Hold Time from CLK
Burst Write Recovery Time
5
—
5
—
5
—
5
—
30
30
70
26
26
70
BL=8, 16
Burst Terminate Recovery Time
BL=Continuous
tTRB
—
—
—
—
3
4
tTRB
Notes:
1. Defined from the valid input edge to the High to Low transition of either ADV#, CE1#, or WE#, whichever occurs last. And
once they are determined, they must not be changed until the end of burst.
2. The output load 50pF with 50ohm termination to VDD*0.5 V.
3. Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to Low transition of
either ADV# or CE1# whichever occurs late for the next access.
4. Defined from the Low to High transition of CE1# to the High to Low transition of either ADV# or CE1# whichever occurs late
for the next access.
256
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Power Down Parameters
32M
64M
Parameter
Symbol
tCSP
Min.
20
Max.
—
Min.
10
Max.
—
Unit
ns
Notes
CE2 Low Setup Time for Power Down Entry
CE2 Low Hold Time after Power Down Entry
CE2 Low Hold Time for Reset to Asynchronous Mode
tC2LP
70
—
70
—
ns
tC2LPR
N/A
50
—
µs
1
2
CE1# High Hold Time following CE2 High after Power
Down Exit [SLEEP mode only]
tCHH
tCHHP
tCHS
300
70
0
—
—
—
300
70
0
—
—
—
µs
µs
ns
CE1# High Hold Time following CE2 High after Power
Down Exit [not in SLEEP mode]
3
2
CE1# High Setup Time following CE2 High after Power
Down Exit
Notes:
1. Applicable when RP=0 (Reset to Page mode). RP (Reset to Page) mode is available only for 64M.
2. Applicable also to power-up.
3. Applicable when Partial mode is set.
Other Timing Parameters
32M
64M
Parameter
CE1 High to OE Invalid Time for Standby Entry
CE1 High to WE Invalid Time for Standby Entry
CE2 Low Hold Time after Power-up
CE1 High Hold Time following CE2 High after Power-up
Input Transition Time
Symbol
tCHOX
tCHWX
tC2LH
tCHH
Min.
10
10
50
300
1
Max.
—
Min.
10
10
50
300
1
Max.
—
Unit
ns
Notes
—
—
ns
1
—
—
µs
—
—
µs
tT
25
25
ns
2
Notes:
1. Some data might be written into any address location if tCHWX(min) is not satisfied.
2. Except for clock input transition time.
3. The Input Transition Time (tT) at AC testing is 5ns for Asynchronous operation and 3ns for Synchronous operation
respectively. If actual tT is longer than 5ns or 3ns specified as AC test condition, it may violate AC specification of some
timing parameters. See the "AC Test Conditions" section
AC Test Conditions
Symbol
VIH
Description
Tes t Se tup
Value
VDD * 0.8
VDD * 0.2
VDD * 0.5
5
Unit
V
Note
Input High Level
Input Low Level
VIL
V
VREF
Input Timing Measurement Level
V
Async.
Sync.
ns
ns
tT
Input Transition Time
Between VIL and VIH
3
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
257
P r e l i m i n a r y
AC Measurement Output Load Circuit
V
*0.5V
DD
50ohm
V
DD
DEVICE
UNDER
TEST
OUT
0.1µF
V
SS
50pF
Figure 12. Output Load Circuit
258
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Timing Diagrams
tRC
ADDRESS VALID
ADDRESS
ADV#
CE1#
Low
tASC
tCE
tCHAH
tASC
tCP
tCHZ
tOE
OE#
tOHZ
tBHZ
tBA
LB# / UB#
tBLZ
tOLZ
DQ
(Output)
VALID DATA OUTPUT
Figure 13. Asynchronous Read Timing #1-1 (Basic Timing)
tOH
Note: This timing diagram assumes CE2=H and WE#=H.
tRC
ADDRESS VALID
ADDRESS
ADV#
tAHV
tAV
tVPL
tASC
tASC
tCE
CE1#
tCP
tOE
tCHZ
OE#
tOHZ
tBHZ
tBA
LB# / UB#
tBLZ
tOLZ
DQ
(Output)
VALID DATA OUTPUT
Figure 14. Asynchronous Read Timing #1-2 (Basic Timing)
tOH
Note: This timing diagram assumes CE2=H and WE#=H.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
259
P r e l i m i n a r y
tAX
tRC
tRC
ADDRESS
CE1#
ADDRESS VALID
ADDRESS VALID
tAA
tAA
tOHAH
Low
tASO
tOE
OE#
LB# / UB#
tOLZ
tOH
tOHZ
tOH
DQ
(Output)
VALID DATA OUTPUT
Figure 15. Asynchronous Read Timing #2 (OE# & Address Access)
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H, ADV#=L and WE#=H.
tAX
tRC
tAX
ADDRESS
ADDRESS VALID
tAA
Low
CE1#, OE#
LB#
tBA
tBA
tBA
UB#
tBHZ
tOH
tBHZ
tOH
tBLZ
tBLZ
DQ1-8
(Output)
VALID DATA
OUTPUT
tBHZ
VALID DATA
OUTPUT
tOH
tBLZ
DQ9-16
(Output)
VALID DATA OUTPUT
Figure 16. Asynchronous Read Timing #3 (LB# / UB# Byte Access)
Note: This timing diagram assumes CE2=H, ADV#=L and WE#=H.
260
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
tRC
ADDRESS
(A21-A3)
ADDRESS VALID
tRC
tPRC
tPRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS VALID
tPAA
tPAA
tPAA
tASC
tCHAH
ADV#
CE1#
tCHZ
tCE
OE#
LB# / UB#
tOH
tCLZ
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Figure 17. Asynchronous Read Timing #4 (Page Address Access after CE1# Control Access)
Note: This timing diagram assumes CE2=H and WE#=H.
tRC
tAX
tRC
tAX
ADDRESS
(A21-A3)
ADDRESS VALID
ADDRESS VALID
tRC
tPRC
tRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
tAA
tPAA
tAA
tPAA
CE1#
Low
tASO
tOE
OE#
tBA
LB# / UB#
tOLZ
tBLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Figure 18. Asynchronous Read Timing #5 (Random and Page Address Access)
Notes:
1. This timing diagram assumes CE2=H, ADV#=L and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
261
P r e l i m i n a r y
tWC
ADDRESS
ADV#
ADDRESS VALID
Low
tAS
tCW
tWP
tBW
tWRC
tWR
tBR
tAS
CE1#
tAS
tAS
WE#
tAS
tAS
LB#, UB#
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Figure 19. Asynchronous Write Timing #1-1 (Basic Timing)
Note: This timing diagram assumes CE2=H and ADV#=L.
tWC
ADDRESS
ADV#
ADDRESS VALID
tVPL
tAHV
tCW
tAS
tWRC
tWR
tBR
tAS
CE1#
tAS
tWP
tAS
WE#
tAS
tBW
tAS
LB#, UB#
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Figure 20. Asynchronous Write Timing #1-2 (Basic Timing)
Note: This timing diagram assumes CE2=H.
262
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tOHAH
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE#
UB#, LB#
OE#
tOES
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Figure 21. Asynchronous Write Timing #2 (WE# Control)
Note: This timing diagram assumes CE2=H and ADV#=L.
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tAS
tWP
tAS
tWP
WE#
LB#
UB#
tBH
tBR
tBS
tBR
tBS
tBH
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 22. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control)
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
263
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tWR
tWR
WE#
LB#
UB#
tAS
tBW
tBS
tBH
tAS
tBW
tBH
tBS
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 23. Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control)
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
LB#
UB#
tAS
tBW
tBR
tBS
tBH
tAS
tBW
tBR
tBS
tBH
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 24. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control)
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
264
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
LB#
tAS
tBW
tBR
tAS
tBW
tBR
tBWO
tDH
tDS
tDH
tDS
DQ1-8
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
tAS
tBW
tBR
tAS
tBR
tBWO
tBW
UB#
tDS
tDH
tDS
tDH
DQ9-16
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
Figure 25. Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control)
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tCW
tWRC
tASC
tCE
tCHAH
tCP
tCP
WE#
UB#, LB#
OE#
tOHCL
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Figure 26. Asynchronous Read / Write Timing #1-1 (CE1# Control)
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. Write address is valid from either CE1# or WE# of last falling edge.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
265
P r e l i m i n a r y
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tWR
tASC
tCE
tCHAH
tCP
tCP
tWP
WE#
UB#, LB#
OE
tOHCL
tOE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Figure 27. Asynchronous Read / Write Timing #1-2 (CE1# / WE# / OE# Control)
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read Sequence.
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tOHAH
tOHAH
tAA
Low
tAS
tWR
tWP
WE#
tOES
UB#, LB#
OE#
tASO
tOE
tOHZ
tOH
tOHZ
tOH
tDS
tDH
tOLZ
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Figure 28. Asynchronous Read / Write Timing #2 (OE#, WE# Control)
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
266
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tAA
tOHAH
tOHAH
Low
WE#
tOES
tAS
tBW
tBR
tBA
UB#, LB#
OE#
tBHZ
tASO
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Figure 29. Asynchronous Read / Write Timing #3 (OE,# WE#, LB#, UB# Control)
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
tCK
CLK
tCK
tCKH
tCKL
tCKT
tCKT
Figure 30. Clock Input Timing
Notes:
1. Stable clock input must be required during CE1#=L.
2. CK is defined between valid clock edges.
t
3. tCKT is defined between VIH Min. and VIL Max
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
267
P r e l i m i n a r y
Case #1
Case #2
CLK
ADDRESS
Valid
Valid
tASCL
tCKVH
tAHV
tVSCK
tCKVH
tAHV
tASVL
tVSCK
ADV#
CE1#
tVPL
tVPL
tVLCL
tCLCK
Low
Figure 31. Address Latch Timing (Synchronous Mode)
Notes:
1. Case #1 is the timing when CE1# is brought to Low after ADV# is brought to Low. Case #2 is the timing when ADV# is
brought to Low after CE1# is brought to Low.
2.
t
VPL is specified from the negative edge of either CE1# or ADV# whichever comes late. At least one valid clock edge must be
input during ADV#=L.
3. tVSCK and tCLCK are applied to the 1st valid clock edge during ADV#=L.
268
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tVSCK
tVSCK
tCKVH
ADV#
CE1#
tVPL
tVHVL
tVPL
tASCL
tASCL
tCLCK
tCLCK
tCKOH
tCP
OE#
WE#
tOLQ
High
tCKBH
tBLQ
LB#, UB#
WAIT#
DQ
tOHTZ
tCKTV
tCKTV
High-Z
High-Z
tOHZ
tOLTL
tCKTX
tAC
tAC
tAC
tCKTX
QBL
Q1
tOLZ
tCKQX
tCKQX
Figure 32. 32M Synchronous Read Timing #1 (OE# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
269
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1#
tCP
tCLCK
tCKCLH
tCLCK
OE#
WE#
High
tCKBH
LB#, UB#
WAIT#
DQ
tCKTV
tCKTV
tCHTZ
tCLTL
tCLZ
tCLTL
tCKTX
tAC
tAC
tAC
tCKTX
tCHZ
Q1
QBL
tCLZ
tCKQX
tCKQX
Figure 33. 32M Synchronous Read Timing #2 (CE1# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
270
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tCKVH
ADV#
tVPL
tVHVL
tVPL
CE1#
Low
OE#
WE#
Low
High
LB#, UB#
WAIT#
DQ
tCKTV
tCKTV
tCKTX
tAC
tAC
tAC
tCKTX
QBL
Q1
tCKQX
tCKQX
Figure 34. 32M Synchronous Read Timing #3 (ADV# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
271
P r e l i m i n a r y
RL=5
CLK
ADDRESS
XXX7Fh
tASVL
tAHV
tCKVH
tVSCK
ADV#
CE1#
OE#
tVPL
tASCL
tCLCK
tOLQ
High
WE#
tBLQ
LB#, UB#
WAIT#
DQ
tCKTV
tCKTV
tCKTV
High-Z
High-Z
tCKTX
tOLTL
tCKTX
tAC
tAC
tCKTX
tAC
tAC
tAC
Q1
Q2
Q3
tOLZ
tCKQX
tCKQX
tCKQX
Figure 35. Synchronous Read - WAIT# Output Timing (Continuous Read)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
272
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tVSCK
tVSCK
tCKVH
ADV#
CE1#
tVPL
tVHVL
tVPL
tASCL
tASCL
tCLCK
tCLCK
tCKOH
tCP
OE#
WE#
tOLQ
High
tCKBH
tBLQ
LB#, UB#
tCKTV
tOHTZ
tOHZ
WAIT#
DQ
High-Z
High-Z
tOLTL
tCKTX
tAC
tAC
tAC
Q1
QBL
tOLZ
tCKQX
tCKQX
Figure 36. 64M Synchronous Read Timing #1 (OE# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
273
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
CE1#
tVPL
tVHVL
tVPL
tASCL
tASCL
tCP
tCLCK
tCKCLH
tCLCK
OE#
WE#
High
tCKBH
LB#, UB#
tCKTV
tCHTZ
tCLTL
WAIT#
DQ
tCLZ
tCLTL
tCKTX
tAC
tAC
tAC
tCHZ
Q1
QBL
tCLZ
tCKQX
tCKQX
Figure 37. 64M Synchronous Read Timing #2 (CE1# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
274
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
tVPL
tVHVL
tVPL
CE1#
Low
OE#
WE#
Low
High
LB#, UB#
WAIT#
DQ
tCKTV
tVLTL
tVLTL
tCKTX
tAC
tAC
tAC
Q1
QBL
tCKQX
tCKQX
Figure 38. 64M Synchronous Read Timing #3 (ADV# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
275
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tVHVL
tWRB
ADV#
CE1#
tVPL
tVPL
tCLCK
tASCL
tASCL
tCLCK
tCP
High
OE#
WE#
tWLD
tCKWH
tBS
tCKBH
tBS
LB#, UB#
WAIT#
DQ
High-Z
tWLTH
tDSCK
tDSCK
tDSCK
tWHTZ
D1
D2
DBL
tDHCK
tDHCK
Figure 39. Synchronous Write Timing #1 (WE# Level Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
276
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tVHVL
tWRB
ADV#
CE1#
tVPL
tVPL
tCLCK
tASCL
tASCL
tCLCK
tCP
tCKCLH
High
OE#
WE#
tWSCK
tCKWH
tWSCK
tCKWH
tBS
tCKBH
tBS
LB#, UB#
WAIT#
High-Z
tWLTH
tDSCK
tDSCK
tDSCK
tCHTZ
tWLTH
D1
D2
DBL
DQ
tDHCK
tDHCK
Figure 40. Synchronous Write Timing #2 (WE# Single Clock Pulse Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
277
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
CE1#
tVHVL
tVPL
tVPL
tWRB
High
OE#
WE#
tBS
tCKBH
tBS
LB#, UB#
WAIT#
DQ
High
tDSCK
tDSCK
tDSCK
D1
D2
DBL
tDHCK
tDHCK
Figure 41. Synchronous Write Timing #3 (ADV# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
278
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tCKVH
tVHVL
tWRB
ADV#
CE1#
tVPL
tVPL
tCLCK
tASCL
tASCL
tCLCK
tCP
High
OE#
WE#
tWLD
tCKWH
tBS
tCKBH
tBS
LB#, UB#
WAIT#
DQ
High-Z
tWLTH
tDSCK
tWHTZ
tWLTH
D1
tDHCK
Figure 42. Synchronous Write Timing #4 (WE# Level Control, Single Write)
Notes:
1. This timing diagram assumes CE2=H, the valid clock edge on rising edge and single write operation.
2. Write data is latched on the valid clock edge.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
279
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
tASVL
tVHVL
tAHV
tCKVH
tVSCK
ADV#
CE1#
tVPL
tCLCK
tCKCLH
tCKCLH
tASCL
tCP
OE#
WE#
LB#, UB#
WAIT#
DQ
tCKBH
tBS
tCKBH
tCHTZ
tCKTV
tCHZ
tCLTH
tAC
tCKTX
QBL
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 43. 32M Synchronous Read to Write Timing #1(CE1# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
280
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
CE1#
tVPL
tVHVL
tCKOH
OE#
tWLD
tCKWH
WE#
tCKBH
tBS
tCKBH
LB#, UB#
tOHTZ
tCKTV
WAIT#
DQ
tOHZ
tAC
tCKTX
tWLTH
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
QBL
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 44. 32M Synchronous Read to Write Timing #2(ADV# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
281
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
tASVL
tAHV
tCKVH
tVSCK
ADV#
tVHVL
tASCL
tVPL
tCLCK
tCKCLH
tCKCLH
CE1#
tCP
OE#
WE#
tCKBH
tBS
tCKBH
LB#, UB#
WAIT#
DQ
tCHTZ
tCHZ
tAC
tCLTH
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
QBL
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 45. 64M Synchronous Read to Write Timing #1(CE1# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
282
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tVHVL
CE1#
tCKOH
OE#
WE#
tWLD
tCKWH
tCKBH
tBS
tCKBH
LB#, UB#
WAIT#
DQ
tOHTZ
tOHZ
tAC
tWLTH
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
QBL
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 46. 64M Synchronous Read to Write Timing #2(ADV# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
283
P r e l i m i n a r y
RL=5
CLK
tCKT
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
CE1#
tVPL
tASCL
tCKCLH
tCP
tCLCK
tWRB
OE#
WE#
tCKBH
LB#, UB#
tCKTV
High-Z
WAIT#
tDSCK
tDSCK
tCHTZ
tCLTL
tCKTX
tAC
tAC
DBL-1
DBL
Q1
Q2
DQ
tDHCK
tDHCK
tCLZ
tCKQX
tCKQX
Figure 47. Synchronous Write to Read Timing #1 (CE1# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
284
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
RL=5
CLK
tCKT
ADDRESS
Valid
tASVL
tVSCK
tAHV
tCKVH
ADV#
CE1#
tVPL
tWRB
Low
OE#
WE#
tOLQ
tCKWH
tCKBH
tBLQ
LB#, UB#
WAIT#
tCKTV
High-Z
tDSCK
tDSCK
tWHTZ
tOLTL
tCKTX
tAC
tAC
DBL-1
DBL
Q1
Q2
DQ
tDHCK
tDHCK
tOLZ
tCKQX
tCKQX
Figure 48. Synchronous Write to Read Timing #2 (ADV# Control)
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
285
P r e l i m i n a r y
CE1#
CE2
tCHS
tC2LH
tCHH
V
DD
VDD min
0V
Figure 49. Power-up Timing #1
Note: The tC2LH specifies after VDD reaches specified minimum level.
CE1#
tCHH
CE2
VDD
VDD min
0V
Figure 50. Power-up Timing #2
Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
CE1#
tCHS
CE2
DQ
tCSP
t
C2LP
tCHH (tCHHP)
High-Z
Power Down Entry
Power Down Mode
Power Down Exit
Figure 51. Power Down Entry and Exit Timing
Note: This Power Down mode can be also used as a reset timing if the POWER-UP timing above could not be satisfied
and Power-Down program was not performed prior to this reset.
286
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
CE1#
OE#
t
CHOX
t
CHWX
WE#
Active (Read)
Standby
Active (Write)
Standby
Figure 52. Standby Entry Timing after Read or Write
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
tRC (min) period for Standby mode from CE1# Low to High transition.
tRC
tWC
tWC
tWC
tWC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
MSB*1
Key*2
ADDRESS
CE1#
tCP*3
(tRC)
tCP
tCP
tCP
tCP
tCP
OE#
WE#
LB#, UB#
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
X
X
RDb
Cycle #6
Cycle #4
Cycle #5
Figure 53. Configuration Register Set Timing #1 (Asynchronous Operation)
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in the "Functional Description" section. If not, the operation and data are
not guaranteed.
3. After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. tCP and
tRC are applicable to returning to asynchronous mode and to synchronous mode respectively.
4. Byte read or write is available in addition to Word read or write. At least one byte control signal (LB# or UB#) need to be
Low.
October 5, 2004 CosmoRAM_00_A0
CosmoRAM
287
P r e l i m i n a r y
CLK
ADDRESS
MSB
MSB
MSB
MSB
MSB
Key
tRCB
tWCB
tWCB
tWCB
tWCB
tRCB
ADV#
CE1#
tTRB
tTRB
tTRB
tTRB
tTRB
tTRB
OE#
WE#
LB#, UB#
WAIT#
RL
RL-1
RDa
Cycle#2
RL-1
RDa
Cycle#3
RL-1
RL-1
RL
RDa
X
X
RDb
Cycle#6
DQ
Cycle#1
Cycle#4
Cycle#5
Figure 54. Configuration Register Set Timing #2 (Synchronous Operation)
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in the "Functional Description" section. If not, the operation and data are
not guaranteed.
3. After tTRB following Cycle #6, the Configuration Register Set is completed and returned to the normal operation.
4. Byte read or write is available in addition to Word read or write. At least one byte control signal (LB# or UB#) need to be
Low.
288
CosmoRAM
CosmoRAM_00_A0 October 5, 2004
P r e l i m i n a r y
Revision Summary
Revision A0 (October 26, 2004)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2003 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Span-
sion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective compa-
nies.
October 26, 2004 S71WS512/256Nx0_00
S71WS512N/256N Based MCPs
289
相关型号：
©2020 ICPDF网 联系我们和版权申明