S71WS512ND0BFIE71 [SPANSION]
Memory Circuit, 32MX16, CMOS, PBGA84, 9 X 12 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84;![S71WS512ND0BFIE71](http://pdffile.icpdf.com/pdf2/p00241/img/icpdf/S71WS512ND0B_1459792_icpdf.jpg)
型号: | S71WS512ND0BFIE71 |
厂家: | ![]() |
描述: | Memory Circuit, 32MX16, CMOS, PBGA84, 9 X 12 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84 |
文件: | 总144页 (文件大小:3335K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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S71WS512Nx0/S71WS256Nx0 Based MCPs
Stacked Multi-chip Product (MCP)
256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with
128 Megabit (8M x 16-Bit) pSRAM Type 4
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Burst Speed: 54MHz
Packages: 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
-25°C to +85°C
-40°C to +85°C
General Description
The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
One or more flash memory die
pSRAM Type 4—Compatible pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheet for
further details.
Flash Density
512Mb
256Mb
128Mb
64Mb
128Mb
64Mb
32Mb
S71WS512ND0
S71WS256ND0
16Mb
Publication Number S71WS512/256Nx0_UT Revision A Amendment 0 Issue Date November 8, 2004
A d v a n c e I n f o r m a t i o n
Table 5.30. Unlock Bypass Entry .......................................... 43
S71WS512Nx0/S71WS256Nx0 Based MCPs
Table 5.31. Unlock Bypass Program ..................................... 44
Table 5.32. Unlock Bypass Reset ......................................... 44
Figure 5.33. Write Operation Status Flowchart....................... 46
Table 5.34. DQ6 and DQ2 Indications ................................... 48
Table 5.35. Write Operation Status ...................................... 49
Table 5.36. Reset .............................................................. 51
Figure 6.2. Lock Register Program Algorithm......................... 57
Table 8.2. SecSi Sector Entry .............................................. 63
Table 8.3. SecSi Sector Program .......................................... 64
Table 8.4. SecSi Sector Entry .............................................. 64
Figure 9.2. Maximum Positive Overshoot Waveform............... 65
Figure 9.3. Test Setup........................................................ 66
Figure 9.4. Input Waveforms and Measurement Levels........... 67
Figure 9.5. VCC Power-up Diagram....................................... 67
Figure 9.6. CLK Characterization.......................................... 69
Figure 9.7. CLK Synchronous Burst Mode Read...................... 71
Figure 9.8. 8-word Linear Burst with Wrap Around................. 72
Figure 9.9. 8-word Linear Burst without Wrap Around ............ 72
Figure 9.10. Linear Burst with RDY Set One Cycle Before Data 73
Figure 9.11. Asynchronous Mode Read ................................. 74
Figure 9.12. Reset Timings ................................................. 75
Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched
Addresses......................................................................... 77
Figure 9.13. Asynchronous Program Operation Timings: WE#
Latched Addresses............................................................. 78
Figure 9.14. Synchronous Program Operation Timings:
CLK Latched Addresses ...................................................... 79
Figure 9.15. Accelerated Unlock Bypass Programming Timing.. 80
Figure 9.16. Data# Polling Timings
(During Embedded Algorithm)............................................. 80
Figure 9.17. Toggle Bit Timings (During Embedded Algorithm) 81
Figure 9.18. Synchronous Data Polling
Timings/Toggle Bit Timings................................................. 81
Figure 9.19. DQ2 vs. DQ6................................................... 82
Figure 9.20. Latency with Boundary Crossing when
Frequency > 66 MHz.......................................................... 82
Figure 9.21. Latency with Boundary Crossing into Program/
Erase Bank....................................................................... 83
Figure 9.22. Example of Wait States Insertion....................... 84
Figure 9.23. Back-to-Back Read/Write Cycle Timings.............. 85
Table 10.2. Sector Protection Commands .............................. 90
Table 10.3. CFI Query Identification String ............................ 91
Table 10.4. System Interface String ..................................... 92
Table 10.5. Device Geometry Definition ................................ 92
Table 10.6. Primary Vendor-Specific Extended Query ............. 93
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ................................................................................................... 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
bProduct Selector Guide . . . . . . . . . . . . . . . . . . . . .5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7
Type 4 - based Pinout ..........................................................................................7
MCP Look-ahead Connection Diagram .........................................................8
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . .9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 11
256Mb - WS256N Flash + 128 pSRAM .......................................................... 11
2x256Mb—WS256N Flash + 128Mb pSRAM ............................................... 11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ........................................................................................... 12
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ............................................................................................13
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm
MCP Compatible Package ................................................................................14
S29WSxxxN MirrorBit™ Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . 15
Application Notes ...........................................................................................18
Specification Bulletins ....................................................................................18
Drivers and Software Support .................................................................... 18
CAD Modeling Support ................................................................................18
Technical Support ...........................................................................................18
Spansion LLC Locations ........................................................18
Table 4.2. S29WS128N Sector & Memory Address Map .......... 20
Table 4.3. S29WS064N Sector & Memory Address Map .......... 21
Table 5.4. Device Operations .............................................. 22
Table 5.7. Address Latency for 5 Wait States (
Table 5.8. Address Latency for 4 Wait States (
Table 5.9. Address Latency for 3 Wait States (
≤
≤
≤
68 MHz) ........ 24
54 MHz) ........ 25
40 MHz) ........ 25
Table 5.10. Address/Boundary Crossing Latency for 6 Wait States
80 MHz) ....................................................................... 25
Table 5.11. Address/Boundary Crossing Latency for 5 Wait States
68 MHz) ....................................................................... 25
Table 5.12. Address/Boundary Crossing Latency for 4 Wait States
54 MHz) ....................................................................... 25
Table 5.13. Address/Boundary Crossing Latency for 3 Wait States
40 MHz) ....................................................................... 25
(≤
(≤
(≤
pSRAM Type 4
(≤
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 99
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 100
Power Up ............................................................................................................100
Figure 11.24. Power Up Timing.......................................... 100
Standby Mode .................................................................................................... 100
Figure 11.25. Standby Mode State Machines ....................... 100
Functional Description . . . . . . . . . . . . . . . . . . . . . 101
Table 11.7. Asynchronous 4 Page Read & Asynchronous Write Mode
(A15/A14=0/0) ............................................................... 101
Table 11.8. Synchronous Burst Read & Asynchronous Write Mode
(A15/A14=0/1) ............................................................... 102
Table 11.9. Synchronous Burst Read & Synchronous Burst Write
Mode(A15/A14=1/0) ........................................................ 103
Figure 5.2. Synchronous Read ............................................. 26
Table 5.14. Burst Address Groups ....................................... 27
Table 5.15. Configuration Register ....................................... 28
Table 5.16. Autoselect Addresses ........................................ 29
Table 5.17. Autoselect Entry ............................................... 29
Table 5.18. Autoselect Exit ................................................. 30
Figure 5.19. Single Word Program........................................ 32
Table 5.20. Single Word Program ........................................ 33
Table 5.21. Write Buffer Program ........................................ 35
Figure 5.22. Write Buffer Programming Operation .................. 36
Table 5.23. Sector Erase .................................................... 38
Figure 5.24. Sector Erase Operation ..................................... 39
Table 5.25. Chip Erase ....................................................... 40
Table 5.26. Erase Suspend ................................................. 41
Table 5.27. Erase Resume .................................................. 41
Table 5.28. Program Suspend ............................................. 42
Table 5.29. Program Resume .............................................. 42
Mode Register Setting Operation . . . . . . . . . . . . 103
November 8, 2004 S71WS512/256Nx0_UTA0
S71WS512Nx0/S71WS256Nx0
2
A d v a n c e I n f o r m a t i o n
Figure 11.39. Timing Waveform Of Write Cycle (Address Latch
Type)............................................................................. 121
Table 11.21. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 121
Asynchronous Write Timing Waveform in Synchronous Mode ........122
Mode Register Set (MRS) ...............................................................................104
Table 11.10. Mode Register Setting According to
Field of Function ...............................................................104
Table 11.11. Mode Register Set ..........................................104
MRS Pin Control Type Mode Register Setting Timing ..........................105
Figure 11.26. Mode Register Setting Timing (OE# = VIH) ...... 106
Table 11.12. MRS AC Characteristics ...................................106
Write Cycle (Low ADV# Type) ...............................................................122
Figure 11.40. Timing Waveform Of Write
Cycle (Low ADV# Type).................................................... 122
Table 11.22. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 122
Write Cycle (Low ADV# Type) ...............................................................123
Figure 11.41. Timing Waveform Of Write Cycle
(Low ADV# Type)............................................................ 123
Table 11.23. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 123
Multiple Write Cycle (Low ADV# Type) ..............................................124
Figure 11.42. Timing Waveform Of Multiple Write Cycle (Low ADV#
Type)............................................................................. 124
Table 11.24. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 125
Asynchronous Operation . . . . . . . . . . . . . . . . . . 107
Asynchronous 4 Page Read Operation ......................................................107
Asynchronous Write Operation ..................................................................107
Asynchronous Write Operation in Synchronous Mode .......................107
Figure 11.27. Asynchronous 4-Page Read............................ 107
Figure 11.28. Asynchronous Write...................................... 107
Synchronous Burst Operation . . . . . . . . . . . . . . 108
Synchronous Burst Read Operation ...........................................................108
Synchronous Burst Write Operation .........................................................108
Figure 11.29. Synchronous Burst Read................................ 108
Figure 11.30. Synchronous Burst Write............................... 109
Synchronous Burst Operation Terminology . . 109
Clock (CLK) ........................................................................................................109
Latency Count ....................................................................................................109
Table 11.13. Latency Count Support ...................................109
Table 11.14. Number of CLocks for 1st Data ........................109
Figure 11.31. Latency Configuration (Read)......................... 110
Burst Length ........................................................................................................110
Burst Stop .............................................................................................................110
Synchronous Burst Operation Terminology . . . 110
Wait Control (WAIT#) ...................................................................................110
Figure 11.32. WAIT# and Read/Write Latency Control........... 111
Burst Type .............................................................................................................111
Table 11.15. Burst Sequence .............................................111
AC Operating Conditions . . . . . . . . . . . . . . . . . . 126
Test Conditions (Test Load and Test Input/Output Reference) ........126
Figure 11.43. AC Output Load Circuit ................................. 126
Table 11.25. Synchronous AC Characteristics ..................... 127
Synchronous Burst Operation
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 11.44. Timing Waveform Of Basic Burst Operation ..... 128
Table 11.26. Burst Operation AC Characteristics .................. 128
Synchronous Burst Read Timing Waveform . . . 129
Read Timings .......................................................................................................129
Figure 11.45. Timing Waveform of Burst Read Cycle (1)....... 129
Table 11.27. Burst Read AC Characteristics ......................... 130
Figure 11.46. Timing Waveform of Burst Read Cycle (2)....... 130
Table 11.28. Burst Read AC Characteristics ......................... 131
Figure 11.47. Timing Waveform of Burst Read Cycle (3)....... 131
Table 11.29. Burst Read AC Characteristics ......................... 132
Write Timings .....................................................................................................133
Figure 11.48. Timing Waveform of Burst Write Cycle (1)....... 133
Table 11.30. Burst Write AC Characteristics ........................ 134
Figure 11.49. Timing Waveform of Burst Write Cycle (2)....... 135
Table 11.31. Burst Write AC Characteristics ........................ 135
Low Power Features . . . . . . . . . . . . . . . . . . . . . . 112
Internal TCSR ......................................................................................................112
Figure 11.33. PAR Mode Execution and Exit ......................... 112
Table 11.16. PAR Mode Characteristics ................................112
Driver Strength Optimization ........................................................................112
Partial Array Refresh (PAR) mode ...............................................................112
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 113
DC Recommended Operating Conditions . . . . . 113
Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . 113
DC and Operating Characteristics . . . . . . . . . . . 114
Common ...............................................................................................................114
Synchronous Burst Read Stop
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 11.50. Timing Waveform of Burst Read Stop by CS#.. 136
Table 11.32. Burst Read Stop AC Characteristics ................. 136
AC Operating Conditions . . . . . . . . . . . . . . . . . . 115
Test Conditions (Test Load and Test Input/Output Reference) ........ 115
Figure 11.34. Output Load................................................. 115
Asynchronous AC Characteristics ...............................................................116
Synchronous Burst Write Stop
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 11.51. Timing Waveform of Burst Write Stop by CS#.. 137
Table 11.33. Burst Write Stop AC Characteristics ................. 137
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 117
Asynchronous Read Timing Waveform ...................................................... 117
Figure 11.35. Timing Waveform Of Asynchronous Read Cycle 117
Table 11.17. Asynchronous Read AC Characteristics .............117
Page Read .........................................................................................................118
Figure 11.36. Timing Waveform Of Page Read Cycle............. 118
Table 11.18. Asynchronous Page Read AC Characteristics ......118
Asynchronous Write Timing Waveform ....................................................119
Figure 11.37. Timing Waveform Of Write Cycle .................... 119
Table 11.19. Asynchronous Write AC Characteristics .............119
Write Cycle 2 ................................................................................................120
Figure 11.38. Timing Waveform of Write Cycle(2)................. 120
Table 11.20. Asynchronous Write AC Characteristics (UB# & LB#
Controlled) ......................................................................120
Write Cycle (Address Latch Type) ..........................................................121
Synchronous Burst Read Suspend Timing
Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 11.52. Timing Waveform of Burst
Read Suspend Cycle (1) ................................................... 138
Table 11.34. Burst Read Suspend AC Characteristics ............ 138
Transition Timing Waveform Between Read And
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 11.53. Synchronous Burst Read to Asynchronous Write
(Address Latch Type)....................................................... 139
Table 11.35. Burst Read to Asynchronous Write (Address Latch
Type) AC Characteristics ................................................... 139
Figure 11.54. Synchronous Burst Read to Asynchronous Write (Low
ADV# Type).................................................................... 140
Table 11.36. Burst Read to Asynchronous Write (Low ADV# Type)
3
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_UTA0 November 8, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics ............................................................140
Timing ........................................................................... 143
Table 11.39. Asynchronous Write (Low ADV# Type) to Burst Read
AC Characteristics ............................................................ 143
Figure 11.58. Synchronous Burst Write to Synchronous Burst Read
Timing ........................................................................... 144
Table 11.40. Asynchronous Write (Low ADV# Type) to Burst Read
AC Characteristics ............................................................ 144
Figure 11.55. Asynchronous Write (Address Latch Type) to
Synchronous Burst Read Timing......................................... 141
Table 11.37. Asynchronous Write (Address Latch Type) to Burst
Read AC Characteristics ....................................................141
Figure 11.56. Asynchronous Write (Low ADV# Type) to
Synchronous Burst Read Timing......................................... 142
Table 11.38. Asynchronous Write (Low ADV# Type) to Burst Read
AC Characteristics ............................................................142
Figure 11.57. Synchronous Burst Read to Synchronous Burst Write
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 146
November 8, 2004 S71WS512/256Nx0_UTA0
S71WS512Nx0/S71WS256Nx0
4
Product Selector Guide
WS256N + 128 pSRAM
pSRAM Flash Speed
pSRAM
Device-Model
density
MHz
speed MHz
DYB Bits - Power Up
0 (Protected)
Supplier
Package
S71WS256ND0-E3
S71WS256ND0-E7
TSD084
9x12x1.2
128M
54
54
Type 4
1 (Unprotected [Default state])
WS512N + 128 pSRAM
pSRAM
speed
MHz
pSRAM Flash Speed
Device-Model
density
MHz
DYB Bits - Power Up
Supplier
Package
S71WS512ND0-Y3
S71WS512ND0-Y7
0
1
1.8V RAM
Type 4
FEA084
9x12x1.4
128Mb
54
54
November 8, 2004 S71WS512/256Nx0_UT
S71WS512Nx0/S71WS256Nx0
5
MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
22
16
DQ15 to DQ0
CLK
WP#
ACC
ACC
CE#
OE#
Flash 1
(Note 3) F1-CE#
OE#
Flash 2
(Note 4)
WE#
F-RST#
AVD#
WE#
RESET#
AVD#
RDY
RDY
(Note 3) F2-CE#
R-VCC
V
SS
22
V
CCQ
V
CC
16
I/O15 to I/O0
CLK
R-CE1#
CE#
WE#
OE#
pSRAM
WAIT#
R-UB#
R-LB#
UB#
LB#
V
SSQ
AVD#
MRS
R-MRS
Notes:
1. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash.
2. Only needed for S71WS512N.
3. For the 128M pSRAM devices, there are 23 shared addresses.
6
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_UT November 8, 2004
Connection Diagrams
Type 4 - based Pinout
84-ball Fine-Pitch Ball Grid Array
Type 4-based Pinout (Top View, Balls Facing Down)
A10
A1
DNU
DNU
B2
B3
RFU
C3
A7
D3
A6
E3
B4
CLK
C4
B5
F2-CE#
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
AVD#
C2
F-WP#
D2
Legend
RFU
D9
R-LB#
D4
F-ACC
D5
WE#
D6
A8
A11
D8
D7
Shared
A3
R-UB# F-RST#
RFU
E6
A19
E7
A12
E8
A15
E9
E2
E4
A18
F4
E5
RDY
F5
Flash XIP only
A2
F2
A1
G2
A0
A5
F3
A20
F6
A9
A13
F8
A21
F9
F7
RAM only
A4
A17
G4
A10
G7
A14
G8
A22
G9
RFU
G5
A23
G6
G3
1st Flash
Only
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-MRS
2nd Flash
Only
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
R-CE1#
DQ0
F-VCC
R-VCC
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
RFU
L9
Reserved for
Future Use
DQ2
DQ5
DQ14
DQ8
DQ11
RFU
L3
L4
L5
L7
L8
L2
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M10
DNU
M1
DNU
Notes:
1. In MCP's based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two
S29WS256N (S71WS512), ball B5 is or F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A21-A0
S71WS256NC0
S71WS512ND0
A23-A22
A23
A22-A0
November 8, 2004 S71WS512/256Nx0_UT
S71WS512Nx0/S71WS256Nx0
7
MCP Look-ahead Connection Diagram
96-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend:
A2
A10
A9
A1
DNU
DNU
DNU
DNU
(Do Not Use)
DNU
B1
B9
B2
B10
DNU
DNU
DNU
DNU
Code Flash Only
pSRAM Only
C4
C5
C6
C7
C8
C9
C2
C3
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK#
R-OE# F2-OE#
D4
D2
D3
A7
D5
D6
D7
A8
D8
D9
D-DM0/
D1, D#
See Table
See Table WE#
E5 E6
F-RST# R1-CE2
A11
F3-CE#
E2
A3
E3
A6
E4
E7
E8
E9
Flash/xRAM
Shared
D-DM1/
D11, D#
A19
A12
A15
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
A18 See Table
A20
A13
A21
MirrorBit Data
Only
G6
G8
G2
A1
G4
G7
G9
G3
A4
G5
A17
R2-CE1
A23
A10
A14
A22
xRAM Shared
H2
A0
H3
H4
H5
H6
H7
H8
H9
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
Flash/Data
Shared
J2
J3
J4
J5
J6
J7
J8
J9
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
F1-CE#
OE#
K2
K5
K3
K4
K6
K7
K8
K9
DQ12
VSS
R1-CE1#
DQ0
DQ10
F-VCC
R1-VCC
DQ7
L2
L9
L4
L5
L6
L7
L8
L3
DQ2
DQ11
A25
DQ5
DQ14
F-WP#
R-VCC
DQ8
DNU
M5
M2
M3
M4
M6
M7
M8
M9
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ
DNU
N1
N2
N10
N9
DNU
DNU
DNU
DNU
P1
P2
P10
P9
DNU
DNU
DNU
DNU
Table
BALL
1.8V
Vcc
3.0V
Vcc
FASL Standard
MCP Packages
D2
NC
F-WP#
ACC
7.0 x 9.0mm
8.0 x 11.6mm
9.0 x 12.0mm
11.0 x 13.0mm
WP#/
ACC
D5
F5
RY/
BY#
F-RDY/
R-WAIT#
Notes:
1. In a 3.0V system, the GL device used as Data has to have WP tied to VCC.
2. F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash.
8
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_UT November 8, 2004
Input/Output Descriptions
A23-A0
DQ15-DQ0
OE#
=
=
=
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
=
=
=
=
Write Enable input.
Ground
V
SS
NC
RDY
No Connect; not connected internally
Ready output. Indicates the status of the Burst read.
The WAIT# pin of the pSRAM is tied to RDY.
CLK
=
Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at V or V
IL
IH
while in asynchronous mode
AVD#
=
Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
F-RST#
F-WP#
=
=
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At V , disables
IL
program and erase functions in the four outermost
sectors. Should be at V for all other conditions.
IH
F-ACC
=
Accelerated input. At V , accelerates
HH
programming; automatically places device in unlock
bypass mode. At V , disables all program and erase
IL
functions. Should be at V for all other conditions.
IH
R-CE1#
F1-CE#
=
=
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative
to CLK for Burst Mode.
F2-CE#
=
Chip-enable input for Flash 2. Asynchronous relative
to CLK for Burst Mode. This applies to the 512Mb
MCP only.
R-MRS
F-VCC
R-VCC
R-UB#
R-LB#
DNU
=
=
=
=
=
=
Mode register select for Type 4.
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Do Not Use.
November 8, 2004 S71WS512/256Nx0_UT
S71WS512Nx0/S71WS256Nx0
9
Ordering Information
The order number (Valid Combination) is formed by the following:
S71WS 256
N
D
0
BA
W
A
3
0
PACKING TYPE
0
1
2
3
=
=
=
=
Tray
Tube
7” Tape and Reel
13” Tape and Reel
SUPPLIER, DYB, SPEED COMBINATION
3
7
=
=
RAM Type 4, 0, 54MHz
RAM Type 4, 1, 54MHz
PACKAGE MODIFIER
A
Y
E
=
=
=
1.2mm, 8 x 11.6, 84-ball FBGA
1.4mm, 9 x 12, 84-ball FBGA
1.2mm, 9 x 12, 84-ball FBGA
TEMPERATURE RANGE
W
I
=
=
Wireless (-25
Industrial (–40
°
C to +85
°
C)
C)
°C to +85
°
PACKAGE TYPE
BA
=
Very Thin Fine-Pitch BGA
Lead (Pb)-free Compliant Package
Very Thin Fine-Pitch BGA
Lead (Pb)-free Package
BF
=
CHIP CONTENTS—2
No second content
CHIP CONTENTS—1
C = 64Mb
D = 128Mb
PROCESS TECHNOLOGY
N
=
110nm MirrorBit™ Technology
FLASH DENSITY
512
256
=
=
512Mb (2x256Mb)
256Mb
DEVICE FAMILY
S71WS= Multi-Chip Product
1.8 Volt-only Simultaneous Read/Write Burst Mode
Flash Memory + xRAM
10
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_UT November 8, 2004
Valid Combinations
256Mb - WS256N Flash + 128 pSRAM
Temperature
Range °C
Burst
Speed
Material
Set
Order Number
Package Marking
DYB Power-up State
Supplier
S71WS256ND0BAWE3
71WS256ND0BAWE3
0(Protected)
1.8V RAM
Type 4
-25° to +85°C
1(Unprotected[Default
State])
S71WS256ND0BAWE7
S71WS256ND0BAIE3
S71WS256ND0BAIE7
S71WS256ND0BFWE3
S71WS256ND0BFWE7
S71WS256ND0BFIE3
S71WS256ND0BFIE7
71WS256ND0BAWE7
71WS256ND0BAIE3
71WS256ND0BAIE7
71WS256ND0BFWE3
71WS256ND0BFWE7
71WS256ND0BFIE3
71WS256ND0BFIE7
Pb-free
compliant
0(Sectors Protected)
1.8V RAM
Type 4
-40° to +85°C
-25° to +85°C
-40° to +85°C
1(Unprotected[Default
State])
54MHz
0(Protected)
1.8V RAM
Type 4
1(Unprotected[Default
State])
Pb-free
0(Protected)
1.8V RAM
Type 4
1(Unprotected[Default
State])
2x256Mb—WS256N Flash + 128Mb pSRAM
Te m p e r a t u re
Range °C
Burst
Speed
Material
Set
Order Number
Package Marking
DYB Power-up State
Supplier
S71WS512ND0BAWE3
71WS512ND0BAWE3
0(Protected)
1.8V RAM
Type 4
-25° to +85°C
-40° to +85°C
1(Unprotected [Default
State])
S71WS512ND0BAWE7
S71WS512ND0BAIE3
S71WS512ND0BAIE7
S71WS512ND0BFWE3
S71WS512ND0BFWE7
71WS512ND0BAWE7
71WS512ND0BAIE3
71WS512ND0BAIE7
71WS512ND0BFWE3
71WS512ND0BFWE7
Pb-free
compliant
0(Protected)
1.8V RAM
Type 4
1(Unprotected [Default
State])
54MHz
0(Protected)
1.8V RAM
Type 4
-25° to +85°C
-40° to +85°C
1(Unprotected [Default
State])
Pb-free
S71WS512ND0BFIE3
S71WS512ND0BFIE7
71WS512ND0BFIE3
71WS512ND0BFIE7
0(Protected)
0(Protected)
1.8V RAM
Type 4
November 8, 2004 S71WS512/256Nx0_UT
S71WS512Nx0/S71WS256Nx0
11
Physical Dimensions
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
0.15
b
M
C
C
A B
0.08
M
NOTES:
PACKAGE
JEDEC
FEA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.10
1.11
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.26
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
12
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_UT November 8, 2004
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TSD 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.94
BODY THICKNESS
BODY SIZE
D
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
A2,A3,A4,A5,A6,7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3426\ 16-038.22
November 8, 2004 S71WS512/256Nx0_UT
S71WS512Nx0/S71WS256Nx0
13
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm MCP
Compatible Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
Note: BSC is an ANSI standard for Basic Space Centering
14
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_UT November 8, 2004
S29WSxxxN MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. They operate up to 80 MHz and use a single VCC of 1.7–1.95 volts that
makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered
power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
Command set compatible with JEDEC standards
110 nm MirrorBit™ Technology
Hardware (WP#) protection of top and bottom
sectors
Simultaneous Read/Write operation with zero
latency
Dual boot sector configuration (top and bottom)
Offered Packages
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8/4
Mbit for WS256N/128N/064N, respectively
—
—
WS064N: 80-ball FBGA (7 mm x 9 mm)
WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Four 16 Kword sectors at both top and bottom of
memory array
Low VCC write inhibit
Persistent and Password methods of Advanced
Sector Protection
254/126/62 64 Kword sectors (WS256N/128N/
064N)
Write operation status bits indicate program and
erase operation completion
Programmable burst read modes
—
Linear for 32, 16 or 8 words linear read with or
without wrap-around
Suspend and Resume commands for Program and
Erase operations
—
Continuous sequential read mode
Unlock Bypass program command to reduce
programming time
SecSi™ (Secured Silicon) Sector region consisting
of 128 words each for factory and customer
Synchronous or Asynchronous program operation,
independent of burst control register settings
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector
(typical)
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
RDY output indicates data available to system
Industrial Temperature range (contact factory)
Performance Characteristics
Read Access Times
Current Consumption (typical values)
Speed Option (MHz)
Max. Synch. Latency, ns (t
80
69
66
69
54
69
Continuous Burst Read @ 66 MHz
35 mA
50 mA
19 mA
19 mA
20 µA
)
Simultaneous Operation (asynchronous)
Program (asynchronous)
IACC
Max. Synch. Burst Access, ns (t
)
9
11.2
70
13.5
70
BACC
Max. Asynch. Access Time, ns (t
)
70
Erase (asynchronous)
ACC
Max CE# Access Time, ns (t
)
70
70
70
Standby Mode (asynchronous)
CE
Max OE# Access Time, ns (t
)
11.2
11.2
13.5
OE
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V ) Per Word
40 µs
9.4 µs
6 µs
CC
Effective Write Buffer Programming (V
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
) Per Word
ACC
150 ms
600 ms
Publication Number S29WSxxxN_M0 Revision F Amendment 0 Issue Date November 4, 2004
P r e l i m i n a r y
1
Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 1.1. Input/Output Descriptions
Symbol
A23–A0
DQ15–DQ0
CE#
Type
Input
Description
Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N).
Data input/output.
I/O
Input
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
OE#
Input
WE#
Input
V
Supply
Input
Device Power Supply.
CC
V
VersatileIO Input. Should be tied to V
.
CC
IO
V
I/O
Ground.
SS
NC
No Connect
Output
Not connected internally.
RDY
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
CLK
Input
Input
increment the internal address counter. Should be at V or V while in asynchronous
IL IH
mode.
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
AVD#
When high, device ignores address inputs.
RESET#
WP#
Input
Input
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V , disables program and erase functions in the four outermost sectors.
IL
Should be at V for all other conditions.
IH
Acceleration Input. At V , accelerates programming; automatically places device in
HH
ACC
RFU
Input
unlock bypass mode. At V , disables all program and erase functions. Should be at V for
IL IH
all other conditions.
Reserved for future use (see MCP look-ahead pinout for use with MCP).
Reserved
16
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_M0F0 November 4, 2004
P r e l i m i n a r y
2 Block Diagram
DQ15–DQ0
VCC
VSS
VIO
RDY
Buffer
RDY
Input/Output
Buffers
Erase Voltage
Generator
WE#
RESET#
WP#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0*
*
WS256N: A23-A0
WS128N: A22-A0
WS064N: A21-A0
Figure 2.1. S29WSxxxN Block Diagram
November 4, 2004 S29WSxxxN_M0_F0
S29WSxxxN MirrorBit™ Flash Family
17
P r e l i m i n a r y
3 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical
support:
Email
US and Canada: HW.support@amd.com
Asia Pacific: asia.support@amd.com
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
November 4, 2004 S29WSxxxN_M0_F0
18
P r e l i m i n a r y
4 Product Overview
The S29WSxxxN family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/
write burst mode Flash device optimized for today’s wireless designs that demand a large
storage array, rich functionality, and low power consumption. These devices are organized in
16, 8 or 4 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read
or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These prod-
ucts also offer single word programming or a 32-word buffer for programming with program/
erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of secured silicon (SecSi™) area for storing customer and factory secured in-
formation. The SecSi Sector is One Time Programmable and Protectable (OTTP).
4.1 Memory Map
The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables 4.1–
4.3.
Table 4.1. S29WS256N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
Notes
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
32
2 MB
0
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SA004 to SA018
SA019 to SA034
SA035 to SA050
SA051 to SA066
SA067 to SA082
SA083 to SA098
SA099 to SA114
SA115 to SA130
SA131 to SA146
SA147 to SA162
SA163 to SA178
SA179 to SA194
SA195 to SA210
SA211 to SA226
SA227 to SA242
SA243 to SA257
SA258
010000h–01FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 7F0000h–7FFFFFh
800000h–80FFFFh to 8F0000h–8FFFFFh
900000h–90FFFFh to 9F0000h–9FFFFFh
A00000h–A0FFFFh to AF0000h–AFFFFFh
B00000h–B0FFFFh to BF0000h–BFFFFFh
C00000h–C0FFFFh to CF0000h–CFFFFFh
D00000h–D0FFFFh to DF0000h–DFFFFFh
E00000h–E0FFFFh to EF0000h–EFFFFFh
F00000h–F0FFFFh to FE0000h–FEFFFFh
FF0000h–FF3FFFh
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
2 MB
15
SA259
FF4000h–FF7FFFh
Contains four smaller sectors at
top of addressable memory.
4
32
SA260
FF8000h–FFBFFFh
SA261
FFC000h–FFFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
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Table 4.2. S29WS128N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
Notes
32
32
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
1 MB
32
0
SA002
008000h–00BFFFh
32
SA003
00C000h–00FFFFh
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
32
SA004 to SA010
SA011 to SA018
SA019 to SA026
SA027 to SA034
SA035 to SA042
SA043 to SA050
SA051 to SA058
SA059 to SA066
SA067 to SA074
SA075 to SA082
SA083 to SA090
SA091 to SA098
SA099 to SA106
SA107 to SA114
SA115 to SA122
SA123 to SA129
SA130
010000h–01FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 470000h–47FFFFh
480000h–48FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 570000h–57FFFFh
580000h–58FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 670000h–67FFFFh
680000h–68FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 770000h–77FFFFh
780000h–78FFFFh to 7E0000h–7EFFFFh
7F0000h–7F3FFFh
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
1 MB
32
15
SA131
7F4000h–7F7FFFh
Contains four smaller sectors at
top of addressable memory.
4
32
SA132
7F8000h–7FBFFFh
32
SA133
7FC000h–7FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
November 4, 2004 S29WSxxxN_M0_F0
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Table 4.3. S29WS064N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
000000h–003FFFh
Notes
SA000
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
32
SA002
008000h–00BFFFh
0.5 MB
0
SA003
00C000h–00FFFFh
SA004
010000h–01FFFFh
3
128
SA005
020000h–02FFFFh
SA006
030000h–03FFFFh
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
4
4
4
4
4
4
4
4
4
4
4
4
4
4
128
128
128
128
128
128
128
128
128
128
128
128
128
128
1
2
SA007–SA010
SA011–SA014
SA015–SA018
SA019–SA022
SA023–SA026
SA027–SA030
SA031–SA034
SA035–SA038
SA039–SA042
SA043–SA046
SA047–SA050
SA051–SA054
SA055–SA058
SA059–SA062
SA063
040000h–04FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0B0000h–0BFFFFh
0C0000h–0CFFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 130000h–13FFFFh
140000h–14FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1B0000h–1BFFFFh
1C0000h–1CFFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 230000h–23FFFFh
240000h–24FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2B0000h–2BFFFFh
2C0000h–2CFFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 330000h–33FFFFh
340000h–34FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3B0000h–3BFFFFh
3C0000h–3CFFFFh
3
4
5
6
All 128 KB sectors.
Pattern for sector address range is
xx0000h–xxFFFFh.
7
8
(see note)
9
10
11
12
13
14
3
128
SA064
3D0000h–3DFFFFh
SA065
3E0000h–3EFFFFh
0.5 MB
15
SA066
3F0000h–3F3FFFh
SA067
3F4000h–3F7FFFh
Contains four smaller sectors at top
of addressable memory.
4
32
SA068
3F8000h–3FBFFFh
SA069
3FC000h–3FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
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5 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, hand-
shaking, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables 10.1 and 10.2). The command register
itself does not occupy any addressable memory location; rather, it is composed of latches that
store the commands, along with the address and data information needed to execute the
command. The contents of the register serve as input to the internal state machine and the
state machine outputs dictate the function of the device. Writing incorrect address and data
values or writing them in an improper sequence may place the device in an unknown state,
in which case the system must write the reset command to return the device to the reading
array data mode.
5.1 Device Operation Table
The device must be setup appropriately for each operation. Table 5.4 describes the required
state of each control pin for any particular operation.
Table 5.4. Device Operations
Operation
CE#
L
OE#
L
WE#
Addresses
Addr In
Addr In
Addr In
Addr In
X
DQ15–0
Data Out
Data Out
I/O
RESET#
CLK
X
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
H
H
L
H
H
H
H
H
L
L
L
X
L
L
L
H
X
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
L
X
L
H
H
Addr In
X
X
H
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
X
X
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start new
Burst read cycle
L
X
H
Addr In
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
5.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation,
data is read from one memory location at a time. Addresses are presented to the device in
random order, and the propagation delay through the device causes the data on its outputs
to arrive asynchronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware
reset. To read data from the memory array, the system must first assert a valid address on
A
–A0, while driving AVD# and CE# to V . WE# should remain at V . The rising edge of
IL IH
max
AVD# latches the address and data will appear on DQ15–DQ0 after address access time
(t ), which is equal to the delay from stable addresses to valid output data. The chip enable
ACC
November 4, 2004 S29WSxxxN_M0_F0
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P r e l i m i n a r y
access time (t ) is the delay from the stable CE# to valid data at the outputs. The output
CE
enable access time (t ) is the delay from the falling edge of OE# to valid data at the output.
OE
5.3 Synchronous (Burst) Read Mode &
Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest
to highest address), the synchronous (or burst read) mode can be used to significantly reduce
the overall time needed for the device to output array data. After an initial access time re-
quired for the data from the first address location, subsequent data is output synchronized to
a clock input provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 5.3.1 and 5.3.2, and 5.3.3.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Regis-
ter settings include the number of wait states to insert before the initial word (t
) of each
IACC
burst access, the burst mode in which to operate, and when RDY will indicate data is ready
to be read. Prior to entering the burst mode, the system should first determine the configu-
ration register settings (and read the current register settings if desired via the Read
Configuration Register command sequence), and then write the configuration register com-
mand sequence. See Section 5.3.4, Configuration Register, and Table 10.1, Memory Array
Commands for further details.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 5.1. Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
t
specification: the time from the rising edge of the first clock cycle after addresses
IACC
are latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that t
lengthened.
is
IACC
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P r e l i m i n a r y
The device outputs subsequent words t
after the active edge of each successive clock cy-
BACC
cle, which also increments the internal address counter. The device outputs burst data at this
rate subject to the following operational conditions:
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-
ble-by-four address incurs the least number of additional wait states that occur after the
initial word. The number of additional wait states required increases for burst operations
in which the starting address is one, two, or three locations above the divisible-by-four
address (i.e., where A[1:0] is 01, 10, or 11).
boundary crossing: a physical aspect of the device that exists every 128 words, starting
at address 00007Fh. Higher operational speeds require one additional wait state. Refer to
Tables 5.10–5.13 for details. Figure 9.20 shows the effects of boundary crossings at higher
frequencies.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation. Tables 5.7–5.13
show the effects of frequency on burst operation.
In all cases, with or without latency, the RDY output indicates when the next data is available
to be read.
Table 5.5 shows the latency that occurs in the S29WS256N device when (x indicates the rec-
ommended number of wait states for various operating frequencies, as shown in Table 5.15,
configuration register bits CR13-CR11).
Tables 5.7–5.9 show the effects of various combinations of the starting address, operating
frequency, and wait state setting (configuration register bits CR13–CR11) for the S29WS128N
and S29WS064N devices. Tables 5.10–5.13 includes the wait state that occurs when crossing
the internal boundary.
Table 5.5. Address Latency for x Wait States (≤ 80 MHz, WS256N only)
Word
Wait States
Cycle
0
1
2
3
x ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
x ws
1 ws
1 ws
1 ws
D4
x ws
D3
1 ws
1 ws
D4
x ws
1 ws
D4
Table 5.6. Address Latency for 6 Wait States (≤ 80 MHz)
Word
Wait States
Cycle
0
1
2
3
6 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
6 ws
1 ws
1 ws
1 ws
D4
6 ws
D3
1 ws
1 ws
D4
6 ws
1 ws
D4
Table 5.7. Address Latency for 5 Wait States (≤ 68 MHz)
Word
Wait States
Cycle
0
1
2
3
5 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
5 ws
D5
5 ws
D3
1 ws
1 ws
D5
5 ws
1 ws
D5
November 4, 2004 S29WSxxxN_M0_F0
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P r e l i m i n a r y
Table 5.8. Address Latency for 4 Wait States (≤ 54 MHz)
Word
Wait States
Cycle
0
1
2
3
4 ws
D0
D1
D2
D3
D1
D2
D2
D3
D4
D4
D3
D4
D5
D5
D4
D5
D6
D7
D7
D6
D7
D8
D8
D7
D8
D9
D9
D8
D9
4 ws
D5
4 ws
D3
D6
D10
D10
4 ws
1 ws
D6
Table 5.9. Address Latency for 3 Wait States (≤ 40 MHz)
Word
Wait States
Cycle
0
1
2
3
3 ws
D0
D1
D2
D3
D1
D2
D3
D4
D2
D3
D4
D5
D3
D4
D5
D6
D4
D5
D6
D7
D8
D6
D7
D8
D9
D7
D8
D8
D9
3 ws
D5
3 ws
D6
D9
D10
D11
3 ws
D7
D10
Table 5.10. Address/Boundary Crossing Latency for 6 Wait States (≤ 80 MHz)
Word
Wait States
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
6 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
6 ws
1 ws
1 ws
1 ws
6 ws
D3
1 ws
1 ws
6 ws
1 ws
Table 5.11. Address/Boundary Crossing Latency for 5 Wait States (≤ 68 MHz)
Word
Wait States
Cycle
0
1
2
3
5 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
5 ws
1 ws
1 ws
1 ws
D4
5 ws
D3
1 ws
1 ws
D4
5 ws
1 ws
D4
Table 5.12. Address/Boundary Crossing Latency for 4 Wait States (≤ 54 MHz)
Word
Wait States
Cycle
0
1
2
3
4 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
4 ws
D5
4 ws
D3
1 ws
1 ws
D5
4 ws
1 ws
D5
Table 5.13. Address/Boundary Crossing Latency for 3 Wait States (≤ 40 MHz)
Word
Wait States
Cycle
0
1
2
3
3 ws
D0
D1
D2
D3
D1
D2
D2
D3
D4
D4
D3
D4
D5
D5
D4
D5
D6
D7
D7
D6
D7
D8
D8
D7
D8
D9
D9
D8
D9
3 ws
D5
3 ws
D3
D6
D10
D10
3 ws
1 ws
D6
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S29WSxxxN_M0_F0 November 4, 2004
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
CR13-CR11 sets initial access time
(from address latched to
Wait tIACC
+
Programmable Wait State Setting
valid data) from 2 to 7 clock cycles
Read Initial Data
RD = DQ[15:0]
RD = Read Data
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
See Tables 5.6–5.13 to determine total
number of clocks required for X.
Read Next Data
RD = DQ[15:0]
Delay X Clocks
Crossing
No
End of Data?
Boundary?
Yes
Yes
Completed
Figure 5.2. Synchronous Read
5.3.1 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addres-
sable memory location. The burst read mode will continue until the system drives CE# high,
RESET# low, or AVD# low in conjunction with a new address.
If the address being read crosses a 128-word line boundary and the subsequent word line is
not programming or erasing, additional latency cycles are required as shown in Tables 5.10–
5.13.
If the address crosses a bank boundary while the subsequent bank is programming or eras-
ing, the device will provide read status information and the clock will be ignored. Upon
completion of status read or program or erase operation, the host can restart a burst read
operation using a new address and AVD# pulse.
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5.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from
consecutive addresses that are determined by the group within which the starting address
falls. The groups are sized according to the number of words read in a single burst sequence
for a given mode (see Table 5.14).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the
device outputs all words in that burst address group until all word are read, regardless of
where the starting address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence
on the starting address written to the device, then wrap back to the first address in the se-
lected address group.
Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no wait states are inserted (except during the initial access).
Table 5.14. Burst Address Groups
Mode
Group Size
8 words
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
16 words
32 words
5.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-
word burst will execute up to the maximum memory address of the selected number of words.
The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address
of the selected group.
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap
around is not enabled. The next address to be read will require a new address and AVD#
pulse. Note that in this burst read mode, the address pointer may cross the boundary that
occurs every 128 words.
5.3.4 Configuration Register
The configuration register sets various operational features, most of which are associated
with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous
read mode, and the configuration register settings are in their default state. The host system
should determine the proper settings for the entire configuration register, and then execute
the Set Configuration Register command sequence, before attempting burst operations. The
configuration register is not reset after deasserting CE#. The Configuration Register can also
be read using a command sequence (see Table 10.1). The following list describes the register
settings.
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Table 5.15. Configuration Register
CR Bit
Function
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
CR15
Set Device Read Mode
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
CR14
Boundary Crossing
Must be set to “1” at higher operating frequencies. See Tables 5.10–5.13.
000 = Data valid on 2nd active CLK edge after addresses latched
001 = Data valid on 3rd active CLK edge after addresses latched
010 = Data valid on 4th active CLK edge after addresses latched (recommended for 54 MHz)
011 = Data valid on 5th active CLK edge after addresses latched (recommended for 66 MHz)
100 = Data valid on 6th active CLK edge after addresses latched (recommended for 80 MHz)
101 = Data valid on 7th active CLK edge after addresses latched (default)
110 = Reserved
CR13
CR12
CR11
Programmable
Wait State
111 = Reserved
Inserts wait states before initial data is available. Setting greater number of wait states before initial data
reduces latency after initial data. See Tables 5.6–5.13.
0 = RDY signal active low
1 = RDY signal active high (default)
CR10
CR9
RDY Polarity
Reserved
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
CR8
RDY
When CR13-CR11 are set to 000, RDY will be active with data regardless of CR8 setting.
CR7
CR6
CR5
CR4
Reserved
Reserved
Reserved
Reserved
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR3
Burst Wrap Around
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR2
CR1
CR0
Burst Length
Note: Configuration Register will be in the default state upon power-up or hardware reset.
Reading the Configuration Table. The configuration register can be read with a four-cycle
command sequence. See Table 10.1 for sequence details. Once the data has been read from
the configuration register, a software reset command is required to set the device into the
correct state.
5.4 Autoselect
The Autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output from the internal register (separate from the
memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment
to automatically match a device to be programmed with its corresponding programming al-
gorithm. The Autoselect codes can also be accessed in-system. When verifying sector
protection, the sector address must appear on the appropriate highest order address bits (see
Tables 5.17 to 5.16). The remaining address bits are don't care. When all necessary bits have
been set as required, the programming equipment may then read the corresponding identifier
code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the com-
mand register. Note that if a Bank Address (BA) on the four uppermost address bits is
asserted during the third write cycle of the Autoselect command, the host system can read
Autoselect data from that bank and then immediately read array data from the other bank,
without exiting the Autoselect mode.
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To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a bank that is
either in the read or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or
erasing in the other bank. Autoselect does not support simultaneous operations or burst
mode.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).
See Table 10.1 for command sequence details.
Table 5.16. Autoselect Addresses
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data
(BA) + 00h 0001h
(BA) + 01h 227Eh
2230 (WS256N)
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh 2231 (WS128N)
2232 (WS064N)
(BA) + 0Fh 2200
DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
Indicator Bits
(See Note)
(BA) + 03h
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled
Sector Block Lock/
Unlock
(SA) + 02h 0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 will be reserved.
Software Functions and Sample Code
Table 5.17. Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Write
Byte Address
BAxAAAh
BAx555h
Word Address
BAx555h
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
0x00AAh
0x0055h
0x0090h
Write
BAx2AAh
Write
BAxAAAh
BAx555h
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Table 5.18. Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Write
Byte Address
Word Address
base + XXXh
Data
Unlock Cycle 1
base + XXXh
0x00F0h
Notes:
1. Any offset within the device will work.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manu-
facturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software develop-
ment guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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5.5 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which
are described in details during the following sections. However, prior to any programming and
or erase operation, devices must be setup appropriately as outlined in Table 5.4.
During a synchronous write operation, to write a command or command sequence (which in-
cludes programming data to the device and erasing sectors of memory), the system must
drive AVD# and CE# to V , and OE# to V when providing an address to the device, and
IL
IH
drive WE# and CE# to V , and OE# to V when writing commands or data.
IL
IH
During an asynchronous write operation, the system must drive CE# and WE# to V and OE#
IL
to V when providing an address, command, and data. Addresses are latched on the last fall-
IH
ing edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#.
Note the following:
When the Embedded Program algorithm is complete, the device then returns to the read
mode.
The system can determine the status of the program operation by using DQ7 or DQ6.
Refer to the Write Operation Status section for information on these status bits.
A “0” cannot be programmed back to a “1.” Attempting to do so will cause the device to
set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding
read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program Algorithm are ig-
nored except the Program Suspend command.
SecSi Sector, Autoselect, and CFI functions are unavailable when a program operation is
in progress.
A hardware reset immediately terminates the program operation and the program com-
mand sequence should be reinitiated once the device has returned to the read mode, to
ensure data integrity.
Programming is allowed in any sequence and across sector boundaries for single word
programming operation.
Programming to the same word address multiple times without intervening erases is lim-
ited. For such application requirements, please contact your local Spansion representa-
tive.
5.5.1. Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four
Flash command write cycles are used to program an individual Flash address. The data for
this programming operation could be 8-, 16- or 32-bits wide. While this method is supported
by all Spansion devices, in general it is not recommended for devices that support Write
Buffer Programming. See Table 10.1 for the required bus cycles and Figure 5.19 for the
flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read
mode and addresses are no longer latched. The system can determine the status of the pro-
gram operation by using DQ7 or DQ6. Refer to the Write Operation Status section for
information on these status bits.
During programming, any command (except the Suspend Program command) is ignored.
The SecSi Sector, Autoselect, and CFI functions are unavailable when a program opera-
tion is in progress.
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A hardware reset immediately terminates the program operation. The program command
sequence should be reinitiated once the device has returned to the read mode, to ensure
data integrity.
Programming to the same address multiple times continuously (for example, “walking” a
bit within a word) for an extended period is not recommended. For more information,
contact your local sales office.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 5.19. Single Word Program
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Software Functions and Sample Code
Table 5.20. Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
5.5.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one pro-
gramming operation. This results in a faster effective word programming time than the
standard “word” programming algorithms. The Write Buffer Programming command se-
quence is initiated by first writing two unlock cycles. This is followed by a third write cycle
containing the Write Buffer Load command written at the Sector Address in which program-
ming will occur. At this point, the system writes the number of “word locations minus 1” that
will be loaded into the page buffer at the Sector Address in which programming will occur.
This tells the device how many write buffer addresses will be loaded with data and therefore
when to expect the “Program Buffer to Flash” confirm command. The number of locations to
program cannot exceed the size of the write buffer or the operation will abort. (Number
loaded = the number of locations to program minus 1. For example, if the system will pro-
gram 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the
first address/data pair to be programmed, and selects the “write-buffer-page” address. All
subsequent address/data pairs must fall within the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses A
- A5.
MAX
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into
the write buffer. (This means Write Buffer Programming cannot be performed across multiple
“write-buffer-pages.” This also means that Write Buffer Programming cannot be performed
across multiple sectors. If the system attempts to load programming data outside of the se-
lected “write-buffer-page”, the operation will ABORT.)
After writing the Starting Address/Data pair, the system then writes the remaining address/
data pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair”
counter will be decremented for every data load operation. Also, the last data loaded at a lo-
cation before the “Program Buffer to Flash” confirm command will be programmed into the
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device. It is the software's responsibility to comprehend ramifications of loading a write-buffer
location more than once. The counter decrements for each data load operation, NOT for each
unique write-buffer-address location. Once the specified number of write buffer locations
have been loaded, the system must then write the “Program Buffer to Flash” command at the
Sector Address. Any other address/data write combinations will abort the Write Buffer Pro-
gramming operation. The device will then “go busy.” The Data Bar polling techniques should
be used while monitoring the last address location loaded into the write buffer. This eliminates
the need to store an address in memory because the system can load the last address loca-
tion, issue the program confirm command at the last loaded address location, and then data
bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to deter-
mine the device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard
suspend/resume commands. Upon successful completion of the Write Buffer Programming
operation, the device will return to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to
Program” step.
Write to an address in a sector different than the one specified during the Write-Buffer-
Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
“Starting Address” during the “write buffer data loading” stage of the operation.
Write data other than the “Confirm Command” after the specified number of “data load”
cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location
loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Oper-
ation was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is required when
using the write buffer Programming features in Unlock Bypass mode. Note that the SecSITM
sector, autoselect, and CFI functions are unavailable when a program operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations.
These flash devices are capable of handling multiple write buffer programming operations on
the same write buffer address range without intervening erases. However, programming the
same word address multiple times without intervening erases requires a modified program-
ming method. Please contact your local SpansionTM representative for details.
Use of the write buffer is strongly recommended for programming when multiple words are
to be programmed. Write buffer programming is approximately eight times faster than pro-
gramming one word at a time.
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Software Functions and Sample Code
Table 5.21. Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Word Address
Base + 555h
Base + 2AAh
Data
00AAh
1
2
3
4
Unlock
Write
0055h
Write Buffer Load Command
Write Word Count
Write
Program Address
Program Address
0025h
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of
words written, the total number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with
the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
UINT16 wc
= words_to_program -1;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
wc--;
goto loop;
/* done when word count equals zero */
/* decrement word count
/* do it again
*/
*/
confirm:
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA 29h
Wait 4 µs
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
No
Write Buffer
Abort Desired?
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write to a Different
Sector Address to Cause
Write Buffer Abort
Yes
Polling Status
= Done?
No
Error?
Yes
No
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 5.22. Write Buffer Programming Operation
5.5.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 10.1,
Memory Array Commands; and Figure 5.24, Sector Erase Operation.) The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automati-
cally programs and verifies the entire memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than t
occurs.
SEA
During the time-out period, additional sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any sequence, and the number of
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sectors may be from one sector to all sectors. The time between these additional cycles must
be less than t
. Any sector erase address and command following the exceeded time-out
SEA
(t
) may or may not be accepted. Any command other than Sector Erase or Erase Suspend
SEA
during the time-out period resets that bank to the read mode. The system can monitor DQ3
to determine if the sector erase timer has timed out (See the “DQ3: Sector Erase Timer” sec-
tion.) The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and
addresses are no longer latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing banks. The system can determine
the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to
“Write Operation Status” for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All
other commands are ignored. However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase command sequence should be reinitiated
once that bank has returned to reading array data, to ensure data integrity.
Figure 5.24 illustrates the algorithm for the erase operation. Refer to the “Erase/Program Op-
erations” section for parameters and timing diagrams.
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Software Functions and Sample Code
Table 5.23. Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Sector Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0030h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors may be selected for erase; command(s) must be written within t
.
SEA
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
(see Figure 5.33)
Yes
Done?
No
No
Error condition (Exceeded Timing Limits)
DQ5 = 1?
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Notes:
1. See Table 10.1 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
Figure 5.24. Sector Erase Operation
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5.5.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 10.1. These commands invoke
the Embedded Erase algorithm, which does not require the system to preprogram prior to
erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The “Command Definition” section
in the appendix shows the address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and
addresses are no longer latched. The system can determine the status of the erase operation
by using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status
bits.
Any commands written during the chip erase operation are ignored. However, note that a
hardware reset immediately terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
Software Functions and Sample Code
Table 5.25. Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0010h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Chip Erase Command
Write
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
5.5.5 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. The bank ad-
dress is required when writing this command. This command is valid only during the sector
erase operation, including the minimum t
time-out period during the sector erase com-
SEA
mand sequence. The Erase Suspend command is ignored if written during the chip erase
operation.
When the Erase Suspend command is written during the sector erase operation, the device
requires a maximum of t
(erase suspend latency) to suspend the erase operation. How-
ESL
November 4, 2004 S29WSxxxN_M0_F0
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ever, when the Erase Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read
mode. The system can read data from or program data to any sector not selected for erasure.
(The device “erase suspends” all sectors selected for erasure.) Reading at any address within
erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7,
or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
Refer to Table 5.35 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-sus-
pend-read mode. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command se-
quence. Refer to the “Write Buffer Programming Operation” section and the “Autoselect
Command Sequence” section for details.
To resume the sector erase operation, the system must write the Erase Resume command.
The bank address of the erase-suspended bank is required when writing this command. Fur-
ther writes of the Resume command are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
Software Functions and Sample Code
Table 5.26. Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 5.27. Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Word Address
Bank Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
5.5.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming
operation or a “Write to Buffer” programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming
process, the device halts the programming operation within t
(program suspend latency)
PSL
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and updates the status bits. Addresses are “don't-cares” when writing the Program Suspend
command.
After the programming operation has been suspended, the system can read array data from
any non-suspended sector. The Program Suspend command may also be issued during a pro-
gramming operation while an erase is suspended. In this case, data may be read from any
addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sec-
tor area, then user must use the proper command sequences to enter and exit this region.
The system may also write the Autoselect command sequence when the device is in Program
Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since
the codes are not stored in the memory array. When the device exits the Autoselect mode,
the device reverts to Program Suspend mode, and is ready for another valid operation. See
“Autoselect Command Sequence” for more information.
After the Program Resume command is written, the device reverts to programming. The sys-
tem can determine the status of the program operation using the DQ7 or DQ6 status bits, just
as in the standard program operation. See “Write Operation Status” for more information.
The system must write the Program Resume command (address bits are “don't care”) to exit
the Program Suspend mode and continue the programming operation. Further writes of the
Program Resume command are ignored. Another Program Suspend command can be written
after the device has resumed programming.
Software Functions and Sample Code
Table 5.28. Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 5.29. Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Byte Address
Word Address
Bank Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
5.5.7 Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip
erase operations are enabled through the ACC function. This method is faster than the stan-
dard chip program and erase command sequences.
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The accelerated chip program and erase functions must not be used more than 10
times per sector. In addition, accelerated chip program and erase should be performed at
room temperature (25°C 10°C).
If the system asserts V
on this input, the device automatically enters the aforementioned
HH
Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be
used to reset the device. Removing V
from the ACC input, upon completion of the embed-
HH
ded program or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to V
.
HH
The ACC pin must not be at V
for operations other than accelerated programming and
HH
accelerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
t
locks all sector if set to V ; t
should be set to V for all other conditions.
ACC IH
ACC
IL
5.5.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the
device enters the Unlock Bypass mode, only two write cycles are required to program data,
instead of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming time. The “Command Definition
Summary” section shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass
Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle must contain the bank address
and the data 90h. The second cycle need only contain the data 00h. The bank then returns
to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on
www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory
software development guidelines.
Table 5.30. Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Unlock
Operation
Write
Write
Write
*/
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
00AAh
0055h
0020h
Unlock
Entry Command
/* Example: Unlock Bypass Entry Command
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
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Table 5.31. Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Write
Byte Address
Base + xxxh
Word Address
Base +xxxh
Data
00A0h
1
2
Program Setup Command
Program Command
Write
Program Address
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Table 5.32. Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Byte Address
Base + xxxh
Base + xxxh
Word Address
Base +xxxh
Base +xxxh
Data
1
2
0090h
0000h
Write
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
5.5.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an
Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence. Note that the Data# Polling is valid only for the last word being programmed
in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on
any word other than the last word to be programmed in the write-buffer-page will return false
status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the program address to read valid status in-
formation on DQ7. If a program address falls within a protected sector, Data# polling on DQ7
is active for approximately t , then that bank returns to the read mode.
PSP
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Em-
bedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. The system must provide an address within any of the sectors
selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately t , then the bank returns to the read
ASP
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the un-
protected sectors, and ignores the selected sectors that are protected. However, if the system
reads DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data on DQ7. Depending on when the
November 4, 2004 S29WSxxxN_M0_F0
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P r e l i m i n a r y
system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-
DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
See the following for more information: Table 5.35, Write Operation Status, shows the out-
puts for Data# Polling on DQ7. Figure 5.33, Write Operation Status Flowchart, shows the
Data# Polling algorithm; and Figure 9.16, Data# Polling Timings
(During Embedded Algorithm), shows the Data# Polling timing diagram.
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START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 5.33. Write Operation Status Flowchart
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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase
algorithm is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior to the program or erase opera-
tion), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected,
DQ6 toggles for approximately t
[all sectors protected toggle time], then returns to read-
ASP
ing array data. If not all selected sectors are protected, the Embedded Erase algorithm erases
the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing
or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase al-
gorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6
stops toggling. However, the system must also use DQ2 to determine which sectors are eras-
ing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately t
the program command sequence is written, then returns to reading array data.
after
PAP
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Em-
bedded Program Algorithm is complete.
See the following for additional information: Figure 5.33, Write Operation Status Flowchart;
Figure 9.17, Toggle Bit Timings (During Embedded Algorithm), and Tables 5.34 and 5.35.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II . The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a
particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or
whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final
WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 5.34 to compare outputs for DQ2 and DQ6. See the following for additional in-
formation: Figure 5.33, the “DQ6: Toggle Bit I” section, and Figures 9.16–9.19.
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Table 5.34. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
toggles,
toggles,
also toggles.
does not toggle.
toggles.
actively erasing,
erase suspended,
at an address within sectors not
selected for erasure,
at an address within a sector
selected for erasure,
does not toggle,
returns array data. The system can
read from any sector not selected for
erasure.
at an address within sectors not
returns array data,
toggles,
selected for erasure,
programming in
erase suspend
at any address,
is not applicable.
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program or erases
operation. The system can read array data on DQ7–DQ0 on the following read cycle. However,
if after the initial two read cycles, the system determines that the toggle bit is still toggling,
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it
is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or erases operation. If it is still toggling,
the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data. The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has not gone high. The system may con-
tinue to monitor the toggle bit and DQ5 through successive read cycles, determining the
status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation. Refer to Figure 5.33 for more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has ex-
ceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,”
indicating that the program or erase cycle was not successfully completed. The device may
output a “1” on DQ5 if the system tries to program a “1” to a location that was previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this con-
dition, the device halts the operation, and when the timing limit has been exceeded, DQ5
produces a “1.”Under both these conditions, the system must write the reset command to re-
turn to the read mode (or to the erase-suspend-read mode if a bank was previously in the
erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command se-
quence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are se-
lected for erasure, the entire time-out also applies after each additional sector erase
command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less
than t
, the system need not monitor DQ3. See Sector Erase Command Sequence for more
SEA
details.
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After the sector erase command is written, the system should read the status of DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence,
and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further com-
mands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is
“0,” the device will accept additional sector erase commands. To ensure the command has
been accepted, the system software should check the status of DQ3 prior to and following
each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. Table 5.35 shows the status of DQ3 relative to the
other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort
Reset command sequence to return the device to reading array data. See Write Buffer Pro-
gramming Operation for more details.
Table 5.35. Write Operation Status
DQ7
DQ5
DQ2
DQ1
Status
(Note 2)
DQ6
Toggle
Toggle
INVALID
(Note 1)
DQ3
N/A
(Note 2)
(Note 4)
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
0
0
No toggle
Toggle
0
Standard
Mode
1
N/A
INVALID
INVALID
INVALID
INVALID
INVALID
Program
Suspend
Mode
Reading within Program Suspended Sector
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Reading within Non-Program Suspended
Sector
(Note 3)
Data
1
Data
No toggle
Data
Data
0
Data
N/A
Data
Toggle
Data
Data
N/A
Erase
Suspended Sector
Erase-Suspend-
Erase
Suspend
Mode
Read
Non-Erase Suspended
Data
Data
Data
Data
Sector
Erase-Suspend-Program
BUSY State
DQ7#
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
Toggle
0
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
Write to
Buffer
(Note 5)
Exceeded Timing Limits
ABORT State
0
1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming
indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
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5.6 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of
memory while programming or erasing another bank of memory. An erase operation may also
be suspended to read from or program another location within the same bank (except the
sector being erased). Figure 9.23, Back-to-Back Read/Write Cycle Timings, shows how read
and write cycles may be initiated for simultaneous operation with zero latency. Refer to the
DC Characteristics (CMOS Compatible) table for read-while-program and read-while-erase
current specification.
5.7 Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device
is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# in-
duced address latches are supported in the Synchronous programming mode. During a
synchronous write operation, to write a command or command sequence (which includes pro-
gramming data to the device and erasing sectors of memory), the system must drive AVD#
and CE# to V , and OE# to V when providing an address to the device, and drive WE# and
IL
IH
CE# to V , and OE# to V when writing commands or data. During an asynchronous write
IL
IH
operation, the system must drive CE# and WE# to V and OE# to V when providing an
IL
IH
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#,
while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one
sector, multiple sectors, or the entire device. Tables 4.1–4.3 indicate the address space that
each sector occupies. The device address space is divided into sixteen banks: Banks 1
through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot
sectors in addition to 64 Kword sectors. A “bank address” is the set of address bits required
to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely
select a sector. I
in “DC Characteristics” represents the active current specification for the
CC2
write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asynchronous” con-
tain timing specification tables and timing diagrams for write operations.
5.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by
simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the
initial word of burst data becomes available after either the falling or rising edge of the RDY
pin (depending on the setting for bit 10 in the Configuration Register). It is recommended
that the host system set CR13–CR11 in the Configuration Register to the appropriate number
of wait states to ensure optimal burst mode operation (see Table 5.15, Configuration
Register).
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
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5.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t , the device immediately terminates any
RP
operation in progress, tristates all outputs, resets the configuration register, and ignores all
read/write commands for the duration of the RESET# pulse. The device also resets the inter-
nal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence.
When RESET# is held at V , the device draws CMOS standby current (I
). If RESET# is
SS
CC4
held at V , but not at V , the standby current will be greater.
IL
SS
RESET# may be tied to the system reset circuitry which enables the system to read the boot-
up firmware from the Flash memory upon a system reset.
See Figures 9.5 and 9.12 for timing diagrams.
5.10 Software Reset
Software reset is part of the command set (see Table 10.1) that also returns the device to
array read mode and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle
was not successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend
mode.
5. after any aborted operations
Software Functions and Sample Code
Table 5.36. Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is
complete
The reset command may be written between the cycles in a program command sequence
before programming begins (prior to the third cycle). This resets the bank to which the
system was writing to the read mode.
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If the program command sequence is written to a bank that is in the Erase Suspend
mode, writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the
reset command returns that bank to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write
the "Write to Buffer Abort Reset" command sequence to RESET the device to reading
array data. The standard RESET command will not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset
command sequence [see command table for details].
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6 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or
erase operations in any or all sectors and can be implemented through software and/or hard-
ware methods, which are independent of each other. This section describes the various
methods of protecting data stored in the memory array. An overview of these methods in
shown in Figure 6.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
(DQ1)
Password Method
(DQ2)
(
WP# = V
IL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(PPB)6,7,8
Memory Array
Sector 0
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector 1
Sector 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N3
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 6.1. Advanced Sector Protection/Unprotection
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6.1 Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied,
and all sectors are unprotected, unless otherwise chosen through the DYB ordering option.
The device programmer or host system must then choose which sector protection method to
use. Programming (setting to “0”) any one of the following two one-time programmable, non-
volatile bits locks the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 6.1. Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
Customer
SecSi Sector
Protection Bit
S29WS256N
1
1
1
DYB Lock Boot Bit
PPB One-Time
0 = sectors
power up
protected
Programmable Bit
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
S29WS128N/
S29WS064N
0 = All PPB erase
command disabled
SecSi Sector
Protection Bit
Undefined
1 = sectors
power up
unprotected
1 = All PPB Erase
command enabled
For programming lock register bits refer to Table 10.2.
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
will abort.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following
three states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed
unless PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 6.2–6.6.
6.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same
endurances as the Flash memory. Preprogramming and verification prior to erasure are han-
dled by the device, and therefore do not require system monitoring.
Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. Entry command disables reads and writes for the bank selected.
3. Reads within that bank will return the PPB status for that sector.
4. Reads from other banks are allowed while writes are not allowed.
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5. All Reads must be performed using the Asynchronous mode.
6. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N)
are written at the same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase command will not execute and will
time-out without programming or erasing the PPB.
8. There are no means for individually erasing a specific PPB and no specific sector address
is required for this operation.
9. Exit command must be issued after the execution which resets the device to read mode
and re-enables reads and writes for Bank 0
10. The programming state of the PPB for a given sector can be verified by writing a PPB
Status Read Command to the device as described by the flow chart below.
6.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually mod-
ified. DYBs only control the protection scheme for unprotected sectors that have their PPBs
cleared (erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs will
be set (programmed to “0”) or cleared (erased to “1”), thus placing each sector in the pro-
tected or unprotected state respectively. This feature allows software to easily protect sectors
against inadvertent changes yet does not prevent the easy removal of protection when
changes are needed.
Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or
reset, the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectors
may be modified depending upon the PPB state of that sector (see Table 6.2).
3. The sectors would be in the protected state If the option to set the DYBs after power up
is chosen (programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unpro-
tectedstate of the sectors respectively. However, if there is a need to change the status
of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit
must be cleared by either putting the device through a power-cycle, or hardware reset.
The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit
once again will lock the PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set com-
mand early in the boot code and protect the boot code by holding WP# = V . Note that
IL
the PPB and DYB bits have the same function when ACC = V
as they do when ACC
HH
=V .
IH
6.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (pro-
grammed to “0”), this bit locks all PPB and when cleared (programmed to “1”), unlocks each
sector. There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password
protection mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to
the desired settings.
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6.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent
Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit.
In addition to this password requirement, after power up and reset, the PPB Lock Bit is set
“0” to maintain the password mode of operation. Successful execution of the Password Unlock
command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs
modifications.
Notes
1. There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set in order to
prevent access.
2. The Password Program Command is only capable of programming “0”s. Programming a
“1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the
data bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Pro-
gram, and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to pre-
vent a hacker from running through all the 64-bit combinations in an attempt to
correctly match a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password
is given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are
ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear
the PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables
reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are
allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the com-
mand and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns
to read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by
writing individual status read commands DYB Status, PPB Status, and PPB Lock Status
to the device.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
* Not on future devices
Program Data (PD): See text for Lock Register
definitions
Caution: Lock data may only be progammed once.
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 6.2. Lock Register Program Algorithm
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6.6 Advanced Sector Protection Software Examples
Table 6.2. Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Table 6.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the
status of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the
PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware
reset or power cycle. See also Figure 6.1 for an overview of the Advanced Sector Protection
feature.
6.7 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at V , the four outermost sectors are locked (device specific).
IL
When ACC is at V , all sectors are locked.
IL
There are additional methods by which intended or accidental erasure of any sectors can be
prevented via hardware means. The following subsections describes these methods:
6.7.1. WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sec-
tors. This function is provided by the WP# pin and overrides the previously discussed Sector
Protection/Unprotection method.
If the system asserts V on the WP# pin, the device disables program and erase functions in
IL
the “outermost” boot sectors. The outermost boot sectors are the sectors containing both the
lower and upper set of sectors in a dual-boot-configured device.
If the system asserts V on the WP# pin, the device reverts to whether the boot sectors were
IH
last set to be protected or unprotected. That is, sector protection or unprotection for these
sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of
the device may result.
The WP# pin must be held stable during a command sequence execution
6.7.2 ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to V ,
IL
all program and erase functions are disabled and hence all sectors are protected.
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6.7.3 Low VCC Write Inhibit
When V is less than V , the device does not accept any write cycles. This protects data
CC
LKO
during V power-up and power-down.
CC
The command register and all internal program/erase circuits are disabled, and the device
resets to reading array data. Subsequent writes are ignored until V
is greater than V
.
CC
LKO
The system must provide the proper signals to the control inputs to prevent unintentional
writes when V is greater than V
.
LKO
CC
6.7.4 Write Pulse “Glitch Protection”
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
6.7.5 Power-Up Write Inhibit
If WE# = CE# = RESET# = V and OE# = V during power up, the device does not accept
IL
IH
commands on the rising edge of WE#. The internal state machine is automatically reset to
the read mode on power-up.
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7 Power Conservation Modes
7.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE# input. The device enters the CMOS
standby mode when the CE# and RESET# inputs are both held at V
± 0.2 V. The device
CC
requires standard access time (t ) for read access, before it is ready to read data. If the de-
CE
vice is deselected during erasure or programming, the device draws active current until the
operation is completed. I
specification
in “DC Characteristics” represents the standby current
CC3
7.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for t
+
ACC
20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to the system. While in synchronous
mode, the automatic sleep mode is disabled. Note that a new burst operation is required to
provide new data. I
specification.
in “DC Characteristics” represents the automatic sleep mode current
CC6
7.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t , the device immediately terminates any
RP
operation in progress, tristates all outputs, resets the configuration register, and ignores all
read/write commands for the duration of the RESET# pulse. The device also resets the inter-
nal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence to ensure data
integrity.
When RESET# is held at V ± 0.2 V, the device draws CMOS standby current (I
). If RE-
SS
CC4
SET# is held at V but not within V ± 0.2 V, the standby current will be greater.
IL
SS
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
7.4 Output Disable (OE#)
When the OE# input is at V , output from the device is disabled. The outputs are placed in
IH
the high impedance state.
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8 SecSiTM (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector provides an extra Flash memory region that enables per-
manent part identification through an Electronic Serial Number (ESN). The SecSi Sector is
256 words in length that consists of 128 words for factory data and 128 words for customer-
secured areas. All SecSi reads outside of the 256-word address range will return invalid data.
The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not
the Factory SecSi Sector is locked when shipped from the factory. The Customer Indicator Bit
(DQ6) is used to indicate whether or not the Customer SecSi Sector is locked when shipped
from the factory.
Please note the following general conditions:
While SecSi Sector access is enabled, simultaneous operations are allowed except for
Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to
the normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
Burst mode reads within SecSi Sector will wrap from address FFh back to address 00h.
Reads outside of sector 0 will return memory array data.
Continuous burst read past the maximum address is undefined.
Sector 0 is remapped from memory array to SecSi Sector array.
Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command must
be issued to exit SecSi Sector Mode.
The SecSi Sector is not accessible when the device is executing an Embedded Program
or Embedded Erase algorithm.
Table 8.1. SecSiTM Sector Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
8.1 Factory SecSiTM Sector
The Factory SecSi Sector is always protected when shipped from the factory and has the Fac-
tory Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to
the field.
These devices are available pre programmed with one of the following:
A random, 8 Word secure ESN only within the Factory SecSi Sector
Customer code within the Customer SecSi Sector through the SpansionTM programming
service.
Both a random, secure ESN and customer code through the Spansion programming ser-
vice.
Customers may opt to have their code programmed through the Spansion programming ser-
vices. Spansion programs the customer's code, with or without the random ESN. The devices
are then shipped from the Spansion factory with the Factory SecSi Sector and Customer SecSi
Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
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8.2 Customer SecSiTM Sector
The Customer SecSi Sector is typically shipped unprotected (DQ6 set to “0”), allowing cus-
tomers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer SecSi Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Customer SecSi Sector area is protected, the Customer Indicator Bit will be per-
manently set to “1.”
The Customer SecSi Sector can be read any number of times, but can be programmed
and locked only once. The Customer SecSi Sector lock must be used with caution as once
locked, there is no procedure available for unlocking the Customer SecSi Sector area and
none of the bits in the Customer SecSi Sector memory space can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when
programming the Customer SecSi Sector, but reading in Banks 1 through 15 is available.
Once the Customer SecSi Sector is locked and verified, the system must write the Exit
SecSi Sector Region command sequence which return the device to the memory array at
sector 0.
8.3 SecSiTM Sector Entry and SecSi Sector Exit
Command Sequences
The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access the SecSi Sector region until the system
issues the four-cycle Exit SecSi Sector command sequence.
See Command Definition Table [SecSiTM Sector Command Table, Appendix
Table 10.1 for address and data requirements for both command sequences.
The SecSi Sector Entry Command allows the following commands to be executed
Read customer and factory SecSi areas
Program the customer SecSi Sector
After the system has written the Enter SecSi Sector command sequence, it may read the
SecSi Sector by using the addresses normally occupied by sector SA0 within the memory ar-
ray. This mode of operation continues until the system issues the Exit SecSi Sector command
sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the SecSi Sector Entry, Pro-
gram, and exit commands. Refer to the Spansion Low Level Driver User’s Guide (available
soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash
memory software development guidelines.
Table 8.2. SecSi Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0088h
Write
Entry Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Entry Command */
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*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 8.3. SecSi Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Table 8.4. SecSi Sector Entry
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0090h
Write
Exit Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
*/
*/
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9 Electrical Specifications
9.1 Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or
I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9.1.
Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions
outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 9.2.
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9.1. Maximum DC
voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+0.8 V
+2.0 V
VCC
+0.5 V
–0.5 V
–2.0 V
1.0 V
20 ns
20 ns
20 ns
Figure 9.1. Maximum Negative Overshoot
Waveform
Figure 9.2. Maximum Positive Overshoot
Waveform
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9.2 Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
(Contact local sales office for VIO = 1.35 to +1.70 V.)
Notes: Operating ranges define those limits between which the functionality of the device
is guaranteed.
9.3 Test Conditions
Device
Under
Test
C
L
Figure 9.3. Test Setup
Table 9.1. Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
3.0 @ 54, 66 MHz
2.5 @ 80 MHz
Input Rise and Fall Times
Input Pulse Levels
ns
0.0–VIO
VIO/2
V
V
Input timing measurement
reference levels
Output timing measurement
reference levels
VIO/2
V
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9.4 Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
9.5 Switching Waveforms
VIO
All Inputs and Outputs
VIO/2
VIO/2
Input
Measurement Level
Output
0.0 V
Figure 9.4. Input Waveforms and Measurement Levels
9.6 VCC Power-up
Parameter
Description
VCC Setup Time
Test Setup
Speed
Unit
ms
tVCS
Notes:
Min
1
1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs
2. VCC ramp rate <1V / 100µs, a Hardware Reset will be required.
tVCS
VCC
VIO
RESET#
Figure 9.5. VCC Power-up Diagram
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9.7 DC Characteristics (CMOS Compatible)
Parameter
Description (Notes)
Input Load Current
Output Leakage Current (3)
Test Conditions (Notes 1, 2, 9)
= V to V , V = V max
Min
Typ
Max
±1
±1
54
60
66
48
54
60
42
48
54
36
42
48
30
36
18
4
Unit
µA
I
V
V
LI
IN
SS
CC
CC
CC
I
= V to V , V = V max
µA
LO
OUT
SS
CC
CC
CC
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
27
28
30
28
30
32
29
32
34
32
35
38
20
27
13
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 8
IH
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 16
IH
I
V
Active burst Read Current
CCB
CC
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 32
IH
CE# = V , OE# = V , WE#
IL
IH
= V , burst length =
IH
Continuous
I
V
V
Non-active Output
OE# = V
IH
IO1
IO
10 MHz
5 MHz
1 MHz
mA
mA
mA
µA
Active Asynchronous
CE# = V , OE# = V , WE#
CC
IL
IH
I
CC1
= V
Read Current (4)
IH
V
1
5
ACC
CE# = V , OE# = V , ACC
IL
IH
I
I
V
V
Active Write Current (5)
Standby Current (6, 7)
CC2
CC
CC
= V
IH
V
19
1
52.5
5
mA
µA
CC
V
ACC
CE# = RESET# =
± 0.2 V
CC3
V
CC
V
20
70
40
150
µA
CC
I
I
I
V
V
Reset Current (7)
Active Current
RESET# = V CLK = V
IL
µA
CC4
CC5
CC6
CC
IL,
CC
CE# = V , OE# = V , ACC = V
50
60
mA
IL
IH
IH
(Read While Write) (7)
V
Sleep Current (7)
CE# = V , OE# = V
2
6
40
20
µA
mA
mA
V
CC
IL
IH
V
CE# = V , OE# = V
ACC
IL
IH,
I
Accelerated Program Current (8)
ACC
V
= 9.5 V
ACC
V
14
20
CC
V
Input Low Voltage
V
V
= 1.8 V
= 1.8 V
–0.5
0.4
IL
IO
IO
V
Input High Voltage
V
– 0.4
V
+ 0.4
V
IH
IO
IO
V
Output Low Voltage
I
I
= 100 µA, V = V
= V
IO
0.1
V
OL
OH
HH
OL
OH
CC
CC min
V
V
Output High Voltage
Voltage for Accelerated Program
= –100 µA, V = V
= V
V – 0.1
IO
V
CC
CC min
IO
8.5
1.0
9.5
1.4
V
V
Low V Lock-out Voltage
V
LKO
CC
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. VCC= VIO
3. CE# must be set high when measuring the RDY pin.
4. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH
5. ICC active while Embedded Erase or Embedded Program is in progress.
6. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns.
.
.
Typical sleep mode current is equal to ICC3
.
7. VIH = VCC ± 0.2 V and VIL > –0.1 V.
8. Total current during accelerated programming is the sum of VACC and VCC
currents.
9. VACC = VHH on ACC input.
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9.8 AC Characteristics
9.8.1. CLK Characterization
Parameter
Description
54 MHz
66 MHz
66
80 MHz
80
Unit
MHz
ns
fCLK
CLK Frequency
Max
Min
54
tCLK
tCH
CLK Period
18.5
15.1
12.5
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Min
7.4
3
6.1
3
5.0
2.5
ns
ns
tCL
tCR
Max
tCF
t
CLK
t
t
CH
CL
CLK
t
t
CF
CR
Figure 9.6. CLK Characterization
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9.8.2 Synchronous/Burst Read
Parameter
JEDEC
Standard
tIACC
tBACC
tACS
tACH
tBDH
tCR
Description
54 MHz
66 MHz
69
80 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Latency
Max
Burst Access Time Valid Clock to Output Delay Max
13.5
5
11.2
9
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Max
4
6
3
7
4
13.5
13.5
11.2
9
tOE
Output Enable to Output Valid
Chip Enable to High Z (Note 2)
Output Enable to High Z (Note 2)
CE# Setup Time to CLK
11.2
tCEZ
10
10
4
tOEZ
tCES
tRDYS
tRACC
tCAS
RDY Setup Time to CLK
5
4
3.5
9
Ready Access Time from CLK
CE# Setup Time to AVD#
AVD# Low to CLK
13.5
11.2
0
tAVC
tAVD
tAOE
4
AVD# Pulse
8
AVD Low to OE# Low
38.4
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
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9.8.3 Timing Diagrams
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCEZ
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
Da + 3
tAOE
tBDH
OE#
tRACC
tOE
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
RDY (n + 3)
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of
wait states can be programmed from two cycles to seven cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”,
additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Figure 9.7. CLK Synchronous Burst Mode Read
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7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
tAOE
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure 9.8. 8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D10
D13
tAOE
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
Figure 9.9. 8-word Linear Burst without Wrap Around
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tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tAOE
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one
cycle before valid data.
Figure 9.10. Linear Burst with RDY Set One Cycle Before Data
9.8.4 AC Characteristics—Asynchronous Read
Parameter
80
MHz
JEDEC Standard
Description
Access Time from CE# Low
54 MHz
66 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCE
tACC
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
70
70
8
Asynchronous Access Time
tAVDP
tAAVDS
tAAVDH
tOE
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
7
6
13.5
11.2
Read
0
10
10
0
tOEH
Output Enable Hold Time
Toggle and Data# Polling
tOEZ
tCAS
Output Enable to High Z (see Note)
CE# Setup Time to AVD#
Note: Not 100% tested.
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CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 9.11. Asynchronous Mode Read
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9.8.5 Hardware Reset (RESET#)
Parameter
JEDEC Std.
Description
All Speed Options
Unit
µs
tRP
RESET# Pulse Width
Reset High Time Before Read (See Note)
Min
Min
30
tRH
200
ns
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
Figure 9.12. Reset Timings
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9.8.6 Erase/Program Timing
Parameter
JEDEC Standard
Description
54 MHz
66 MHz
80 MHz Unit
t
t
Write Cycle Time (Note 1)
Min
Min
70
5
ns
ns
ns
AVAV
WC
Synchronous
Asynchronous
Synchronous
Asynchronous
t
t
Address Setup Time (Notes 2, 3)
Address Hold Time (Notes 2, 3)
AVWL
WLAX
AS
0
9
t
t
Min
ns
AH
20
8
t
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
AVDP
t
t
t
Data Setup Time
45
20
DVWH
DS
DH
t
Data Hold Time
0
0
WHDX
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
GHWL
GHWL
t
0
CAS
t
t
0
WHEH
WLWH
WHWL
CH
t
t
t
Write Pulse Width
30
20
0
WP
t
Write Pulse Width High
WPH
t
Latency Between Read and Write Operations
SR/W
t
V
V
V
Rise and Fall Time
500
1
VID
ACC
ACC
t
Setup Time (During Accelerated Programming)
VIDS
t
Setup Time
CC
50
5
VCS
t
t
CE# Setup Time to WE#
ELWL
CS
t
AVD# Setup Time to WE#
5
AVSW
AVHW
t
AVD# Hold Time to WE#
5
t
AVD# Setup Time to CLK
5
AVSC
t
AVD# Hold Time to CLK
5
AVHC
t
Clock Setup Time to WE#
5
CSW
t
Noise Pulse Margin on WE#
Sector Erase Accept Time-out
Erase Suspend Latency
3
WEP
t
50
20
20
100
1
SEA
t
ESL
PSL
ASP
t
Program Suspend Latency
t
Toggle Time During Sector Protection
Toggle Time During Programming Within a Protected Sector
t
PSP
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and
Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,
addresses are latched on the rising edge of CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
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Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
VA
VA
Addresses
Data
2AAh
555h for
chip erase
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses
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Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
AVD
V
IL
tAVSW
tAVHW
tAVDP
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. CLK can be either V or V .
IL
IH
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the
Configuration Register.
Figure 9.13. Asynchronous Program Operation Timings: WE# Latched Addresses
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Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
AVD
tAS
tAH
tAVSC
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 9.14. Synchronous Program Operation Timings: CLK Latched Addresses
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CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 9.15. Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
Addresses
VA
VA
High Z
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data#
Polling will output true data.
Figure 9.16. Data# Polling Timings (During Embedded Algorithm)
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AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
Data
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
will stop toggling.
Figure 9.17. Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
will stop toggling.
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before
data.
Figure 9.18. Synchronous Data Polling Timings/Toggle Bit Timings
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Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 9.19. DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14)
in the Configuration Register is set to 0
Figure 9.20. Latency with Boundary Crossing when Frequency > 66 MHz
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Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is < 66 MHz and the Boundary Crossing bit (D14) in
the Configuration Register is set to 0.
Figure 9.21. Latency with Boundary Crossing into Program/Erase Bank
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Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Configuration Register Setup:
D13, D12, D11 = “111” ⇒ Reserved
D13, D12, D11 = “110” ⇒ Reserved
D13, D12, D11 = “101” ⇒ 5 programmed, 7 total
D13, D12, D11 = “100” ⇒ 4 programmed, 6 total
D13, D12, D11 = “011” ⇒ 3 programmed, 5 total
D13, D12, D11 = “010” ⇒ 2 programmed, 4 total
D13, D12, D11 = “001” ⇒ 1 programmed, 3 total
D13, D12, D11 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Figure 9.22. Example of Wait States Insertion
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Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
Figure 9.23. Back-to-Back Read/Write Cycle Timings
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9.8.7 Erase and Programming Performance
Parameter
Typ (Note 1)
0.6
Max (Note 2)
Unit
Comments
64 Kword
16 Kword
VCC
VCC
3.5
2
Sector Erase Time
s
<0.15
153.6 (WS256N)
77.4 (WS128N)
39.3 (WS064N)
308 (WS256N)
154 (WS128N)
78 (WS064N)
Excludes 00h
programming prior
to erasure (Note 4)
VCC
Chip Erase Time
s
130.6 (WS256N)
65.8 (WS128N)
33.4 (WS064N)
262 (WS256N)
132 (WS128N)
66 (WS064N)
ACC
VCC
ACC
VCC
ACC
VCC
ACC
40
24
400
240
94
Single Word Programming Time
(Note 8)
µs
µs
µs
9.4
6
Effective Word Programming Time
utilizing Program Write Buffer
60
300
192
3000
1920
Total 32-Word Buffer Programming
Time
157.3 (WS256N)
78.6 (WS128N)
39.3 (WS064N)
314.6 (WS256N)
157.3 (WS128N)
78.6 (WS064N)
VCC
Excludes system
level overhead
(Note 5)
Chip Programming Time (Note 3)
s
100.7 (WS256N)
50.3 (WS128N)
25.2 (WS064N)
201.3 (WS256N)
100.7 (WS128N)
50.3 (WS064N)
ACC
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 10,000
cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 1.70 V, 100,000 cycles.
3. Typical chip programming time is considerably less than the maximum chip programming
time listed, and is based on single word programming.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed
to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence
for the program command. See the Appendix for further information on command
definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications
and operating conditions.
7. Refer to Application Note “Erase Suspend/Resume Timing” for more details.
8. Word programming specification is based upon a single word programming operation not
utilizing the write buffer.
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9.8.8 BGA Ball Capacitance
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ.
5.3
5.8
6.3
Max
6.3
6.8
7.3
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT = 0
VIN = 0
pF
Control Pin Capacitance
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C; f = 1.0 MHz.
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10 Appendix
This section contains information relating to software control or interfacing with the Flash de-
vice. For additional information and assistance regarding software, see the Additional
Resources section on page 18, or explore the Web at www.amd.com and www.fujitsu.com.
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Table 10.1. Memory Array Commands
Bus Cycles (Notes 1–5)
Third Fourth
Addr
First
Addr
Second
Fifth
Addr
Sixth
Addr Data
Command Sequence
(Notes)
Data
RD
Addr
Data
Data
Addr
Data
Data
Asynchronous Read (6)
Reset (7)
Manufacturer ID
1
1
4
6
RA
XXX
555
555
F0
AA
2AA
2AA
55
55
[BA]555
[BA]555
90
90
[BA]X00
[BA]X01
0001
227E
Device ID (9)
AA
BA+X0E
PA
Data
PD
BA+X0F 2200
Indicator Bits (10)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
4
6
1
3
6
6
1
1
4
4
1
3
2
1
555
555
SA
AA
AA
29
AA
AA
AA
B0
30
AA
AA
98
AA
A0
98
2AA
2AA
55
55
555
PA
A0
25
PA
PA
PD
Write to Buffer (11)
Program Buffer to Flash
Write to Buffer Abort Reset (12)
Chip Erase
WC
WBL
PD
555
555
555
BA
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase/Program Suspend (13)
Erase/Program Resume (14)
Set Configuration Register (18)
Read Configuration Register
CFI Query (15)
BA
555
555
[BA]555
555
XXX
XXX
2AA
2AA
55
55
555
555
D0
C6
X00
X00
CR
CR
Entry
2AA
PA
55
PD
555
20
Program (16)
CFI (16)
Reset
2
XXX
90
XXX
00
Entry
3
4
1
555
555
00
AA
AA
2AA
2AA
55
55
555
555
88
A0
Program (17)
Read (17)
PA
PD
00
Data
Exit (17)
4
555
AA
2AA
55
555
90
XXX
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 5.4 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer. The number
of cycles in the command sequence is 37 for full page
programming (32 words). Less than 32 word programming is not
recommended.
12. Command sequence resets device for next command after write-
to-buffer operation.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address will equal 55h on all
future devices, but 555h for WS256N/128N/064N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
17. Requires Entry command sequence prior to execution. SecSi
Sector Exit Reset command is required to exit this mode; device
may otherwise be placed in an unknown state.
8. The system must provide the bank address. See Autoselect
section for more information.
9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231
(WS128N).
10. See Table 5.16 for indicator bit values.
18. Requires reset command to configure the Configuration Register.
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Table 10.2. Sector Protection Commands
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Command Sequence
(Notes)
Addr
Data
AA
Addr
Data
55
Addr
Data
Addr Data Addr Data Addr Data Addr Data
Command Set Entry (5)
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
555
XX
2AA
77
555
40
Lock
Register
Bits
Program (6)
A0
data
Read (6)
77
data
90
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (9)
XX
XX
2AA
00
00
55
555
XX
AA
555
60
A0
PWD[0-3]
PWD1
03
Password
Protection
0...00 PWD0 0...01
0...02
00
PWD2 0...03 PWD3
Unlock
00
XX
555
XX
XX
SA
25
90
00
XX
PWD0
01
PWD1
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
00
AA
2AA
SA
55
[BA]555
C0
A0
00
Non-Volatile
Sector
Protection (PPB)
80
00
30
RD(0)
90
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XX
555
XX
BA
XX
2AA
XX
00
55
00
Global
Volatile Sector
Protection
Freeze
AA
[BA]555
[BA]555
50
E0
A0
PPB Lock Bit Status Read
RD(0)
Command Set Exit (7)
Command Set Entry (5)
DYB Set
2
3
2
2
1
2
XX
555
XX
XX
SA
90
AA
XX
2AA
SA
00
55
00
01
(PPB Lock)
A0
Volatile Sector
Protection
(DYB)
DYB Clear
A0
SA
DYB Status Read
Command Set Exit (7)
RD(0)
90
XX
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
Notes:
1. All values are in hexadecimal.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation will abort and return the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses will equal 00h, but are
currently 77h for WS256N, WS128N, and WS064N. See Tables
6.1 and 6.2 for explanation of lock bits.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 6.2 for details.
11. “All PPB Erase” command will pre-program all PPBs before
erasure to prevent over-erasure.
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10.1 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software in-
terrogation handshake, which allows specific vendor-specified soft-ware algorithms to be
used for entire families of devices. Software support can then be device-independent, JEDEC
ID-independent, and forward- and back-ward-compatible for the specified flash device fami-
lies. Flash vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h,
to address (BA)555h any time the device is ready to read array data. The system can read
CFI information at the addresses given in Tables 10.3–10.6) within that bank. All reads out-
side of the CFI address range, within the bank, will return non-valid data. Reads from other
banks are allowed, writes are not. To terminate reading CFI data, the system must write the
reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-
A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 10.3. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
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Table 10.4. System Interface String
Addresses
Data
Description
V
Min. (write/erase)
CC
1Bh
0017h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
1Ch
0019h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0006h
0009h
000Ah
0000h
0004h
0004h
0003h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
Max. voltage (00h = no V pin present)
PP
PP
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10.5. Device Geometry Definition
Addresses
Data
Description
0019h (WS256N)
0018h (WS128N)
0017h (WS064N)
27h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ah
2Bh
0006h
0000h
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FDh (WS256N)
007Dh (WS128N)
003Dh (WS064N)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0002h
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
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Table 10.6. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0034h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0100h
Silicon Technology (Bits 5-2) 0100 = 0.11 µm
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
0002h
0001h
0000h
0008h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
00F3h (WS256N)
006Fh (WS128N)
0037h (WS064N)
Simultaneous Operation
Number of Sectors in all banks except boot bank
4Ah
4Bh
Burst Mode Type
00 = Not Supported, 01 = Supported
0001h
0000h
Page Mode Type
4Ch
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word
Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0001h = Dual Boot Device
4Fh
50h
51h
52h
53h
0001h
0001h
0001h
0007h
0014h
Program Suspend. 00h = not supported
Unlock Bypass
00 = Not Supported, 01=Supported
SecSi Sector (Customer OTP Area) Size 2N bytes
Hardware Reset Low Time-out during an embedded algorithm to read
mode Maximum 2N ns
Hardware Reset Low Time-out not during an embedded algorithm to read
mode Maximum 2N ns
54h
0014h
55h
56h
57h
0005h
0005h
0010h
Erase Suspend Time-out Maximum 2N ns
Program Suspend Time-out Maximum 2N ns
Bank Organization: X = Number of banks
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
58h
Bank 0 Region Information. X = Number of sectors in bank
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Table 10.6. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
59h
Bank 1 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
Bank 2 Region Information. X = Number of sectors in bank
Bank 3 Region Information. X = Number of sectors in bank
Bank 4 Region Information. X = Number of sectors in bank
Bank 5 Region Information. X = Number of sectors in bank
Bank 6 Region Information. X = Number of sectors in bank
Bank 7 Region Information. X = Number of sectors in bank
Bank 8 Region Information. X = Number of sectors in bank
Bank 9 Region Information. X = Number of sectors in bank
Bank 10 Region Information. X = Number of sectors in bank
Bank 11 Region Information. X = Number of sectors in bank
Bank 12 Region Information. X = Number of sectors in bank
Bank 13 Region Information. X = Number of sectors in bank
Bank 14 Region Information. X = Number of sectors in bank
Bank 15 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
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11 Commonly Used Terms
Term
Definition
ACCelerate. A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above VCC. In some devices ACC
may protect all sectors when at a low voltage.
ACC
Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]
Amax
Amin
Least significant bit of the address input signals (A0 for all devices in this document).
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Asynchronous
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Autoselect
Bank
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.
Boot sector
Boundary
Burst Read
Byte
Location at the beginning or end of series of memory locations.
See synchronous read.
8 bits
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
CFI
Clear
Zero (Logic Low Level)
Special purpose register which must be programmed to enable synchronous read
mode
Configuration Register
Synchronous method of burst read whereby the device will read continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Continuous Read
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
Erase Suspend/Erase Resume
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
BGA
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
Linear Read
or without wraparound before requiring a new initial address
.
Multi-Chip Package. A method of combining integrated circuits in a single package by
“stacking” multiple die of the same or different devices.
MCP
Memory Array
MirrorBit™ Technology
The programmable area of the product available for data storage.
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
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Term
Definition
Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
Page
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less “page”
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Page Read
Sector protection method which uses a programmable password, in addition to the
Password Protection
Persistent Protection
Program
Persistent Protection method, for protection of sectors in the Flash memory device
.
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Stores data into a Flash memory by selectively clearing bits of the memory array in
order to leave a data pattern of “ones” and “zeros”.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read
Host bus cycle that causes the Flash to output data onto the data bus.
Dynamic storage bits for holding device control information or tracking the status of
an operation.
Registers
Secured Silicon. An area consisting of 256 bytes in which any word may be
programmed once, and the entire area may be protected once from any future
programming. Information in this area may be programmed at the factory or by the
user. Once programmed and protected there is no way to change the secured
information. This area is often used to store a software readable identification such as
a serial number.
SecSi™
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase will ignore program or erase commands related to that
sector.
Sector Protection
Sector
An Area of the memory array in which all bits must be erased together by an erase
operation.
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Simultaneous Operation
Synchronous Operation
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
VersatileIO™ (VIO
Unlock Bypass
Word
)
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two
“Unlock” write cycles, of the usual 4 cycle Program command, are not required –
reducing all Program commands to two bus cycles while in this mode.
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
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Term
Definition
Special burst read mode where the read address “wraps” or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Wraparound
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with
“writing command cycles” to enter or exit a particular mode of operation.
Write
Multi-word area in which multiple words may be programmed as a single operation. A
Write Buffer
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
Write Buffer Programming
Write Operation Status
operation. Using Write Buffer Programming will result in
time than by using single word at a time programming commands.
≥
8 times faster programming
Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits
.
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pSRAM Type 4
8M x 16-bit Synchronous Burst pSRAM
Features
Process Technology: CMOS
Organization: 8M x16 bit
Power Supply Voltage: 1.7~2.0V
Three State Outputs
Supports MRS (Mode Register Set)
MRS control - MRS Pin Control
Supports Power Saving modes - Partial Array Refresh mode Internal TCSR
Supports Driver Strength Optimization for system environment power saving
Supports Asynchronous 4-Page Read and Asynchronous Write Operation
Supports Synchronous Burst Read and Asynchronous Write Operation (Ad-
dress Latch Type and Low ADV Type)
Supports Synchronous Burst Read and Synchronous Burst Write Operation
Synchronous Burst (Read/Write) Operation
— Supports 4 word / 8 word / 16 word and Full Page(256 word) burst
— Supports Linear Burst type & Interleave Burst type
— Latency support:
Latency 5 @ 66MHz(tCD 10ns)
Latency 4 @ 54MHz(tCD 10ns)
— Supports Burst Read Suspend in No Clock toggling
— Supports Burst Write Data Masking by /UB & /LB pin control
— Supports WAIT pin function for indicating data availability.
Max. Burst Clock Frequency: 66MHz
Pin Description
Pin Name
CLK
Function
Type
Description
Clock
Commands are referenced to CLK
ADV#
MRS#
Address Valid
Valid Address is latched by ADV falling edge
MRS# low enables Mode Register to be set
CS# low enables the chip to be active
Mode Register set
CS#
Chip Select
CS# high disables the chip and puts it into standby
mode
Input
OE#
WE#
LB#
Output Enable
Write Enable
OE# low enables the chip to output the data
WE# low enables the chip to start writing the data
Lower Byte (I/O0~7
)
UB# (LB#) low enables upper byte (lower byte) to
start operating
UB#
Upper Byte (I/O8~15)
Valid addresses input when ADV is low
Mode setting input when MRS is low
A0-A22
Address 0 ~ Address 22
Depending on UB# or LB# status, word (16-bit,
UB# & LB# low) data, upper byte (8-bit, UB# low &
LB# high) data or lower byte (8-bit, LB# low & UB#
high) data is loaded
I/O0-I/O15
Data Inputs / Outputs
Input/Output
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Pin Name
VCC
Function
Voltage Source
Type
Description
Power
Power
GND
Core Power supply
I/O Power supply
Core ground Source
I/O Ground Source
VCCQ
Voltage Source
VSS
Ground Source
VSSQ
I/O Ground Source
Valid Data Indicator
GND
WAIT#
Output
WAIT# indicates whether data is valid or not
Power Up Sequence
After applying V up to minimum operating voltage (1.7V), drive CS# high first
CC
and then drive MRS# high. This gets the device into power up mode. Wait 200 µs
minimum to get into the normal operation mode. During power up mode, the
standby current cannot be guaranteed. To obtain stable standby current levels,
at least one cycle of active operation should be implemented regardless of wait
time duration. To obtain appropriate device operation, be sure to follow the
proper power up sequence.
1. Apply power.
2. Maintain stable power (V min.=1.7V) for a minimum 200 µs with CS# and
CC
MRS# high.
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Timing Diagrams
Power Up
200 µs
VCC(Min)
VCC
Min. 0ns
Min. 0ns
MRS#
CS#
Min. 200 µs
PowerUp Mode
Normal Operation
Figure 11.24. Power Up Timing
Notes:
1. After VCC reaches VCC(Min.), wait 200 µs with CS# and MRS# high. This puts the device into normal operation.
Standby Mode
CS# = V
CS# = UB# = LB# = V
WE# = V , MRS# = V
CS# = V , UB# or LB# = V
IL IL
IH
IL
IH
MRS# = V
MRS# = V
CS# = V
IH
IH
IL
IH
MRS# = V
IH
Initial State
(wait 200µs)
Standby
Mode
PAR
Mode
Power On
MRS Setting
Active
MRS# = V
IL
MRS Setting
CS# = V
IL
WE# = V , MRS#=V
IL IL
Figure 11.25. Standby Mode State Machines
The default mode after power up is Asynchronous mode (4 Page Read and Asyn-
chronous Write). But this default mode is not 100% guaranteed, so the MRS#
setting sequence is highly recommended after power up.
For entry to PAR mode, drive the MRS# pin into V for over 0.5µs or longer (sus-
IL
pend period) during standby mode after the MRS# setting has been completed
(A4=1, A3=0). If the MRS# pin is driven into V during PAR mode, the device
IH
reverts to standby mode without the wake up sequence.
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Functional Description
Table 11.7. Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0)
Mode
CS#
MRS#
OE#
X
WE#
LB#
X
UB#
X
I/O
I/O
Power
Standby
PAR
0-7
8-15
Deselected
Deselected
H
H
L
L
L
L
L
L
L
L
L
H
L
X
X
H
X
H
H
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
Output Disabled
Outputs Disabled
Lower Byte Read
Upper Byte Read
Word Read
H
H
H
H
H
H
H
H
L
H
X
X
X
Active
Active
Active
Active
Active
Active
Active
Active
Active
H
L
H
H
L
L
D
OUT
L
H
L
High-Z
D
D
OUT
OUT
L
L
D
OUT
Lower Byte Write
Upper Byte Write
Word Write
H
H
H
H
L
H
L
D
High-Z
IN
L
H
L
High-Z
D
D
IN
IN
L
L
D
IN
Mode Register Set
L
L
L
High-Z
High-Z
Legend:X = Don’t care (must be low or high state).
Notes:
1. In asynchronous mode, Clock and ADV# are ignored.
2. The WAIT# pin is High-Z in asynchronous mode.
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Table 11.8. Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1)
Mode
CS# MRS# OE# WE# LB# UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
Deselected
H
H
L
H
L
X
X
H
X
X
X
H
X
X
X
X
H
X
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Standby
(note 2)
(note 2)
X
X
Deselected
PAR
(note 2)
(note 2)
X
Output Disabled
Outputs Disabled
H
H
H
H
Active
Active
(note 2)
X
L
(note 2)
Read Command
Lower Byte Read
Upper Byte Read
Word Read
L
L
L
L
H
H
H
H
X
L
L
L
H
H
H
H
X
L
X
H
L
High-Z
High-Z
High-Z
Active
Active
Active
Active
D
H
H
H
OUT
H
L
High-Z
D
D
OUT
L
D
OUT
OUT
X
Lower Byte Write
Upper Byte Write
Word Write
L
L
L
L
H
H
H
L
H
H
H
H
L
L
L
L
L
H
L
H
L
L
L
D
High-Z
Active
Active
Active
Active
IN
(note 2)
or
or
or
or
X
High-Z
D
D
IN
IN
(note 2)
X
D
IN
(note 2)
X
Mode Register Set
L
High-Z
High-Z
(note 2)
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram
for WAIT# pin function.
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Table 11.9. Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14=1/0)
Mode
CS# MRS#
OE#
WE#
LB#
UB#
I/O
I/O
CLK
ADV#
Power
0-7
8-15
X
X
X
X
X
X
Deselected
H
H
L
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Standby
(note1)
(note1)
(note1) (note1)
(note 2)
(note 2)
X
X
X
X
X
X
Deselected
PAR
(note1)
(note1)
(note1) (note1)
(note 2)
(note 2)
Output
Disabled
X
H
H
H
H
X
H
X
H
H
H
Active
Active
(note 2)
Outputs
Disabled
X
X
X
L
(note1)
(note1)
(note 2)
Read
Command
X
L
L
L
L
H
H
H
H
H
H
H
H
X
L
X
H
L
High-Z
High-Z
High-Z
Active
Active
Active
Active
(note1)
LowerByte
Read
L
L
L
D
H
H
H
OUT
UpperByte
Read
H
L
High-Z
D
D
OUT
OUT
Word Read
L
D
OUT
Write
X
L
L
L
H
H
H
High-Z
High-Z
High-Z
Active
Active
Active
L
Command
(note1)
or
LowerByte
Write
X
H
H
L
H
L
D
H
H
IN
(note1)
UpperByte
Write
X
H
High-Z
D
D
IN
IN
(note1)
X
Word Write
L
L
H
L
H
H
L
L
L
L
D
H
Active
Active
IN
(note1)
Mode
Register
Set
High-Z
High-Z
L
or
Notes:
1. X must be low or high state.
2. X means “Don’t care” (can be low, high or toggling).
3. WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram
for WAIT# pin function.
Mode Register Setting Operation
The device has several modes:
Asynchronous Page Read mode
Asynchronous Write mode
Synchronous Burst Read mode
Synchronous Burst Write mode
Standby mode and Partial Array Refresh (PAR) mode.
Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS)
option. The MRS option also defines burst length, burst type, wait polarity and
latency count at synchronous burst read/write mode.
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Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of
the pSRAM. It programs Partial Array Refresh (PAR), burst length, burst type, la-
tency count and various vendor specific options to make pSRAM useful for a
variety of different applications. The default values of mode register are defined,
therefore when the reserved address is input, the device runs at default modes.
The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS#
to V and driving OE# to V during valid addressing. The mode register is di-
IL
IH
vided into various fields depending on the fields of functions. The PAR field uses
A0~A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses
A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Driver
Strength uses A16~A17.
Refer to the Table below for detailed Mode Register Settings. A18~A22 addresses
are “Don’t care” in the Mode Register Setting.
Table 11.10. Mode Register Setting According to Field of Function
Address
Function
A17-A16
A15-A14
A13
A12
A11-A19
A8
A7-A5
A4-A3
A2
A1-A0
DS
MS
WP
RFU
Latency
BT
BL
PAR
PARA
PARS
Note: DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Re-
served for Future Use).
Table 11.11. Mode Register Set
Driver Strength
A16 DS
Mode Select
MS
A17
0
A15
0
A14
0
0
1
0
Full Drive (note 1)
1/2 Drive
Async. 4 Page Read / Async. Write (note 1)
Sync. Burst Read / Async. Write
0
0
1
1
1/4 Drive
1
0
Sync. Burst Read / Sync. Burst Write
WAIT# Polarity
RFU
RFU
Latency Count
Burst Type
BT
Burst Length
A6 A5
A13
WP
A12
0
A11 A10 A9
Latency
A8
0
A7
BL
Low Enable
(note 1)
Must
(note 1)
Linear
(note 1)
0
1
0
0
0
3
0
1
0
4 word
High Enable
1
—
0
0
0
0
1
1
1
0
1
4
5
6
1
Interleave
0
1
1
1
0
1
1
0
1
8 word
16 word (note 1)
Full (256 word)
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Partial Array Refresh
PAR Array
PARA
PAR Size
A4
A3
PAR
A2
A1
A0
PARS
Bottom Array
(note 1)
Full Array
(note 1)
1
0
PAR Enable
0
0
0
PAR Disable
(note 1)
1
1
1
Top Array
0
1
3/4 Array
1
1
0
1
1/2 Array
1/4 Array
Notes:
1. Default mode. The address bits other than those listed in the table above are reserved. For example, Burst Length address
bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then
the mode will be set to the default mode. Each field has its own default mode, but this default mode is not 100% guaranteed,
so the MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as
“0”. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion. The 256 word Full
page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.
MRS Pin Control Type Mode Register Setting Timing
In this device, the MRS pin is used for two purposes. One is to get into the mode
register setting and the other is to execute Partial Array Refresh mode.
To get into the Mode Register Setting, the system must drive the MRS# pin to V
IL
and immediately (within 0.5µs) issue a write command (drive CS#, ADV#, UB#,
LB# and WE# to V and drive OE# to V during valid address). If the subse-
IL
IH
quent write command (WE# signal input) is not issued within 0.5µs, then the
device may get into the PAR mode.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
tWC
Address
CS#
tCW
tAW
tBW
UB#, LB#
WE#
tWP
tAS
tWU
tMW
MRS#
Register Update Complete
Register Write Complete
Register Write Start
(MRS SETTING TIMING)
1. Clock input is ignored.
Figure 11.26. Mode Register Setting Timing (OE# = VIH
)
Table 11.12. MRS AC Characteristics
Speed
Parameter List
Symbol
tMW
Min
0
Max
500
—
Units
ns
MRS# Enable to Register Write Start
End of Write to MRS# Disable
MRS
tWU
0
ns
Note: VCC=1.7~2.0V, TA=-40 to 85°C, Maximum Main Clock Frequency=66MHz
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
106
P r e l i m i n a r y
Asynchronous Operation
Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are
driven to V under the valid address without toggling page addresses (A0, A1).
IL
If the page addresses (A0, A1) are toggled under the other valid address, the first
data will be out with the normal read cycle time (tRC) and the second, the third
and the fourth data will be out with the page cycle time (tPC). (MRS# and WE#
should be driven to V during the asynchronous (page) read operation) Clock,
IH
ADV#, WAIT# signals are ignored during the asynchronous (page) read
operation.
Asynchronous Write Operation
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven
to V under the valid address. MRS# and OE# should be driven to V during the
IL
IH
asynchronous write operation. Clock, ADV#, WAIT# signals are ignored during
the asynchronous (page) read operation.
Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS#, WE# and UB# or LB# are driven to V under
IL
the valid address. Clock input does not have any affect to the write operation
(MRS# and OE# should be driven to V during write operation. ADV# can be ei-
IH
ther toggling for address latch or held in V ). Clock, ADV#, WAIT# signals are
IL
ignored during the asynchronous (page) read operation.
A22~A2
A1~A0
CS#
UB#, LB#
OE#
Data Out
Figure 11.27. Asynchronous 4-Page Read
Address
CS#
UB#, LB#
WE#
High-Z
Data in
High-Z
High-Z
Data out
Figure 11.28. Asynchronous Write
107
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Operation
Burst mode operations enable the system to get high performance read and write
operation. The address to be accessed is latched on the rising edge of clock or
ADV# (whichever occurs first). CS# should be setup before the address latch.
During this first clock rising edge, WE# indicates whether the operation is going
to be a Read (WE# High) or a Write (WE# Low).
For the optimized Burst Mode of each system, the system should determine how
many clock cycles are required for the first data of each burst access (Latency
Count), how many words the device outputs during an access (Burst Length) and
which type of burst operation (Burst Type: Linear or Interleave) is needed. The
Wait Polarity should also be determined (See Table 11.11).
Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is
detected during the ADV# low pulse. ADV# and CS# should be set up before the
clock rising. During the Read command, WE# should be held in V . The multiple
IH
clock risings (during the low ADV# period) are allowed, but the burst operation
starts from the first clock rising. The first data will be out with Latency count and
t
.
CD
Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is
detected during the ADV# and WE# low pulse. ADV#, WE# and CS# should be
set up before the clock rising. The multiple clock risings (during the low ADV#
period) are allowed but, the burst operation starts from the first clock rising. The
first data will be written in the Latency clock with t
.
DS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
ADV#
Addr.
CS#
UB#, LB#
OE#
Data Out
WAIT#
Figure 11.29. Synchronous Burst Read
Note: Latency 5, BL 4, WP: Low Enable
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
108
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10 11 12 13
CLK
ADV#
Addr.
CS#
UB#, LB#
WE#
Data in
WAIT#
Figure 11.30. Synchronous Burst Write
Note: Latency 5, BL 4, WP: Low Enable
Synchronous Burst Operation Terminology
Clock (CLK)
The clock input is used as the reference for synchronous burst read and write op-
eration of the pSRAM. The synchronous burst read and write operations are
synchronized to the rising edge of the clock. The clock transitions must swing be-
tween V and V .
IL
IH
Latency Count
The Latency Count configuration tells the device how many clocks must elapse
from the burst command before the first data should be available on its data pins.
This value depends on the input clock frequency. Table 11.13 shows the sup-
ported Latency Count.
Table 11.13. Latency Count Support
Clock Frequency
Latency Count
Up to 66 MHz
Up to 54 MHz
Up to 40 MHz
5
4
3
Table 11.14. Number of CLocks for 1st Data
Set Latency
Latency 3
Latency 4
Latency 5
# of Clocks for 1st data (Read)
# of Clocks for 1st data (Write)
4
2
5
3
6
4
109
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
T
Clock
ADV#
Address
Latency 3
Latency 4
Latency 5
Latency 6
DQ1
DQ2
DQ3
DQ2
DQ1
DQ4
DQ3
DQ2
DQ1
DQ5
DQ4
DQ3
DQ2
DQ6
DQ5
DQ4
DQ3
DQ7
DQ6
DQ5
DQ4
DQ8
DQ7
DQ6
DQ5
DQ9
DQ8
DQ7
DQ6
Data out
Data out
Data out
Data out
DQ1
Figure 11.31. Latency Configuration (Read)
Note: The first data will always keep the Latency. From the second data on, some period of wait time may be caused
by WAIT# pin.
Burst Length
Burst Length identifies how many data the device outputs during an access. The
device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256
word Full page burst mode needs to meet t
2500ns max.
(Burst Cycle time) parameter as
BC
The first data will be output with the set Latency + t . From the second data on,
CD
the data will be output with t
from each clock.
CD
Burst Stop
Burst stop is used when the system wants to stop burst operation on purpose. If
driving CS# to V during the burst read operation, the burst operation is
IH
stopped. During the burst read operation, the new burst operation cannot be is-
sued. The new burst operation can be issued only after the previous burst
operation is finished.
The burst stop feature is very useful because it enables the user to utilize the un-
supported burst length such as 1 burst or 2 burst, used mostly in the mobile
handset application environment.
Synchronous Burst Operation Terminology
Wait Control (WAIT#)
The WAIT# signal is the device’s output signal that indicates to the host system
when it’s data-out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the
WAIT# polarity (WP) can be configured. The polarity can be programmed to be
either low enable or high enable.
For the timing of WAIT# signal, the WAIT# signal should be set active one clock
prior to the data regardless of Read or Write cycle.
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
110
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
ADV#
CS#
Latency 5
Read
Data out
DQ0 DQ1
DQ2
DQ3
High-Z
High-Z
WAIT#
Latency 5
Write
Data in
D0
D1
D2
D3
WAIT#
Figure 11.32. WAIT# and Read/Write Latency Control
Note: LATENCY: 5, Burst Length: 4, WP: Low Enable
Burst Type
The device supports Linear type burst sequence and Interleave type burst se-
quence. Linear type burst sequentially increments the burst address from the
starting address. The detailed Linear and Interleave type burst address sequence
is shown in Table 11.15.
Table 11.15. Burst Sequence
Burst Address Sequence (Decimal)
Wrap (note 1)
Start
Address
4 word Burst
8 word Burst
Linear
16 word Burst
Full Page(256 word)
Linear
Linear
Interleave
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Interleave
0-1-2-...-6-7
1-0-3-...-7-6
2-3-0-...-4-5
3-2-1-...-5-4
4-5-6-...-2-3
5-4-7-...-3-2
6-7-4-...-0-1
7-6-5-...-1-0
Linear
Interleave
0-1-2-3-4...14-15
1-0-3-2-5...15-14
2-3-0-1-6...12-13
3-2-1-0-7...13-12
4-5-6-7-0...10-11
5-4-7-6-1...11-10
6-7-4-5-2...8-9
7-6-5-4-3...9-8
~
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-...-5-6-7
1-2-...-6-7-0
2-3-...-7-0-1
3-4-...-0-1-2
4-5-...-1-2-3
5-6-...-2-3-4
6-7-...-3-4-5
7-0-...-4-5-6
0-1-2-...-14-15
1-2-3-...-15-0
2-3-4-...-0-1
3-4-5-...-1-2
4-5-6-...-2-3
5-6-7-...-3-4
6-7-8-...-4-5
7-8-9-...-5-6
~
0-1-2-...-254-255
1-2-3-...-255-0
2
2-3-4-...-255-0-1
3-4-5-...-255-0-1-2
4-5-6-...-255-0-1-2-3
5-6-7-...-255-...-3-4
6-7-8-...-255-...-4-5
7-8-9-...-255-...-5-6
~
3
4
5
6
7
~
14
15
~
14-15-0-...-12-13
15-0-1-...-13-14
14-15-12-...-0-1
15-14-13-...-1-0
14-15-...-255-...-12-13
15-16-...-255-...-13-14
~
255
255-0-1-...-253-254
111
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Low Power Features
Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very
useful tool for reducing standby current at room temperature (below 40°C).
DRAM cells have weak refresh characteristics in higher temperatures. High tem-
peratures require more refresh cycles, which can lead to standby current
increase.
Without the internal TCSR, the refresh cycle should be set at worst condition so
as to cover the high temperature (85°C) refresh characteristics. But with internal
TCSR, a refresh cycle below 40°C can be optimized, so the standby current at
room temperature can be greatly reduced. This feature is beneficial since most
mobile phones are used at or below 40°C in the phone standby mode.
0.5 µs
MRS#
Normal
Operation
Normal
Operation
Suspend
PAR mode
MODE
CS#
Figure 11.33. PAR Mode Execution and Exit
Table 11.16. PAR Mode Characteristics
Address (Bottom Array) Address (Top Array)
Memory Cell
Standby Current
(µA, Max)
Wait
Time (µs)
Power Mode
(note 2)
(note 2)
Data
Standby (Full Array)
Partial Refresh(3/4 Block)
Partial Refresh(1/2 Block)
Partial Refresh(1/4 Block)
000000h ~ 7FFFFFh
000000h ~ 5FFFFFh
000000h ~ 3FFFFFh
000000h ~ 1FFFFFh
000000h ~ 7FFFFFh
200000h ~ 7FFFFFh
400000h ~ 7FFFFFh
600000h ~ 7FFFFFh
200
170
150
140
Valid (note 1)
0
Notes:
1. Only the data in the refreshed block are valid.
2. The PAR Array can be selected through Mode Register Set (see “Mode Register Setting Operation” on page 103).
Driver Strength Optimization
The optimization of output driver strength is possible through the mode register
setting to adjust for the different data loadings. Through this driver strength op-
timization, the device can minimize the noise generated on the data bus during
read operation. The device supports full drive, 1/2 drive and 1/4 drive.
Partial Array Refresh (PAR) mode
The PAR mode enables the user to specify the active memory array size. The
pSRAM consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or
all blocks as active memory arrays through the Mode Register Setting. The active
memory array is periodically refreshed whereas the disabled array is not re-
freshed, so the previously stored data is lost. Even though PAR mode is enabled
through the Mode Register Setting, PAR mode execution by the MRS# pin is still
needed. The normal operation can be executed even in refresh-disabled array as
long as the MRS# pin is not driven to the Low condition for over 0.5µs. Driving
the MRS# pin to the High condition puts the device back to the normal operation
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
112
P r e l i m i n a r y
mode from the PAR executed mode. Refer to Figure 11.33 and Table 11.16 for
PAR operation and PAR address mapping.
Absolute Maximum Ratings
Item
Symbol
VIN , VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 2.5V
1.0
Unit
V
Voltage on any pin relative to VSS
Power supply voltage relative to VSS
Power Dissipation
V
PD
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" section may cause permanent damage to the device.
Functional operation should be restricted to use under recommended operating conditions only. Exposure to absolute
maximum rating conditions longer than one second may affect reliability.
DC Recommended Operating Conditions
Symbol
VCC
Parameter
Power Supply Voltage
Ground
Min
1.7
Typ
1.85
0
Max
Unit
2.0
VSS
0
0
VCC + 0.2 (note 2)
0.4
V
VIH
Input High Voltage
Input Low Voltage
0.8 x VCC
-0.2 (note 3)
—
VIL
—
Notes:
1. TA=-40 to 85°C, unless otherwise specified.
2. Overshoot: VCC+1.0V in case of pulse width ≤ 20ns.
3. Undershoot: -1.0V in case of pulse width ≤ 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (Ta = 25°C, f = 1 MHz)
Symbol
CIN
Parameter
Test Condition
VIN = 0V
Min
—
Max
8
Unit
pF
Input Capacitance
CIO
Input/Output Capacitance
VOUT = 0V
—
10
pF
Note: This parameter is sampled periodically and is not 100% tested.
113
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
DC and Operating Characteristics
Common
Item
Symbol
Test Conditions
Min
-1
Typ
—
Max
Unit
µA
Input Leakage Current
Output Leakage Current
I
V
=V to V
CC
1
1
LI
IN
SS
I
CS#=V , MRS#=V , OE#=V or WE#=V , V =V to V
CC
-1
—
µA
LO
IH
IH
IH
IL
IO
SS
Average Operating
Current
Cycle time=t +3t , I =0mA, 100% duty, CS#=V , MRS#=V
,
RC
IH
PC IO
IL
IH
I
—
—
40
mA
CC2
V
=V or V
IN
IL
Output Low Voltage
Output High Voltage
V
I
I
=0.1mA
—
1.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.2
—
V
V
OL
OL
V
=-0.1mA
OH
OH
< 40°C
< 85°C
TBD
200
TBD
TBD
TBD
170
150
140
µA
µA
CS# ≥ V -0.2V, MRS# ≥ V -0.2V, Other
inputs = V to V
CC
CC
Standby Current (CMOS)
Partial Refresh Current
Notes:
I
SB1
SS
CC
3/4 Block
1/2 Block
1/4 Block
3/4 Block
1/2 Block
1/4 Block
< 40°C
< 85°C
µA
µA
I
MRS# ≤ 0.2V, CS# ≥ V -0.2V Other inputs =
V
SBP
CC
(note 1)
to V
SS CC
1. Full Array Partial Refresh Current (ISBP) is same as Standby Current (ISB1).
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
114
P r e l i m i n a r y
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to V -0.2V
CC
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x V
Output load (See Figure 11.34): CL=50pF
CC
Vtt = 0.5 x V
DDQ
50
Dout
Z0=50
30pF
Figure 11.34. Output Load
115
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Asynchronous AC Characteristics
(V =1.7~2.0V, TA=-40 to 85 °C)
CC
Speed Bins
Symbol
tRC
Parameter
Read Cycle Time
Min
70
25
—
—
—
—
—
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
tPC
Page Read Cycle Time
—
tAA
Address Access Time
70
tPA
Page Access Time
20
tCO
Chip Select to Output
70
tOE
Output Enable to Valid Output
UB#, LB# Access Time
35
tBA
35
tLZ
Chip Select to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#, LB# Disable to High-Z Output
Output Disable to High-Z Output
Output Hold
—
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
—
5
—
0
7
0
7
0
7
3
—
tWC
tCW
tADV
tAS
Write Cycle Time
70
60
7
—
Chip Select to End of Write
ADV# Minimum Low Pulse Width
Address Set-up Time to Beginning of Write
Address Set-up Time to ADV# Falling
Address Hold Time from ADV# Rising
—
—
0
—
tAS(A)
tAH(A)
tCSS(A)
tAW
0
—
7
—
CS# Setup Time to ADV# Rising
Address Valid to End of Write
UB#, LB# Valid to End of Write
Write Pulse Width
10
60
60
—
—
tBW
—
tWP
55 (Note 1)
—
tWHP
tWR
tWLRL
tDW
WE# High Pulse Width
5 ns
0
Latency-1 clock
Write Recovery Time
—
—
—
—
ns
clock
ns
ns
WE# Low to Read Latency
Data to Write Time Overlap
Data Hold from Write Time
1
30
0
tDH
Notes:
1. tWP (min)=70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
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P r e l i m i n a r y
Timing Diagrams
Asynchronous Read Timing Waveform
MRS# = V , WE# = V , WAIT# = High-Z
IH
IH
tRC
Address
tAA
tOH
tCO
CS#
tCHZ
tBA
UB#, LB#
tBHZ
tOE
OE#
t
OLZ
tLBZLZ
tOHZ
t
Data out
High-Z
Data Valid
Figure 11.35. Timing Waveform Of Asynchronous Read Cycle
Notes:
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device interconnection.
3. In asynchronous read cycle, Clock, ADV# and WAIT# signals are ignored.
Table 11.17. Asynchronous Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
—
—
—
3
Max
—
Units
Symbol
tOLZ
tBLZ
Min
5
Max
—
—
—
7
Units
tAA
70
70
35
35
—
5
tCO
tLZ
10
0
ns
ns
tBA
tCHZ
tBHZ
tOHZ
tOE
0
7
tOH
0
7
117
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Page Read
MRS# = V , WE# = V , WAIT# = High-Z
IH
IH
t
RC
Valid
Address
A22~A2
A1~A0
tOH
t
AA
Valid
Valid
Valid
Valid
Address
Address Address Address
tPC
tCO
CS#
tBA
UB#, LB#
tBHZ
tOE
OE#
t
CHZ
t
tBOLZLZ
t
OHZ
t
PA
t
LZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data out
High Z
Figure 11.36. Timing Waveform Of Page Read Cycle
Notes:
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device interconnection.
3. In asynchronous 4 page read cycle, Clock, ADV# and WAIT# signals are ignored.
Table 11.18. Asynchronous Page Read AC Characteristics
Speed
Speed
Symbol
tRC
Min
70
—
Max
—
Units
Symbol
tOH
Min
3
Max
—
—
—
—
7
Units
tAA
70
—
tOLZ
tBLZ
tLZ
5
tPC
25
—
5
tPA
20
70
35
35
ns
10
0
ns
tCO
—
tCHZ
tBHZ
tOHZ
tBA
—
0
7
tOE
—
0
7
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
118
P r e l i m i n a r y
Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
tWC
Address
tWR
tCW
CS#
tAW
t
BW
UB#, LB#
WE#
tWP
tAS
tDW
tDH
High-Z
High-Z
Data in
Data out
Data Valid
High-Z
High-Z
Figure 11.37. Timing Waveform Of Write Cycle
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
2. tCW is measured from the CS# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Table 11.19. Asynchronous Write AC Characteristics
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tAS
Min
0
Max
—
Units
70
tCW
60
60
—
tWR
0
—
ns
tAW
—
ns
tDW
30
0
—
tBW
60
—
tDH
—
tWP
55 (note 1)
—
Notes:
1.
tWP(min) = 70ns for continuous write operation over 50 times.
119
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Write Cycle 2
MRS# = V , OE# = V , WAIT# = High-Z, UB# & LB# Controlled
IH
IH
tWC
Address
tWR
tCW
CS#
tAW
tBW
UB#, LB#
tAS
tWP
WE#
tDH
tDW
Data Valid
Data in
Data out
High-Z
High-Z
Figure 11.38. Timing Waveform of Write Cycle(2)
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
2. tCW is measured from the CS# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Table 11.20. Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tAS
Min
0
Max
—
Units
70
tCW
60
60
—
tWR
0
—
ns
tAW
—
ns
tDW
30
0
—
tBW
60
—
tDH
—
tWP
55 (note 1)
—
Notes:
1. tWP(min) = 70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
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P r e l i m i n a r y
Write Cycle (Address Latch Type)
MRS# = V , OE# = V , WAIT# = High-Z, WE# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
tADV
ADV#
tAS(A)
tAH(A)
Address
Valid
tCSS(A)
tCW
CS#
t
tBW
AW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDW
tDH
Data in
Data Valid
Read Latency5
High-Z
High-Z
Data out
Figure 11.39. Timing Waveform Of Write Cycle (Address Latch Type)
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation. A write ends at
the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of
write.
2.
t
AW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW
.
3. tCW is measured from the CS# going low to the end of write.
4. tBW is measured from the UB# and LB# going low to the end of write.
5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 11.21. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tADV
Min
7
Max
—
Units
Symbol
tBW
Min
Max
—
Units
ns
60
tAS(A)
tAH(A)
tCSS(A)
tCW
0
—
tWP
55 (note 2)
—
7
—
tWLRL
tAS
1
0
—
clock
ns
10
60
60
—
—
—
tDW
30
0
—
ns
tAW
—
tDH
—
Notes:
1. Address Latch Type, WE# Controlled.
2. tWP(min) = 70ns for continuous write operation over 50 times.
121
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Asynchronous Write Timing Waveform in Synchronous Mode
Write Cycle (Low ADV# Type)
MRS# = V , OE# = V , WAIT# = High-Z, WE# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
tWR
tCW
tAW
CS#
tBW
UB#, LB#
tWLRL
tWP
WE#
tAS
tDH
tDW
Data in
Data Valid
Read Latency 5
High-Z
Data out
High-Z
Figure 11.40. Timing Waveform Of Write Cycle (Low ADV# Type)
Notes:
1. Low ADV# type write cycle - WE# Controlled.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
3. tCW is measured from the CS# going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
6. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 11.22. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Max
—
Units
70
clock
tCW
60
60
—
0
—
tAW
—
ns
tWR
0
—
ns
tBW
60
—
tDW
30
0
—
tWP
55 (note 2)
—
tDH
—
Notes:
1. Low ADV# Type, WE# Controlled.
2. WP(min) = 70ns for continuous write operation over 50 times.
t
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
122
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Write Cycle (Low ADV# Type)
MRS# = V , OE# = V , WAIT# = High-Z, UB# & LB# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
tWC
Address
CS#
tWR
tCW
t
AW
tBW
UB#, LB#
WE#
tAS
tWLRL
tWP
tDH
tDW
Data Valid
Data in
Read Latency 5
High-Z
Data out
High-Z
Figure 11.41. Timing Waveform Of Write Cycle (Low ADV# Type)
Notes:
1. Low ADV# type write cycle - UB# and LB# Controlled.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
3. tCW is measured from the CS# going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
6. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 11.23. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
tWC
Min
Max
—
Units
Symbol
tWLRL
tAS
Min
1
Max
—
Units
70
clock
tCW
60
60
—
0
—
tAW
—
ns
tWR
0
—
ns
tBW
60
—
tDW
30
0
—
tWP
55 (note 2)
—
tDH
—
Notes:
1. Low ADV# type multiple write, UB#, LB# controlled.
2. tWP(min) = 70ns for continuous write operation over 50 times.
123
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
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Multiple Write Cycle (Low ADV# Type)
MRSE = V , OE# = V , WAIT# = High-Z, WE# Controlled
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
ADV#
Address
tWC
tWC
tWR
tWR
t
AW
tCW
t
AW
tCW
CS#
tBW
tBW
UB#, LB#
tWHP
tWP
tWP
WE#
tAS
tAS
tDH
tDH
tDW
tDW
Data in
Data Valid
DataValid
Data out
High-Z
High-Z
Figure 11.42. Timing Waveform Of Multiple Write Cycle (Low ADV# Type)
Notes:
1. Low ADV# type multiple write cycle.
2. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with
asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write
ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the
end of write.
3. tCW is measured from the CS# going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going
high.
6. Clock input does not have any affect on the asynchronous multiple write operation if tWHP is shorter than the (Read Latency
- 1) clock duration.
7.
tWP(min) = 70ns for continuous write operation over 50 times.
July 30, 2004 pSRAM_Type04_17A0
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P r e l i m i n a r y
Table 11.24. Asynchronous Write in Synchronous Mode AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
—
Min
5ns
0
Max
t
t
t
t
70
t
Latency-1 clock
—
WC
CW
AW
BW
WHP
60
60
—
t
—
—
—
—
AS
—
ns
t
0
WR
DW
ns
60
—
t
30
0
t
55 (note 2)
—
t
DH
WP
Notes:
1. Low ADV# type multiple write, WE# Controlled.
2.
tWP(min) = 70ns for continuous write operation over 50 times.
125
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
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AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to V -0.2V
CC
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x V
Output load (See Figure 11.34): CL = 30pF
CC
Vtt = 0.5 x V
DDQ
50
Ω
Dout
Z0=50
Ω
30pF
Figure 11.43. AC Output Load Circuit
July 30, 2004 pSRAM_Type04_17A0
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P r e l i m i n a r y
Table 11.25. Synchronous AC Characteristics
Speed
Parameter List
Symbol
Units
Min
15
—
0
Max
200
2500
—
Clock Cycle Time
T
Burst Cycle Time
t
BC
Address Set-up Time to ADV# Falling (Burst)
Address Hold Time from ADV# Rising (Burst)
ADV# Setup Time
t
t
AS(B)
AH(B)
7
—
t
t
5
—
ADVS
ADVH
ADV# Hold Time
7
—
CS# Setup Time to Clock Rising (Burst)
Burst End to New ADV# Falling
Burst Stop to New ADV# Falling
CS# Low Hold Time from Clock
CS# High Pulse Width
t
5
—
CSS(B)
t
7
—
BEADV
Burst Operation
(Common)
ns
t
12
7
—
BSADV
t
—
CSLH
CSHP
ADHP
t
t
55
—
—
—
—
—
1
—
ADV# High Pulse Width
—
Chip Select to WAIT# Low
t
10
10
12
7
WL
ADV# Falling to WAIT# Low
Clock to WAIT# High
t
AWL
t
WH
WZ
Chip De-select to WAIT# High-Z
UB#, LB# Enable to End of Latency Clock
Output Enable to End of Latency Clock
UB#, LB# Valid to Low-Z Output
Output Enable to Low-Z Output
Latency Clock Rising Edge to Data Output
Output Hold
t
t
—
clock
clock
BEL
OEL
BLZ
OLZ
t
t
1
—
5
—
t
5
—
t
—
3
10
—
CD
OH
Burst Read Operation
t
ns
Burst End Clock to Output High-Z
Chip De-select to Output High-Z
Output Disable to Output High-Z
UB#, LB# Disable to Output High-Z
t
—
—
—
—
10
7
HZ
t
CHZ
OHZ
t
7
t
7
BHZ
WE# Set-up Time to Command Clock
WE# Hold Time from Command Clock
WE# High Pulse Width
tWES
tWEH
tWHP
tBS
5
5
5
5
5
7
7
5
3
—
—
—
—
—
—
—
—
—
UB#, LB# Set-up Time to Clock
UB#, LB# Hold Time from Clock
Byte Masking Set-up Time to Clock
Byte Masking Hold Time from Clock
Data Set-up Time to Clock
Burst Write Operation
tBH
ns
tBMS
tBMH
tDS
Data Hold Time from Clock
tDHC
Note: (VCC = 1.7~2.0V, TA=-40 to 85 °C, Maximum Main Clock Frequency = 66MHz.
127
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Operation Timing Waveform
Latency = 5, Burst Length = 4 (MRS# = V )
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
tADVH
tADVS
ADV#
tBEADV
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
Undefined
Data out
Data in
DQ0 DQ1 DQ2 DQ3
D0
D1
D2
D3
D0
Burst Command Clock
Burst Read End Clock
Burst Write End Clock
Figure 11.44. Timing Waveform Of Basic Burst Operation
Table 11.26. Burst Operation AC Characteristics
Speed
Speed
Symbol
Min
15
—
5
Max
200
2500
—
Units
Symbol
tAS(B)
Min
0
Max
Units
T
—
—
—
—
tBC
tAH(B)
7
ns
ns
tADVS
tADVH
tCSS(B)
tBEADV
5
7
—
7
July 30, 2004 pSRAM_Type04_17A0
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P r e l i m i n a r y
Synchronous Burst Read Timing Waveform
Read Timings
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V , MRS# = V ). CS#
IH
IH
Toggling Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
t
CSHP
tCSS(B)
tBC
tBHZ
tBEL
LB#, UB#
OE#
tBLZ
tOHZ
tOEL
t
t
CHZ
t
OLZ
Latency 5
tCD
tOH
HZ
Undefined
Data out
WAIT#
DQ0 DQ1 DQ2 DQ3
tWZ
t
WL
t
WH
tWH
tWL
High-Z
Figure 11.45. Timing Waveform of Burst Read Cycle (1)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
129
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Table 11.27. Burst Read AC Characteristics
Speed
Speed
Symbol
tCSHP
tBEL
Min
5
Max
—
Units
Symbol
tOHZ
tBHZ
tCD
Min
—
—
—
3
Max
7
Units
ns
1
—
7
clock
ns
tOEL
1
—
10
—
10
12
7
tBLZ
5
—
tOH
ns
tOLZ
tHZ
5
—
tWL
—
—
—
—
—
10
7
tWH
tCHZ
tWZ
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V , MRS# = V ).
IH
IH
CS# Low Holding Consecutive Burst Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
CLK
t
ADVH
ADVS
t
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tCD
tOH
tHZ
Undefined
Data out
WAIT#
DQ0 DQ1 DQ2 DQ3
tAWL
tWH
t
WL
t
WH
High-Z
Figure 11.46. Timing Waveform of Burst Read Cycle (2)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge).
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
5. Burst Cycle Time (tBC) should not be over 2.5µs.
July 30, 2004 pSRAM_Type04_17A0
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Table 11.28. Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
tBLZ
tOLZ
tHZ
1
—
tOH
5
—
tWL
—
—
—
10
10
12
ns
5
—
ns
tAWL
tWH
—
10
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V , MRS# = V ).
IH
IH
Last data sustaining
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
t
ADVH
ADVS
t
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
tOH
tCD
Latency 5
Undefined
Data out
WAIT#
DQ0 DQ1 DQ2 DQ3
t
WL
t
WH
High-Z
Figure 11.47. Timing Waveform of Burst Read Cycle (3)
Notes:
1. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge).
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. Burst Cycle Time (tBC) should not be over 2.5µs.
131
pSRAM Type 4
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Table 11.29. Burst Read AC Characteristics
Speed
Speed
Symbol
tBEL
Min
1
Max
—
Units
Symbol
tCD
Min
—
3
Max
10
—
Units
clock
tOEL
1
—
tOH
ns
tBLZ
5
—
tWL
—
—
10
12
ns
tOLZ
5
—
tAWL
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pSRAM Type 4
132
P r e l i m i n a r y
Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V , MRS# = V ).
IH
IH
CS# Toggling Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
tADVH
tADVS
ADV#
tBEADV
tCSHP
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
tBC
tCSS(B)
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
tWH
Latency 5
tWH
Data in
WAIT#
D0
D1
D2
D3
D0
tWZ
tWL
tWL
High-Z
Figure 11.48. Timing Waveform of Burst Write Cycle (1)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
4. D2 is masked by UB# and LB#.
5. Burst Cycle Time (tBC) should not be over 2.5µs.
133
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Table 11.30. Burst Write AC Characteristics
Speed
Speed
Symbol
tCSHP
tBS
Min
5
Max
—
Units
Symbol
tWHP
tDS
Min
5
Max
—
Units
5
—
5
—
tBH
5
—
tDHC
tWL
3
—
ns
tBMS
tBMH
tWES
tWEH
7
—
ns
—
—
—
10
12
7
7
—
tWH
5
—
tWZ
5
—
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pSRAM Type 4
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P r e l i m i n a r y
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V , MRS# = V ).
IH
IH
CS# Low Holding Consecutive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
ADV
t
ADVH
ADVS
t
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Valid
Don’t Care
t
CSS(B)
tBC
tBS
tBMS
tBH
tBMH
LB#, UB#
WE#
tWEH
tWHP
tWES
tDS
tDHC
tDHC
Latency 5
Latency 5
Data in
WAIT#
D0
D1
D2
D3
D0
tWL
tAWL
tWH
tWH
High-Z
Figure 11.49. Timing Waveform of Burst Write Cycle (2)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
4. D2 is masked by UB# and LB#.
5. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
6. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.31. Burst Write AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
5
Max
—
Min
5
Max
—
t
t
t
WHP
BS
5
—
t
5
—
BH
DS
t
7
—
t
3
—
BMS
BMH
WES
WEH
DHC
ns
ns
t
t
7
—
t
—
—
—
10
10
12
WL
5
—
t
AWL
t
5
—
t
WH
135
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= V , MRS# = V ).
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
CLK
t
ADVH
ADVS
t
ADV#
tBSADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid
tCSHP
tCSS(B)
tCSLH
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
tOH
tCHZ
tCD
Latency 5
Undefined
Data
DQ0
DQ1
tWZ
t
WL
tWL
tWH
High-Z
High-Z
WAIT#
Figure 11.50. Timing Waveform of Burst Read Stop by CS#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Table 11.32. Burst Read Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
—
3
Max
10
—
t
t
BSADV
CD
t
t
—
ns
t
CSLH
CSHP
OH
5
—
t
—
—
—
—
7
CHZ
ns
t
1
—
t
10
12
7
BEL
OEL
BLZ
WL
WH
WZ
clock
ns
t
t
1
—
t
5
—
t
t
5
—
OLZ
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
136
P r e l i m i n a r y
Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= V , MRS# = V ).
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
T
CLK
t
ADVH
ADVS
t
ADV#
tBSADV
tAH(B)
tAS(B)
Don’t Care
Address
CS#
Valid
Valid
tCSHP
t
CSS(B)
tCSLH
tBS
tBH
LB#, UB#
WE#
tWHP
t
WEH
t
WES
tDS
tDHC
Latency 5
Latency 5
Data in
WAIT#
D0
D1
D0
D1
D2
tWZ
t
WL
t
WL
tWH
tWH
High-Z
High-Z
Figure 11.51. Timing Waveform of Burst Write Stop by CS#
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Table 11.33. Burst Write Stop AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
12
7
Max
—
Min
5
Max
—
t
t
WHP
BSADV
t
t
—
t
5
—
CSLH
CSHP
DS
5
—
t
3
—
DHC
ns
t
5
—
t
—
—
—
10
12
7
ns
BS
WL
WH
WZ
t
5
—
t
t
BH
t
5
—
WES
WEH
t
5
—
137
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= V , MRS# = V ).
IH
IH
0
1
2
3
4
5
6
7
8
9
10
11
T
CLK
t
ADVH
ADVS
t
ADV#
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
tCSS(B)
tBC
tBEL
LB#, UB#
OE#
tBLZ
tOEL
t
OLZ
Latency 5
tOHZ
tOLZ
tOH
tCD
tHZ
High-Z
Undefined
Data out
WAIT#
DQ0 DQ1
DQ1 DQ2 DQ3
tWZ
t
WL
t
WH
High-Z
Figure 11.52. Timing Waveform of Burst Read Suspend Cycle (1)
Notes:
1. If the clock input is halted during burst read operation, the data output will be suspended. During the burst read suspend
period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data will be output first.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during suspend
period, the previous data will be sustained.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.34. Burst Read Suspend AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
1
Max
—
Min
—
Max
10
7
t
t
HZ
BEL
OEL
BLZ
OLZ
clock
t
t
1
—
t
—
OHZ
5
—
t
—
10
12
7
WL
WH
WZ
ns
t
5
—
t
t
—
ns
t
—
3
10
—
—
CD
OH
t
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
138
P r e l i m i n a r y
Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4, WP = Low enable (MRS# = V ).
IH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tADV
tAH(A)
tBEADV
tAS(A)
tAH(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tAW
tCW
tBC
tCSS(A)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
WAIT#
tWL
tWZ
tWH
High-Z
High-Z
Read Latency 5
Figure 11.53. Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.35. Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
139
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAS(B)
Address
CS#
Valid
Don’t Care
Valid Adderss
tWR
tAW
tCW
tCSS(B)
tBC
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tHZ
High-Z
Data out
WAIT#
tWL
tWZ
tWH
High-Z
High-Z
Read Latency 5
Figure 11.54. Synchronous Burst Read to Asynchronous Write (Low ADV# Type)
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.36. Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
t
1
—
clock
BEADV
WLRL
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
140
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADVS
ADV#
tADV
tAH(A)
tAS(A)
tAS(B)
Address
CS#
Don’t Care
tAW
tCW
Don’t Care
tBC
Valid
Valid
tCSS(A)
tCSS(B)
tWLRL
tWP
WE#
OE#
tAS
tOEL
tBEL
tBW
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
Read Latency 5
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
WAIT#
Figure 11.55. Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.37. Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
WLRL
141
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
T
0
CLK
tADVH
tAH(B)
tADtHAPDVS
ADV#
Address
CS#
tAS(B)
tWC
Valid
Valid
Don’t Care
tBC
tAW
tCW
tWR
tCSS(B)
tWLRL
tWP
tBW
WE#
OE#
tAS
tOEL
tBEL
LB#, UB#
Data in
tDH
tDW
Data Valid
Latency 5
tCD
tOH
tHZ
Data out
High-Z
DQ0 DQ1 DQ2 DQ3
tWH
tWL
tWZ
High-Z
Read Latency 5
WAIT#
Figure 11.56. Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.38. Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
1
—
clock
t
—
ns
WLRL
ADHP
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
142
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBEL
tBS
tBH
LB#, UB#
Data in
tDS
Latency 5
tDHC
tWZ
D0 D1 D2 D3
High-Z
Latency 5
High-Z
tCD
tOH
DQ0 DQ1 DQ2 DQ3
tWZ
tHZ
High-Z
Data out
WAIT#
tWH
tWL
tWH
tWL
High-Z
Figure 11.57. Synchronous Burst Read to Synchronous Burst Write Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.39. Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
143
pSRAM Type 4
pSRAM_Type04_17A0 July 30, 2004
P r e l i m i n a r y
Latency = 5, Burst Length = 4 (MRS# = V ).
IH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
CLK
tADVH
tADVS
ADV#
tBEADV
tAH(B)
tAH(B)
tAS(B)
tAS(B)
Valid
Don’t Care
Valid
Address
CS#
tCSS(B)
tBC
tBC
tCSS(B)
tWES
tWEH
WE#
OE#
tOEL
tBS
tBH
tBEL
LB#, UB#
tDS
Latency 5
tDHC
D0 D1 D2
D3
High-Z
Data in
Data out
WAIT#
Latency 5
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
High-Z
tWL
tWH
tWZ
tWH
tWL
High-Z
Figure 11.58. Synchronous Burst Write to Synchronous Burst Read Timing
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (tWH): Data available (driven by Latency-1 clock)
/WAIT High-Z (tWZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (tBC) should not be over 2.5µs.
Table 11.40. Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed
Speed
Symbol
Units
Symbol
Units
Min
Max
Min
Max
t
7
—
ns
BEADV
July 30, 2004 pSRAM_Type04_17A0
pSRAM Type 4
144
P r e l i m i n a r y
Revision Summary
Revision A0 (November 8, 2004)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2003-2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Span-
sion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective compa-
nies.
November 8, 2004 S71WS512/256Nx0_UT
S71WS512Nx0/S71WS256Nx0
146
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Memory Circuit, 32MX16, CMOS, PBGA84, 12 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84
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Memory Circuit, 32MX16, CMOS, PBGA84, 12 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84
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SPANSION
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