S72NS256ND0AFW7J3 [SPANSION]
Based MCPs; 基于MCP的
| 型号： | S72NS256ND0AFW7J3 |
| 厂家： | 
SPANSION |
| 描述： | Based MCPs |
| 文件： | 总17页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S72NS-N Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBitTM Flash Memory & DRAM
128 Mb (8 M x 16 bit)/256 Mb (16 M x 16 bit),
110nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/Write,
Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR
DRAM
ADVANCE
INFORMATION
Data Sheet
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S72NS128_256ND0_00 Revision B Amendment 1 Issue Date November 9, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
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“This document states the current technical specifications regarding the Spansion product(s) described
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Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V range. Changes
IO
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S72NS128/256ND0 Based MCPs
S72NS128_256ND0_00_B1 November9,2005
S72NS-N Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBitTM Flash Memory & DRAM
128/256 Mb (8/16 M x 16 bit), 110nm CMOS 1.8 Volt-only,
Multiplexed, Simultaneous Read/Write, Burst Mode Flash Memory
and 128/256-Mb (8/16-M x 16-bit) DDR DRAM
ADVANCE
INFORMATION
Data Sheet
General Description
This document contains information on the S72NS-N MCP product family. Refer to the S29NS-N
data sheet (S29NS256/128N_01, revision A4) for full electrical specifications of the Flash memory
component. Refer to the DDR SDRAM Type 1 data sheet (revision A2) for full electrical specifica-
tions of the DDR SDRAM component. Refer to the DDR SDRAM Type 5 data sheet (revision A0)
for full electrical specifications of the DDR SDRAM component
The S72NS Series is a product line of stacked Multi-Chip Product (MCP) products and consists of:
One or more NS family multiplexed Flash memory die
DDR DRAM
The products covered by this document are listed in the table below.
DRAM Density
Flash Density
128 Mb
128 Mb
256 Mb
S72NS128ND0
S72NS256ND0
S72NS512ND0
S72NS256ND0
256 Mb
512 Mb
S72NS512NE0
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V
Packages, 133-ball FBGA
Burst Speeds
— 11.0 x 10.0 x 1.0 mm
— Flash = 66 MHz, 80 MHz
— DRAM = 133 MHz
— 8.0 x 8.0 x 1.0 mm
Operating Temperature of 25°C to +85°C
Product Selector Guide
Device- Model#
S72NS256ND0-7K
S72NS256ND0-7J
S72NS256ND0-73
S72NS256ND0-72
S72NS128ND0-1K
S72NS128ND0-1J
S72NS128ND0-13
S72NS128ND0-12
S72NS512ND0-7K
S72NS512ND0-7J
S72NS512ND0-73
S72NS512ND0-72
S72NS512NE0-7K
S72NS512NE0-7J
S72NS512NE0-73
S72NS512NE0-72
Flash Density DRAM Density
Flash Speed (MHz)
DRAM Speed (MHz) Supplier
Package
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
DRAM
Type 1
NLC133,
11x10mm
256 Mb
128 Mb
512 Mb
512 Mb
128 Mb
128 Mb
128 Mb
256 Mb
DRAM
Type 5
133
DRAM
Type 1
NLE133,
8x8mm
DRAM
Type 5
DRAM
Type 1
DRAM
Type 5
MTA133
11x10mm
133
DRAM
Type 1
DRAM
Type 5
Publication Number S72NS128_256ND0_00 Revision B Amendment 1 Issue Date November 9, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
Contents
1
2
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 256 Mb Flash + 128 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 512 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 512 Mb Flash + 256 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 128 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA)
3
4
5
11.0 x 10.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5.2 NLE133—133-ball Fine-Pitch Ball Grid Array (FBGA)
8.0 x 8.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 MTA133—133-ball Fine-Pitch Ball Grid Array (FBGA)
10.0 x 11.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
2
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
1 MCP Block Diagrams
F-RST#
F-VPP
RST#
VPP
A15-A0
ADQ15-ADQ0
DQ15-DQ0
CLK
F-CLK
F-RDY
F-WP#
WP#
MUX
Flash
Memory
NS-N
RDY
F-CE#
F-OE#
CE#
OE#
A16-Amax
A16-Amax
F-WE#
WE#
VCC
VCCQ
F-VCC
F-VCCQ
AVD#
F-VSS
AVD#
VSS
F2-CE#
Second NS-N (if needed)
CLK
CLK#
D-CLK
D-RAS#
D-CAS#
RAS#
D-CLK#
D-LDQS
D-UDQS
D-LDQM
D-UDQM
D-TEST
CAS#
BA0
DQS0
D-BA0
DQS1
DDR
DRAM
Memory
LDQM
UDQM
TEST
BA1
CKE
D-BA1
D-CKE
WE#
D-WE#
DQ15-DQ0
VSS
D-DQ15 - D-DQ0
D-VSS
D-Amax - D-A0
VSSQ
D-VSSQ
VCC
D-VCC
VCCQ
D-VCCQ
(Note 3)
Notes:
1. Amax indicates highest address bit for memory component:
a. Amax = A23 for NS256N, A22 for NS128N
b. Amax = A11 for 128 Mb DDR DRAM, A12 for 256-Mb DDR DRAM
2. For Flash, A0 – A15 is tied to DQ0 – DQ15.
3. For the NS512N, two NS-N devices are included. All signals are common to both except for CE#. F-CE# becomes F1-CE#, while the CE#
for the second flash is F2-CE#. This way, the two NS-N devices are separately accessed.
Figure 1.1. MCP Block Diagram
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
3
A d v a n c e I n f o r m a t i o n
2 Connection Diagrams
2.1
256 Mb Flash + 128 Mb DDR SDRAM Pinout
Legend
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DNU
D-TEST
D-VSSQ
D-VCCQ
D-DQ9
D-DQ8
D-VSS
D-VCC
D-VCC
D-DQ5
D-DQ3
D-VSSQ
DNU
DNU
Do Not Use
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
DNU
D-VSS
D-DQ13
D-UDQS
D-DQ10
D-VSSQ
D-VCCQ
D-VCCQ
D-LDQM
D-DQ6
D-DQ4
D-DQ1
D-VCCQ
DNU
C1
D-VCC
D1
C2
D-DQ15
D2
C3
D-DQ14
D3
C4
D-DQ12
D4
C5
C6
C7
C8
C9
C10
C11
C12
D-DQ2
D12
C13
D-DQ0
D13
C14
D-VSS
D14
Code Flash Only
D-DQ11
D-UDQM
D-VSS
D-VCC
D-VSSQ
D-DQ7
D-LDQS
RFU
NC
NC
INDEX
F-OE#
ADQ8
D-VCC
E1
E2
E3
E12
E13
E14
DRAM Only
RFU
A22
A17
ADQ9
ADQ1
ADQ0
F1
A23
F2
A19
F3
A18
F12
F-VSS
G12
F13
ADQ3
G13
F14
ADQ2
G14
Reserved for
Future Use
G1
G2
G3
F-CE#
H1
F-WP#
H2
F-WE#
H3
F-VCCQ
H12
ADQ11
H13
ADQ10
H14
No Connect
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1
J2
J3
J12
J13
J14
A16
F-VSS
NC
F-VSS
F-VSS
ADQ5
Index Location
K1
K2
K3
NC
K12
NC
K13
K14
A21
F-AVD#
ADQ7
ADQ6
L1
L2
L3
L12
LA13
L14
A20
F-RST#
D-CE#
F-VCCQ
ADQ15
ADQ14
M1
NC
M2
NC
M3
M4
M5
M6
M7
M8
M9
M10
M11
RFU
M12
NC
M13
M14
D-A3
D-A6
D-A9
D-CKE
D-VSS
D-WE#
D-A10
D-A1
F-RDY
F-VSS
N1
DNU
P1
N2
D-VSS
P2
N3
D-VCC
P3
N4
D-A5
P4
N5
D-A8
P5
N6
D-CAS#
P6
N7
D-CLK#
P7
N8
D-BA1
P8
N9
D-A11
P9
N10
D-A2
P10
N11
RFU
N12
RFU
N13
F-VCC
P13
N14
DNU
P14
DNU
P11
P12
DNU
DNU
NC
D-A4
D-A7
D-RAS#
D-CLK
D-VCC
D-BA0
D-A0
D-VCC
D-VSS
DNU
Figure 2.1. 133-ball Fine-Pitch Ball Grid Array, 256 Mb Flash + 128 Mb DDR DRAM
4
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
2.2 512 Mb Flash + 128 Mb DDR SDRAM Pinout
Legend
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DNU
D-TEST
D-VSSQ
D-VCCQ
D-DQ9
D-DQ8
D-VSS
D-VCC
D-VCC
D-DQ5
D-DQ3
D-VSSQ
DNU
DNU
Do Not Use
Flash Shared
Flash 1 Only
Flash 2 Only
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
DNU
D-VSS
D-DQ13
D-UDQS
D-DQ10
D-VSSQ
D-VCCQ
D-VCCQ
D-LDQM
D-DQ6
D-DQ4
D-DQ1
D-VCCQ
DNU
C1
D-VCC
D1
C2
D-DQ15
D2
C3
D-DQ14
D3
C4
D-DQ12
D4
C5
C6
C7
C8
C9
C10
C11
C12
D-DQ2
D12
C13
D-DQ0
D13
C14
D-VSS
D14
D-DQ11
D-UDQM
D-VSS
D-VCC
D-VSSQ
D-DQ7
D-LDQS
RFU
NC
NC
INDEX
F-OE#
ADQ8
D-VCC
E1
E2
E3
E12
E13
E14
RFU
A22
A17
ADQ9
ADQ1
ADQ0
F1
A23
F2
A19
F3
A18
F12
F-VSS
G12
F13
ADQ3
G13
F14
ADQ2
G14
G1
G2
G3
F1-CE#
H1
F-WP#
H2
F-WE#
H3
F-VCCQ
H12
ADQ11
H13
ADQ10
H14
DRAM Only
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1
J2
J3
J12
J13
J14
Reserved for
Future Use
A16
F-VSS
NC
F-VSS
F-VSS
ADQ5
K1
K2
K3
NC
K12
NC
K13
K14
A21
F-AVD#
ADQ7
ADQ6
L1
L2
L3
L12
LA13
L14
No Connect
A20
F-RST#
D-CE#
F-VCCQ
ADQ15
ADQ14
M1
NC
M2
NC
M3
M4
M5
M6
M7
M8
M9
M10
M11
RFU
M12
M13
M14
D-A3
D-A6
D-A9
D-CKE
D-VSS
D-WE#
D-A10
D-A1
F2-CE#
F-RDY
F-VSS
Index Location
N1
DNU
P1
N2
D-VSS
P2
N3
D-VCC
P3
N4
D-A5
P4
N5
D-A8
P5
N6
D-CAS#
P6
N7
D-CLK#
P7
N8
D-BA1
P8
N9
D-A11
P9
N10
D-A2
P10
N11
RFU
N12
RFU
N13
F-VCC
P13
N14
DNU
P14
DNU
P11
P12
DNU
DNU
NC
D-A4
D-A7
D-RAS#
D-CLK
D-VCC
D-BA0
D-A0
D-VCC
D-VSS
DNU
Figure 2.2. 133-ball Fine-Pitch Ball Grid Array, 512 Mb Flash + 128 Mb DDR DRAM
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
5
A d v a n c e I n f o r m a t i o n
2.3
512 Mb Flash + 256 Mb DDR SDRAM Pinout
Legend
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DNU
D-TEST
D-VSSQ
D-VCCQ
D-DQ9
D-DQ8
D-VSS
D-VCC
D-VCC
D-DQ5
D-DQ3
D-VSSQ
DNU
DNU
Do Not Use
Flash Shared
Flash 1 Only
Flash 2 Only
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
DNU
D-VSS
D-DQ13
D-UDQS
D-DQ10
D-VSSQ
D-VCCQ
D-VCCQ
D-LDQM
D-DQ6
D-DQ4
D-DQ1
D-VCCQ
DNU
C1
D-VCC
D1
C2
D-DQ15
D2
C3
D-DQ14
D3
C4
D-DQ12
D4
C5
C6
C7
C8
C9
C10
C11
C12
D-DQ2
D12
C13
D-DQ0
D13
C14
D-VSS
D14
D-DQ11
D-UDQM
D-VSS
D-VCC
D-VSSQ
D-DQ7
D-LDQS
RFU
NC
NC
INDEX
F-OE#
ADQ8
D-VCC
E1
E2
E3
E12
E13
E14
RFU
A22
A17
ADQ9
ADQ1
ADQ0
F1
A23
F2
A19
F3
A18
F12
F-VSS
G12
F13
ADQ3
G13
F14
ADQ2
G14
G1
G2
G3
F1-CE#
H1
F-WP#
H2
F-WE#
H3
F-VCCQ
H12
ADQ11
H13
ADQ10
H14
DRAM Only
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1
J2
J3
J12
J13
J14
Reserved for
Future Use
A16
F-VSS
NC
F-VSS
F-VSS
ADQ5
K1
K2
K3
NC
K12
NC
K13
K14
A21
F-AVD#
ADQ7
ADQ6
L1
L2
L3
L12
LA13
L14
No Connect
A20
F-RST#
D-CE#
F-VCCQ
ADQ15
ADQ14
M1
NC
M2
NC
M3
M4
M5
M6
M7
M8
M9
M10
M11
RFU
M12
M13
M14
D-A3
D-A6
D-A9
D-CKE
D-VSS
D-WE#
D-A10
D-A1
F2-CE#
F-RDY
F-VSS
Index Location
N1
DNU
P1
N2
D-VSS
P2
N3
D-VCC
P3
N4
D-A5
P4
N5
D-A8
P5
N6
D-CAS#
P6
N7
D-CLK#
P7
N8
D-BA1
P8
N9
D-A11
P9
N10
D-A2
P10
N11
D-A12
P11
N12
RFU
N13
F-VCC
P13
N14
DNU
P14
DNU
P12
DNU
DNU
NC
D-A4
D-A7
D-RAS#
D-CLK
D-VCC
D-BA0
D-A0
D-VCC
D-VSS
DNU
Figure 2.3. 133-ball Fine-Pitch Ball Grid Array, 512 Mb Flash + 256 Mb DDR DRAM
6
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
2.4 128 Mb Flash + 128 Mb DDR SDRAM Pinout
Legend
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DNU
D-TEST
D-VSSQ
D-VCCQ
D-DQ9
D-DQ8
D-VSS
D-VCC
D-VCC
D-DQ5
D-DQ3
D-VSSQ
DNU
DNU
Do Not Use
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
DNU
D-VSS
D-DQ13
D-UDQS
D-DQ10
D-VSSQ
D-VCCQ
D-VCCQ
D-LDQM
D-DQ6
D-DQ4
D-DQ1
D-VCCQ
DNU
C1
D-VCC
D1
C2
D-DQ15
D2
C3
D-DQ14
D3
C4
D-DQ12
D4
C5
C6
C7
C8
C9
C10
C11
C12
D-DQ2
D12
C13
D-DQ0
D13
C14
D-VSS
D14
Code Flash Only
D-DQ11
D-UDQM
D-VSS
D-VCC
D-VSSQ
D-DQ7
D-LDQS
RFU
NC
NC
INDEX
F-OE#
ADQ8
D-VCC
E1
E2
E3
E12
E13
E14
DRAM Only
RFU
A22
A17
ADQ9
ADQ1
ADQ0
F1
NC
F2
A19
F3
A18
F12
F-VSS
G12
F13
ADQ3
G13
F14
ADQ2
G14
Reserved for
Future Use
G1
G2
G3
F-CE#
H1
F-WP#
H2
F-WE#
H3
F-VCCQ
H12
ADQ11
H13
ADQ10
H14
No Connect
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1
J2
J3
J12
J13
J14
A16
F-VSS
NC
F-VSS
F-VSS
ADQ5
Index Location
K1
K2
K3
NC
K12
NC
K13
K14
A21
F-AVD#
ADQ7
ADQ6
L1
L2
L3
L12
LA13
L14
A20
F-RST#
D-CE#
F-VCCQ
ADQ15
ADQ14
M1
NC
M2
NC
M3
M4
M5
M6
M7
M8
M9
M10
M11
RFU
M12
NC
M13
M14
D-A3
D-A6
D-A9
D-CKE
D-VSS
D-WE#
D-A10
D-A1
F-RDY
F-VSS
N1
DNU
P1
N2
D-VSS
P2
N3
D-VCC
P3
N4
D-A5
P4
N5
D-A8
P5
N6
D-CAS#
P6
N7
D-CLK#
P7
N8
D-BA1
P8
N9
D-A11
P9
N10
D-A2
P10
N11
RFU
N12
RFU
N13
F-VCC
P13
N14
DNU
P14
DNU
P11
P12
DNU
DNU
NC
D-A4
D-A7
D-RAS#
D-CLK
D-VCC
D-BA0
D-A0
D-VCC
D-VSS
DNU
Figure 2.4. 133-ball Fine-Pitch Ball Grid Array, 128 Mb Flash + 128 Mb DDR DRAM
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
7
A d v a n c e I n f o r m a t i o n
3 Input/Output Descriptions
A23 – A0
DQ15 – DQ0
F-CE#
=
=
=
Flash Address inputs
Flash Data input/output
Flash Chip-enable input. Asynchronous relative to CLK for Burst
Mode
F-OE#
F-WE#
=
Flash Output Enable input. Asynchronous relative to CLK for Burst
mode.
Flash Write Enable input
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Flash Ground
=
=
=
=
=
F-V
F-V
F-V
CC
CCQ
SS
F-RDY
Flash ready output. Indicates the status of the Burst read. V
=
OL
data invalid. V
= data valid.
OH
F-CLK
=
Flash Clock. The first rising edge of CLK in conjunction with AVD#
low latches the address input and activates burst mode operation.
After the initial word is output, subsequent rising edges of CLK
increment the internal address counter. CLK should remain low
during asynchronous access.
F-AVD#
=
Flash Address Valid input. Indicates to device that the valid address
is present on the address inputs. V = for asynchronous mode,
IL
indicates valid address; for burst mode, causes starting address to
be latched on rising edge of CLK. V = device ignores address
IH
inputs
F-RST#
F-WP#
=
=
=
Flash hardware reset input. V = device resets and returns to
reading array data
IL
Flash hardware write protect input. V = disables program and
IL
erase functions in the four outermost sectors
F-V
Flash accelerated input. At V , accelerates programming;
PP
HH
automatically places device in unlock bypass mode. At V , disables
IL
all program and erase functions. Should be at V for all other
IH
conditions.
D-A11 – D-A0
D-DQ15 – D-DQ0 =
D-CLK
D-CE#
D-CKE
D-BA1 – BA0
D-RAS#
D-CAS#
D-DM1 – D-DM0
D-WE#
=
DRAM Address inputs.
DRAM Data input/output
DRAM System Clock
DRAM Chip Select
DRAM Clock Enable
=
=
=
=
=
=
=
=
=
=
=
=
=
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
DRAM Data Input/Output Mask
DRAM Write Enable input
DRAM Ground
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
D-V
D-V
D-V
D-V
SS
SSQ
CCQ
CC
D-UDQS
DRAM Upper Data Strobe, output with read data and input with
write data
D-LDQS
=
DRAM Lower Data Strobe, output with read data and input with
write data
D-CLK#
RFU
NC
=
=
=
=
DDR Clock for negative edge of CLK
Reserved for Future Use
No Connect. Can be connected to ground or left floating.
Internal Test mode pin for DDR DRAM only. Do not apply any signal
on this pin. Can be connected to ground or left floating.
D-TEST
8
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
4 Ordering Information
The order number (Valid Combination) is formed by the following:
S72NS
256
N
D0
AF
W
7
K
0
PACKING TYPE
0
2
3
=
=
=
Tray
7-inch Tape and Reel
13-inch Tape and Reel
MODEL NUMBER
K
J
3
2
=
=
=
=
DRAM Type 1, 66 MHz Flash/133 MHz DRAM
DRAM Type 1, 80 MHz Flash/133 MHz DRAM
DRAM Type 5, 66 MHz Flash/133 MHz DRAM
DRAM Type 5, 80 MHz Flash/133 MHz DRAM
PACKAGE MODIFIER
7
1
=
=
DDR DRAM, 133-ball, 11x10 mm, FBGA Multi-chip Package
DDR DRAM, 133-ball, 8.0x8.0 mm, FBGA Multi-chip Package
TEMPERATURE RANGE
Wireless (-25°C to +85°C)
W
=
PACKAGE TYPE
AF
AJ
ZJ
=
Thin profile Fine-pitch BGA Pb-free package
(0.5 mm pitch, 1.0 mm height)
= Thin profile Fine-pitch BGA Pb-free LF35 package
(0.5 mm pitch, 1.0 mm height)
= Thin profile Fine-pitch BGA Pb-free LF35 package
(0.5 mm pitch, 1.2 mm height)
DRAM AND DATA FLASH DENSITY
D0
E0
=
=
128 Mb DRAM, No Data Flash
256 Mb DRAM, No Data Flash
PROCESS TECHNOLOGY
110 nm, MirrorBitTM Technology
N
=
CODE FLASH DENSITY
512
256
128
=
=
=
512 Mb
256 Mb
128 Mb
PRODUCT FAMILY
S72NS Multi-Chip Product (MCP)
1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus
Valid Combinations
Code Flash
Density
(Mb)
DRAM
Density
(Mb)
Package Type/
Marking/
Material
Product
Family
Process
Technology
Tempe rature
Range
Package
Modifier
Model
Number
Packing
Type
128
256
512
1
7
D0
E0
AF, AJ
ZJ
S72NS
N
W
K, J, 2, 3
0, 2, 3
Valid Combinations
Notes:
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
9
A d v a n c e I n f o r m a t i o n
5 Physical Dimensions
5.1
NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA)
11.0 x 10.0 x 1.0 mm MCP Package
NOTES:
PACKAGE
JEDEC
NLC 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.0 mm x 10.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
1.00
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.90
0.20
0.70
10.9
9.9
1.10
0.30
0.82
11.1
10.1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
0.76
BODY THICKNESS
BODY SIZE
D
11.0
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
10.0
BODY SIZE
D1
E1
6.50 BSC.
6.50 BSC.
14
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
D5-D11, E4-E11, F4-F11
G4-G11, H4-H11, J4-J11
K4-K11, L4-L11
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3436 \ 16-039.22 \ 12.09.04
10
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
5.2 NLE133—133-ball Fine-Pitch Ball Grid Array (FBGA)
8.0 x 8.0 x 1.0 mm MCP Package
D1
D
A
A1 CORNER
eD
+0.20
-0.50
1.00
A1 ID.
14 13 12 11 10
9
8
7
6
5
4
3
2
1
eE
0.10
C
A
B
0.50 REF
C
D
E
0.50 REF
7
SE
F
G
H
J
E
E1
K
L
M
N
P
B
φb
SD
6
7
0.10
C
φ 0.08
φ 0.15
M
M
C
C
A
B
TOP VIEW
BOTTOM VIEW
0.10
C
A2
A
A1
0.08
C
C
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
JEDEC
NLE 133
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
8.00 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1
SPP-010.
SYMBOL
MIN
NOM
1.00
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.90
0.20
0.70
7.90
7.90
1.10
0.30
0.82
8.10
8.10
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
A2
0.76
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
8.00
E
8.00
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
6.50 BSC.
6.50 BSC.
14
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
SD / SE
BALL PITCH
SOLDER BALL PLACEMENT
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS
H4-H11,J4-J11,K4-K11,L4-L11
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3513 \ 16-038.22 \ 08.09.05
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
11
A d v a n c e I n f o r m a t i o n
5.3
MTA133—133-ball Fine-Pitch Ball Grid Array (FBGA)
10.0 x 11.0 x 1.0 mm MCP Package
A
D
PIN A1
CORNER
D1
PIN A1
CORNER
9
eD
INDEX MARK
A
B
C
D
E
SE
7
F
G
H
E
B
E1
J
K
L
M
N
eE
P
0.10
(2X)
C
14 13 12 11 10
9
8
7
6
5
4
2
1
3
SD
BOTTOM VIEW
7
0.10
(2X)
C
TOP VIEW
0.10
0.08
C
C
A2
A
A1
C
SIDE VIEW
6
133X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
MTA 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
JEDEC
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D X E
11.00 mm x 10.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3.0, SPP-010.
SYMBOL
MIN
NOM
---
MAX
1.30
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.91
---
---
BALL HEIGHT
---
1.06
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
11.00 BSC.
10.00 BSC.
6.50 BSC.
6.50 BSC.
14
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
14
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
133
N
133
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PERIMETERS
BALL DIAMETER
R
2
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
eD
SE SD
0.25
0.30
0.35
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALL
4L ~ 4E, 5L ~ 5D, 6L ~ 6D,
7L ~ 7D, 8L ~ 8D, 9L ~ 9D,
10L ~ 10D, 11L ~ 11D
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3529 / 16.038 / 11.08.05
12
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
6 Revision Summary
MCP Revision History
Revision A0 (January 3, 2005)
Initial release.
Revision A1 (April 25, 2005)
Global
Updated the flash module
Updated the SDRAM Type 1 module
Revision A2 (May 20, 2005)
Global
Data sheet format modularized.
Distinctive Characteristics
Package description changed from 10.0 x 11.0 x 1.0 to 11.0 x 10.0 x 1.0
MCP Block Diagrams
Changed the F-ACC signal to F-VPP
Changed the ACC description to VPP
Connection Diagrams
Changed the F-ACC pin to F-VPP
Input/Output Descriptions
Updated description for F-RDY
Changed the F-ACC description to F-VPP
Updated description for NC and D-TEST
Product Revision Identification
New section added.
Revision B0 (August 15, 2005)
Global
Data sheet revised to include 128/128 MCP details.
Distinctive Characteristics
Package description changed to include new 128/128 MCP details and update the Product Se-
lector Guide table.
Connection Diagrams
New 128 Mb Flash + 128 Mb DDR SDRAM Pinout added.
Ordering Information
New valid combinations added to the table.
Physical Dimensions
New illustration for 8.0 x 8.0 x 1.0 mm MCP Package added.
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
13
A d v a n c e I n f o r m a t i o n
Revision B1 (November 9, 2005)
Added DDR DRAM Type 5 Information
Updated General Description, Product Selector Guide, Ordering Information, and Valid Combina-
tions with DDR DRAM Type 5 Information.
S29NS-N Flash Module
Removed all of the Revision Summary except for A4 (request from customer).
SDRAM (Micron) Revision Summary
Removed all of the Revision Summary except for A1 (request from customer).
SDRAM (Elpida) Revision Summary
New SDRAM to be added to MCP
S29NS-N Revision Summary
Revision A4 Flash Module (April 21, 2005)
Global Changes
Removed all ordering options and package information listed in revision A4 of the discrete data sheet.
Removed 54 MHz speed option.
Changed ACC to V
PP.
Read Access Times
Removed burst access for 54MHz.
Defined asynchronous random access and synchronous random access to 80 ns for all speed options.
DC Characteristics
CMOS Compatible Table.
Updated I
and I
values from 40 µA to 70 µA.
CC3
CC6
SDRAM Type 1 Revision Summary
Revision A2 (November 1, 2005)
Features
Changed V /V
range from 1.7 V-1.9 V to 1.7 V-1.95 V
DD DDQ
Indicated temperature range (-40°C to 85°C)
Stopping the External Clock
Removed information that limited the rate of frequency change.
IDD Specifications and Conditions table
Specifications and conditions updated.
Electrical Characteristics and Recommended AC Operating Conditions table
Removed t
parameter
REFC
SDRAM Type 5 Revision Summary
Revision A0 (September 30, 2005)
Initial release. New SDRAM module.
14
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is
without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of
third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright © 2005 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion.
Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
15
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