S72NS256RD0AHBG03 [SPANSION]
Memory Circuit, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133;
| 型号： | S72NS256RD0AHBG03 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133 |
| 文件： | 总13页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S72NS-R Based MCPs
MirrorBit® Flash Memory and DRAM
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed
Simultaneous Read/Write, Burst Mode Flash Memory
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
S72NS-R Based MCPs Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S72NS-R_00
Revision 07
Issue Date May 10, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
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S72NS-R Based MCPs
S72NS-R_00_07 May 10, 2010
S72NS-R Based MCPs
MirrorBit® Flash Memory and DRAM
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed
Simultaneous Read/Write, Burst Mode Flash Memory
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V
Packages
– 8.0 x 8.0 mm, 133-ball MCP
Burst Speeds
– 11.0 x 10.0 mm, 133-ball MCP
– Flash = 83MHz, 104 MHz
– DDR DRAM = 133 MHz, 166 MHz
Operating Temperature of –25°C to +85°C
General Description
This document contains information on the S72NS-R MCP stacked products. Refer to the S29NS-R data sheet
(S29NS-R_00) for full electrical specifications of the Flash memory component.
The S72NS Series is a product line of stacked products (MCPs), and consists of:
S29NS family multiplexed Flash memory die
DDR DRAM
The products covered by this document are listed in the tables below.
DRAM Density
Flash Density
128 Mb
128 Mb
256 Mb
S72NS128RD0
S72NS256RD0
S72NS512RD0
256 Mb
512 Mb
S72NS512RE0
DDR Specification Reference
Spansion Documentation
Publication Number
DRAM_15
Density
Manufacturer
DRAM Type 5
DRAM Type 1
DRAM Type 6
DRAM Type 5
DRAM Type 1
128 Mb
DRAM_07
CustComspec_02
DRAM_14
256 Mb
DRAM_08
Publication Number S72NS-R_00
Revision 07
Issue Date May 10, 2010
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
1. Product Selector Guide
Flash
DDR DRAM Flash Speed
DDR DRAM
DRAM
Device OPN
Density
Density
(MHz)
Speed (MHz)
Supplier
Package
S72NS128RD0AHBL0 (1)
S72NS128RD0AHBG0
S72NS128RD0AHBM0
S72NS256RD0AHBL0
S72NS256RD0AHBG0
S72NS256RD0AHBM0
S72NS512RD0AHGL0
S72NS512RD0AHGG0
S72NS512RD0AHGM0
S72NS512RD0KHFL0
S72NS512RD0KHFM0
S72NS512RE0AHGG4
S72NS512RE0AHGL0
S72NS512RE0AHGG0
S72NS512RE0KHFL0
S72NS512RE0KHFG0
Type 5
Type 1
Type 6
Type 5
Type 1
Type 6
Type 5
Type 1
Type 6
Type 5
Type 6
Type 1
Type 5
Type 1
Type 5
Type 1
8.0 x 8.0 mm
133-ball MCP (RLB133)
128 Mb
128 Mb
83
166
166
8.0 x 8.0 mm
133-ball MCP (RLB133)
256 Mb
512 Mb
128 Mb
128 Mb
83
83
11.0 x 10.0mm
133-ball MCP (RLD133)
166
166
12.0 x 12.0 mm
128-ball PoP (ALF128)
104
83
11.0 x 10.0 mm
133-ball MCP (RLD133)
512 Mb
256 Mb
12.0 x 12.0 mm
128-ball PoP (ALF128)
Notes
1. For S72NS128RD0AHBL0 only: the Factory Secured Silicon Area contains a random, 128-bit Electronic Serial Number (ESN), stored in
the address range 000000h-000007h.
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
2. Product Block Diagram
F-RST#
RST#
ACC
A15-A0
ADQ15-ADQ0
F-ACC
DQ15-DQ0
CLK
F-CLK
F-RDY
MUX
Flash
Memory
S29NS-R
RDY
F-CE#
F-OE#
CE#
OE#
Amax - A16
Amax - A16
F-WE#
WE#
VCC
F-VCC
AVD#
F-VSS
AVD#
VSS
VCCQ
F-VCCQ
CLK
CLK#
D-CLK
D-RAS#
D-CAS#
RAS#
CAS#
D-CLK#
DQS0
D-LDQS
D-UDQS
D-LDQM
D-UDQM
D-TEST
D-DQ15 - D-DQ0
D-VSS
BA0
BA1
CKE
WE#
D-BA0
D-BA1
D-CKE
D-WE#
D-CE#
DQS1
DDR
DRAM
Memory
LDQM
UDQM
TEST
DQ15-DQ0
VSS
CE#
D-Amax - D-A0
VSSQ
D-VSSQ
VCC
D-VCC
VCCQ
D-VCCQ
Notes:
1. Amax indicates highest address bit for memory component:
a. Amax = A25 for NS01GR, A24 for NS512R, A23 for NS256R, A22 for NS128R
b. Amax = A11 for 128 Mb DDR DRAM
c. Amax = A12 for 256 Mb DDR DRAM
2. For Flash, A15 - A0 is tied to DQ15 - DQ0.
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
3. Connection Diagrams
Figure 3.1 133-ball Fine-Pitch Ball Grid Array MCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
Index Location
DNU D-TEST D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU
DNU
DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQD-VCCQD-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU
D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS
Do Not Use
No Connect
RFU
A24
NC
A22
A19
NC
NC
A17
INDEX
F-OE# ADQ8 D-VCC
ADQ9 ADQ1 ADQ0
F-VSS ADQ3 ADQ2
F-VCCQ ADQ11 ADQ10
ADQ13 ADQ12 ADQ4
F-VSS F-VSS ADQ5
DRAM Only
Code Flash Only
A23
A18
Reserved for Future Use
G
F-CE#
F-WE#
H
J
F-ACC F-VCC F-CLK
A16
F-VSS
NC
NC
K
L
A21 F-AVD#
NC
ADQ7 ADQ6
A20 F-RST# D-CE#
F-VCCQ ADQ15 ADQ14
M
N
NC
NC
D-A3
D-A6
D-A9 D-CKE D-VSS D-WE# D-A10
D-A8 D-CAS# D-CLK# D-BA1 D-A11
D-A1
D-A2
NC
NC
NC
F-RDY F-VSS
F-VCC DNU
DNU D-VSS D-VCC D-A5
D-A12
P
DNU
DNU
NC
D-A4
D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU
DNU
Note:
Additional NC locations are in reference to the superset connection diagram shown here
Device OPN
S72NS128RD0
S72NS256RD0
S72NS512RD0
S72NS512RE0
Flash Address Amax
DDR DRAM Address Amax
Additional NC Locations
Ball F1, Ball E1, Ball N11
Ball E1, Ball N11
Ball N11
A22
A23
A24
A24
A11
A11
A11
A12
N/A
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S72NS-R Based MCPs
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
4. Input/Output Descriptions
Amax – A16
ADQ15 – ADQ0
F-CE#
=
=
=
=
=
=
=
=
=
=
Flash Address inputs
Flash multiplexed Address and Data
Flash Chip-enable input.
F-OE#
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
Flash Write Enable input
F-WE#
F-VCC
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Flash Ground
F-VCCQ
F-VSS
F-RDY
Flash ready output. Indicates the status of the Burst read. V = data invalid. V = data valid.
OL OH
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates
burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal
address counter. CLK should remain low during asynchronous access.
F-CLK
=
Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. V = for
IL
F-AVD#
asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising
edge of CLK. V = device ignores address inputs
IH
F-RST#
F-ACC
=
=
Flash hardware reset input. V = device resets and returns to reading array data
IL
Flash accelerated input. At V , accelerates programming; automatically places device in unlock bypass
HH
mode. At V , disables all program and erase functions. Should be at V for all other conditions.
IL
IH
D-A12 – D-A0
D-DQ15 – D-DQ0
D-CLK
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
DRAM Address inputs.
DRAM Data input/output
DRAM System Clock
D-CE#
DRAM Chip Select
D-CKE
DRAM Clock Enable
D-BA1 – BA0
D-RAS#
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
DRAM Data Input Mask
DRAM Write Enable input
DRAM Ground
D-CAS#
D-UDQM – D-LDQM
D-WE#
D-VSS
D-VSSQ
D-VCCQ
D-VCC
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
D-UDQS
D-LDQS
D-CLK#
DRAM Upper Data Strobe, output with read data and input with write data
DRAM Lower Data Strobe, output with read data and input with write data
DDR Clock for negative edge of CLK
RFU
Reserved for Future Use
NC
No Connect. Can be connected to ground or left floating.
Internal Test mode pin for DDR DRAM only. Do not apply any signal on this pin. Can be connected to ground
or left floating.
D-TEST
DNU
=
Do Not Use
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S72NS-R Based MCPs
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5. Ordering Information
The order number (Valid Combination) is formed by the following:
S72NS
256
R
D0
AH
B
L
C
3
PACKING TYPE
0 = Tray
3 = 13-inch Tape and Reel
FLASH and DDR SPEED
0 = 83 MHz Flash, 166 MHz DDR DRAM
4 = 104 MHz Flash, 166 MHz DDR DRAM
DDR Supplier
G = DRAM Type 1 x16 DDR DRAM
L = DRAM Type 5 x16 DDR DRAM
M = DRAM Type 6 x16 DDR DRAM
PACKAGE MODIFIER
B = 133-ball, 8x8mm, FBGA MCP
G = 133-ball, 11x10mm, FBGA MCP
PACKAGE AND MATERIAL TYPE
AH = Thin profile Fine-pitch BGA Pb-free Low-Halogen MCP (0.5 mm pitch)
DDR DRAM AND DATA FLASH DENSITY
D0 = 128 Mb DDR, No Data Flash
E0 = 256 Mb DDR, No Data Flash
PROCESS TECHNOLOGY
R = 65 nm, MirrorBit® Technology
CODE FLASH DENSITY
512 = 512 Mb
256 = 256 Mb
128 = 128 Mb
PRODUCT FAMILY
S72NS Multi-Chip Product (MCP)
1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus
Valid Combinations
Product
Family
Code Flash
Density (Mb)
Process
Technology
DDR Density Package Type/
Flash & DDR
Speed
(Mb)
Material
AHB, KHF
AHG, KHF
DDR Vendor
G, L, M
Packing Type
128
256
512
D0
S72NS
R
0, 4
0, 3 (Note 1)
E0
G, L
Notes
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type designator from ordering part number.
3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
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S72NS-R Based MCPs
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6. Physical Dimensions
6.1
RLB133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm
NOTES:
PACKAGE
JEDEC
RLB 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
8.0 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
0.80
0.18
0.62
7.90
7.90
NOM
0.90
MAX
NOTE
OVERALL THICKNESS
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.00
0.28
0.74
8.10
8.10
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.23
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
0.68
BODY THICKNESS
D
8.00
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
8.00
BODY SIZE
D1
E1
6.50 BSC.
6.50 BSC.
14
BALL FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
N
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
e
0.25
0.30
0.35
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.25 BSC.
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
D5-D11, E4-E11, F4-F11
G4-G11, H4-H11, J4-J11
K4-K11, L4-L11
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3627 \ 16-039.63 \ 8.21.7
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6.2
RLD133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 mm
NOTES:
PACKAGE
JEDEC
RLD 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.0 mm x 10.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
OVERALL THICKNESS
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.80
0.18
0.62
1.00
---
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.74
BODY THICKNESS
D
11.00 BSC.
10.00 BSC.
6.50 BSC.
6.50 BSC.
14
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
BALL FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
N
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
e
0.25
0.30
0.35
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.25 BSC.
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
D5-D11, E4-E11, F4-F11
G4-G11, H4-H11, J4-J11
K4-K11, L4-L11
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3674 \ 16-039.63 \ 2.11.8
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S72NS-R Based MCPs
S72NS-R_00_07 May 10, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6.3
ALF128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm
NOTES:
PACKAGE
JEDEC
ALF 128
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
D x E
12.00 mm x 12.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3.0, SPP-010.
SYMBOL
MIN
NOM
0.95
MAX
NOTE
A
A1
A2
D
0.85
0.38
0.49
1.05
0.48
0.59
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.43
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.54
BODY THICKNESS
12.00 BSC.
12.00 BSC.
11.05 BSC.
11.05 BSC.
18
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
18
128
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
N
128
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PERIMETERS
BALL DIAMETER
R
2
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
eD
SE / SD
0.43
0.48
0.53
0.65 BSC.
0.65 BSC.
0.325 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
C3-C16,D3-D16,E3-E16,
F3-F16,G3-G16,H3-H16,
J3-J16,K3-K16,L3-L16,
M3-M16,N3-N16,P3-P16,
R3-R16,T3-T16
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3658 \ 16-038.24 \ 10.12.7
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S72NS-R Based MCPs
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
7. Revision History
Section
Description
Revision 01 (August 7, 2007)
Initial release
Revision 02 (August 24, 2007)
Global
Updated package names and drawings for S72NS-R MCPs
Updated speed grades for all S72NS-R product offerings
Revision 03 (January 15, 2008)
Global
Revision 04 (February 13, 2008)
Global
Changed RSA133 package to RLD133 and updated outline drawing
Corrected typographical character errors in example OPN
Ordering Information
Revision 05 (May 9, 2008)
Global
Added ALF128 package and updated DRAM publication numbers
Updated OPNs
Ordering Information
Revision 06 (December 4, 2008)
General Description
DDR Specification Reference
Product Selector Guide
Revision 07 (May 10, 2010)
Product Selector Guide
Removed 1Gb flash density
Changed publication number for 128 Mb DRAM Type 6 from DRAM_09 to CustComspec_02
Added ESN note for S72NS128RD0AHBL0
Added OPN S72NS512RE0AHGG4
12
S72NS-R Based MCPs
S72NS-R_00_07 May 10, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2007-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
May 10, 2010 S72NS-R_00_07
S72NS-R Based MCPs
13
相关型号：
S72NS256RD0AHBG40
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBG43
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBL00
Memory Circuit, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBL03
Memory Circuit, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBL40
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBL43
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBM00
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBM03
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBM40
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
S72NS256RD0AHBM43
Memory Circuit, Flash+SDRAM, 16MX16, CMOS, PBGA133, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133
SPANSION
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