S72NS512PD0KFFLG0 [SPANSION]
Memory Circuit, 32MX16, CMOS, PBGA128, 12 X 12 MM, 0.48 MM PITCH, LEAD FREE, FBGA-128;
| 型号： | S72NS512PD0KFFLG0 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 32MX16, CMOS, PBGA128, 12 X 12 MM, 0.48 MM PITCH, LEAD FREE, FBGA-128 动态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S72NS-P MCP/PoP Memory System
Solutions
MirrorBit® Flash Memory and DRAM
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed
Simultaneous Read/Write, Burst Mode Flash Memory
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
S72NS-P MCP/PoP Memory System Solutions Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S72NS-P_00
Revision 07
Issue Date September 24, 2008
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
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S72NS-P MCP/PoP Memory System Solutions
S72NS-P_00_07 September 24, 2008
S72NS-P MCP/PoP Memory System
Solutions
MirrorBit® Flash Memory and DRAM
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed
Simultaneous Read/Write, Burst Mode Flash Memory
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V
Packages
– 11.0 x 10.0 mm, 133-ball MCP
Burst Speeds
– 8.0 x 8.0 mm, 133-ball MCP
– 12.0 x 12.0 mm, 128-ball PoP
– Flash = 66 MHz, 83 MHz
– DRAM = 133 MHz, 166 MHz
Operating Temperature of –25°C to +85°C
General Description
This document contains information on the S72NS-P MCP stacked products. Refer to the S29NS-P data sheet (S29NS-P_00)
for full electrical specifications of the Flash memory component.
The S72NS Series is a product line of stacked products (MCPs and PoPs), and consists of:
NS family multiplexed Flash memory die
DDR DRAM
The products covered by this document are listed in the tables below.
DRAM Density
Flash Density
128 Mb
128 Mb
256 Mb
S72NS128PD0
S72NS256PD0
S72NS512PD0
256 Mb
512 Mb
S72NS512PE0
For detailed specifications, please refer to the individual data sheets.
Density
Manufacturer
Publication Number
DRAM1
DRAM_07
128
SDRAM_07 (90 nm)
DRAM_15 (70 nm)
DRAM5
Density
Manufacturer
Publication Number
DRAM1
DRAM_08
256
SDRAM_11 (90 nm)
DRAM_14 (70 nm)
DRAM5
Publication Number S72NS-P_00
Revision 07
Issue Date September 24, 2008
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
1. Product Selector Guide
Flash
Density
DDR DRAM
Density
Flash Speed
(MHz)
DDR DRAM
Speed (MHz)
Supplier
(1)
Device OPN
Package
S72NS128PD0AJBGG
S72NS128PD0AJBGC
S72NS128PD0AHBLG
S72NS128PD0AHBLC
S72NS256PD0AJBGG
S72NS256PD0AJBGC
S72NS256PD0AJBLG
S72NS256PD0AJBLC
S72NS512PD0AJGGG
S72NS512PD0AJGGC
S72NS512PD0AJGLG
S72NS512PD0AHGLG
S72NS512PD0AJGLC
S72NS512PD0AHGL4 (2)
S72NS512PE0AJGLG
S72NS512PE0AJGLC
S72NS512PE0KFFGG
S72NS512PE0KFFG0
66
83
66
83
66
83
66
83
66
83
66
66
83
66
66
83
66
83
DRAM1
DRAM5
DRAM1
DRAM5
DRAM1
8.0 x 8.0 mm 133-ball MCP
(NSC133)
128 Mb
128 Mb
128 Mb
133
133
8.0 x 8.0 mm 133-ball MCP
(NSC133)
256 Mb
512 Mb
133
11.0 x 10.0 mm 133-ball MCP
(NLC133)
128 Mb
DRAM5
166
133
11.0 x 10.0 mm 133-ball MCP
(NLC133)
512 Mb
512 Mb
256 Mb
256 Mb
DRAM5
DRAM1
133
166
12.0 x 12.0 mm 128-ball PoP
0.48 mm ball (ALF128)
Note
1. Please contact your local Spansion sales representative for exact RAM version as multiple DRAM5 versions may exist for a given product.
2. Not recommended for new designs.
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
2. Product Block Diagram
F-RST#
RST#
ACC
A15-A0
ADQ15-ADQ0
F-ACC
F-WP#
DQ15-DQ0
CLK
F-CLK
F-RDY
WP#
MUX
Flash
Memory
NS-P
RDY
F-CE#
F-OE#
CE#
OE#
Amax - A16
Amax - A16
F-WE#
WE#
VCC
F-VCC
AVD#
F-VSS
AVD#
VSS
VCCQ
F-VCCQ
F2-CE#
CLK
CLK#
D-CLK
D-RAS#
D-CAS#
RAS#
CAS#
D-CLK#
DQS0
D-LDQS
D-UDQS
D-LDQM
D-UDQM
D-TEST
D-DQ15 - D-DQ0
D-VSS
BA0
BA1
CKE
WE#
D-BA0
D-BA1
D-CKE
D-WE#
D-CE#
DQS1
DDR
DRAM
Memory
LDQM
UDQM
TEST
DQ15-DQ0
VSS
CE#
D-Amax - D-A0
VSSQ
D-VSSQ
VCC
D-VCC
VCCQ
D-VCCQ
Notes:
1. Amax indicates highest address bit for memory component:
a. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P
b. Amax = A11 for 128 Mb DDR DRAM
c. Amax = A12 for 256 Mb DDR DRAM
2. For Flash, A15 - A0 is tied to DQ15 - DQ0.
3. F2-CE# applicable for second Flash die, if any.
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3. Connection Diagrams
Figure 3.1 133-ball Fine-Pitch Ball Grid Array MCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
Index Location
DNU
DNU D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU
DNU
DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQD-VCCQD-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU
D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS
Do Not Use
No Connect
RFU
A24
A23
NC
A22
A19
NC
A17
A18
INDEX
F-OE# ADQ8 D-VCC
ADQ9 ADQ1 ADQ0
F-VSS ADQ3 ADQ2
F-VCCQ ADQ11 ADQ10
ADQ13 ADQ12 ADQ4
F-VSS F-VSS ADQ5
DRAM Only
Code Flash Only
Reserved for Future Use
G
F-CE# F-WP# F-WE#
F-ACC F-VCC F-CLK
H
J
A16
F-VSS
NC
NC
K
L
A21 F-AVD#
NC
ADQ7 ADQ6
A20 F-RST# D-CE#
F-VCCQ ADQ15 ADQ14
M
N
NC
NC
D-A3
D-A6
D-A9 D-CKE D-VSS D-WE# D-A10
D-A8 D-CAS# D-CLK# D-BA1 D-A11
D-A1
D-A2
NC
NC
NC
F-RDY F-VSS
F-VCC DNU
DNU D-VSS D-VCC D-A5
D-A12
P
DNU
DNU
NC
D-A4
D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU
DNU
Note:
Additional NC locations are in reference to the superset connection diagram shown here
Device OPN
S72NS128PD0
S72NS256PD0
S72NS512PD0
S72NS512PE0
Flash Address Amax
DDR DRAM Address Amax
Additional NC Locations
Ball F1, Ball E1, Ball N11
Ball E1, Ball N11
Ball N11
A22
A23
A24
A24
A11
A11
A11
A12
N/A
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Figure 3.2 128-ball Fine Pitch Ball Grid Array PoP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Legend
A
B
C
D
E
F
NC
NC
D-DQ1 D-VSS VCC
N-CLE F-A17 F-A19 F-A21 F-A23 F-A25
DPD
F-ACC N-WE# F-WE# N2-CE#/ NC
F3-CE#
NC
No Connect
NC D-VCCQ D-DQ0 D-VCC VSS
D-VSSQ D-DQ2
N-ALE F-A16 F-A18 F-A20 F-A22 F-A24 F-A26 F-RST# N-RE# F-OE# N1-CE#/ N-RY/BY# NC
F4-CE#
DDR DRAM Only
NOR Flash Only
F2/
N3-CE#
WP1#
WP2#
D-A1
D-A3
D-DQ3 D-DQ4
F1/
N4-CE#
Reserved for
Future Use
D-DQ5 D-VCCQ
D-VSSQ D-DQ6
D-A0
D-A2
NAND Flash Only
G
NOR/NAND
Shared Only
D-DQ7 D-DQS0
D-BA0 D-BA1
D1-CE# D2-CE#
D-RAS# D-CAS#
D-WE# D1-CKE
D-VCC D2-CKE
D-A4 D-VSS
H
J
NOR or NAND,
Not Both
D-DM0 D-CLK
D-CLK# D-DQS1
D-DM1 D-DQ8
K
L
D-DQ9 D-VCCQ
D-VSSQ D-DQ10
D-DQ11 D-DQ12
D-DQ13 D-VCCQ
D-VSSQ D-DQ14
D-DQ15 D-VCC
M
N
D-A6
D-A8
D-A5
D-A7
D-A9
P
R
T
D-A10
D-A12 D-A11
U
NC
NC
D-VSS VCC
ADQ0 ADQ2 VCCQ ADQ4 ADQ6 F-CLK
VCC
ADQ8 ADQ10 VCCQ ADQ12 ADQ14 D-A14 D-A13
NC
NC
V
NC
VSS
ADQ1 ADQ3 VSSQ ADQ5 ADQ7 F-AVD# VSS
ADQ9 ADQ11 VSSQ ADQ13 ADQ15 F-RDY
NC
Note:
Additional NC locations are in reference to the superset connection diagram shown here
Device OPN
Flash Address Amax
DRAM Address Amax
Additional NC Locations
Ball A6, A11, A12, A14, A16,
B6, B12, B14, B16, B17, C17,
D18, H18, L18, U16, U17
S72NS512PE0
A24
A12
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
4. Input/Output Descriptions
Signal
Amax – A16
Description
Flash
DRAM
Flash Address inputs
ADQ15 – ADQ0
F-CE#
Flash multiplexed Address and Data
Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
Flash Write Enable input
X
X
X
X
X
X
F-OE#
F-WE#
F-VCC
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
F-VCCQ
F-VSS
Flash Ground
Flash ready output. Indicates the status of the Burst read. V = data invalid. V
OL
data valid.
=
OH
F-RDY
X
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the
address input and activates burst mode operation. After the initial word is output,
subsequent rising edges of CLK increment the internal address counter. CLK should
remain low during asynchronous access.
F-CLK
X
Flash Address Valid input. Indicates to device that the valid address is present on the
address inputs. V = for asynchronous mode, indicates valid address; for burst mode,
IL
F-AVD#
X
causes starting address to be latched on rising edge of CLK. V = device ignores
IH
address inputs
F-RST#
F-WP#
Flash hardware reset input. V = device resets and returns to reading array data
X
X
IL
Flash hardware write protect input. V = disables program and erase functions in the
IL
four outermost sectors
Flash accelerated input. At V , accelerates programming; automatically places
HH
F-ACC
device in unlock bypass mode. At V , disables all program and erase functions.
X
IL
Should be at V for all other conditions.
IH
D-A12 – D-A0
D-DQ15 – D-DQ0
D-CLK
DRAM Address inputs.
DRAM Data input/output
DRAM System Clock
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D-CE#
DRAM Chip Select
D-CKE
DRAM Clock Enable
D-BA1 – BA0
D-RAS#
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
D-CAS#
D-UDQM – D-LDQM DRAM Data Input Mask
D-WE#
D-VSS
D-VSSQ
D-VCCQ
D-VCC
D-UDQS
D-LDQS
D-CLK#
RFU
DRAM Write Enable input
DRAM Ground
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
DRAM Upper Data Strobe, output with read data and input with write data
DRAM Lower Data Strobe, output with read data and input with write data
DDR Clock for negative edge of CLK
Reserved for Future Use
NC
No Connect. Can be connected to ground or left floating.
Do Not Use. This signal must be left floating
DNU
Note
Signal descriptions apply only to valid products offered in the S72NS-P product family.
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5. Ordering Information
The order number (Valid Combination) is formed by the following:
S72NS
256
P
D0
AJ
B
L
G
3
PACKING TYPE
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
FLASH and DDR SPEED
4 = 66 MHz Flash, 166 MHz DRAM
G = 66 MHz Flash, 133 MHz DRAM
C = 83 MHz Flash, 133 MHz DRAM
0 = 83 MHz Flash, 166 MHz DRAM
DDR SUPPLIER
G = DRAM Type 1 x16 DDR DRAM
L = DRAM Type 5 x16 DDR DRAM
PACKAGE MODIFIER
G = 133-ball, 11x10 mm, FBGA MCP
B = 133-ball, 8x8 mm, FBGA MCP
F = 128-ball, 12x12 mm, 0.48 mm ball, FBGA PoP (ALF128)
PACKAGE AND MATERIAL TYPE
AJ = Thin profile Fine-pitch BGA Pb-free MCP (0.5 mm pitch)
KF = Thin profile Fine-pitch BGA Pb-free PoP
AH = Thin profile Fine-pitch BGA Pb-free Low-Halogen MCP (0.5 mm pitch)
KH = Thin profile Fine--pitch BGA Pb-Free Low-Halogen PoP
DDR DRAM AND DATA FLASH DENSITY
D0 = 128 Mb DRAM, No Data Flash
E0 = 256 Mb DRAM, No Data Flash
PROCESS TECHNOLOGY
P = 90 nm, MirrorBit® Technology
CODE FLASH DENSITY
512 = 512 Mb
256 = 256 Mb
128 = 128 Mb
PRODUCT FAMILY
S72NS Multi-Chip Memory Subsystem (MCP/PoP))
1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus
Valid Combinations
DRAM
Code Flash
Density
(Mb)
Product
Family
Process
Technology
Density
(Mb)
Package Type/
Material
Flash & DDR
Speed
Packing
Type
DDR Vendor
128
256
512
G, C
D0
AJB, AHB
0, 2, 3
(Note 1)
S72NS
P
G, L
G, C, 0
D0, E0
AHG, AJG, KFF
G, C, 0, 4
Notes:
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type designator from ordering part number.
3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
September 24, 2008 S72NS-P_00_07
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9
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6. Physical Dimensions
6.1
NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 mm
NOTES:
PACKAGE
JEDEC
NLC 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.0 mm x 10.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
1.00
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.90
0.20
0.70
10.9
9.9
1.10
0.30
0.82
11.1
10.1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
0.76
BODY THICKNESS
BODY SIZE
D
11.0
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
10.0
BODY SIZE
D1
E1
6.50 BSC.
6.50 BSC.
14
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
D5-D11, E4-E11, F4-F11
G4-G11, H4-H11, J4-J11
K4-K11, L4-L11
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3436 \ 16-039.22 \ 12.09.04
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6.2
NSC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm
NOTES:
PACKAGE
JEDEC
NSC 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
8.00 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1
SPP-010.
SYMBOL
MIN
NOM
1.00
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.90
0.20
0.70
1.10
0.30
0.82
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
A2
0.76
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
8.00 BSC
8.00 BSC
6.50 BSC.
6.50 BSC.
14
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
BALL PITCH
0.50 BSC.
0.50 BSC
0.25 BSC.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
SD / SE
BALL PITCH
SOLDER BALL PLACEMENT
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS
H4-H11,J4-J11,K4-K11,L4-L11
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3583 \ 16-039.22 \ 8.15.06
September 24, 2008 S72NS-P_00_07
S72NS-P MCP/PoP Memory System Solutions
11
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6.3
ALF128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm
PACKAGE
JEDEC
ALF 128
N/A
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER ASME
Y14.5M-1994.
NOTE
12.00 mm x 12.00 mm
PACKAGE
D X E
2. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL
MIN
0.85
0.38
0.49
NOM
0.95
MAX
1.05
0.48
0.59
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010.
A
A1
A2
D
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.43
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
0.54
BODY THICKNESS
12.00 BSC.
12.00 BSC.
11.05 BSC.
11.05 BSC
18
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
18
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND
B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN
THE OUTER ROW.
128
N
128
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PERIMETERS
BALL DIAMETER
R
2
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
eD
SE SD
0.43
0.48
0.53
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.65 BSC.
0.65 BSC.
0.325 BSC.
BALL PITCH
BALL PITCH
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C3-C16, D3-D16, E3-E16,
F3-F16, G3-G16, H3-H16,
J3-J16, K3-K16, L3-L16,
M3-M16, N3-N16, P3-P16,
R3-R16, T3-T16
ALF128-pod \F16.039.24 \ 10.12.7
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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
7. Revision History
Section
Description
Revision 01 (September 6, 2006)
Initial release
Revision 02 (March 15, 2007)
Removed PoP option, including OPNs, valid combinations, connection diagrams and package
drawings
Global
General Description
Added DRAM Type 5 option for 256Mb DDR DRAM
Added RLB133 Package drawing
Physical Dimensions
Revision 03 (August 31, 2007)
Global
Added S72NS512PE0 PoP product offering
General Description
Added DRAM Type 1 option for 256 Mb DDR DRAM
Product Selector Guide
Physical Dimensions
Revision 04 (October 15, 2007)
Added OPNs for S72NS512PE0 PoP including speed and package options
Removed RLB133 and added ALF128 and ALE128 packages
Added S72NS512PD0 Low-Halogen product offering
Global
Removed product offerings paired with DRAM Type 3 - modified Product Selector Guide and
Ordering Information sections
Ordering Information
Revision 05 (February 14, 2008)
Global
Added AH product descriptor for Pb-free Low-Halogen package
Added S72NS128PD0 Low-halogen product offering
Ordering Information
Physical Dimensions
Revision 06 (May 22, 2008)
Revised product nomenclature to reflect accurate speed, material and package options
Removed ALF128, ALE128 and added DLA128 packages
Changed 128 Mb DRAM1 data sheet Publication Number to DRAM_07
Added 128 Mb DRAM5 70 nm Version data sheet Publication Number
Changed 256 Mb DRAM1 data sheet Publication Number to DRAM_08
Added 256 Mb DRAM5 70 nm Version data sheet Publication Number
General Description
Product Selector Guide
Ordering Information
Added Notes 1 and 2
Added S72NS512PD0AHGL4
Updated Package Modifier D package name to DLA128
Removed Package Modifier F
Added 66 MHz Flash, 166 MHz DRAM speed option
Corrected 80 MHz Flash option to 83 MHz
Revision 07 (September 24, 2008)
Global
Removed OPNs S72NS512PE0KFDGG and S72NS512PE0KFDG0
Added OPNs S72NS512PE0KFFGG and S72NS512PE0KFFG0
Physical Dimensions
Removed DLA128; added ALF128
September 24, 2008 S72NS-P_00_07
S72NS-P MCP/PoP Memory System Solutions
13
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2006-2008 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
14
S72NS-P MCP/PoP Memory System Solutions
S72NS-P_00_07 September 24, 2008
相关型号：
S72NS512PD0KFFLG2
Memory Circuit, 32MX16, CMOS, PBGA128, 12 X 12 MM, 0.48 MM PITCH, LEAD FREE, FBGA-128
SPANSION
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