S72WS256NFFBAW4Y2 [SPANSION]
Based MCP/PoP Products; 基于MCP / POP产品型号: | S72WS256NFFBAW4Y2 |
厂家: | SPANSION |
描述: | Based MCP/PoP Products |
文件: | 总30页 (文件大小:980K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S72WS-N Based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus
256/512 Mb Simultaneous Read/Write, Burst Mode Flash Memory
512 Mb NAND Flash
1024 Mb NAND Interface ORNAND Flash Memory on Bus 1
512/256/128 Mb (8M/4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Bus 2
ADVANCE
INFORMATION
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Each product described
herein may be designated as Advance Information, Preliminary, or Full
Production. See “Notice On Data Sheet Designations” for definitions.
Publication Number S72WS-N_00 Revision A Amendment 8 Issue Date June 1, 2006
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with the DC Characteristics table and the AC Erase and Program table (in the
table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
S72WS-N based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus
256/512 Mb Simultaneous Read/Write, Burst Mode Flash Memory
512 Mb NAND Flash
1024 Mb NAND Interface ORNAND Flash Memory on Bus 1
512/256/128 Mb (8M/4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Bus 2
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
High Performance
Flash access time: 80 ns for NOR Flash, 25 ns for ORNAND Flash
Flash burst frequencies: 54 MHz, 66MHz, 80MHz
Mobile SDRAM burst frequency: 104 MHz, 133 MHz (DDR)
Package:
— 9.0 x 12.0 mm MCP BGA
— 11.0 x 13.0 mm MCP BGA
— 15.0 x 15.0 x 1.2 mm MCP Package-on-Package (PoP)
Operating Temperature
— –25°C to +85°C (wireless)
General Description
The S72WS series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
One or two NOR flash memory dies
One NAND Interface ORNAND die
Separate bus for one or more Mobile SDRAM die
The products covered by this document are listed in the table below.
NOR Flash Density
NAND Flash Density
SDRAM Density
Device
512Mb
256Mb
128Mb
1024Mb
512Mb
512Mb
256Mb
128Mb
S72WS256ND0
S72WS256NDE
S72WS256NEE
S72WS512NFG
S72WS512NEG
S72WS512NEF
S72WS512NFF
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Note: For a list of PoP OPNs, please contact the local sales representative or refer to the Ordering In-
formation valid combinations tables.
For detailed specifications, please refer to the individual data sheets.
Document
Publication Identification Number (PID)
S29WS-N_00
S30MS-P_00
SDRAM_01
S29WS256N
S30MS01GP/512P
128 Mb Mobile SDRAM Type 1
128 Mb Mobile SDRAM Type 2
128 Mb Mobile DDR-DRAM Type 5
256 Mb Mobile SDRAM Type 2
512 Mb Mobile DDR-DRAM Type 1
512 Mb Mobile SDRAM Type 4
512 Mb NAND Type 1
SDRAM_05
SDRAM_07
SDRAM_05
SDRAM_09
SDRAM_06
NAND_01
512 Mb Mobile DDR-DRAM Type 5
512 Mb Mobile DDR-DRAM Type 2
DRAM_04
DRAM_05
Publication Number S72WS-N_00 Revision A Amendment 8 Issue Date June 1, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice
A d v a n c e I n f o r m a t i o n
Table of Contents
S72WS-N Based MCP/PoP Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 NOR Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 NOR Flash + ORNAND Flash + DRAM Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 NOR Flash + ORNAND Flash + DRAM Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 2 x 256Mb NOR Flash with 256Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 2 x 256Mb NOR Flash with 128Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 256Mb NOR Flash with 128Mb SDR/DDR-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 512 Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256-Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . 9
2
3
3.4.1
3.5 512Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256 Mb SDRAM on Bus 2. . . . . . . . . . . . . . . .10
3.5.1 x8 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 512Mb NOR Flash with 512-Mb NAND on Bus 1 and 512-Mb SDRAM on Bus 2. . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.1 x16 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
x16 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6.2 Connection Diagram for 15 x 15 Package-on-Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.7 Lookahead Diagram on Split Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 NOR Flash and DRAM Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.8.1
ORNAND Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4
5
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.1 TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 FEA137—137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.3 FVD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 11 x 13 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4 BWA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 BWB160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 BTA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.7 ALH160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6
2
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
1 Product Selector Guide
1.1
NOR Flash + DRAM Products
Flash
Density Density
(Code)
Flash
Burst
Speed
(MHz)
SDRAM SDRAM burst
Density Speed (MHz)
DRAM
Supplier
Device-Model#
DYB
Package
(Data)
S72WS256ND0BAWB7
S72WS256ND0BAWBB
S72WS256NDEBAWU7
S72WS256NDEBAWUB
S72WS256NEEBAWU7
S72WS256NEEBAWUB
S72WS256ND0BFWB7
S72WS256ND0BFWBB
S72WS256NDEBFWU7
S72WS256NDEBFWUB
S72WS256NEEBFWU7
S72WS256NEEBFWUB
1
2
1
2
1
2
1
2
1
2
1
2
sector
256 Mb
—
54 MHz
54 MHz
54 MHz
54 MHz
128
128
256
128
128
256
104 MHz
104 MHz
104 MHz
104 MHz
9x12x1.2
unprotected
sector
unprotected
256 Mb 256 Mb
9x12x1.4
9x12x1.2
9x12x1.4
sector
unprotected
256 Mb
—
sector
unprotected
256 Mb 256 Mb
133 MHz
(DDR)
sector
S72WS256ND0KFWD3
S72WS256ND0BFW93
15x15x1.25
9x12x1.2
unprotected
256 Mb
66 MHz
128
5
133 MHz
(DDR)
sector
unprotected
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
3
A d v a n c e I n f o r m a t i o n
1.2
NOR Flash + ORNAND Flash + DRAM Products
NOR ORNAND
ORNAND
Bus
Width
SDRAM
Density
Flash
Speed
DRAM
Speed
ECC
required?
Device-Model#
Flash
Flash
Density
Supplier
Package
Density
DRAM
S72WS512NFFBFWZ2
S72WS512NFFBFWZJ
Type 1
133MHz
(DDR)
512Mb
(NAND)
66MHz
Yes
11x13x1.4mm
DRAM
Type 5
X16
S72WS512NFG-L7
S72WS512NFG-L6
S72WS512NFG-L5
S72WS512NFG-47
S72WS512NFG-46
S72WS512NFG-45
S72WS512NFG-LZ
S72WS512NFG-LY
S72WS512NFG-LW
S72WS512NFG-4Z
S72WS512NFG-4Y
S72WS512NFG-4W
S72WS512NFG-N7
S72WS512NFG-N6
S72WS512NFG-N5
S72WS512NFG-67
S72WS512NFG-66
S72WS512NFG-65
S72WS512NFG-NZ
S72WS512NFG-NY
S72WS512NFG-NW
S72WS512NFG-6Z
S72WS512NFG-6Y
S72WS512NFG-6W
S72WS512NEG-LZ
S72WS512NEG-LY
S72WS512NEG-LW
S72WS512NEG-4Z
S72WS512NEG-4Y
S72WS512NEG-4W
S72WS512NEG-NZ
S72WS512NEG-NY
S72WS512NEG-NW
S72WS512NEG-6Z
S72WS512NEG-6Y
S72WS512NEG-6W
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
54MHz
66MHz
80MHz
DRAM
Type 4
X8
X16
X8
No
DRAM
Type 2
512Mb
X16
X8
DRAM
Type 4
512Mb
1024Mb
104MHz
Yes
11x13x1.4mm
X16
X8
X16
X8
DRAM
Type 2
No
256 Mb
X16
X8
Yes
Yes
DRAM
Type2
S72WS512NEFKFWHJ
256Mb
512Mb
15x15x1.25mm
15x15x1.25mm
15x15x1.25mm
512Mb
(NAND)
133MHz DRAM
S72WS512NFFKFWZ2 512Mb
S72WS512NFFKFWZJ
66MHz
x16
(DDR)
Type 1
DRAM
Type 5
4
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
2 MCP Block Diagram
2.1
NOR Flash + ORNAND Flash + DRAM Products
F-Vcc
F-AVD#
F-CLK
AVD#
CLK
F-ACC
ACC
F-WP#
F-RESET#
F1-CE#
F-WE#
WP#
RESET#
CE#
RDY
DQ8:15
DQ0:7
RDY
DQ8:15
WE#
OE#
DQ0:7
WS256N
Vss
F-OE#
F-A23:A0
F-VCCQ
A23-A0
F2-CE#
CE#
N-Vcc
N-WP#
N-CE#
N-WE#
N-RE#
N-ALE
N-CLE
N-PRE
WP#
CE#
WE#
RE#
ALE
CLE
PRE
IO0:7
MS01GP
RY/BY#
RY/BY#
Vss
D-Vcc
V-Vccq
A12-A0
CE#
D-A12-A0
D-CE#
DQ0:15
D-DQ15-DQ0
WE#
BA0
D-WE#
D-BA0
BA1
D-BA1
CKE
D-CKE
D-RAS#
D-CAS#
D-DM0
D-DM1
RAS#
CAS#
DM0
DM1
SDRAM
D-Vss
D-Vssq
Notes:
1. For a one-Flash configuration, F1-CE# = CE#.
For a two-Flash configuration, F1-CE# = CE for Flash 1 and F2-CE# = CE for Flash 2; F2-CE# is the
chip-enable pin for the second Flash.
2. If ORNAND is not present in the MCP, then the MS01GP block will not be present in the figure above. In
that case, the common signals go only to the WS256N flash, while the SDRAM signals remain unchanged.
3. If ORNAND supports a x16 bus, then NOR DQ0-DQ15 is shared with ORNAND I/O0-I/O15.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
5
A d v a n c e I n f o r m a t i o n
3 Connection Diagram
3.1
2 x 256Mb NOR Flash with 256Mb SDRAM
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE D-CLK
RFU
RFU
D-VSS
D-VCC
D-A12
D-A11
D-VSS D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS# D-WE#
D-A9
D-A8
D-VSSQ D-VCCQ
D-A7
D-A6
RFU D-CAS#
C1
D-A10 AVD#
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
VSS
CLK
RFU
RFU
RFU
RFU
RFU
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0 F-WP#
D-DM0
F-ACC
WE#
A11
F2-CE# D-A5
E9 E10
A15 D-VCCQ
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
Flash 1 only
SDRAM only
D-VCCQ
D-DM1 F-RST#
RFU
A19
A12
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
D-VSSQ
A18
F-RDY
A20
A13
A21 D-VSSQ
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
A22 D-DQ15
H9 H10
A16 D-DQ14
J9 J10
RFU D-DQ13
G10
D-DQ0
A17
A23
A10
A14
Reserved for
Future Use
H1
H2
A0
H3
H4
H7
H8
D-DQ1
VSS
DQ1
DQ6
RFU
Flash 2 only
Flash Shared
J1
J2
J3
J4
J5
J6
J7
J8
D-DQ2 F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
RFU
DQ0
DQ10
F-VCC
RFU
DQ12
DQ7
VSS D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
RFU
D-BA0
D-DQ6
D-DQ7 D-VSSQ D-VCCQ D-DQ8
D-DQ9
D-BA1
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
RFU
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
RFU
Note: M8 is RFU for SDR-DRAM and F-V
for DDR-DRAM, as indicated in subsequent connection
CCQ
diagrams.
6
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
3.2
2 x 256Mb NOR Flash with 128Mb SDRAM
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE D-CLK
RFU
RFU
D-VSS
D-VCC
RFU
D-A11
D-VSS D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS# D-WE#
D-A9
D-A8
D-VSSQ D-VCCQ
D-A7
D-A6
RFU D-CAS#
C1
D-A10 AVD#
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
VSS
CLK
RFU
RFU
RFU
RFU
RFU
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0 F-WP#
D-DM0
F-ACC
WE#
A11
F2-CE# D-A5
E9 E10
A15 D-VCCQ
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
Flash 1 only
SDRAM only
D-VCCQ
D-DM1 F-RST#
RFU
A19
A12
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
D-VSSQ
A18
F-RDY
A20
A13
A21 D-VSSQ
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
Reserved for
Future Use
D-DQ0
A17
A23
A10
A14
A22 D-DQ15
H1
H2
A0
H3
H4
H7
H8
H9
H10
D-DQ1
VSS
DQ1
DQ6
RFU
A16 D-DQ14
Flash 2 only
Flash Shared
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2 F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
RFU
DQ0
DQ10
F-VCC
RFU
DQ12
DQ7
VSS D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
RFU
D-BA0
D-DQ6
D-DQ7 D-VSSQ D-VCCQ D-DQ8
D-DQ9
D-BA1
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
RFU
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
RFU
Note: M8 is RFU for SDR-DRAM and F-VCCQ for DDR-DRAM, as indicated in subsequent connection
diagrams.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
7
A d v a n c e I n f o r m a t i o n
3.3
256Mb NOR Flash with 128Mb SDR/DDR-DRAM
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE D-CLK
D-CLK#
RFU
D-VSS
D-VCC
RFU
D-A11
D-VSS D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS# D-WE#
D-A9
D-A8
D-VSSQ D-VCCQ
D-A7
D-A6
RFU D-CAS#
C1
D-A10 AVD#
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
VSS
CLK
RFU
RFU
RFU
RFU
RFU
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0 F-WP#
D-DM0
F-ACC
WE#
A11
RFU
D-A5
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
Flash 1 only
SDRAM only
D-VCCQ
D-DM1 F-RST#
RFU
A19
A12
A15 D-VCCQ
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
D-VSSQ
A18
F-RDY
A20
A13
A21 D-VSSQ
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
D-DQ0
A17
A23
A10
A14
A22 D-DQ15
Reserved for
Future Use
H1
H2
A0
H3
H4
H7
H8
H9
H10
D-DQ1
VSS
DQ1
DQ6
RFU
A16 D-DQ14
Flash 2 only
Flash Shared
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2 F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
RFU
DQ0
DQ10
F-VCC
RFU
DQ12
DQ7
VSS D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
DDR only
D-DQ4
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
RFU
F-VCCQ
RFU D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
RFU
D-BA0
D-DQ6
D-DQ7 D-VSSQ D-VCCQ D-DQ8
D-DQ9
D-BA1
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
D-DQS0 D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
RFU D-DQS1
Note: DDR-only signals are RFUs in the case of the SDR-DRAM based MCPs.
8
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
3.4 512 Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256-Mb SDRAM
on Bus 2
3.4.1
x16 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-V
SS
D-V
CC
D-V
SS
D-CKE
D-CLK
RFU
D-A12
D-A11
D-CE#
RFU
B9
B1
B2
B3
B4
B5
B6
B7
B8
B10
Legend
D-RAS# D-WE#
D-A9
D-A8
D-V
SSQ
D-V
CCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
Reserved for
Future Use
D-A10
AVD#
V
CLK
F2-CE# F-V
N-PRE
N-ALE
N-CLE
SS
CC
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0
F-WP#
D-DM0
F-ACC
WE#
A11
N-CE#
D-A5
Do Not Use
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
D-V
D-DM1 F-RST#
DNU
A19
A12
A15
D-V
CCQ
CCQ
NOR Flash 1
Only
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
D-V
SSQ
A18
RDY
A20
A13
A21
D-V
SSQ
NOR Flash 2
Only
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
D-DQ0
A17
A23
A10
A14
A22
D-DQ15
NAND Flash 1
Only
H1
H2
A0
H3
H4
H7
H8
H9
H10
D-DQ1
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DRAM Only
D-DQ2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
NOR Flash
Shared
D-DQ3
DNU
DQ0
DQ10
F-V
CC
N-V
CC
DQ12
DQ7
V
D-DQ12
SS
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP# D-DQ11
All Flash
Shared
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
V
F-V
RFU
DNU
F-V
CCQ
RFU
D-DQ10
SS
CC
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
D-BA0
D-DQ6
D-DQ7
D-V
D-V
CCQ
D-DQ8
D-DQ9
P8
D-BA1
N-RE#
SSQ
P1
P2
P3
P4
P5
P6
P7
P9
P10
RFU
D-V
SS
D-A1
D-A2
D-V
SS
D-V
CC
D-A3
D-A4 N-RY/BY#
RFU
Note: 1.DDR-only signals are RFU in the case of SDR-DRAM based MCPs.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
9
A d v a n c e I n f o r m a t i o n
3.5
512Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256 Mb SDRAM
on Bus 2
3.5.1
x8 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-V
SS
D-V
CC
D-V
SS
D-CKE
D-CLK
RFU
RFU
D-A12
D-A11
D-CE#
B9
B1
B2
B3
B4
B5
B6
B7
B8
B10
D-RAS# D-WE#
D-A9
D-A8
D-V
SSQ
D-V
CCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
D-A10
AVD#
V
CLK
F2-CE# F-V
N-PRE
N-ALE
N-CLE
SS
CC
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0
F-WP#
D-DM0
F-ACC
WE#
A11
N-CE#
D-A5
Reserved for
Future Use
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
D-V
D-DM1 F-RST#
DNU
A19
A12
A15
D-V
CCQ
CCQ
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
Do Not Use
D-V
SSQ
A18
RDY
A20
A13
A21
D-V
SSQ
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
NOR Flash 1
Only
D-DQ0
A17
A23
A10
A14
A22
D-DQ15
H1
H2
A0
H3
H4
H7
H8
H9
H10
D-DQ1
V
DQ1
DQ6
RFU
A16
D-DQ14
SS
NOR Flash 2
Only
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
NAND Flash 1
Only
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
DNU
DQ0
DQ10
F-V
CC
N-V
CC
DQ12
DQ7
V
D-DQ12
SS
DRAM Only
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP# D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
NOR Flash
Shared
D-DQ5
RFU
RFU
V
F-V
RFU
DNU
F-V
CCQ
RFU
D-DQ10
SS
CC
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
All Flash
Shared
N-WE#
D-BA0
D-DQ6
D-DQ7
D-V
D-V
CCQ
D-DQ8
D-DQ9
D-BA1
N-RE#
SSQ
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
RFU
D-V
SS
D-A1
D-A2
D-V
SS
D-V
CC
D-A3
D-A4
DNU
10
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
3.6 512Mb NOR Flash with 512-Mb NAND on Bus 1 and 512-Mb SDRAM on Bus 2
3.6.1
x16 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-V
SS
D-V
CC
D-V
SS
D-CKE
D-CLK
RFU
D-A12
D-A11
D-CE#
D-CLK#
B9
B1
B2
B3
B4
B5
B6
B7
B8
B10
Legend
D-RAS# D-WE#
D-A9
D-A8
D-V
SSQ
D-V
CCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
Reserved for
Future Use
D-A10
AVD#
V
CLK
F2-CE# F-V
N-PRE
N-ALE
N-CLE
SS
CC
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0
F-WP#
D-DM0
F-ACC
WE#
A11
N-CE#
D-A5
Do Not Use
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
D-V
D-DM1 F-RST#
DNU
A19
A12
A15
D-V
CCQ
CCQ
NOR Flash 1
Only
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
D-V
SSQ
A18
RDY
A20
A13
A21
D-V
SSQ
NOR Flash 2
Only
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
D-DQ0
A17
A23
A10
A14
A22
D-DQ15
NAND Flash 1
Only
H1
H2
A0
H3
H4
H7
H8
H9
H10
D-DQ1
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DRAM Only
D-DQ2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
NOR Flash
Shared
D-DQ3
DNU
DQ0
DQ10
F-V
CC
N-V
CC
DQ12
DQ7
V
D-DQ12
SS
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP# D-DQ11
All Flash
Shared
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
V
F-V
RFU
DNU
F-V
CCQ
RFU
D-DQ10
SS
CC
DDR only
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
D-BA0
D-DQ6
D-DQ7
D-V
D-V
CCQ
D-DQ8
D-DQ9
P8
D-BA1
N-RE#
SSQ
P1
P2
P3
P4
P5
P6
P7
P9
P10
D-V
SS
D-A1
D-A2
D-V
SS
D-V
CC
D-A3
D-A4 N-RY/BY#
D-DQS1
D-DQS0
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
11
A d v a n c e I n f o r m a t i o n
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-
ods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of time.
3.6.2
Connection Diagram for 15 x 15 Package-on-Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
Legend
A
B
C
D
E
F
F-V
N-V
F-V
F-V
D-V
F-A19
F-A21 F-A23
F-A22
F-A18 F-A20
RFU
RFU
F-A3
F-A2
F-A5
F-A4
F-A7
F-A6
F-A9
F-A8
F-A13
RFU
NC
F-A1
F-A0
N-CLE F-A11
F-A15 F-A17
F-A14 F-A16
SSQ
CCQ
SS
SS
SSQ
CCQ
SS
F-V
F-V
CCQ
N-V
CC
F-V
F-V
F-V
D-V
DD
D-V
SS
N-ALE F-A10 F-A12
SSQ
CC
No Connect
N-RY/BY#
D-DQ0
RFU
N-WE#
D-DQ1
F-RST#
F1-CE# F2-CE#
Reserved for
Future Use
D-V
D-V
SSQ
N1-CE#
N-RE#
RFU
DDQ
N-WP#
D-DQ3
D-DQ2
Control for
NOR/PS/NAND
F-WE# F-WP#
D-DQ5 D-DQ4
G
D-V
SSQ
D-V
DDQ
F-OE#
H
J
D-WE#
B: Data
A: Addr
D-V
DD
D-V
SS
D-DQ7
D-DQ6
K
D-DM0 D-DQS0
D-A0
D-A2
D-A4
D-A6
D-A1
D-A3
D-A5
D-A7
L
D-DQS1
D-DM1
D-V
SSQ
D-V
M
N
P
DDQ
A: A/D.
B: Data
D-DQ8
D-DQ9
D-V
SS
D-V
DD
D-BA0 D-BA1
B: Addr
Ground
Power
D-DQ11
D-DQ13
D-DQ10
D-DQ12
D1-CS# RFU
R
D-CAS#
D-A9
T
D-RAS#
D-V
SSQ
D-V
D-A8
U
DDQ
D-A11
RFU
D-DQ14
D-CLK
D-A10
D-A12
V
D-DQ15
W
Y
D-CKE
Control for
DDR, PS
F-V
/
D-V
SS
PP
D-CLK#
RFU
RFU
NC
N-ACC
F-DQ12/
N-ADQ12
F-DQ14/
N-ADQ14
F-DQ10/
CCQ N-ADQ10
F-DQ0/
N-ADQ0
F-DQ6/
CCQ N-ADQ6
F-DQ2/
N-ADQ2
F-DQ4/
N-ADQ4
F-DQ8/
N-ADQ8
F-V
F-V
D-V
DD
F-V
SS
F-V
F-V
F-V
CC
F-V
F-V
F-V
N-V
F-ADV#
F-WAIT
RFU
NC
AA
AB
RFU
RFU
F-CLK
RFU
RFU
CCQ
CCQ
CC
F-DQ13/
N-ADQ13
F-DQ15/
SSQ N-ADQ15
F-DQ11/
N-ADQ11
F-DQ1/
N-ADQ1
F-DQ7/
N-ADQ7
F-DQ3/
N-ADQ3
F-DQ5/
N-ADQ5
F-DQ9/
RFU
F-V
F-V
D-V
DD
F-V
N-V
CCQ
SSQ
SSQ
SSQ
SSQ
SS
N-ADQ9
12
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
3.7
Lookahead Diagram on Split Bus
A1
D-CKE
A2
A3
A4
D-A14
A5
A6
A7
A8
A9
A10
D-V
SS
D-V
CC
D-V
SS
D-CLK D-CLK#
D-A12
D-A11
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS# D-WE#
D-A9
D-A8
D-V
SSQ
D-V
CCQ
D-A7
D-A6
D-A13
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
F-AVD#
V
F-CLK
F2-CE# F-V
N-PRE
N-ALE
N-CLE
D-A15
SS
CC
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D-A0
F-WP#
D-DM0
F-ACC
F-WE#
A11
N1-CE#
D-A5
x16 DRAM
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
D-V
D-DM1 F-RST#
DNU
A19
A12
A15
D-V
CCQ
CCQ
NOR Flash
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
D-V
SSQ
A18
F-RDY
A20
A13
A21
D-V
SSQ
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
NAND Flash
D-DQ0
A17
A23
A10
A14
A22
D-DQ15
H1
H2
A0
H3
H4
H7
H8
H9
H10
Flash
Shared
D-DQ1
V
DQ1
DQ6
A24
A16
D-DQ14
SS
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
Do Not Use
DDR Only
D-DQ2
F1-CE#
F-OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
DNU
DQ0
DQ10
F-V
CC
N-V
CC
DQ12
DQ7
V
D-DQ12
SS
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-V
CC
DQ8
DQ2
DQ11
A25
DQ5
DQ14
N-WP# D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
A27
A26
V
F-V
N2-CE#
DNU
F-V
CCQ
D-CLK# D-DQ10
SS
CC
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
D-BA0
D-DQ6
D-DQ7
D-V
D-V
CCQ
D-DQ8
D-DQ9
P8
D-BA1
N-RE#
SSQ
P1
P2
P3
P4
P5
P6
P7
P9
P10
D-DQS0
D-V
SS
D-A1
D-A2
D-V
SS
D-V
CC
D-A3
D-A4 N-RY/BY# D-DQS1
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
13
A d v a n c e I n f o r m a t i o n
3.8 NOR Flash and DRAM Input/Output Descriptions
A23-A0
=
NOR Flash Address inputs
DQ15-DQ0
=
Flash Data input/output, shared between NOR and ORNAND
Flash. DQ0-DQ7 shared for x8 ORNAND
F2-CE#
F1-CE#
OE#
=
=
=
NOR Flash Chip-enable input # 2. Asynchronous relative to CLK
for burst mode.
NOR Flash Chip-enable input #1. Asynchronous relative to CLK
for Burst Mode.
NOR Flash Output Enable input. Asynchronous relative to CLK
for Burst mode.
F-WE#
F-VCC
=
=
=
=
=
=
NOR Flash Write Enable input.
NOR Flash device power supply (1.7 V - 1.95V).
Input/Output Buffer power supply.
Ground
Reserved for Future Use
Flash ready output. Indicates the status of the Burst read. VOL
= data valid. Shared between NOR and ORNAND Flash.
F-VCC
q
VSS
RFU
RDY
CLK
=
NOR Flash Clock. The first rising edge of CLK in conjunction with
AVD# low latches the address input and activates burst mode
operation. After the initial word is output, subsequent rising
edges of CLK increment the internal address counter. CLK
should remain low during asynchronous access.
AVD#
=
NOR Flash Address Valid input. Indicates to device that the valid
address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst
mode, causes starting address to be latched on rising edge of
CLK.
VIH= device ignores address inputs
F-RST#
F-WP#
F-ACC
=
=
=
NOR Flash hardware reset input. VIL= device resets and returns
to reading array data
NOR Flash hardware write protect input. VIL = disables program
and erase functions in the four outermost sectors.
NOR Flash accelerated input. At VHH, accelerates
programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should
be at VIH for all other conditions.
D-A12-D-A0
D-DQ15-D-DQ0
D-CLK
D-CE#
D-CKE
D-BA1-BA0
D-RAS#
D-CAS#
D-DM1-D-DM0
D-WE#
D-VSS
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SDRAM Address inputs
SDRAM Data input/output
SDRAM System Clock
SDRAM Chip Select
SDRAM Clock Enable
SDRAM Bank Select
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Data Input/Output Mask
SDRAM Write Enable input
SDRAM Ground
SDRAM Input/Output Buffer ground
SDRAM Input/Output Buffer power supply
SDRAM device power supply
D-VSSQ
D-VCCQ
D-VCC
14
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
3.8.1
ORNAND Signal Descriptions
N-PRE
=
ORNAND Power-On Read Enable. Tie to VSS on
customer board if not used
N-ALE
N-CLE
N-CE#
N-WP#
N-WE#
N-RE#
N-RY/BY#
N-I/O0-N-I/O15
N-VCC
=
=
=
=
=
=
=
=
=
ORNAND Address Latch Enable
ORNAND Command Latch Enable
ORNAND Chip-enablE
ORNAND Write-protect
ORNAND Write-enable
ORNAND Read-enable
ORNAND Ready-Busy—this is shared with NOR RDY
ORNAND I/O Signals (I/O0-I/O7 for x8 bus width)
ORNAND Power Supply
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
15
A d v a n c e I n f o r m a t i o n
4 Ordering Information
The order number is formed by a valid combinations of the following:
S72WS 512
N
EG BA
W
4
Y
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
Refer to the Valid Combinations Tables
PACKAGE MODIFIER
Refer to the Valid Combinations Tables
TEMPERATURE RANGE
W
=
Wireless (-25°C to +85°C)
PACKAGE TYPE
BA
BF
KF
=
=
=
Very-thin Fine-pitch BGA Lead (Pb)-free compliant package
Very-thin Fine-pitch BGA Lead (Pb)-free package
Fine-pitch Package-on-Package (PoP) Lead (Pb)-free
SDRAM & DATA FLASH DENSITY
EE
DE
D0
FG
EG
EF
FF
=
=
=
=
=
=
=
256 Mb SDRAM, 256 Mb Data Flash
128 Mb SDRAM, 256 Mb Data Flash
128 Mb SDRAM, No Data Flash
512 Mb SDRAM, 1024 Mb ORNAND Flash
256 Mb SDRAM, 1024 Mb ORNAND Flash
256Mb SDRAM, 512Mb NAND Flash
512Mb SDRAM, 512Mb NAND Flash
PROCESS TECHNOLOGY
110 nm, MirrorBitTM Technology
N
=
CODE FLASH DENSITY
256
512
=
=
256Mb
512Mb
PRODUCT FAMILY
S72WS Multi-chip Product (MCP)
1.8-volt Simultaneous Read/Write, Burst Mode Flash Memory and Mobile
SDRAM on Split Bus
16
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
S72WS256ND0 Valid Combinations
SDRAM
Burst
Speed
NOR Flash
Burst Speed
Package
Marking
SDRAM Supplier
Package Type
Base Ordering
Part Number
Package &
Temperature
Model
Number
Packing
Type
BFW
93
B7
BB
66 MHz
54 MHz
Supplier 5
Supplier 1
Supplier 2
133 MHz
104 MHz
9x12x1.2mm
137-ball
BAW, BFW
0, 2, 3
(Note 1)
S72WS256ND0
(Note 2)l
15x15x1.25mm
160-ball
KFW
D3
66 MHz
Supplier 5
133 MHz
S72WS256NDE Valid Combinations
SDRAM
Burst
Speed
NOR Flash
Burst Speed
Package
Marking
SDRAM Supplier
Package Type
Base Ordering
Part Number
Package &
Te mp e ratu re
Model
Number
Packing
Type
U7
UB
Supplier 1
Supplier 2
0, 2, 3
(Note 1)
9x12x1.4mm
137-ball
S72WS256NDE
BAW, BFW
54 MHz
104 MHz
(Note 2)
S72WS256NEE Valid Combinations
SDRAM
Burst
Speed
Flash
Burst Speed
Package
Marking
SDRAM Supplier
Package Type
Base Ordering
Part Number
Package &
Te mp e ratu re
Model
Number
Packing
Type
U7
UB
Supplier 1
Supplier 2
0, 2, 3
(Note 1)
9x12x1.4mm
137-ball
S72WS256NEE
BAW, BFW
54 MHz
104 MHz
(Note 2)
S72WS512NFF Valid Combinations
Flash
Speed
DRAM
Speed
Package
Marking
DRAM Supplier
Package
Base Ordering
Part Number
Package &
Te mp e ratu re
Model
Number
Packing
Type
11 x 13 mm
137-ball
BAW, BFW
KFW
ZJ
Z2
ZT
DRAM Type 1
15 x 15 5mm
160-ball
11 x 13 mm
137-ball
BAW, BFW
KFW
0, 2, 3
(Note 1)
S72WS512NFF
66 MHz
DRAM Type 5
DRAM Type 2
133 MHz
(Note 2)
15 x 15 5mm
160-ball
11 x 13 mm
137-ball
BAW, BFW
KFW
15 x 15 5mm
160-ball
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
17
A d v a n c e I n f o r m a t i o n
S72WS512NFG Valid Combinations
SDRAM
Flash
Package
Marking
SDRAM Supplier
Burst
Package Type
Base Ordering
Part Number
Package &
Te mp e ratu re
Model
Number
Packing
Type
Burst Speed
Speed
L7
L6
L5
DRAM Type 4
47
46
45
LZ
LY
LW
4Z
4Y
4W
N7
N6
N5
67
66
65
NZ
NY
NW
6Z
6Y
6W
DRAM Type 2
0, 2, 3
(Note 1)
11x13x1.4mm
137-ball
S72WS512NFG
BAW, BFW
54 MHz
104 MHz
(Note 2)
DRAM Type 4
DRAM Type 2
S72WS512NEG Valid Combinations
SDRAM
Burst
Speed
Flash
Burst Speed
Package
Marking
SDRAM Supplier
Package Type
Base Ordering
Part Number
Package &
Te mp e ratu re
Model
Number
Packing
Type
LZ
LY
LW
4Z
4Y
4W
NZ
NY
NW
6Z
6Y
0, 2, 3
(Note 1)
11x13.1x1.4mm
137-ball
S72WS512NEG
BAW, BFW
54 MHz
DRAM Type 2
104 MHz
(Note 2)
6W
18
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
S72WS512NEF Valid Combinations
SDRAM
Burst
Speed
Flash
Burst Speed
Package
Marking
SDRAM Supplier
Package Type
Base Ordering
Part Number
Package &
Te mp e ratu re
Model
Number
Packing
Type
0, 2, 3
(Note 1)
15x15x1.2 mm
160-ball
S72WS512NEF
KFW
HJ
66 MHz
DRAM Type 2
133 MHz
(Note 2)
Notes:
Valid Combinations
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
19
A d v a n c e I n f o r m a t i o n
5 Physical Dimensions
5.1
TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
P
N M L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
B
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
137X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLD 137
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
D
12.00 BSC.
9.00 BSC.
10.40 BSC.
7.20 BSC.
14
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
137
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
G5,H5,H6
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3393\ 16-038.22a
20
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
5.2 FEA137—137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
P
N M L K
INDEX MARK
9
PIN A1
CORNER
Pin A1
Corner
7
SD
TOP VIEW
0.15
(2X)
C
BOTTOM VIEW
0.20
0.08
C
C
A2
A
A1
C
SIDE VIEW
6
137X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
D X E
SYMBOL
A
FEA 137
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
NOTE
12.00mm X 9.00mm PACKAGE
MIN.
-
NOM.
MAX.
1.40
-
-
-
PROFILE
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.10
1.11
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
-
1.26
BODY THICKNESS
BODY SIZE
A2
12.00 BSC
9.00 BSC
10.40 BSC
7.20 BSC
14
D
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
E
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
D1
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
10
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
1.37
BALL DIAMETER
0.35
0.40
0.45
b
eE
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
0.80 BSC
0.80 BSC
0.40 BSC
BALL PITCH
eD
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
SD/SE
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
G5, H5, H8
DEPOPULATED SOLDER BALLS
9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
21
A d v a n c e I n f o r m a t i o n
5.3
FVD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 11 x 13 mm Package
D1
A
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
E1
5
4
3
2
eE
1
N
L
J
H
G
F
E
D
C
B
A
P
M
K
PIN A1
9
PIN A1
CORNER
B
CORNER
7
INDEX MARK
0.15
(2X)
C
SD
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
C
C
A2
A
A1
0.08
C
6
137X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
FVD 137
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
13.00 mm x 11.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
1.40
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.10
1.09
---
---
BALL HEIGHT
A2
---
1.24
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
13.00 BSC.
11.00 BSC.
10.40 BSC.
7.20 BSC.
14
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
10
137
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.35
0.40
0.45
BALL DIAMETER
0.80 BSC.
0.80 BSC
0.40 BSC.
G5,H5,H6
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
SD SE
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3522 \ 16-038.21 \ 09.29.05
22
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
5.4 BWA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
9
PIN A1
CORNER
eD
INDEX MARK
A
B
C
D
E
F
G
H
J
K
L
SE
7
E
B
E1
M
N
P
R
T
U
eE
V
W
Y
AA
AB
0.10
(2X)
C
22 21 20 19 18 17 16 15 14 13 12 11 10
9
7
6
5
8
4
3
2
1
SD
7
0.10
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
C
C
A2
A
A1
0.10
C
6
160X
b
0.15
0.08
M
C
C
A B
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
BWA 160
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
15.00 mm x 15.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
1.25
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.35
0.74
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
---
0.84
BODY THICKNESS
BODY SIZE
15.00 BSC.
15.00 BSC.
13.65 BSC.
13.65 BSC.
22
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
22
160
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
N
160
MAXIMUM NUMBER OF BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
R
2
NUMBER OF LAND PARAMETERS
BALL DIAMETER
Øb
eE
eD
SD SE
0.40
0.45
0.50
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
0.65 BSC.
0.65 BSC.
0.325 BSC.
BALL PITCH
BALL PITCH
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SOLDER BALL PLACEMENT
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
C3~C20,D3~D20,E3~E20,F3~F20 DEPOPULATED SOLDER BALLS
G3~G20,H3~H20,J3~J20,K3~K20
L3~L20,M3~M20,N3~N20,P3~P20
R3~R20,T3~T20,U3~U20,V3~V20
W3~W20,Y3~Y20
3518 \ 16-038.46 \ 02.23.06
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
23
A d v a n c e I n f o r m a t i o n
5.5 BWB160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
9
PIN A1
CORNER
eD
INDEX MARK
A
B
C
D
E
F
G
H
J
K
L
SE
7
E
B
E1
M
N
P
R
T
U
eE
V
W
Y
AA
AB
0.10
(2X)
C
22 21 20 19 18 17 16 15 14 13 12 11 10
9
7
6
5
4
8
3
2
1
SD
7
0.10
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.10
C
A2
A
A1
C
C
SIDE VIEW
6
160X
b
0.15
0.08
M
M
C
C
A B
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
BWB 160
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
15.00 mm x 15.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
1.30
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.40
0.74
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
---
0.84
BODY THICKNESS
BODY SIZE
15.00 BSC.
15.00 BSC.
13.65 BSC.
13.65 BSC.
22
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
22
160
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
N
160
MAXIMUM NUMBER OF BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
R
2
NUMBER OF LAND PARAMETERS
BALL DIAMETER
Øb
eE
eD
SD / SE
0.45
0.50
0.55
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
0.65 BSC.
0.65 BSC.
0.325 BSC.
BALL PITCH
BALL PITCH
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SOLDER BALL PLACEMENT
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
C3~C20,D3~D20,E3~E20,F3~F20 DEPOPULATED SOLDER BALLS
G3~G20,H3~H20,J3~J20,K3~K20
L3~L20,M3~M20,N3~N20,P3~P20
R3~R20,T3~T20,U3~U20,V3~V20
W3~W20,Y3~Y20
3523 \ 16-038.46 \ 02.23.06
24
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
5.6 BTA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
9
PIN A1
CORNER
eD
INDEX MARK
A
B
C
D
E
F
G
H
J
K
L
SE
7
E
B
E1
M
N
P
R
T
U
eE
V
W
Y
AA
AB
0.10
(2X)
C
22 21 20 19 18 17 16 15 14 13 12 11 10
9
7
6
5
4
8
3
2
1
SD
7
0.10
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.10
C
C
A2
A
A1
C
6
160X
b
0.15
0.08
M
C
C
A B
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
BTA 160
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
15.00 mm x 15.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
1.30
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.40
0.74
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
---
0.84
BODY THICKNESS
BODY SIZE
15.00 BSC.
15.00 BSC.
13.65 BSC.
13.65 BSC.
22
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
22
160
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
N
160
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PARAMETERS
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
R
2
Ø b
eE
eD
SD SE
0.45
0.50
0.55
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
0.65 BSC.
0.65 BSC.
0.325 BSC.
BALL PITCH
BALL PITCH
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SOLDER BALL PLACEMENT
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
C3~C20,D3~D20,E3~E20,F3~F20 DEPOPULATED SOLDER BALLS
G3~G20,H3~H20,J3~J20,K3~K20
L3~L20,M3~M20,N3~N20,P3~P20
R3~R20,T3~T20,U3~U20,V3~V20
W3~W20,Y3~Y20
3550 \ 16-038.55 \ 02.23.06
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
25
A d v a n c e I n f o r m a t i o n
5.7 ALH160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
PIN A1
CORNER
9
eD
INDEX MARK
A
B
C
D
E
F
G
H
J
K
L
SE
7
E1
M
N
P
R
T
U
E
B
eE
V
W
Y
AA
AB
0.10
(2X)
C
22 21 20 19 18 17 16 15 14 13 12 11 10
9
7
6
5
4
8
3
2
1
SD
7
0.10
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.10
0.10
C
C
A2
A
A1
C
6
160X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
ALH 160
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
D x E
15.00 mm x 15.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
A
A1
A2
D
1.10
---
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.40
0.53
---
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
0.65
BODY THICKNESS
BODY SIZE
15.00 BSC.
15.00 BSC.
13.65 BSC.
13.65 BSC.
22
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
22
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
160
N
160
MAXIMUM NUMBER OF BALLS
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
R
2
NUMBER OF LAND PERIMETERS
BALL DIAMETER
Øb
eE
eD
SE SD
0.45
0.50
0.55
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.65 BSC.
0.65 BSC
0.325 BSC.
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C3-C20,D3-D20,E3-E20,
F3-F20,G3-G20,H3-H20,
J3-J20,K3-K20,L3-L20,
M3-M20,N3-N20,P3-P20,
R3-R20,T3-T20,U3-U20,
V3-V20,W3-W20,Y3-Y20
3553 \ 16-038.24 \ 3.21.06
26
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
6 MCP Revision Summary
Revision A (August 26, 2004)
Initial release
Revision A 1 (June 1, 2005)
Added SDRAM Type 2 module
Added Lead (Pb)-free options
Added FEA137 package diagram
Revision A2 (October 7, 2005)
Global
Updated the S29WS-N NOR Flash Module
Added the S30MS-P ORNAND Flash Module
Added SDRAM Type 4 module
Product Selector Guide
Updated the Product Selector Guide
Connection Diagrams
Added two diagrams for the x8 and x16 ORNAND connections
Pin Descriptions
Updated descriptions and added descriptions for ORNAND signals
Ordering Information
Added new options
Added Package-on-Package (PoP) options
Valid Combinations
Updated the valid combinations tables
Physical Dimensions
Added the FGA137 package diagram
Added the BWA160 package diagram
Added the BWB160 package diagram
Revision A3 (November 9, 2005)
Updated the SDRAM Type 1 module
Changed the status of all RAM modules to Preliminary from Advanced.
Revision A4 (December 14, 2005)
Product Selector Guides
Updated the tables
Connection Diagrams
Added the 512 Mb NOR Flash with 512 Mb NAND on Bus 1 and 512 Mb SDRAM on Bus 2 diagram
Ordering Information
Added new model number, package modifier and SDRAM & Data Flash density options
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
27
A d v a n c e I n f o r m a t i o n
Valid Combinations
Updated all tables with new options
Revision A5 (December 16, 2005)
Connection Diagrams
Updated the pinouts to include DDR signals
Qualified 133 MHz as DDR based frequency
Revision A6 (March 21, 2006)
NOR Flash + ORNAND Flash + DRAM MCPs Product Selector Guide
Updated the model numbers
Ordering Information Table
Updated the table
Valid Combinations
Updated the tables
Physical Dimensions
Added the ALH160 package
Revision A7 (April 18, 2006)
Connection Diagrams
Updated the pinouts
Revision A8 (June 1, 2006)
Added 2 OPNs for products with DRAM Type 5
Updated product selector guide
Updated valid combination table
Added BTA160 package diagram
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2006 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trade-
marks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
28
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
相关型号:
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