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S72WS256PE0HF0LH0 [SPANSION]

based MCP/PoP Products; 基于MCP / POP产品
S72WS256PE0HF0LH0
型号： S72WS256PE0HF0LH0
厂家： SPANSION    SPANSION
描述：

based MCP/PoP Products
基于MCP / POP产品
文件： 总17页 (文件大小：664K)
中文：  中文翻译
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S72WS-P based MCP/PoP Products  
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus  
Simultaneous Read/Write, Burst Mode NOR Flash  
NAND Flash or NAND Interface ORNAND™ Flash  
on Bus 1 Mobile SDRAM on Bus 2  
S72WS-P based MCP/PoP Products Cover Sheet  
Data Sheet (Advance Information)  
Notice to Readers: This document states the current technical specifications regarding the Spansion  
product(s) described herein. Each product described herein may be designated as Advance Information,  
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.  
Publication Number S72WS-P_00 Revision A Amendment 4 Issue Date May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
Notice On Data Sheet Designations  
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of  
product information or intended specifications throughout the product life cycle, including development,  
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify  
that they have the latest information before finalizing their design. The following descriptions of Spansion data  
sheet designations are presented here to highlight their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion LLC is developing one or more specific  
products, but has not committed any design to production. Information presented in a document with this  
designation is likely to change, and in some cases, development on the product may discontinue. Spansion  
LLC therefore places the following conditions upon Advance Information content:  
“This document contains information on one or more products under development at Spansion LLC.  
The information is intended to help you evaluate this product. Do not design in this product without  
contacting the factory. Spansion LLC reserves the right to change or discontinue work on this  
proposed product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a commitment  
to production has taken place. This designation covers several aspects of the product life cycle, including  
product qualification, initial production, and the subsequent phases in the manufacturing process that occur  
before full production is achieved. Changes to the technical specifications presented in a Preliminary  
document should be expected while keeping these aspects of production under consideration. Spansion  
places the following conditions upon Preliminary content:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. The Preliminary status of this document indicates that product qualification has been  
completed, and that initial production has begun. Due to the phases of the manufacturing process that  
require maintaining efficiency and quality, this document may be revised by subsequent versions or  
modifications due to changes in technical specifications.”  
Combination  
Some data sheets contain a combination of products with different designations (Advance Information,  
Preliminary, or Full Production). This type of document distinguishes these products and their designations  
wherever necessary, typically on the first page, the ordering information page, and pages with the DC  
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first  
page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal changes  
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include  
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed  
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a  
description or to correct a typographical error or incorrect specification. Spansion LLC applies the following  
conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. Spansion LLC deems the products to have been in sufficient production volume  
such that subsequent versions of this document are not expected to change. However, typographical  
or specification corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.  
ii  
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus  
Simultaneous Read/Write, Burst Mode NOR Flash  
NAND Flash or NAND Interface ORNAND™ Flash  
on Bus 1 Mobile SDRAM on Bus 2  
Data Sheet (Advance Information)  
Features  
„ Power supply voltage of 1.7 to 1.95V  
„ Package:  
„ Flash access time: 80 ns for NOR Flash, 25 ns for ORNAND  
„ 9.0 x 12.0 mm MCP  
Flash  
„ 11.0 x 13.0 mm MCP  
„ Flash burst frequencies: 66 MHz, 80 MHz, 108 MHz  
„ 15.0 x 15.0 mm Package-on-Package (PoP)  
„ Operating Temperature  
„ –25°C to +85°C (wireless)  
„ Mobile SDRAM burst frequency: 104 MHz (SDR), 133 MHz  
(DDR)  
The S72WS series is a product line of stacked packages and consists of:  
„ One or two NOR flash memory die  
„ One NAND Interface ORNAND die  
„ Separate bus for one or more Mobile SDRAM die  
The products covered by this document are listed in the table below.  
ORNAND™ Flash  
NOR Flash Density  
Density  
NAND Flash Density  
512Mb  
DRAM Density  
256Mb  
Device  
512Mb  
256Mb  
128Mb  
1024Mb  
512Mb  
512Mb  
128Mb  
X (DDR)  
X (DDR)  
S72WS256PD0 (MCP)  
S72WS256PD0 (POP)  
S72WS512PE0 (MCP)  
S72WS512PEF (POP)  
S72WS512PEF (POP)  
S72WS512PFF (MCP)  
S72WS512PFF (POP)  
S72WS512PFF (MCP)  
S72WS512PFF (POP)  
S72WS512PFG (MCP)  
S72WS512PFG (POP)  
X
X
X
X
X
X
X
X
X
X
X
X (SDR)  
X (SDR)  
X (SDR)  
X
X
X
X
X (DDR)  
X (DDR)  
X (DDR)  
X (DDR)  
X (DDR)  
X (DDR)  
X
X
X
X
Note:  
For a full list of OPNs, please contact the local sales representative or refer to the Ordering Information valid combinations tables.  
For detailed specifications, please refer to the individual data sheets.  
Document  
Publication Identification Number (PID)  
S29WS-P_00  
S29WS-P  
S30MS-P  
S30MS-P_00  
128 Mb Mobile DDR-DRAM Type 5  
256 Mb Mobile SDR-DRAM Type 2  
512 Mb Mobile DDR-DRAM Type 1  
512 Mb Mobile SDR-DRAM Type 4  
512 Mb NAND Type 1  
SDRAM_07  
SDRAM_05  
SDRAM_09  
SDRAM_06  
NAND_01  
512 Mb Mobile DDR-DRAM Type 5  
DRAM_04  
Publication Number S72WS-P_00 Revision A Amendment 4 Issue Date May 29, 2006  
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design  
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
1. Product Selector Guide  
1.1  
NOR Flash + DRAM Products  
NOR Flash  
Density  
NOR Flash  
Speed  
DRAM  
Density  
Device  
DRAM Speed  
DRAM Supplier  
Package  
PoP  
15 x 15 mm  
S72WS256PD0KFKLG  
256 Mb  
512 Mb  
66 MHz  
128 Mb  
133 MHz (DDR)  
Type 5  
MCP  
9 x 12 mm  
S72WS256PD0HF6LG  
S72WS512PE0HF61R  
MCP  
9 x 12 mm  
80 MHz  
256 Mb  
104 MHz (SDR)  
Type 2  
1.2  
NOR Flash + ORNAND Flash + DRAM Products  
NOR  
Flash  
Density  
NOR  
Flash  
Speed  
ORNAND ORNAND  
Flash  
Bus  
ECC  
DRAM  
DRAM  
Speed  
DRAM  
Supplier  
Device-Model#  
Density  
Width  
Required Density  
Package  
PoP  
S72WS512PEFKFKHH  
256 Mb  
Type 2  
15 x 15 mm  
160-ball  
PoP  
S72WS512PFFKFKGH  
S72WS512PFFJF9GH  
S72WS512PFGJF9GH  
S72WS512PFGKFKGH  
S72WS512PFFJF9LD  
S72WS512PFFKFKLD  
512Mb  
15 x 15 mm  
160-ball  
MCP  
11 x 13 mm  
137-ball  
66 MHz  
x16  
Yes  
Type 1  
MCP  
11 x 13 mm  
137-ball  
133 MHz  
(DDR)  
512 Mb  
1024 Mb  
512 Mb  
512 Mb  
PoP  
15 x 15 mm  
160-ball  
MCP  
11 x 13 mm  
137-ball  
80 MHz  
x16  
Yes  
Type 5  
PoP  
15 x 15 mm  
160-ball  
1.3  
NOR Flash + NAND Flash + DRAM Products  
NOR  
Flash  
NOR  
Flash  
NAND  
Flash  
NAND  
Bus  
ECC  
Required  
DRAM  
Density  
DRAM  
Speed  
DRAM  
Supplier  
Device-Model#  
Density Speed Density  
Width  
Package  
PoP  
S72WS512PEFKFKHJ  
256 Mb  
Type 2  
15 x 15 mm  
160-ball  
PoP  
S72WS512PFFKFKGJ  
S72WS512PFFJF9GJ  
S72WS512PFFKFKLE  
S72WS512PFFJF9LE  
66 MHz  
15 x 15 mm  
160-ball  
Type 1  
MCP  
11 x 13 mm 137-  
ball  
133 MHz  
(DDR)  
512Mb  
512Mb  
x16  
Yes  
512 Mb  
PoP  
15 x 15 mm  
160-ball  
80 MHz  
Type 5  
MCP  
11 x 13 mm  
137-ball  
2
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
2. MCP Block Diagram  
2.1  
NOR Flash + DRAM Products  
A0-Amax  
A0-Amax  
RDY  
F-DQ15 - F-DQ0  
F-RDY  
DQ0-DQ15  
WS-P  
NOR Flash  
Memory  
F-CLK  
F-ADV#  
F-CE#  
CLK  
ADV#  
CE#  
OE#  
F-OE#  
F-RST#  
F-ACC  
VSS  
F-VSS  
RESET#  
ACC  
VSSQ  
F-VSS Q  
WP#  
F-WP#  
F-WE#  
WE#  
VCC  
F-VCC  
VCCQ  
F-VCC Q  
D-RAS#  
D-CAS#  
D-BA0  
D-BA1  
D-CKE  
RAS#  
CAS#  
BA0  
BA1  
CKE  
WE#  
CE#  
A0-Amax  
VCC  
CLK  
CLK#  
DQS0  
DQS1  
LDQM  
UDQM  
D-CLK  
D-CLK#  
D-DQS0  
D-DQS1  
D-DM0  
D-DM1  
DDR  
DRAM  
MEMORY  
D-WE#  
D-CE#  
D-A0 - D-Amax  
D-VCC  
D-DQ15 - D-DQ0  
D-VSS  
DQ15-DQ0  
VSS  
D-VCCQ  
VCCQ  
VSSQ  
D-VSSQ  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
3
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
2.2  
NOR Flash + (OR)NAND Flash + DRAM Products  
A0-A24  
A0-A24  
F-RDY  
RDY  
DQ0-DQ15  
DQ0-DQ15  
WS512P  
NOR Flash  
Memory  
F-CLK  
F-AVD#  
F-CE#  
CLK  
AVD#  
CE#  
OE#  
F-OE#  
F-RST#  
F-ACC  
RESET#  
ACC  
VSS  
VSSQ  
F-VSS  
F-VSSQ  
F-WP#  
F-WE#  
WP#  
WE#  
VCC  
VCCQ  
F-VCC  
F-VCCQ  
I/O0-I/O15  
N-RY/BY#  
RB#  
N-CLE  
N-CE#  
N-ALE  
CLE  
CE#  
ALE  
MS512P x16  
ORNAND Flash  
Memory  
N-PRE  
N-RE#  
N-WP#  
N-WE#  
PRE  
RE#  
WP#  
WE#  
VSS  
VCC  
N-VSS  
N-VCC  
D-RAS#  
D-CAS#  
D-BA0  
RAS#  
CAS#  
BA0  
CLK  
CLK#  
DQS0  
DQS1  
LDQM  
UDQM  
D-CLK  
D-CLK#  
D-DQS0  
D-DQS1  
D-DM0  
D-DM1  
512Mb  
DDR  
D-BA1  
D-CKE  
BA1  
CKE  
D-WE#  
D-CE#  
WE#  
CE#  
DRAM  
D-A0 - D-A12  
D-VCC  
D-VCCQ  
A0-A12  
VCC  
VCCQ  
DQ15-DQ0  
VSS  
VSSQ  
D-DQ15 - D-DQ0  
D-VSS  
MEMORY  
D-VSSQ  
Note  
1. For MCPs, VSS is shared between all Flash (NOR and ORNAND). Also, VSSQ is tied to VSS internally within the MCP.  
4
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
3. Connection Diagrams  
3.1  
256Mb NOR Flash with 128Mb SDR/DDR-DRAM  
137-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
D-CKE D-CLK  
D-CLK#  
RFU  
D-VSS  
D-VCC  
RFU  
D-A11  
D-VSS D-CE#  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
D-RAS# D-WE#  
D-A9  
D-A8  
D-VSSQ D-VCCQ  
D-A7  
D-A6  
RFU D-CAS#  
C1  
D-A10 AVD#  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
RFU  
VSS  
CLK  
RFU  
RFU  
RFU  
RFU  
RFU  
Legend  
D1  
D2  
D3  
A7  
D4  
D5  
D6  
D7  
A8  
D8  
D9  
D10  
D-A0 F-WP#  
D-DM0  
F-ACC  
WE#  
A11  
RFU  
D-A5  
E1  
E2  
A3  
E3  
A6  
E4  
E5  
E6  
E7  
E8  
E9  
E10  
NOR Flash only  
DRAM only  
D-VCCQ  
D-DM1 F-RST#  
RFU  
A19  
A12  
A15 D-VCCQ  
F1  
F2  
A2  
F3  
A5  
F4  
F5  
F6  
F7  
A9  
F8  
F9  
F10  
D-VSSQ  
A18  
F-RDY  
A20  
A13  
A21 D-VSSQ  
G1  
G2  
A1  
G3  
A4  
G4  
G6  
G7  
G8  
G9  
G10  
D-DQ0  
A17  
A23  
A10  
A14  
A22 D-DQ15  
Reserved for  
Future Use  
H1  
H2  
A0  
H3  
H4  
H7  
H8  
H9  
H10  
D-DQ1  
VSS  
DQ1  
DQ6  
RFU  
A16 D-DQ14  
J1  
J2  
J3  
J4  
J5  
J6  
J7  
J8  
J9  
J10  
DDR DRAM only  
D-DQ2 F1-CE#  
OE#  
DQ9  
DQ3  
DQ4  
DQ13  
DQ15  
RFU D-DQ13  
K1  
K2  
K3  
K4  
K5  
K6  
K7  
K8  
K9  
K10  
D-DQ3  
RFU  
DQ0  
DQ10  
F-VCC  
RFU  
DQ12  
DQ7  
VSS D-DQ12  
L1  
L2  
L3  
L4  
L5  
L6  
L7  
L8  
L9  
L10  
D-DQ4  
RFU  
DQ8  
DQ2  
DQ11  
RFU  
DQ5  
DQ14  
RFU D-DQ11  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
M9  
M10  
D-DQ5  
RFU  
RFU  
VSS  
F-VCC  
RFU  
RFU  
F-VCCQ  
RFU D-DQ10  
N1  
N2  
N3  
N4  
N5  
N6  
N7  
N8  
N9  
N10  
RFU  
RFU  
D-BA0  
D-DQ6  
D-DQ7 D-VSSQ D-VCCQ D-DQ8  
D-DQ9  
D-BA1  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
P8  
P9  
P10  
D-DQS0 D-VSS  
D-A1  
D-A2  
D-VSS  
D-VCC  
D-A3  
D-A4  
RFU D-DQS1  
Note: DDR-only signals are RFUs in the case of the SDR DRAM-based solutions.  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
5
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
3.2  
512Mb NOR Flash with 512-Mb (OR)NAND on Bus 1 and 512-Mb DRAM on  
Bus 2  
137-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
D-V  
SS  
D-V  
CC  
D-V  
SS  
D-CKE  
D-CLK  
RFU  
D-A12  
D-A11  
D-CE#  
D-CLK#  
B9  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B10  
Legend  
D-RAS# D-WE#  
D-A9  
D-A8  
D-V  
SSQ  
D-V  
CCQ  
D-A7  
D-A6  
RFU  
D-CAS#  
C1  
C2  
C3  
C4  
C5  
C6  
F-V  
C7  
C8  
C9  
C10  
RFU  
Reserved for  
Future Use  
D-A10  
F-AVD#  
V
F-CLK  
RFU  
N-PRE  
N-ALE  
N-CLE  
SS  
CC  
D1  
D2  
D3  
A7  
D4  
D5  
D6  
D7  
A8  
D8  
D9  
D10  
D-A0  
F-WP#  
D-DM0  
F-ACC  
F-WE#  
A11  
N-CE#  
D-A5  
Do Not Use  
E1  
E2  
A3  
E3  
A6  
E4  
E5  
E6  
E7  
E8  
E9  
E10  
D-V  
D-DM1 F-RST#  
DNU  
A19  
A12  
A15  
D-V  
CCQ  
CCQ  
NOR Flash Only  
F1  
F2  
A2  
F3  
A5  
F4  
F5  
F6  
F7  
A9  
F8  
F9  
F10  
D-V  
SSQ  
A18  
F-RDY  
A20  
A13  
A21  
D-V  
SSQ  
ORNAND Flash Only  
G1  
G2  
A1  
G3  
A4  
G4  
G6  
G7  
G8  
G9  
G10  
D-DQ0  
A17  
A23  
A10  
A14  
A22  
D-DQ15  
DRAM Only  
H1  
H2  
A0  
H3  
H4  
H7  
H8  
H9  
H10  
D-DQ1  
VSS  
DQ1  
DQ6  
A24  
A16  
D-DQ14  
All Flash  
Shared  
J1  
J2  
J3  
J4  
J5  
J6  
J7  
J8  
J9  
J10  
D-DQ2  
F1-CE#  
F-OE#  
DQ9  
DQ3  
DQ4  
DQ13  
DQ15  
DNU  
D-DQ13  
K1  
K2  
K3  
K4  
K5  
K6  
K7  
K8  
K9  
K10  
D-DQ3  
DNU  
DQ0  
DQ10  
F-V  
CC  
N-V  
CC  
DQ12  
DQ7  
V
D-DQ12  
SS  
L1  
L2  
L3  
L4  
L5  
L6  
L7  
L8  
L9  
L10  
D-DQ4  
N-VCC  
DQ8  
DQ2  
DQ11  
RFU  
DQ5  
DQ14  
N-WP# D-DQ11  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
M9  
M10  
D-DQ5  
RFU  
RFU  
V
F-V  
CC  
RFU  
DNU  
F-V  
DNU  
D-DQ10  
SS  
CCQ  
N1  
N2  
N3  
N4  
N5  
N6  
N7  
N8  
N9  
N10  
N-WE#  
D-BA0  
D-DQ6  
D-DQ7  
D-V  
D-V  
D-DQ8  
D-DQ9  
D-BA1  
N-RE#  
SSQ  
CCQ  
P1  
P2  
P3  
P4  
P5  
D-V  
P6  
P7  
P8  
P9  
P10  
D-V  
SS  
D-A1  
D-A2  
D-V  
CC  
D-A3  
D-A4 N-RY/BY#  
D-DQS1  
D-DQS0  
SS  
6
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
3.2.0.1  
Special Handling Instructions For FBGA Package  
Special handling is required for Flash Memory products in FBGA packages.  
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The  
package and/or data integrity may be compromised if the package body is exposed to temperatures above  
150×C for prolonged periods of time.  
3.2.1  
Package-on-Package Connection Diagram  
160-ball Fine Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Legend  
A
B
C
D
E
F
F-V  
N-V  
F-V  
F-V  
D-V  
F-A19  
F-A21 F-A23  
F-A22  
F-A18 F-A20  
RFU  
F-A3  
F-A2  
F-A5  
F-A7  
F-A6  
F-A9  
F-A8  
F-A13  
RFU  
NC  
F-A1  
F-A0  
N-CLE F-A11  
F-A15 F-A17  
NC  
SSQ  
SS  
SS  
SSQ  
SS  
F-V  
F-V  
CCQ  
N-V  
CC  
F-V  
SSQ  
F-V  
F-V  
D-V  
F-A24  
D-V  
SS  
F-A14 F-A16  
F-A4  
N-ALE F-A10 F-A12  
CCQ  
CC  
CCQ  
DD  
NOR Flash Only  
N-RY/  
BY#  
RFU  
N-WE#  
F-RST#  
F1-CE#  
N1-CE#  
F2-CE#  
D-DQ1  
D-DQ0  
Reserved for  
Future Use  
D-V  
D-V  
RFU  
DDQ  
SSQ  
N-WP#  
N-RE#  
D-DQ3  
D-DQ2  
DDR DRAM Only  
F-WE# F-WP#  
D-DQ5 D-DQ4  
G
D-V  
D-V  
DDQ  
F-OE#  
H
J
D-WE#  
SSQ  
ORNAND Flash Only  
D-V  
DD  
D-V  
SS  
D-DQ7  
D-DQ6  
Flash Shared Only  
K
D-DM0  
D-DQS0  
D-A0  
D-A2  
D-A4  
D-A6  
D-A1  
D-A3  
D-A5  
D-A7  
L
D-DQS1  
D-DM1  
No Connect  
D-V  
D-V  
M
N
P
SSQ  
DDQ  
D-DQ8  
D-DQ9  
D-V  
SS  
D-V  
DD  
D-BA0 D-BA1  
D-DQ11  
D-DQ13  
D-DQ10  
D-DQ12  
D1-CS#  
RFU  
D-CAS#  
D-A9  
R
T
D-RAS#  
D-A8  
D-V  
D-V  
U
SSQ  
DDQ  
D-A11  
RFU  
D-DQ14  
D-CLK  
D-CLK#  
D-A10  
V
D-DQ15  
D-A12  
F-ACC  
W
Y
D-CKE  
D-V  
SS  
RFU  
RFU  
NC  
F-DQ12/  
N-ADQ12  
F-DQ14/  
N-ADQ14  
F-DQ10/  
N-ADQ10  
F-DQ0/  
N-ADQ0  
F-DQ6/  
N-ADQ6  
F-DQ2/  
N-ADQ2  
F-DQ4/  
N-ADQ4  
F-DQ8/  
N-ADQ8  
F-V  
F-V  
D-V  
DD  
F-V  
SS  
F-V  
F-V  
F-V  
CC  
F-V  
F-V  
N-V  
F-ADV#  
F-WAIT  
RFU  
AA  
AB  
RFU  
RFU  
F-CLK  
RFU  
RFU  
CCQ  
CCQ  
CCQ  
CCQ  
CC  
F-DQ13/  
N-ADQ13  
F-DQ15/  
N-ADQ15  
F-DQ11/  
N-ADQ11  
F-DQ1/  
N-ADQ1  
F-DQ7/  
N-ADQ7  
F-DQ3/  
N-ADQ3  
F-DQ5/  
N-ADQ5  
F-DQ9/  
RFU  
F-V  
F-V  
F-V  
D-V  
DD  
N-V  
SS  
N-PRE  
CCQ  
NC  
SSQ  
SSQ  
SSQ  
SSQ  
N-ADQ9  
3.2.2  
Look-ahead Ballout for Future Designs  
Please refer to the Design-in Scalable Wireless Solutions with Spansion Products application note  
(publication number: Design_Scalable_Wireless_A0_E). Contact your local Spansion sales representative for  
more details.  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
7
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
3.3  
NOR Flash and DRAM Input/Output Descriptions  
Amax-A0  
DQ15-DQ0  
F-CE#  
F-OE#  
F-WE#  
F-VCC  
=
=
=
=
=
=
=
=
=
=
=
NOR Flash Address inputs  
Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND  
NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode.  
NOR Flash Output Enable input. Asynchronous relative to CLK for Burst mode.  
NOR Flash Write Enable input.  
NOR Flash device power supply (1.7 V - 1.95V).  
Input/Output Buffer power supply.  
F-VCCQ  
VSS  
Ground  
RFU  
Reserved for Future Use  
F-RDY  
F-CLK  
Flash ready output. Indicates the status of the Burst read. VOL = data valid.  
NOR Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input  
and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK  
increment the internal address counter. CLK should remain low during asynchronous access.  
F-AVD#  
=
NOR Flash Address Valid input. Indicates to device that the valid address is present on the address  
inputs.  
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be  
latched on rising edge of CLK.  
VIH= device ignores address inputs  
F-RST#  
F-WP#  
=
=
NOR Flash hardware reset input. VIL= device resets and returns to reading array data  
NOR Flash hardware write protect input. VIL = disables program and erase functions in the four  
outermost sectors.  
F-ACC  
=
NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock  
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.  
D-Amax-D-A0  
D-DQ15-D-DQ0  
D-CLK  
=
=
=
=
=
=
=
=
=
=
=
=
SDRAM Address inputs  
SDRAM Data input/output  
SDRAM System Clock  
D-CE#  
SDRAM Chip Select  
D-CKE  
SDRAM Clock Enable  
D-BA1-BA0  
D-RAS#  
SDRAM Bank Select  
SDRAM Row Address Strobe  
SDRAM Column Address Strobe  
SDRAM Data Input/Output Mask  
SDRAM Write Enable input  
SDRAM Ground  
D-CAS#  
D-DM1-D-DM0  
D-WE#  
D-VSS  
D-CLK#  
DDR SDRAM Clock - in addition to D-CLK, this signal is available for DDRAMs that need CLK# for  
normal operations  
D-VSSQ  
D-VCCQ  
D-VCC  
=
=
=
=
SDRAM Input/Output Buffer ground  
SDRAM Input/Output Buffer power supply  
SDRAM device power supply  
D-DQS0 - D-  
DQS1  
DDR SDRAM Data Strobe pins. DQS provides the read data strobes (as output) and the write data  
strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively.  
3.3.1  
ORNAND Signal Descriptions  
N-PRE  
N-ALE  
=
=
=
=
=
=
=
=
=
=
ORNAND Power-On Read Enable. Tie to VSS on customer board if not used  
ORNAND Address Latch Enable  
ORNAND Command Latch Enable  
ORNAND Chip-enablE  
N-CLE  
N-CE#  
N-WP#  
ORNAND Write-protect  
N-WE#  
ORNAND Write-enable  
N-RE#  
ORNAND Read-enable  
N-RY/BY#  
N-I/O0-N-I/O15  
N-VCC  
ORNAND Ready-Busy  
ORNAND I/O Signals (I/O0-I/O7 for x8 bus width)  
ORNAND Power Supply  
8
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
4. Ordering Information  
The order number is formed by a valid combinations of the following:  
S72WS  
512  
P
D0  
HF  
0
L
G
0
PACKING TYPE  
0 = Tray  
2 = 7” Tape and Reel  
3 = 13” Tape and Reel  
MODEL NUMBER 2  
G = 66MHz/133MHz Speed, No Data Flash  
H = 66MHz/133MHz Speed, Spansion MS-P as Data Flash  
J = 66MHz/133MHz Speed, NAND Type 1 as Data Flash  
R = 80MHz/104MHz Speed, No Data Flash  
D = 80MHz/133MHz Speed, Spansion MS-P as Data Flash  
E = 80MHz/133MHz Speed, NAND Type 1 as Data Flash  
MODEL NUMBER 1  
L = x16 DDR DRAM Type 5  
G = x16 DDR DRAM Type 1  
H = x16 DDR DRAM Type 2  
1 = x16 SDR DRAM Type 2  
PACKAGE DESCRIPTOR  
Depends on Character 12. For a more detailed description see Table 4.1.  
PACKAGE TYPE & MATERIAL SET  
HF = 1.2mm MCP FBGA, Pb-free  
KF = 1.2mm POP FBGA, Pb-free  
JF = 1.4mm MCP FBGA, Pb-free  
DRAM & ORNAND FLASH DENSITY  
D0 = 128 Mb DRAM, No Data Flash  
EF = 256Mb DRAM, 512Mb NAND Flash  
FF = 512Mb DRAM, 512Mb NAND Flash  
E0 = 256Mb DRAM, No Data Flash  
PROCESS TECHNOLOGY  
P = 90 nm, MirrorBitTM Technology  
CODE FLASH DENSITY  
256 = 256Mb  
512 = 512Mb  
PRODUCT FAMILY  
S72WS Stacked Products (MCP/PoP)  
1.8 V NOR Flash and ORNAND Flash on Bus 1 with Mobile DRAM on Bus 2  
Table 4.1 Character Position Descriptions (Sheet 1 of 2)  
Character 14 Description  
Character 12  
Character 13  
Package Area  
7x9 mm  
Package Ball Count  
Raw Ball Size  
0
1
2
3
4
5
6
7
8
9
56  
80  
7x9 mm  
8x11.6 mm  
8x11.6 mm  
9x12 mm  
64  
84  
84  
H, J, or G  
0.35 mm  
9x12 mm  
115  
137  
84  
9x12 mm  
11x13 mm  
11x13 mm  
11x13 mm  
115  
137  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
9
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
Table 4.1 Character Position Descriptions (Sheet 2 of 2)  
Character 14 Description  
Character 12  
Character 13  
Package Area  
11x11 mm  
11x11 mm  
12x12 mm  
12x12 mm  
14x14 mm  
14x14 mm  
15x15 mm  
15x15 mm  
17x17 mm  
17x17 mm  
Package Ball Count  
Raw Ball Size  
0.45 mm  
0.50 mm  
0.45 mm  
0.50 mm  
0.45 mm  
0.50 mm  
0.45 mm  
0.50 mm  
0.45 mm  
0.50 mm  
A
B
D
F
112  
112  
128  
128  
152  
152  
160  
160  
192  
192  
G
H
J
K
K
L
M
4.1  
Valid Combinations  
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local  
sales office to confirm availability of specific valid combinations and to check on newly released  
combinations.  
S72WS-P Valid Combinations  
Base Ordering  
Package &  
Material Set  
Package  
Descriptor  
NOR Flash  
Speed  
DRAM  
Supplier  
Package  
Markings  
Number  
Packing Type  
DRAM Speed Package Type  
15x15 mm  
(PoP)  
KF  
HF  
HF  
KF  
HF  
K
6
6
K
6
S72WS256PD0  
66 MHz  
Type 5  
133 MHz  
9x12 mm  
(MCP)  
9x12 mm  
104 MHz  
S72WS512PE0  
S72WS512PEF  
80 MHz  
66 MHz  
66 MHz  
Type 2  
Type 2  
Type 1  
(MCP)  
15x15 mm  
133 MHz  
(PoP)  
15x15 mm  
(PoP)  
0, 2, 3 (Note 1)  
(Note 2)  
66 MHz  
80 MHz  
66 MHz  
80 MHz  
Type 1  
Type 5  
Type 1  
Type 5  
11x13 mm  
JF  
9
S72WS512PFF  
S72WS512PFG  
133 MHz  
(MCP)  
15x15 mm  
(PoP)  
KF  
K
11x13 mm  
(MCP)  
JF  
9
66 MHz  
Type 1  
133 MHz  
15x15 mm  
(PoP)  
KF  
K
Notes:  
1. Packing Type 0 is standard. Specify other options as required.  
2. BGA package marking omits leading S and packing type designator from ordering part number.  
10  
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
5. Physical Dimensions  
5.1  
TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package  
A
D1  
D
eD  
0.15  
(2X)  
C
10  
9
8
SE  
7
7
6
E
B
E1  
5
4
3
2
1
eE  
J
H
G
F
E
D
C
B
A
P
N M L K  
INDEX MARK  
10  
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.15  
(2X)  
C
TOP VIEW  
BOTTOM VIEW  
0.20  
0.08  
C
C
A2  
A
C
A1  
SIDE VIEW  
6
137X  
b
0.15  
0.08  
M
C
C
A
B
M
NOTES:  
PACKAGE  
JEDEC  
TLD 137  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
12.00 mm x 9.00 mm  
PACKAGE  
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
NOTE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
1.20  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.17  
0.81  
---  
BALL HEIGHT  
BODY THICKNESS  
BODY SIZE  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
A2  
---  
0.97  
D
12.00 BSC.  
9.00 BSC.  
10.40 BSC.  
7.20 BSC.  
14  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
10  
137  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
φb  
0.35  
0.40  
0.45  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eE  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
G5,H5,H6  
BALL PITCH  
eD  
SD / SE  
BALL PITCH  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
SOLDER BALL PLACEMENT  
DEPOPULATED SOLDER BALLS  
9. N/A  
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
3393\ 16-038.22a  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
11  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
5.2  
FVD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package  
D1  
A
D
eD  
0.15  
(2X)  
C
10  
9
8
SE  
7
7
6
E
E1  
5
4
3
2
eE  
1
N
L
J
H
G
F
E
D
C
B
A
P
M
K
PIN A1  
9
PIN A1  
CORNER  
B
CORNER  
7
INDEX MARK  
0.15  
(2X)  
C
SD  
TOP VIEW  
SIDE VIEW  
BOTTOM VIEW  
0.20  
C
C
A2  
A
A1  
0.08  
C
6
137X  
b
0.15  
0.08  
M
C
C
A B  
M
NOTES:  
PACKAGE  
JEDEC  
FVD 137  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
13.00 mm x 11.00 mm  
PACKAGE  
NOTE  
3. BALL POSITION DESIGNATION PER JEP95, SECTION  
4.3, SPP-010.  
SYMBOL  
MIN  
NOM  
---  
MAX  
1.40  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.10  
1.09  
---  
---  
BALL HEIGHT  
A2  
---  
1.24  
BODY THICKNESS  
BODY SIZE  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
D
13.00 BSC.  
11.00 BSC.  
10.40 BSC.  
7.20 BSC.  
14  
E
BODY SIZE  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
10  
137  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
Øb  
eE  
0.35  
0.40  
0.45  
BALL DIAMETER  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
G5,H5,H6  
BALL PITCH  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eD  
SD SE  
BALL PITCH  
SOLDER BALL PLACEMENT  
DEPOPULATED SOLDER BALLS  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
3522 \ 16-038.21 \ 09.29.05  
12  
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
5.3  
BWB160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package  
A
D
PIN A1  
CORNER  
D1  
9
PIN A1  
CORNER  
eD  
INDEX MARK  
A
B
C
D
E
F
G
H
J
K
L
SE  
7
E
B
E1  
M
N
P
R
T
U
eE  
V
W
Y
AA  
AB  
0.10  
(2X)  
C
22 21 20 19 18 17 16 15 14 13 12 11 10  
9
7
6
5
4
8
3
2
1
SD  
BOTTOM VIEW  
7
0.10  
(2X)  
C
TOP VIEW  
0.20  
0.10  
C
A2  
A
A1  
C
C
SIDE VIEW  
6
160X  
0.15  
0.08  
b
M
M
C
C
A B  
NOTES:  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
PACKAGE  
JEDEC  
BWB 160  
N/A  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
15.00 mm x 15.00 mm  
PACKAGE  
NOTE  
3. BALL POSITION DESIGNATION PER JEP95, SECTION  
4.3, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
A2  
D
1.30  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.40  
0.74  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
---  
0.84  
BODY THICKNESS  
BODY SIZE  
15.00 BSC.  
15.00 BSC.  
13.65 BSC.  
13.65 BSC.  
22  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MD  
ME  
n
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
22  
160  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
N
160  
MAXIMUM NUMBER OF BALLS  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
R
2
NUMBER OF LAND PARAMETERS  
BALL DIAMETER  
Øb  
eE  
eD  
SD / SE  
0.45  
0.50  
0.55  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
0.65 BSC.  
0.65 BSC.  
0.325 BSC.  
BALL PITCH  
BALL PITCH  
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
SOLDER BALL PLACEMENT  
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.  
?
C3~C20,D3~D20,E3~E20,F3~F20 DEPOPULATED SOLDER BALLS  
G3~G20,H3~H20,J3~J20,K3~K20  
L3~L20,M3~M20,N3~N20,P3~P20  
R3~R20,T3~T20,U3~U20,V3~V20  
W3~W20,Y3~Y20  
3523 \ 16-038.46 \ 02.23.06  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
13  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
5.4  
BTA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package  
A
D
PIN A1  
CORNER  
D1  
9
PIN A1  
CORNER  
eD  
INDEX MARK  
A
B
C
D
E
F
G
H
J
K
L
SE  
7
E
B
E1  
M
N
P
R
T
U
eE  
V
W
Y
AA  
AB  
0.10  
(2X)  
C
22 21 20 19 18 17 16 15 14 13 12 11 10  
9
7
6
4
8
5
3
2
1
SD  
7
0.10  
(2X)  
C
TOP VIEW  
SIDE VIEW  
BOTTOM VIEW  
0.20  
0.10  
C
C
A2  
A
A1  
C
6
160X  
b
0.15  
0.08  
M
C
C
A B  
M
NOTES:  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
PACKAGE  
JEDEC  
BTA 160  
N/A  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
15.00 mm x 15.00 mm  
PACKAGE  
NOTE  
3. BALL POSITION DESIGNATION PER JEP95, SECTION  
4.3, SPP-010.  
SYMBOL  
MIN  
NOM  
---  
MAX  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
A2  
D
---  
1.30  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.40  
0.74  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
---  
0.84  
BODY THICKNESS  
BODY SIZE  
15.00 BSC.  
15.00 BSC.  
13.65 BSC.  
13.65 BSC.  
22  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MD  
ME  
n
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
22  
160  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
N
160  
MAXIMUM NUMBER OF BALLS  
NUMBER OF LAND PARAMETERS  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
R
2
Ø b  
eE  
eD  
SD SE  
0.45  
0.50  
0.55  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
0.65 BSC.  
0.65 BSC.  
0.325 BSC.  
BALL PITCH  
BALL PITCH  
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
SOLDER BALL PLACEMENT  
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.  
C3~C20,D3~D20,E3~E20,F3~F20 DEPOPULATED SOLDER BALLS  
G3~G20,H3~H20,J3~J20,K3~K20  
L3~L20,M3~M20,N3~N20,P3~P20  
R3~R20,T3~T20,U3~U20,V3~V20  
W3~W20,Y3~Y20  
3550 \ 16-038.55 \ 02.23.06  
14  
S72WS-P based MCP/PoP Products  
S72WS-P_00_A4 May 29, 2006  
D a t a S h e e t  
( A d v a n c e I n f o r m a t i o n )  
6. Revision History  
6.1  
6.2  
Revision A1 (February 23, 2006)  
Initial release.  
Revision A2 (March 29, 2006)  
Modified Block Diagram for Section 2.1 and Section 2.2 2.  
Updated PoP Connection Diagram in Section 3.2.2 3.  
Updated Section 3.3 to append F-RDY and N-RY/BY# as separate signals  
6.3  
6.4  
Revision A3 (April 11, 2006)  
Added a note to the NOR Flash + (OR)NAND Flash + DRAM Products block diagram  
Updated pin M8 on the 256Mb NOR Flash with 128Mb SDR/DDR-DRAM connection diagram  
Revision A4 (May 29, 2006)  
Added OPNs for products based on DRAM Type 5  
Updated Product Selector Guide  
Updated Ordering Information  
Updated Valid Combinations  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without  
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as  
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to  
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal  
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,  
the prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under  
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this  
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular  
purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no  
liability for any damages of any kind arising out of the use of the information in this document.  
Copyright © 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof  
are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.  
S72WS-P_00_A4 May 29, 2006  
S72WS-P based MCP/PoP Products  
15  

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