S73WS256ND0BAWT73 [SPANSION]
Stacked Multi-Chip Product (MCP); 堆叠式多芯片产品（ MCP ）
| 型号： | S73WS256ND0BAWT73 |
| 厂家： | 
SPANSION |
| 描述： | Stacked Multi-Chip Product (MCP) |
| 文件： | 总251页 (文件大小：5244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S73WS256N Based MCPs
Stacked Multi-Chip Product (MCP)
512/256 Megabit (32M/16M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory with
256/128 Megabit (4M/2M x 16-bit x 4 Banks) Mobile SDRAM
on Shared Data Bus
ADVANCE
INFORMATION
Data Sheet
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Publication Number S73WS256N_00 Revision A Amendment 3 Issue Date December 16, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
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S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
S73WS256N based MCPs
Stacked Multi-Chip Product (MCP)
512/256 Megabit (32M/16M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory with 256/
128 Megabit (4M/2M x 16-bit x 4 Banks) Mobile SDRAM on
Shared Data Bus
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
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Flash Memory Density
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Publication Number S73WS256N_00 Revision A Amendment 3 Issue Date December 16, 2005
A d v a n c e I n f o r m a t i o n
1 Product Selector Guide
Flash
Flash
Density Density Flash Initial/Burst SDRAM SDRAM burst
Device-Model#
(Code)
(Data)
Speed (ns/MHz)
Density Speed (MHz)
Supplier
DYB
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S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
Table of Contents
S73WS256N Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1
2
3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 2 x 256Mb Flash with 256Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 2 x 256Mb Flash with 128Mb SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 256MbFlash with 128Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4 Lookahead Diagram on Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Symbol for MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.1 TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 FTF137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 x 1.4 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . .21
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4
5
6
7
8
9
10 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
12.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.3 Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.4 Synchronous (Burst) Read Mode & Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.4.1 Continuous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.4.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12.4.3 8-, 16-, 32-Word Linear Burst without Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12.4.4 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12.5 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.6 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.6.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.6.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.6.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.6.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.6.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.6.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.6.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.6.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.6.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.7 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.8 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.9 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.10 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.11 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
13.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
3
A d v a n c e I n f o r m a t i o n
13.7.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.3 Low V Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CC
13.7.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.7.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
14.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
15.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
16.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
16.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.6
V
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CC
16.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
16.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
16.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
17 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
17.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
18 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Mobile SDRAM Type 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
19 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
20 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
23 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
24 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
25 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
26 Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
27 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
28 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
29 Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
30 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
31 Temperature Compensated Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
32 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
33 Driver Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
34 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
35 Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
36 No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
37 Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
38 Active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
39 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
40 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
41 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
42 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
43 Burst Terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
44 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
45 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
46 Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
47 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
47.1 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
47.2 Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
47.3 Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
47.4 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
47.5 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
47.6 Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
47.7 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
47.8 Burst Read/Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
47.9 Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
47.9.1 Read with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
47.10 Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
48 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
49 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
49.1 Revision A0 (April 1, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
49.2 Revision A1 (April 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
49.3 Revision A2 (April 25, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
49.4 Revision A3 (April 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Mobile SDRAM Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
50 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
51 DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
52 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
53 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
54 AC Operating Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
55 Operating AC Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
56 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
57 Simplified Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
58 Mode Register Field Table to Program Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
59 Normal MRS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
60 EMRS for PASR (Partial Array Self Ref) & DS (Driver Strength) . . . . . . . . . . . . . . . . . . . . 169
61 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
62 Internal Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . 170
63 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
64 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
64.1 Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
64.2 Burst Length = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
65.1 Addresses of 64Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.1.1 Bank Addresses (BA0 ~ BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.1.2 Address Inputs (A0 ~ A11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.2 Addresses of 128Mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.2.1 Bank Addresses (BA0 ~ BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.2.2 Address Inputs (A0 ~ A11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.4 Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.5 NOP and Device Deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.6 DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.7 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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65.8 Extended Mode Register Set (EMRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
65.9 Bank Activate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
65.10 Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
65.11 Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
65.12 All Banks Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
65.13 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
65.14 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
65.15 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
65.16 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
65.17 Basic Feature and Function Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
65.17.1 Auto Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
65.17.2 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
66 About Burst Type Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
67 About Burst Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
68 Function Truth Table (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
69 Function Truth Table (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
70 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
71 SDRAM Type 2 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Mobile SDRAM Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
72 Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
73 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
74 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
75 DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
76 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
77 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
78 AC Operating Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
79 Operating AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
80 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
81 Simplified Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
82 Mode Register Field Table to Program Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
82.1 Normal MRS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
82.2 EMRS for PASR (Partial Array Self Refresh) and DS (Driver Strength). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
83 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
83.1 Internal Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
84 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
85 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
85.1 Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
85.2 Burst Length = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
86 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
86.1 Addresses of 256Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
86.1.1. Bank Addresses (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
86.1.2 Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
86.2 Addresses of 512Mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.2.1. Bank Addresses (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.2.2 Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.3 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.4 Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.5 NOP and Device Deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.6 DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
86.7 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
86.8 Extended Mode Register Set (EMRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
86.9 Bank Activate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
86.10 Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
86.11 Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
86.12 All Banks Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
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86.13 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
86.14 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
86.15 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
86.16 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
87 Basic Feature and Function Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
87.1 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
87.2 DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
87.3 CAS# Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
87.4 CAS# Interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
87.5 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
87.6 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
88 Burst Type Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
89 Burst Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
90 Function Truth Table 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
91 Function Truth Table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
92 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
93 SDRAM Type 2 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
94 MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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List of Tables
7DEOHꢀꢋꢃꢇ
,QSXWꢒ2XWSXWꢀ'HVFULSWLRQV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢏꢑ
6ꢏꢉ:6ꢏꢊꢎ1ꢀ6HFWRUꢀꢓꢀ0HPRU\ꢀ$GGUHVVꢀ0DS ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢏꢎ
6ꢏꢉ:6ꢇꢏꢋ1ꢀ6HFWRUꢀꢓꢀ0HPRU\ꢀ$GGUHVVꢀ0DS ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢏꢈ
'HYLFHꢀ2SHUDWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢏꢋ
:RUGꢀ6HOHFWLRQꢀZLWKLQꢀDꢀ3DJH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢏꢉ
$GGUHVVꢀ/DWHQF\ꢀꢁ6ꢏꢉ:6ꢏꢊꢎ1ꢂꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢇ
$GGUHVVꢀ/DWHQF\ꢀꢁ6ꢏꢉ:6ꢇꢏꢋ1ꢂꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢇ
$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢏꢉ:6ꢏꢊꢎ1ꢀ#ꢀꢋꢌ0+]ꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢇ
$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢏꢉ:6ꢏꢊꢎ1ꢀ#ꢀꢎꢎꢀ0+]ꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢇ
$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢏꢉ:6ꢏꢊꢎ1ꢀ#ꢀꢊꢍ0+]ꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢇ
$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀꢁ6ꢏꢉ:6ꢇꢏꢋ1ꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢇ
%XUVWꢀ$GGUHVVꢀ*URXSV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢑ
&RQILJXUDWLRQꢀ5HJLVWHUꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢍ
$XWRVHOHFWꢀ$GGUHVVHV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢊ
$XWRVHOHFWꢀ(QWU\ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢎ
$XWRVHOHFWꢀ([LW ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢑꢎ
6LQJOHꢀ:RUGꢀ3URJUDP ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢑꢉ
:ULWHꢀ%XIIHUꢀ3URJUDP ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢇ
6HFWRUꢀ(UDVH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢑ
&KLSꢀ(UDVH ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢊ
(UDVHꢀ6XVSHQG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢎ
(UDVHꢀ5HVXPH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢎ
3URJUDPꢀ6XVSHQG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢈ
3URJUDPꢀ5HVXPHꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢈ
8QORFNꢀ%\SDVVꢀ(QWU\ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢋ
8QORFNꢀ%\SDVVꢀ3URJUDPꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢉ
8QORFNꢀ%\SDVVꢀ5HVHWꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢍꢉ
'4ꢎꢀDQGꢀ'4ꢏꢀ,QGLFDWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢑ
:ULWHꢀ2SHUDWLRQꢀ6WDWXVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢊ
5HVHW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢊꢈ
/RFNꢀ5HJLVWHU ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢎꢌ
6HFWRUꢀ3URWHFWLRQꢀ6FKHPHV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢎꢎ
ꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ$GGUHVVHV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢎꢉ
6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ(QWU\ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢈꢇ
6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ3URJUDPꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢈꢇ
6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ([LW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢈꢇ
7HVWꢀ6SHFLILFDWLRQVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢈꢑ
6\QFKURQRXVꢀ:DLWꢀ6WDWHꢀ5HTXLUHPHQWVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢈꢈ
ꢀ0HPRU\ꢀ$UUD\ꢀ&RPPDQGV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢉꢈ
6HFWRUꢀ3URWHFWLRQꢀ&RPPDQGV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢉꢋ
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6\VWHPꢀ,QWHUIDFHꢀ6WULQJ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢉꢉ
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3ULPDU\ꢀ9HQGRUꢅ6SHFLILFꢀ([WHQGHGꢀ4XHU\ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢇꢌꢇ
%XUVWꢀ'HILQLWLRQ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢇꢌ
&$6ꢀ/DWHQF\ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢇꢏ
7UXWKꢀ7DEOHꢀꢇꢀꢅꢀ&RPPDQGVꢀDQGꢀ'40ꢀ2SHUDWLRQꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢇꢊ
7UXWKꢀ7DEOHꢀꢏꢀꢅꢀ&.( ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢑꢊ
7UXWKꢀ7DEOHꢀꢑꢀꢅꢀ&XUUHQWꢀ6WDWHꢀ%DQNꢀQꢄꢀ&RPPDQGꢀWRꢀ%DQNꢀQ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢑꢎ
7UXWKꢀ7DEOHꢀꢍꢀꢅꢀ&XUUHQWꢀ6WDWHꢀ%DQNꢀQꢄꢀ&RPPDQGꢀWRꢀ%DQNꢀP ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢑꢈ
'&ꢀ(OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ2SHUDWLQJꢀ&RQGLWLRQVꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢑꢉ
$&ꢀ(OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ2SHUDWLQJꢀ&RQGLWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢍꢌ
(OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ5HFRPPHQGHGꢀ$&ꢀ2SHUDWLQJꢀ&RQGLWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢍꢌ
$&ꢀ)XQFWLRQDOꢀ&KDUDFWHULVWLFV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢍꢇ
,''ꢀ6SHFLILFDWLRQVꢀDQGꢀ&RQGLWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢍꢏ
7DEOHꢀꢇꢇꢃꢇ
7DEOHꢀꢇꢇꢃꢏꢃ
7DEOHꢀꢇꢏꢃꢇ
7DEOHꢀꢇꢏꢃꢏ
7DEOHꢀꢇꢏꢃꢑ
7DEOHꢀꢇꢏꢃꢍ
7DEOHꢀꢇꢏꢃꢊ
7DEOHꢀꢇꢏꢃꢎ
7DEOHꢀꢇꢏꢃꢈ
7DEOHꢀꢇꢏꢃꢋ
7DEOHꢀꢇꢏꢃꢉ
7DEOHꢀꢇꢏꢃꢇꢌ
7DEOHꢀꢇꢏꢃꢇꢇ
7DEOHꢀꢇꢏꢃꢇꢏ
7DEOHꢀꢇꢏꢃꢇꢑ
7DEOHꢀꢇꢏꢃꢇꢍꢃ
7DEOHꢀꢇꢏꢃꢇꢊꢃ
7DEOHꢀꢇꢏꢃꢇꢎꢃ
7DEOHꢀꢇꢏꢃꢇꢈꢃ
7DEOHꢀꢇꢏꢃꢇꢋꢃ
7DEOHꢀꢇꢏꢃꢇꢉꢃ
7DEOHꢀꢇꢏꢃꢏꢌꢃ
7DEOHꢀꢇꢏꢃꢏꢇꢃ
7DEOHꢀꢇꢏꢃꢏꢏꢃ
7DEOHꢀꢇꢏꢃꢏꢑꢃ
7DEOHꢀꢇꢏꢃꢏꢍꢃ
7DEOHꢀꢇꢏꢃꢏꢊꢃ
7DEOHꢀꢇꢏꢃꢏꢎꢃ
7DEOHꢀꢇꢏꢃꢏꢈꢃ
7DEOHꢀꢇꢑꢃꢇ
7DEOHꢀꢇꢑꢃꢏ
7DEOHꢀꢇꢊꢃꢇ
7DEOHꢀꢇꢊꢃꢏꢃ
7DEOHꢀꢇꢊꢃꢑꢃ
7DEOHꢀꢇꢊꢃꢍꢃ
7DEOHꢀꢇꢎꢃꢇ
7DEOHꢀꢇꢎꢃꢏ
7DEOHꢀꢇꢈꢃꢇ
7DEOHꢀꢇꢈꢃꢏꢃ
7DEOHꢀꢇꢈꢃꢑꢃ
7DEOHꢀꢇꢈꢃꢍꢃ
7DEOHꢀꢇꢈꢃꢊꢃ
7DEOHꢀꢇꢈꢃꢎꢃ
7DEOHꢀꢏꢊꢃꢇ
7DEOHꢀꢏꢈꢃꢇ
7DEOHꢀꢑꢍꢃꢇ
7DEOHꢀꢍꢈꢃꢇ
7DEOHꢀꢍꢈꢃꢏ
7DEOHꢀꢍꢈꢃꢑ
7DEOHꢀꢍꢋꢃꢇ
7DEOHꢀꢍꢋꢃꢏ
7DEOHꢀꢍꢋꢃꢑ
7DEOHꢀꢍꢋꢃꢍ
7DEOHꢀꢍꢋꢃꢊ
7DEOHꢀꢍꢋꢃꢎ
7DEOHꢀꢍꢋꢃꢈ
7DEOHꢀꢋꢏꢃꢇ
,
ꢀꢅꢀ6HOIꢀ5HIUHVKꢀ&XUUHQWꢀ2SWLRQV ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢍꢑ
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5HJLVWHUꢀ3URJUDPPHGꢀZLWKꢀ([WHQGHGꢀ056 ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢇꢏ
8
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
List of Figures
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6ꢏꢉ:6ꢅ1ꢀ%ORFNꢀ'LDJUDP ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢏꢍ
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([WHQGHGꢀ0RGHꢀ5HJLVWHU ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢇꢍ
$FWLYDWLQJꢀDꢀ6SHFLILFꢀ5RZꢀLQꢀDꢀ6SHFLILFꢀ%DQNꢀ5HJLVWHU ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢇꢉ
5HDGꢀ&RPPDQGꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢏꢇ
:ULWHꢀ&RPPDQG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢏꢎ
,QLWLDOL]HꢀDQGꢀ/RDGꢀ0RGHꢀ5HJLVWHU ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢍꢍ
'&ꢀ2XWSXWꢀ/RDGꢀ&LUFXLWꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢎꢊ
$&ꢀ2XWSXWꢀ/RDGꢀ&LUFXLWꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢎꢎ
&ORFNꢀ6XVSHQG ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢈꢊ
'40ꢀ2SHUDWLRQ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢈꢎ
&$6ꢔꢀ,QWHUUXSWꢀꢁꢇꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢈꢈ
&$6ꢔꢀ,QWHUUXSWꢀꢁꢏꢂꢆꢀ5HDGꢀ,QWHUUXSWHGꢀE\ꢀ:ULWHꢀꢓꢀ'40 ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢈꢋ
:ULWHꢀ,QWHUUXSWHGꢀE\ꢀ3UHFKDUJHꢀꢓꢀ'40 ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢈꢉ
3UHFKDUJHꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢈꢉ
$XWRꢀ3UHFKDUJH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢋꢌ
%XUVWꢀ6WRSꢀDQGꢀ,QWHUUXSWHGꢀE\ꢀ3UHFKDUJH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢋꢌ
056ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢇꢋꢇ
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
9
A d v a n c e I n f o r m a t i o n
)LJXUHꢀꢎꢊꢃꢇꢌ
)LJXUHꢀꢎꢊꢃꢇꢇ
)LJXUHꢀꢎꢊꢃꢇꢏ
)LJXUHꢀꢈꢌꢃꢇ
)LJXUHꢀꢈꢌꢃꢏ
)LJXUHꢀꢈꢌꢃꢑ
)LJXUHꢀꢈꢌꢃꢍ
)LJXUHꢀꢈꢌꢃꢊ
)LJXUHꢀꢈꢌꢃꢎ
)LJXUHꢀꢈꢌꢃꢈ
)LJXUHꢀꢈꢌꢃꢋ
)LJXUHꢀꢈꢌꢃꢉ
)LJXUHꢀꢈꢌꢃꢇꢌ
)LJXUHꢀꢈꢌꢃꢇꢇ
)LJXUHꢀꢈꢌꢃꢇꢏ
)LJXUHꢀꢈꢌꢃꢇꢑ
)LJXUHꢀꢈꢌꢃꢇꢍ
)LJXUHꢀꢈꢌꢃꢇꢊ
)LJXUHꢀꢈꢌꢃꢇꢎ
)LJXUHꢀꢈꢌꢃꢇꢈ
)LJXUHꢀꢈꢋꢃꢇ
)LJXUHꢀꢈꢋꢃꢏ
)LJXUHꢀꢋꢑꢃꢇ
)LJXUHꢀꢋꢈꢃꢇ
)LJXUHꢀꢋꢈꢃꢏ
)LJXUHꢀꢋꢈꢃꢇ
)LJXUHꢀꢋꢈꢃꢏ
)LJXUHꢀꢋꢈꢃꢑ
)LJXUHꢀꢋꢈꢃꢍ
)LJXUHꢀꢋꢈꢃꢊ
)LJXUHꢀꢋꢈꢃꢎ
)LJXUHꢀꢋꢈꢃꢈ
)LJXUHꢀꢋꢈꢃꢋ
)LJXUHꢀꢋꢈꢃꢉ
)LJXUHꢀꢋꢈꢃꢇꢌ
)LJXUHꢀꢋꢈꢃꢇꢇ
)LJXUHꢀꢋꢈꢃꢇꢏ
)LJXUHꢀꢋꢈꢃꢇꢑ
)LJXUHꢀꢋꢈꢃꢇꢍ
)LJXUHꢀꢋꢈꢃꢇꢊ
)LJXUHꢀꢉꢏꢃꢇ
)LJXUHꢀꢉꢏꢃꢏ
)LJXUHꢀꢉꢏꢃꢑ
)LJXUHꢀꢉꢏꢃꢍ
)LJXUHꢀꢉꢏꢃꢊ
)LJXUHꢀꢉꢏꢃꢎ
)LJXUHꢀꢉꢏꢃꢈ
)LJXUHꢀꢉꢏꢃꢋ
)LJXUHꢀꢉꢏꢃꢉ
)LJXUHꢀꢉꢏꢃꢇꢌ
)LJXUHꢀꢉꢏꢃꢇꢇ
)LJXUHꢀꢉꢏꢃꢇꢏ
)LJXUHꢀꢉꢏꢃꢇꢑ
)LJXUHꢀꢉꢏꢃꢇꢍ
)LJXUHꢀꢉꢏꢃꢇꢊ
)LJXUHꢀꢉꢏꢃꢇꢎ
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&ORFNꢀ6XVSHQGꢀ'XULQJꢀ5HDGꢀꢁ%/ꢀ ꢀꢍꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢇꢉ
:ULWHꢀ0DVNꢀꢁ%/ꢀ ꢀꢍꢂ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢇꢉ
5HDGꢀ0DVNꢀꢁ%/ꢀ ꢀꢍꢂꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢌ
'40ꢀZLWKꢀ&/RFNꢀ6XVSHQGHGꢀꢁ)XOOꢀ3DJHꢀ5HDGꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢌ
5HDGꢀ,QWHUUXSWHGꢀE\ꢀ5HDGꢀꢁ%/ꢀ ꢀꢍꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢌ
:ULWHꢀ,QWHUUXSWHGꢀE\ꢀ:ULWHꢀꢁ%/ꢀ ꢀꢏꢂꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢌ
:ULWHꢀ,QWHUUXSWHGꢀE\ꢀ5HDGꢀꢁ%/ꢀ ꢀꢏꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢇ
5HDGꢀ,QWHUUXSWHGꢀE\ꢀ:ULWHꢀDQGꢀ'40 ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢏ
:ULWHꢀ,QWHUUXSWHGꢀE\ꢀ3UHFKDUJHꢀDQGꢀ'40 ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢑ
3UHFKDUJHꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢑ
$XWRꢀ3UHFKDUJH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢍ
%XUVWꢀ6WRSꢀDQGꢀ,QWHUUXSWHGꢀE\ꢀ3UHFKDUJH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢊ
0RGHꢀ5HJLVWHUꢀ6HW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢊ
&ORFNꢀ6XVSHQGꢀ([LWꢀDQGꢀ3RZHUꢀ'RZQꢀ([LW ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢎ
$XWRꢀ5HIUHVKꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢎ
6HOIꢀ5HIUHVK ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢏꢎ
3RZHUꢀ8Sꢀ6HTXHQFH ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢑꢇ
6LQJOHꢀ%LWꢀ5HDGꢅ:ULWHꢅ5HDGꢀ&\FOHꢀꢁ6DPHꢀ3DJHꢂꢀ#&$6ꢀ/DWHQF\ ꢑꢄꢀ%XUVWꢀ/HQJWK ꢇ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢑꢏ
5HDGꢀꢓꢀ:ULWHꢀ&\FOHꢀDWꢀ6DPHꢀ%DQNꢀ#%XUVWꢀ/HQJWK ꢍꢄꢀW
5HDGꢀꢓꢀ:ULWHꢀ&\FOHꢀDWꢀ6DPHꢀ%DQNꢀ#%XUVWꢀ/HQJWK ꢍꢄꢀW
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3DJHꢀ:ULWHꢀ&\FOHꢀDWꢀ'LIIHUHQWꢀ%DQNꢀ#%XUVWꢀ/HQJWK ꢍꢄꢀW ꢏ&/. ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢑꢎ
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5HDGꢀꢓꢀ:ULWHꢀ&\FOHꢀDWꢀ'LIIHUHQWꢀ%DQNꢀ#%XUVWꢀ/HQJWK ꢍ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢑꢈ
5HDGꢀꢓꢀ:ULWHꢀ&\FOHꢀZLWKꢀ$XWRꢀ3UHFKDUJHꢀ,ꢀ#%XUVWꢀ/HQJWK ꢍꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢑꢋ
5HDGꢀꢓꢀ:ULWHꢀ&\FOHꢀZLWKꢀ$XWRꢀ3UHFKDUJHꢀꢏꢀ#%XUVWꢀ/HQJWK ꢍ ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢑꢉ
&ORFNꢀ6XVSHQVLRQꢀꢓꢀ'40ꢀ2SHUDWLRQꢀ&\FOHꢀ#&$6ꢀ/DWHQF\ ꢏꢄꢀ%XUVWꢀ/HQJWK ꢍ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢌ
5HDGꢀ,QWHUUXSWHGꢀE\ꢀ3UHFKDUJHꢀ&RPPDQGꢀꢓꢀ5HDGꢀ%XUVWꢀ6WRSꢀ&\FOHꢀ#)XOOꢀ3DJHꢀ%XUVW ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢇ
:ULWHꢀ,QWHUUXSWHGꢀE\ꢀ3UHFKDUJHꢀ&RPPDQGꢀꢓꢀ:ULWHꢀ%XUVWꢀ6WRSꢀ&\FOHꢀ#ꢀ)XOOꢀ3DJHꢀ%XUVWꢄꢀW5'/ ꢏ&/.ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢏ
%XUVWꢀ5HDGꢀ6LQJOHꢀELWꢀ:ULWHꢀ&\FOHꢀ#%XUVWꢀ/HQJWK ꢏꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢑ
$FWLYHꢒ3UHFKDUJHꢀ3RZHUꢀ'RZQꢀ0RGHꢀ#&$6ꢀ/DWHQF\ ꢏꢄꢀ%XUVWꢀ/HQJWK ꢍꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢍ
6HOIꢀ5HIUHVKꢀ(QWU\ꢀꢓꢀ([LWꢀ&\FOHꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢊ
([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀ6HWꢀ&\FOHꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢏꢍꢈ
10
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
2 MCP Block Diagram
V
f
CC
max +1*
V
V
ID
A23 - A0
CC
DQ15 to DQ0
16
CLK
WP#
ACC
CE#
OE#
WE#
CLK
WP#f1
ACC
Flash 1
(Note 1) CE#f1
OE#
Flash 2
(Note 2)
WE#
RDY
RDY
RESET#
AVD#
RESET#
AVD#
DQ15 to DQ0
CE#f2
V
SS
D-V
CC
D-V
CCQ
D-max + 1*
A12 - A0
V
V
CCQ
CC
D-CLK
CLK
CE#
WE#
16
D-CE#
D-WE#
DQ15 to DQ0
D-BA0
D-BA1
BA0
BA1
D-CKE
D-RAS#
D-CAS#
D-DM0
CKE
SDRAM
RAS#
CAS#
DM0
D-DM1
DM1
V
SSQ
D-V
SSQ
* Amax = A23
D-Amax = A12
Ir)
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)RUꢂDꢂWZRꢃ)ODVKꢂFRQILJXUDWLRQꢄꢂ&(ꢅIꢀꢂ ꢂ&(ꢂIRUꢂ)ODVKꢂꢀꢂDQGꢂ&(ꢅIꢆꢂ ꢂ&(ꢂIRUꢂ)ODVKꢂꢆꢇꢂ&(ꢅIꢆꢂLVꢂWKHꢂ
FKLSꢃHQDEOHꢂSLQꢂIRUꢂWKHꢂVHFRQGꢂ)ODVKꢁ
ꢆꢁ )ODVKꢂDQGꢂ6'5$0ꢂVKDUHꢂFRPPRQꢂ$ꢀꢆꢃ$ꢈꢂDQGꢂ'4ꢀꢉꢃ'4ꢈꢁ
ꢊꢁ $SSOLFDEOHꢂRQO\ꢂIRUꢂWKHꢂ6ꢋꢊ:6ꢆꢉꢌ1'(ꢂDQGꢂ6ꢋꢊ:6ꢆꢉꢌ1((ꢂGHYLFHVꢁ
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
11
A d v a n c e I n f o r m a t i o n
3 Connection Diagrams
3.1
2 x 256Mb Flash with 256Mb SDRAM
ꢄꢅꢆꢇEDOOꢀ)LQHꢇ3LWFKꢀ%DOOꢀ*ULGꢀ$UUD\
ꢁ7RSꢀ9LHZꢄꢀ%DOOVꢀ)DFLQJꢀ'RZQꢂ
A1
A2
A9
A10
A3
A4
A5
A6
A7
A8
D-CKE D-CLK
DNU
DNU
DNU
DNU
DNU
DNU
D-VSS D-CE#
B1
B2
B9
B10
B3
B4
B5
B6
B7
B8
D-RAS# D-WE#
RFU D-CAS#
DNU
DNU
DNU
DNU
DNU
DNU
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
C1
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
DNU
Legend
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
D1
WP#
D-DM0
ACC
WE#
A11
F2-CE# DNU
DNU
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
E1
Flash/SDRAM Shared
SDRAM only
D-DM1 F-RST#
RFU
A19
A12
A15
DNU
DNU
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
F1
A18
RDY
A20
A13
A21
DNU
DNU
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
DNU
G1
A17
A23
A10
A14
A22
DNU
Reserved for
Future Use
H2
A0
H3
H4
H7
H8
H9
H10
DNU
H1
VSS
DQ1
DQ6
RFU
A16
DNU
Data Flash only
J2
J3
J4
J5
J6
J7
J8
J9
J10
J1
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
DNU
DNU
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
K1
Flash/Data Shared
RFU
DQ0
DQ10
F-VCC
D-VCC
DQ12
DQ7
VSS
DNU
L2
L3
L4
L5
L6
L7
L8
L9
L10
L1
Code Flash Only
Do Not Use
D-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
DNU
DNU
M2
M3
M4
M5
M6
M7
M8
M9
M10
DNU
M1
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
DNU
N1
N2
N9
N10
RFU
N3
N4
N5
N6
N7
N8
DNU
DNU
DNU
DNU
DNU
DNU
RFU
D-BA0
D-BA1
P1
P2
P9
P10
RFU
P3
P4
P5
P6
P7
P8
RFU
D-VSS
RFU
DNU
DNU
DNU
DNU
DNU
DNU
Ir)
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ꢂWRꢂ'ꢃ9 ꢁ
66
66
664
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ꢁ
6SHFLDOꢀ+DQGOLQJꢀ,QVWUXFWLRQVꢀ)RUꢀ)%*$ꢀ3DFNDJH
6SHFLDOꢀKDQGOLQJꢀLVꢀUHTXLUHGꢀIRUꢀ)ODVKꢀ0HPRU\ꢀSURGXFWVꢀLQꢀ)%*$ꢀSDFNDJHVꢃ
)ODVKꢀPHPRU\ꢀGHYLFHVꢀLQꢀ)%*$ꢀSDFNDJHVꢀPD\ꢀEHꢀGDPDJHGꢀLIꢀH[SRVHGꢀWRꢀXOWUDꢅ
VRQLFꢀFOHDQLQJꢀPHWKRGVꢃꢀ7KHꢀSDFNDJHꢀDQGꢒRUꢀGDWDꢀLQWHJULW\ꢀPD\ꢀEHꢀFRPSURPLVHGꢀ
LIꢀWKHꢀSDFNDJHꢀERG\ꢀLVꢀH[SRVHGꢀWRꢀWHPSHUDWXUHVꢀDERYHꢀꢇꢊꢌ°&ꢀIRUꢀSURORQJHGꢀSHULꢅ
RGVꢀRIꢀWLPHꢃ
12
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
3.2
2 x 256Mb Flash with 128Mb SDRAM
ꢄꢅꢆꢇEDOOꢀ)LQHꢇ3LWFKꢀ%DOOꢀ*ULGꢀ$UUD\
ꢁ7RSꢀ9LHZꢄꢀ%DOOVꢀ)DFLQJꢀ'RZQꢂ
A1
A2
A9
A10
A3
A4
A5
A6
A7
A8
DNU
DNU
DNU
DNU
DNU
DNU
D-CKE D-CLK
D-VSS D-CE#
B1
B2
B9
B10
B3
B4
B5
B6
B7
B8
D-RAS# D-WE#
RFU D-CAS#
DNU
DNU
DNU
DNU
DNU
DNU
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
DNU
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
DNU
WP#
D-DM0
ACC
WE#
A11
F2-CE# DNU
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
Flash/SDRAM Shared
SDRAM only
DNU
D-DM1 F-RST#
RFU
A19
A12
A15
DNU
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
DNU
A18
RDY
A20
A13
A21
DNU
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
DNU
DNU
A17
A23
A10
A14
A22
Reserved for
Future Use
H1
H2
A0
H3
H4
H7
H8
H9
H10
DNU
DNU
VSS
DQ1
DQ6
RFU
A16
Data Flash only
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DNU F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
DNU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
Flash/Data Shared
DNU
RFU
DQ0
DQ10
F-VCC
D-VCC
DQ12
DQ7
VSS
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
Code Flash Only
Do Not Use
DNU
D-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
DNU
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
DNU
DNU
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
N1
N2
N9
N10
RFU
N3
N4
N5
N6
N7
N8
DNU
DNU
DNU
DNU
DNU
DNU
RFU
D-BA0
D-BA1
P1
P2
P9
P10
RFU
P3
P4
P5
P6
P7
P8
RFU
D-VSS
RFU
DNU
DNU
DNU
DNU
DNU
DNU
Ir)
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ꢂWRꢂ'ꢃ9 ꢁ
66
66
664
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ꢁ
6SHFLDOꢀ+DQGOLQJꢀ,QVWUXFWLRQVꢀ)RUꢀ)%*$ꢀ3DFNDJH
6SHFLDOꢀKDQGOLQJꢀLVꢀUHTXLUHGꢀIRUꢀ)ODVKꢀ0HPRU\ꢀSURGXFWVꢀLQꢀ)%*$ꢀSDFNDJHVꢃ
)ODVKꢀPHPRU\ꢀGHYLFHVꢀLQꢀ)%*$ꢀSDFNDJHVꢀPD\ꢀEHꢀGDPDJHGꢀLIꢀH[SRVHGꢀWRꢀXOWUDꢅ
VRQLFꢀFOHDQLQJꢀPHWKRGVꢃꢀ7KHꢀSDFNDJHꢀDQGꢒRUꢀGDWDꢀLQWHJULW\ꢀPD\ꢀEHꢀFRPSURPLVHGꢀ
LIꢀWKHꢀSDFNDJHꢀERG\ꢀLVꢀH[SRVHGꢀWRꢀWHPSHUDWXUHVꢀDERYHꢀꢇꢊꢌ°&ꢀIRUꢀSURORQJHGꢀSHULꢅ
RGVꢀRIꢀWLPHꢃ
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
13
A d v a n c e I n f o r m a t i o n
3.3
256MbFlash with 128Mb SDRAM
ꢄꢅꢆꢇEDOOꢀ)LQHꢇ3LWFKꢀ%DOOꢀ*ULGꢀ$UUD\
ꢁ7RSꢀ9LHZꢄꢀ%DOOVꢀ)DFLQJꢀ'RZQꢂ
A1
A2
A9
A10
A3
A4
A5
A6
A7
A8
D-CKE D-CLK
DNU
DNU
DNU
DNU
DNU
DNU
D-VSS D-CE#
B1
B2
B9
B10
B3
B4
B5
B6
B7
B8
D-RAS# D-WE#
RFU D-CAS#
DNU
DNU
DNU
DNU
DNU
DNU
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
DNU
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
Legend
D1
D2
D3
A7
D4
D5
D6
D7
A8
D8
D9
D10
DNU
DNU
WP#
D-DM0
ACC
WE#
A11
RFU
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
Flash/SDRAM Shared
SDRAM only
DNU
D-DM1 F-RST#
RFU
A19
A12
A15
DNU
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
DNU
A18
RDY
A20
A13
A21
DNU
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
DNU
DNU
A17
A23
A10
A14
A22
Reserved for
Future Use
H1
H2
A0
H3
H4
H7
H8
H9
H10
DNU
DNU
VSS
DQ1
DQ6
RFU
A16
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
Code Flash Only
Do Not Use
DNU F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
DNU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
DNU
RFU
DQ0
DQ10
F-VCC
D-VCC
DQ12
DQ7
VSS
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
DNU
D-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
DNU
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
DNU
DNU
RFU
RFU
VSS
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DNU
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DNU
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D-BA1
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P2
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P10
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P4
P5
P6
P7
P8
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14
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
3.4 Lookahead Diagram on Shared Bus
A8
A9
A10
A6
A7
A2
A1
A4
A5
Legend:
A3
DNU
DNU
DNU
D-CLK
D-VSS
D-CE#
D-CKE
DNU
DNU
DNU
RFU
(Reserved for
Future Use)
B7
B8
B5
B6
B9
B10
B1
B2
B3
B4
DNU
DNU
DNU
DNU
D-RAS# D-WE#
D-DQS3 D-CAS#
DNU
DNU
C1
C2
C4
C5
C6
C7
C8
C9
C3
C10
Code Flash Only
DNU
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK#
R-OE# F2-OE#
DNU
D1
D4
D2
D3
D5
D6
D7
A8
D8
DD99
D10
D-DM0/
R-LB#
DNU
WP#
D-A7
ACC
WE#
A11
F3-CE#
DNU
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Only
E1
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
E10
D-DM1/
R-UB#
DNU
F-RST#
R-CE2
A19
A12
A15
DNU
Flash/Data
Shared
F1
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
F10
DNU
RDY/WAIT#
A18
A20
A13
A21
DNU
G1
G2
A1
G3
A4
G4
G6
G7
G8
G9
G10
DNU
Flash/xRAM
Shared
DNU
A17
A23
A10
A14
A22
H1
H2
A0
H3
H4
H7
H8
H9
H10
DNU
pSRAM Only
xRAM Shared
VSS
DQ1
DQ6
A24
A16
DNU
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
R-CRE
or R-MRS
DNU
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
F1-CE#
OE#
K1
K2
K5
K7
K3
K4
K6
K8
K9
K10
DNU
DQ12
VSS
DNU
R-CE1#
DQ0
DQ10
F-VCC
R-VCC
DQ7
SDRAM Only
L1
L2
L4
L5
L6
L7
L8
LL99
L3
L10
DNU
DQ2
DQ11
A25
DQ5
DQ14
WP#
DNU
R-VCC
DQ8
M1
M5
M9
M2
M3
M4
MM66
M7
M8
M10
DNU
DNU
DD-CLK#
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ
N10
N1
N2
N9
N4
N5
N6
N7
N8
N3
D-BA0
F-DQS1
F-DQS0
D-BA1
DNU
DNU
DNU
DNU
DNU
DNU
P1
P2
P10
P5
P9
P3
P4
P6
P7
P8
D-DQS0
D-VSS
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DNU
DNU
DNU
DNU
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December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
15
A d v a n c e I n f o r m a t i o n
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S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
5 Logic Symbol for MCP
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CLK
16
CE#F1
CE#F2
OE#
DQ15-DQ0
WE#
RESET#
AVD#
RDY
WP#
ACC
D-CLK#
D-CE#
D-CKE
D-BA1-BA0
D-DM1-DM0
D-RAS#
D-CAS#
D-WE#
D-A12-A0
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
17
A d v a n c e I n f o r m a t i o n
6 Ordering Information
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S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
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December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
19
A d v a n c e I n f o r m a t i o n
7 Physical Dimensions
7.1
TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
P
N M L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
B
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
137X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLD 137
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
D
12.00 BSC.
9.00 BSC.
10.40 BSC.
7.20 BSC.
14
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
137
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
G5,H5,H6
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3393\ 16-038.22a
20
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e I n f o r m a t i o n
7.2 FTF137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 x 1.4 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
P
N M L K
INDEX MARK
9
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
A2
A
A1
C
C
SIDE VIEW
6
137X
b
M
0.15
0.08
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
FTF 137
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
1.02
---
BALL HEIGHT
A2
---
1.17
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
12.00 BSC.
9.00 BSC.
10.40 BSC.
7.20 BSC.
14
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
10
137
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
0.80 BSC.
0.80 BSC
0.40 BSC.
G5,H5,H6
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3532 \ 16-038.21 \ 12.13.05
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
21
S29WS-N MirrorBitTM Flash Family
S29WS256N, S29WS128N
256/128 Megabit (16/8 M x 16 bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory
PRELIMINARY
Data Sheet
General Description
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Publication Number S29WS-N_m0 Revision I Amendment 0 Issue Date December 3, 2005
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P r e l i m i n a r y
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Table 8.1 Input/Output Descriptions
Symbol
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Type
,QSXW
Description
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December 3, 2005 S29WS-N_m0_I0
23
P r e l i m i n a r y
9 Block Diagram
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Figure 9.1. S29WS-N Block Diagram
24
S29WS-N_m0_I0 December3,2005
P r e l i m i n a r y
10 Additional Resources
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December 3, 2005 S29WS-N_m0_I0
25
P r e l i m i n a r y
11 Product Overview
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V\QFKURQRXVꢀꢁEXUVWꢂꢀUHDGꢀRUꢀOLQHDUꢀUHDGꢀꢁꢋꢅꢄꢀꢇꢎꢅꢄꢀRUꢀꢑꢏꢅZRUGꢀDOLJQHGꢀJURXSꢂꢀZLWKꢀRUꢀZLWKRXWꢀZUDS
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PLQJꢀZLWKꢀSURJUDPꢒHUDVHꢀDQGꢀVXVSHQGꢀIXQFWLRQDOLW\ꢃꢀ$GGLWLRQDOꢀIHDWXUHVꢀLQFOXGHꢆ
$GYDQFHGꢀ6HFWRUꢀ3URWHFWLRQꢀPHWKRGVꢀIRUꢀSURWHFWLQJꢀVHFWRUVꢀDVꢀUHTXLUHG
ꢏꢊꢎꢀZRUGVꢀRIꢀ6HFXUHGꢀ6LOLFRQꢀDUHDꢀIRUꢀVWRULQJꢀFXVWRPHUꢀDQGꢀIDFWRU\ꢀVHFXUHGꢀLQIRUPDWLRQꢃꢀ7KH
6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀLVꢀ2QHꢀ7LPHꢀ3URJUDPPDEOHꢃ
11.1 Memory Map
7KHꢀ6ꢏꢉ:6ꢏꢊꢎꢒꢇꢏꢋ1ꢀ0ELWꢀGHYLFHVꢀFRQVLVWꢀRIꢀꢇꢎꢀEDQNVꢀRUJDQL]HGꢀDVꢀVKRZQꢀLQꢀ7DEOHꢀꢇꢇꢃꢇ±7DEOH
ꢇꢇꢃꢏꢃ
Table 11.1 S29WS256N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
Notes
6$ꢌꢌꢌ
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ꢀꢌ
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6$ꢌꢌꢑ
ꢌꢌ&ꢌꢌꢌK±ꢌꢌ))))K
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6$ꢌꢌꢍꢀWRꢀ6$ꢌꢇꢋ
6$ꢌꢇꢉꢀWRꢀ6$ꢌꢑꢍ
6$ꢌꢑꢊꢀWRꢀ6$ꢌꢊꢌ
6$ꢌꢊꢇꢀWRꢀ6$ꢌꢎꢎ
6$ꢌꢎꢈꢀWRꢀ6$ꢌꢋꢏ
6$ꢌꢋꢑꢀWRꢀ6$ꢌꢉꢋ
6$ꢌꢉꢉꢀWRꢀ6$ꢇꢇꢍ
6$ꢇꢇꢊꢀWRꢀ6$ꢇꢑꢌ
6$ꢇꢑꢇꢀWRꢀ6$ꢇꢍꢎ
6$ꢇꢍꢈꢀWRꢀ6$ꢇꢎꢏ
6$ꢇꢎꢑꢀWRꢀ6$ꢇꢈꢋ
6$ꢇꢈꢉꢀWRꢀ6$ꢇꢉꢍ
6$ꢇꢉꢊꢀWRꢀ6$ꢏꢇꢌ
6$ꢏꢇꢇꢀWRꢀ6$ꢏꢏꢎ
6$ꢏꢏꢈꢀWRꢀ6$ꢏꢍꢏ
6$ꢏꢍꢑꢀWRꢀ6$ꢏꢊꢈ
6$ꢏꢊꢋ
ꢌꢇꢌꢌꢌꢌK±ꢌꢇ))))KꢀWRꢀꢌ)ꢌꢌꢌꢌK±ꢌ)))))K
ꢇꢌꢌꢌꢌꢌK±ꢇꢌ))))KꢀWRꢀꢇ)ꢌꢌꢌꢌK±ꢇ)))))K
ꢏꢌꢌꢌꢌꢌK±ꢏꢌ))))KꢀWRꢀꢏ)ꢌꢌꢌꢌK±ꢏ)))))K
ꢑꢌꢌꢌꢌꢌK±ꢑꢌ))))KꢀWRꢀꢑ)ꢌꢌꢌꢌK±ꢑ)))))K
ꢍꢌꢌꢌꢌꢌK±ꢍꢌ))))KꢀWRꢀꢍ)ꢌꢌꢌꢌK±ꢍ)))))K
ꢊꢌꢌꢌꢌꢌK±ꢊꢌ))))KꢀWRꢀꢊ)ꢌꢌꢌꢌK±ꢊ)))))K
ꢎꢌꢌꢌꢌꢌK±ꢎꢌ))))KꢀWRꢀꢎ)ꢌꢌꢌꢌK±ꢎ)))))K
ꢈꢌꢌꢌꢌꢌK±ꢈꢌ))))KꢀWRꢀꢈ)ꢌꢌꢌꢌK±ꢈ)))))K
ꢋꢌꢌꢌꢌꢌK±ꢋꢌ))))KꢀWRꢀꢋ)ꢌꢌꢌꢌK±ꢋ)))))K
ꢉꢌꢌꢌꢌꢌK±ꢉꢌ))))KꢀWRꢀꢉ)ꢌꢌꢌꢌK±ꢉ)))))K
$ꢌꢌꢌꢌꢌK±$ꢌ))))KꢀWRꢀ$)ꢌꢌꢌꢌK±$)))))K
%ꢌꢌꢌꢌꢌK±%ꢌ))))KꢀWRꢀ%)ꢌꢌꢌꢌK±%)))))K
&ꢌꢌꢌꢌꢌK±&ꢌ))))KꢀWRꢀ&)ꢌꢌꢌꢌK±&)))))K
'ꢌꢌꢌꢌꢌK±'ꢌ))))KꢀWRꢀ')ꢌꢌꢌꢌK±')))))K
(ꢌꢌꢌꢌꢌK±(ꢌ))))KꢀWRꢀ()ꢌꢌꢌꢌK±()))))K
)ꢌꢌꢌꢌꢌK±)ꢌ))))KꢀWRꢀ)(ꢌꢌꢌꢌK±)())))K
))ꢌꢌꢌꢌK±))ꢑ)))K
ꢏꢀ0%
ꢏꢀ0%
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ꢏꢀ0%
ꢏꢀ0%
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ꢏꢀ0%
ꢏꢀ0%
ꢏꢀ0%
ꢏꢀ0%
ꢏꢀ0%
ꢏꢀ0%
ꢏꢀ0%
ꢏꢀ0%
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
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ꢇꢏꢋꢀ
ꢇꢏꢋ
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ꢏ
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ꢎ
$OOꢀꢇꢏꢋꢀ.%ꢀVHFWRUVꢃꢀ
3DWWHUQꢀIRUꢀVHFWRUꢀDGGUHVVꢀUDQJHꢀ
LVꢀ[[ꢌꢌꢌꢌK±[[))))Kꢃ
ꢁVHHꢀQRWHꢂ
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ꢋ
ꢉ
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ꢇꢏ
ꢇꢑ
ꢇꢍ
ꢏꢀ0%
ꢇꢊ
6$ꢏꢊꢉ
))ꢍꢌꢌꢌK±))ꢈ)))K
&RQWDLQVꢀIRXUꢀVPDOOHUꢀVHFWRUVꢀDWꢀ
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6$ꢏꢎꢌ
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6$ꢏꢎꢇ
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WKDWꢂDUHꢂQRWꢂH[SOLFLWO\ꢂOLVWHGꢂꢏVXFKꢂDVꢂ6$ꢈꢈꢉ±6$ꢈꢀꢋꢐꢂKDYHꢂVHFWRUꢂVWDUWLQJꢂDQGꢂHQGLQJꢂDGGUHVVHVꢂWKDWꢂIRUPꢂWKHꢂVDPHꢂSDWWHUQꢂDVꢂDOOꢂRWKHUꢂVHFWRUVꢂ
RIꢂWKDWꢂVL]Hꢁꢂ)RUꢂH[DPSOHꢄꢂDOOꢂꢀꢆꢑꢂ.%ꢂVHFWRUVꢂKDYHꢂWKHꢂSDWWHUQꢂ[[ꢈꢈꢈꢈꢈK±[[))))Kꢁ
26
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 11.2. S29WS128N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
Notes
ꢑꢏ
6$ꢌꢌꢌ
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ꢑꢏ
6$ꢌꢌꢇ
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ERWWRPꢀRIꢀDGGUHVVDEOHꢀPHPRU\ꢃ
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ꢑꢏ
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6$ꢌꢌꢏ
ꢌꢌꢋꢌꢌꢌK±ꢌꢌ%)))K
ꢑꢏ
6$ꢌꢌꢑ
ꢌꢌ&ꢌꢌꢌK±ꢌꢌ))))K
ꢈ
ꢋ
ꢋ
ꢋ
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ꢋ
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ꢋ
ꢋ
ꢋ
ꢋ
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ꢋ
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ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
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ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋꢀ
ꢇꢏꢋ
ꢑꢏ
6$ꢌꢌꢍꢀWRꢀ6$ꢌꢇꢌ
6$ꢌꢇꢇꢀWRꢀ6$ꢌꢇꢋ
6$ꢌꢇꢉꢀWRꢀ6$ꢌꢏꢎ
6$ꢌꢏꢈꢀWRꢀ6$ꢌꢑꢍ
6$ꢌꢑꢊꢀWRꢀ6$ꢌꢍꢏ
6$ꢌꢍꢑꢀWRꢀ6$ꢌꢊꢌ
6$ꢌꢊꢇꢀWRꢀ6$ꢌꢊꢋ
6$ꢌꢊꢉꢀWRꢀ6$ꢌꢎꢎ
6$ꢌꢎꢈꢀWRꢀ6$ꢌꢈꢍ
6$ꢌꢈꢊꢀWRꢀ6$ꢌꢋꢏ
6$ꢌꢋꢑꢀWRꢀ6$ꢌꢉꢌ
6$ꢌꢉꢇꢀWRꢀ6$ꢌꢉꢋ
6$ꢌꢉꢉꢀWRꢀ6$ꢇꢌꢎ
6$ꢇꢌꢈꢀWRꢀ6$ꢇꢇꢍ
6$ꢇꢇꢊꢀWRꢀ6$ꢇꢏꢏ
6$ꢇꢏꢑꢀWRꢀ6$ꢇꢏꢉ
6$ꢇꢑꢌꢀ
ꢌꢇꢌꢌꢌꢌK±ꢌꢇ))))KꢀWRꢀꢌꢈꢌꢌꢌꢌK±ꢌꢈ))))K
ꢌꢋꢌꢌꢌꢌK±ꢌꢋ))))KꢀWRꢀꢌ)ꢌꢌꢌꢌK±ꢌ)))))K
ꢇꢌꢌꢌꢌꢌK±ꢇꢌ))))KꢀWRꢀꢇꢈꢌꢌꢌꢌK±ꢇꢈ))))K
ꢇꢋꢌꢌꢌꢌK±ꢇꢋ))))KꢀWRꢀꢇ)ꢌꢌꢌꢌK±ꢇ)))))K
ꢏꢌꢌꢌꢌꢌK±ꢏꢌ))))KꢀWRꢀꢏꢈꢌꢌꢌꢌK±ꢏꢈ))))K
ꢏꢋꢌꢌꢌꢌK±ꢏꢋ))))KꢀWRꢀꢏ)ꢌꢌꢌꢌK±ꢏ)))))K
ꢑꢌꢌꢌꢌꢌK±ꢑꢌ))))KꢀWRꢀꢑꢈꢌꢌꢌꢌK±ꢑꢈ))))K
ꢑꢋꢌꢌꢌꢌK±ꢑꢋ))))KꢀWRꢀꢑ)ꢌꢌꢌꢌK±ꢑ)))))K
ꢍꢌꢌꢌꢌꢌK±ꢍꢌ))))KꢀWRꢀꢍꢈꢌꢌꢌꢌK±ꢍꢈ))))K
ꢍꢋꢌꢌꢌꢌK±ꢍꢋ))))KꢀWRꢀꢍ)ꢌꢌꢌꢌK±ꢍ)))))K
ꢊꢌꢌꢌꢌꢌK±ꢊꢌ))))KꢀWRꢀꢊꢈꢌꢌꢌꢌK±ꢊꢈ))))K
ꢊꢋꢌꢌꢌꢌK±ꢊꢋ))))KꢀWRꢀꢊ)ꢌꢌꢌꢌK±ꢊ)))))K
ꢎꢌꢌꢌꢌꢌK±ꢎꢌ))))KꢀWRꢀꢎꢈꢌꢌꢌꢌK±ꢎꢈ))))K
ꢎꢋꢌꢌꢌꢌK±ꢎꢋ))))KꢀWRꢀꢎ)ꢌꢌꢌꢌK±ꢎ)))))K
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December 3, 2005 S29WS-N_m0_I0
27
P r e l i m i n a r y
12 Device Operations
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2SHUDWLRQVꢀDUHꢀLQLWLDWHGꢀE\ꢀZULWLQJꢀVSHFLILFꢀFRPPDQGVꢀRUꢀDꢀVHTXHQFHꢀZLWKꢀVSHFLILFꢀDGGUHVVꢀDQG
GDWDꢀSDWWHUQVꢀLQWRꢀWKHꢀFRPPDQGꢀUHJLVWHUVꢀꢁVHHꢀ7DEOHVꢀꢇꢈꢃꢇꢀDQGꢀꢇꢈꢃꢏꢂꢃꢀ7KHꢀFRPPDQGꢀUHJLVWHU
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12.1 Device Operation Table
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Table 12.1 Device Operations
Operation
CE#
/
OE#
/
WE#
Addresses
$GGUꢀ,Q
$GGUꢀ,Q
$GGUꢀ,Q
$GGUꢀ,Qꢀ
;
DQ15–0
'DWDꢀ2XW
'DWDꢀ2XW
,ꢒ2
RESET#
CLK
;
AVD#
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+
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+
;
;
;
;
+,*+ꢀ=
+,*+ꢀ=
;
;
;
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;
;
Burst Read Operations (Synchronous)
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/
/
;
/
+
+
$GGUꢀ,Q
;
;
+
+
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;
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/
;
+
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12.2 Asynchronous Read
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$ꢌꢄꢀZKLOHꢀGULYLQJꢀ$9'ꢔꢀDQGꢀ&(ꢔꢀWRꢀ9,/ꢃꢀ:(ꢔꢀPXVWꢀUHPDLQꢀDWꢀ9,+ꢃꢀ7KHꢀULVLQJꢀHGJHꢀRIꢀ$9'ꢔ
ODWFKHVꢀWKHꢀDGGUHVVꢃꢀ7KHꢀ2(ꢔꢀVLJQDOꢀPXVWꢀEHꢀGULYHQꢀWRꢀ9,/ꢄꢀRQFHꢀ$9'ꢔꢀKDVꢀEHHQꢀGULYHQꢀWRꢀ9,+
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HGJHꢀRIꢀ2(ꢔꢃ
28
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.3 Page Read Mode
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7KHꢀUDQGRPꢀRUꢀLQLWLDOꢀSDJHꢀDFFHVVꢀLVꢀW$&&ꢀRUꢀW&(ꢀDQGꢀVXEVHTXHQWꢀSDJHꢀUHDGꢀDFFHVVHVꢀꢁDVꢀORQJꢀDV
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ꢒ$9'ꢔꢀZKHQꢀSHUIRUPLQJꢀGDWDꢀSROOLQJꢀWRꢀ62ꢀUHDGꢃꢀ
Table 12.2 Word Selection within a Page
:RUG
$ꢄ
ꢌ
$ꢋ
ꢌ
ꢀ:RUGꢀꢌ
ꢀ:RUGꢀꢇ
ꢀ:RUGꢀꢏ
ꢀ:RUGꢀꢑ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢇ
12.4 Synchronous (Burst) Read Mode & Configuration Register
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6LQFHꢀWKHꢀGHYLFHꢀGHIDXOWVꢀWRꢀDV\QFKURQRXVꢀUHDGꢀPRGHꢀDIWHUꢀSRZHUꢅXSꢀRUꢀDꢀKDUGZDUHꢀUHVHWꢄꢀWKH
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December 3, 2005 S29WS-N_m0_I0
29
P r e l i m i n a r y
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ꢇꢏꢃꢍꢃꢍꢄꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢄꢀDQGꢀ7DEOHꢀꢇꢈꢃꢇꢄꢀ 0HPRU\ꢀ$UUD\ꢀ&RPPDQGVꢀIRUꢀIXUWKHUꢀGHWDLOVꢃ
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 12.1. Synchronous/Asynchronous State Diagram
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30
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 12.3 Address Latency (S29WS256N)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢌ
ꢇ
ꢏ
ꢑ
[ꢀZV
'ꢌ
'ꢇ
'ꢏ
'ꢑ
'ꢇ
'ꢏ
'ꢏ
'ꢑ
'ꢑ
'ꢍ
'ꢍ
'ꢍ
'ꢍ
'ꢊ
'ꢊ
'ꢊ
'ꢊ
'ꢎ
'ꢎ
'ꢎ
'ꢎ
'ꢈ
'ꢈ
'ꢈ
'ꢈ
'ꢋ
'ꢋ
'ꢋ
'ꢋ
[ꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
[ꢀZV
'ꢑ
ꢇꢀZV
ꢇꢀZV
[ꢀZV
ꢇꢀZV
Table 12.4 Address Latency (S29WS128N)
:RUG
:DLWꢀ6WDWHV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
&\FOH
ꢌ
ꢇ
ꢏ
ꢑ
'ꢌ
'ꢇ
'ꢏ
'ꢑ
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'ꢏ
'ꢏ
'ꢑ
'ꢑ
'ꢍ
'ꢍ
'ꢍ
'ꢍ
'ꢊ
'ꢊ
'ꢊ
'ꢊ
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'ꢎ
'ꢎ
'ꢎ
'ꢈ
'ꢈ
'ꢈ
'ꢈ
'ꢋ
'ꢋ
'ꢋ
'ꢋ
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
'ꢑ
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
Table 12.5 Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢌ
ꢇ
ꢏ
ꢑ
ꢈꢀZV
'ꢌ
'ꢇ
'ꢏ
'ꢑ
'ꢇ
'ꢏ
'ꢏ
'ꢑ
'ꢑ
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
'ꢍ
'ꢍ
'ꢍ
'ꢍ
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'ꢊ
'ꢊ
'ꢊ
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'ꢎ
'ꢎ
'ꢎ
ꢈꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢈꢀZV
'ꢑ
ꢇꢀZV
ꢇꢀZV
ꢈꢀZV
ꢇꢀZV
Table 12.6 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢌ
ꢇ
ꢏ
ꢑ
ꢀꢎꢀZV
'ꢌ
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'ꢏ
'ꢏ
'ꢑ
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'ꢍ
'ꢍ
'ꢍ
'ꢊ
'ꢊ
'ꢊ
'ꢊ
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'ꢎ
'ꢎ
'ꢎ
'ꢈ
'ꢈ
'ꢈ
'ꢈ
ꢎꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
ꢎꢀZV
'ꢑ
ꢇꢀZV
ꢇꢀZV
ꢎꢀZV
ꢇꢀZV
Table 12.7 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
:RUG
:DLWꢀ6WDWHV
&\FOH
ꢌ
ꢇ
ꢏ
ꢑ
ꢊꢀZV
'ꢌ
'ꢇ
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'ꢊ
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'ꢎ
'ꢎ
'ꢎ
'ꢈ
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'ꢈ
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ꢊꢀZV
ꢇꢀZV
ꢇꢀZV
ꢇꢀZV
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'ꢑ
ꢇꢀZV
ꢇꢀZV
'ꢍ
ꢊꢀZV
ꢇꢀZV
'ꢍ
Table 12.8 Address/Boundary Crossing Latency (S29WS128N)
:RUG
:DLWꢀ6WDWHV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
ꢊꢄꢀꢎꢄꢀꢈꢀZV
&\FOH
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ꢌ
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ꢇꢀZV
December 3, 2005 S29WS-N_m0_I0
31
P r e l i m i n a r y
Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
Read Initial Data
RD = DQ[15:0]
RD = Read Data
Wait X Clocks:
5HIHUꢂWRꢂWKHꢂ/DWHQF\ꢂWDEOHVꢁ
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
Read Next Data
RD = DQ[15:0]
No
Delay X Clocks
Crossing
Boundary?
No
End of Data?
Yes
Yes
Completed
Figure 12.2. Synchronous Read
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32
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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DGGUHVVꢀJURXSꢃꢀ
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Table 12.9 Burst Address Groups
Mode
Group Size
ꢋꢀZRUGV
Group Address Ranges
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EXUVWꢀH[HFXWHVꢀXSꢀWRꢀWKHꢀPD[LPXPꢀPHPRU\ꢀDGGUHVVꢀRIꢀWKHꢀVHOHFWHGꢀQXPEHUꢀRIꢀZRUGVꢃꢀ7KHꢀEXUVW
VWRSVꢀDIWHUꢀꢋꢄꢀꢇꢎꢄꢀRUꢀꢑꢏꢀDGGUHVVHVꢀDQGꢀGRHVꢀQRWꢀZUDSꢀDURXQGꢀWRꢀWKHꢀILUVWꢀDGGUHVVꢀRIꢀWKHꢀVHOHFWHG
JURXSꢃꢀ
)RUꢀH[DPSOHꢄꢀLIꢀWKHꢀVWDUWLQJꢀDGGUHVVꢀLQꢀWKHꢀꢋꢅꢀZRUGꢀPRGHꢀLVꢀꢑ&KꢄꢀWKHꢀDGGUHVVꢀUDQJHꢀWRꢀEHꢀUHDG
ZRXOGꢀEHꢀꢑꢉꢅꢍꢌKꢄꢀDQGꢀWKHꢀEXUVWꢀVHTXHQFHꢀZRXOGꢀEHꢀꢑ&ꢅꢑ'ꢅꢑ(ꢅꢑ)ꢅꢍꢌꢅꢍꢇꢅꢍꢏꢅꢍꢑKꢀLIꢀZUDSꢀDURXQG
LVꢀQRWꢀHQDEOHGꢃꢀ7KHꢀQH[WꢀDGGUHVVꢀWRꢀEHꢀUHDGꢀUHTXLUHVꢀDꢀQHZꢀDGGUHVVꢀDQGꢀ$9'ꢔꢀSXOVHꢃꢀ1RWHꢀWKDW
LQꢀWKLVꢀEXUVWꢀUHDGꢀPRGHꢄꢀWKHꢀDGGUHVVꢀSRLQWHUꢀPD\ꢀFURVVꢀWKHꢀERXQGDU\ꢀWKDWꢀRFFXUVꢀHYHU\ꢀꢇꢏꢋ
ZRUGVꢄꢀZKLFKꢀZLOOꢀLQFXUꢀWKHꢀDGGLWLRQDOꢀERXQGDU\ꢀFURVVLQJꢀZDLWꢀVWDWHꢃ
ꢄꢈꢎꢒꢎꢒ &RQILJXUDWLRQꢀ5HJLVWHU
7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀVHWVꢀYDULRXVꢀRSHUDWLRQDOꢀSDUDPHWHUVꢀDVVRFLDWHGꢀZLWKꢀEXUVWꢀPRGHꢃꢀ8SRQ
SRZHUꢅXSꢀRUꢀKDUGZDUHꢀUHVHWꢄꢀWKHꢀGHYLFHꢀGHIDXOWVꢀWRꢀWKHꢀDV\QFKURQRXVꢀUHDGꢀPRGHꢄꢀDQGꢀWKHꢀFRQꢅ
ILJXUDWLRQꢀUHJLVWHUꢀVHWWLQJVꢀDUHꢀLQꢀWKHLUꢀGHIDXOWꢀVWDWHꢃꢀ7KHꢀKRVWꢀV\VWHPꢀVKRXOGꢀGHWHUPLQHꢀWKH
SURSHUꢀVHWWLQJVꢀIRUꢀWKHꢀHQWLUHꢀFRQILJXUDWLRQꢀUHJLVWHUꢄꢀDQGꢀWKHQꢀH[HFXWHꢀWKHꢀ6HWꢀ&RQILJXUDWLRQꢀ5HJꢅ
LVWHUꢀFRPPDQGꢀVHTXHQFHꢄꢀEHIRUHꢀDWWHPSWLQJꢀEXUVWꢀRSHUDWLRQVꢃꢀ7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀLVꢀQRW
UHVHWꢀDIWHUꢀGHDVVHUWLQJꢀ&(ꢔꢃꢀ7KHꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀFDQꢀDOVRꢀEHꢀUHDGꢀXVLQJꢀDꢀFRPPDQGꢀVHꢅ
TXHQFHꢀꢁVHHꢀ7DEOHꢀꢇꢈꢃꢇꢂꢃꢀ7KHꢀIROORZLQJꢀOLVWꢀGHVFULEHVꢀWKHꢀUHJLVWHUꢀVHWWLQJVꢃꢀ
December 3, 2005 S29WS-N_m0_I0
33
P r e l i m i n a r y
Table 12.10 Configuration Register
&5ꢀ%LW
)XQFWLRQ
6HWWLQJVꢀꢂ%LQDU\ꢃ
6HWꢀ'HYLFHꢀ5HDGꢀ
0RGH
ꢌꢀ ꢀ6\QFKURQRXVꢀ5HDGꢀꢁ%XUVWꢀ0RGHꢂꢀ(QDEOHG
ꢇꢀ ꢀ$V\QFKURQRXVꢀ5HDGꢀ0RGHꢀꢁGHIDXOWꢂꢀ(QDEOHG
&5ꢇꢊ
ꢇꢀ ꢀ6ꢏꢉ:6ꢏꢊꢎ1ꢀDWꢀꢎꢀRUꢀꢈꢀ:DLWꢀ6WDWHꢀVHWWLQJ
ꢌꢀ ꢀ$OOꢀRWKHUV
&5ꢇꢍ
5HVHUYHG
ꢉꢒ 0+]
ꢊꢊ 0K] ꢏꢋ 0+]
6ꢏꢉ:6ꢇꢏꢋ1
6ꢏꢉ:6ꢏꢊꢎ1
6ꢏꢉ:6ꢇꢏꢋ1
6ꢏꢉ:6ꢏꢊꢎ1
6ꢏꢉ:6ꢇꢏꢋ1
ꢌꢇꢇꢀ ꢀ'DWDꢀYDOLGꢀRQꢀꢊWKꢀDFWLYHꢀ&/.ꢀHGJHꢀDIWHUꢀDGGUHVVHVꢀ
&5ꢇꢑ
&5ꢇꢏ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ODWFKHGꢀ
ꢇꢌꢌꢀ ꢀ'DWDꢀYDOLGꢀRQꢀꢎWKꢀDFWLYHꢀ&/.ꢀHGJHꢀDIWHUꢀDGGUHVVHVꢀ
ODWFKHGꢀ
ꢇꢌꢇꢀ ꢀ'DWDꢀYDOLGꢀRQꢀꢈWKꢀDFWLYHꢀ&/.ꢀHGJHꢀDIWHUꢀDGGUHVVHVꢀ
ODWFKHGꢀꢁGHIDXOWꢂ
ꢇꢇꢌꢀ ꢀ5HVHUYHG
ꢇꢇꢇꢀ ꢀ5HVHUYHG
ꢇ
ꢇ
3URJUDPPDEOH
:DLWꢀ6WDWH
,QVHUWVꢀZDLWꢀVWDWHVꢀEHIRUHꢀLQLWLDOꢀGDWDꢀLVꢀDYDLODEOHꢃꢀ6HWWLQJꢀ
JUHDWHUꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀEHIRUHꢀLQLWLDOꢀGDWDꢀUHGXFHVꢀ
ODWHQF\ꢀDIWHUꢀLQLWLDOꢀGDWDꢃ
&5ꢇꢇ
ꢌ
ꢇ
6ꢏꢉ:6ꢏꢊꢎ1
ꢁ1RWHVꢀꢇꢄꢀꢏꢂ
ꢌꢀ ꢀ5'<ꢀVLJQDOꢀDFWLYHꢀORZ
&5ꢇꢌ
&5ꢉ
5'<ꢀ3RODULW\
5HVHUYHG
ꢇꢀ ꢀ5'<ꢀVLJQDOꢀDFWLYHꢀKLJKꢀꢁGHIDXOWꢂ
ꢇꢀ ꢀGHIDXOW
ꢌꢀ ꢀ5'<ꢀDFWLYHꢀRQHꢀFORFNꢀF\FOHꢀEHIRUHꢀGDWD
ꢇꢀ ꢀ5'<ꢀDFWLYHꢀZLWKꢀGDWDꢀꢁGHIDXOWꢂ
:KHQꢀ&5ꢇꢑꢅ&5ꢇꢇꢀDUHꢀVHWꢀWRꢀꢌꢌꢌꢄꢀ5'<ꢀLVꢀDFWLYHꢀZLWKꢀGDWDꢀ
UHJDUGOHVVꢀRIꢀ&5ꢋꢀVHWWLQJꢃ
&5ꢋ
5'<
&5ꢈ
&5ꢎ
&5ꢊ
&5ꢍ
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
ꢇꢀ ꢀGHIDXOW
ꢇꢀ ꢀGHIDXOW
ꢌꢀ ꢀGHIDXOW
ꢌꢀ ꢀGHIDXOW
ꢌꢀ ꢀ1Rꢀ:UDSꢀ$URXQGꢀ%XUVWꢀ
ꢇꢀ ꢀ:UDSꢀ$URXQGꢀ%XUVWꢀꢁGHIDXOWꢂ
,JQRUHGꢀLIꢀLQꢀFRQWLQXRXVꢀPRGH
&5ꢑ
%XUVWꢀ:UDSꢀ$URXQG
ꢌꢌꢌꢀ ꢀ&RQWLQXRXVꢀꢁGHIDXOWꢂ
ꢌꢇꢌꢀ ꢀꢋꢅ:RUGꢀ/LQHDUꢀ%XUVW
ꢌꢇꢇꢀ ꢀꢇꢎꢅ:RUGꢀ/LQHDUꢀ%XUVW
ꢇꢌꢌꢀ ꢀꢑꢏꢅ:RUGꢀ/LQHDUꢀ%XUVW
ꢁ$OOꢀRWKHUꢀELWꢀVHWWLQJVꢀDUHꢀUHVHUYHGꢂ
&5ꢏ
&5ꢇ
&5ꢌ
%XUVWꢀ/HQJWK
Ir)
ꢀꢁ 5HIHUꢂWRꢂ7DEOHVꢂꢀꢆꢁꢊꢂꢃꢂꢀꢆꢁꢑꢂIRUꢂZDLWꢂVWDWHVꢂUHTXLUHPHQWVꢁ
ꢆꢁ 5HIHUꢂWRꢂ6\QFKURQRXVꢂ%XUVWꢂ5HDGꢂWLPLQJꢂGLDJUDPV
ꢊꢁ &RQILJXUDWLRQꢂ5HJLVWHUꢂLVꢂLQꢂWKHꢂGHIDXOWꢂVWDWHꢂXSRQꢂSRZHUꢃXSꢂRUꢂKDUGZDUHꢂUHVHWꢁ
5HDGLQJꢂWKHꢂ&RQILJXUDWLRQꢂ7DEOHꢁꢂ7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀFDQꢀEHꢀUHDGꢀZLWKꢀDꢀIRXUꢅF\FOHꢀFRPꢅ
PDQGꢀVHTXHQFHꢃꢀ6HHꢀ7DEOHꢀꢇꢈꢃꢇꢀIRUꢀVHTXHQFHꢀGHWDLOVꢃꢀ$ꢀVRIWZDUHꢀUHVHWꢀFRPPDQGꢀLVꢀUHTXLUHGꢀDIWHU
UHDGLQJꢀRUꢀVHWWLQJꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀWRꢀVHWꢀWKHꢀGHYLFHꢀLQWRꢀWKHꢀFRUUHFWꢀVWDWHꢃ
34
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.5 Autoselect
7KHꢀ$XWRVHOHFWꢀLVꢀXVHGꢀIRUꢀPDQXIDFWXUHUꢀ,'ꢄꢀ'HYLFHꢀLGHQWLILFDWLRQꢄꢀDQGꢀVHFWRUꢀSURWHFWLRQꢀLQIRUPDꢅ
WLRQꢃꢀ7KLVꢀPRGHꢀLVꢀSULPDULO\ꢀLQWHQGHGꢀIRUꢀSURJUDPPLQJꢀHTXLSPHQWꢀWRꢀDXWRPDWLFDOO\ꢀPDWFKꢀD
GHYLFHꢀZLWKꢀLWVꢀFRUUHVSRQGLQJꢀSURJUDPPLQJꢀDOJRULWKPꢃꢀ7KHꢀ$XWRVHOHFWꢀFRGHVꢀFDQꢀDOVRꢀEHꢀDFꢅ
FHVVHGꢀLQꢅV\VWHPꢃꢀ:KHQꢀYHULI\LQJꢀVHFWRUꢀSURWHFWLRQꢄꢀWKHꢀVHFWRUꢀDGGUHVVꢀPXVWꢀDSSHDUꢀRQꢀWKH
DSSURSULDWHꢀKLJKHVWꢀRUGHUꢀDGGUHVVꢀELWVꢀꢁVHHꢀ7DEOHꢀꢇꢏꢃꢇꢇꢂꢃꢀ7KHꢀUHPDLQLQJꢀDGGUHVVꢀELWVꢀDUHꢀGRQꢗW
FDUHꢃꢀ7KHꢀPRVWꢀVLJQLILFDQWꢀIRXUꢀELWVꢀRIꢀWKHꢀDGGUHVVꢀGXULQJꢀWKHꢀWKLUGꢀZULWHꢀF\FOHꢀVHOHFWVꢀWKHꢀEDQN
IURPꢀZKLFKꢀWKHꢀ$XWRVHOHFWꢀFRGHVꢀDUHꢀUHDGꢀE\ꢀWKHꢀKRVWꢃꢀ$OOꢀRWKHUꢀEDQNVꢀFDQꢀEHꢀDFFHVVHGꢀQRUPDOO\
IRUꢀGDWDꢀUHDGꢀZLWKRXWꢀH[LWLQJꢀWKHꢀ$XWRVHOHFWꢀPRGHꢃꢀ
7RꢀDFFHVVꢀWKHꢀ$XWRVHOHFWꢀFRGHVꢄꢀWKHꢀKRVWꢀV\VWHPꢀPXVWꢀLVVXHꢀWKHꢀ$XWRVHOHFWꢀFRPPDQGꢃ
7KHꢀ$XWRVHOHFWꢀFRPPDQGꢀVHTXHQFHꢀPD\ꢀEHꢀZULWWHQꢀWRꢀDQꢀDGGUHVVꢀZLWKLQꢀDꢀEDQNꢀWKDWꢀLVꢀHLWKHU
LQꢀWKHꢀUHDGꢀRUꢀHUDVHꢅVXVSHQGꢅUHDGꢀPRGHꢃꢀ
7KHꢀ$XWRVHOHFWꢀFRPPDQGꢀPD\ꢀQRWꢀEHꢀZULWWHQꢀZKLOHꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀSURJUDPPLQJꢀRU
HUDVLQJꢃꢀ$XWRVHOHFWꢀGRHVꢀQRWꢀVXSSRUWꢀVLPXOWDQHRXVꢀRSHUDWLRQVꢀRUꢀEXUVWꢀPRGHꢃꢀ
7KHꢀV\VWHPꢀPXVWꢀZULWHꢀWKHꢀUHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀWRꢀWKHꢀUHDGꢀPRGHꢀꢁRUꢀHUDVHꢅVXVSHQGꢅ
UHDGꢀPRGHꢀLIꢀWKHꢀEDQNꢀZDVꢀSUHYLRXVO\ꢀLQꢀ(UDVHꢀ6XVSHQGꢂꢃꢀ
6HHꢀ7DEOHꢀꢇꢈꢃꢇꢀIRUꢀFRPPDQGꢀVHTXHQFHꢀGHWDLOVꢃ
Table 12.11 Autoselect Addresses
Description
0DQXIDFWXUHUꢀ,'
'HYLFHꢀ,'ꢄꢀ:RUGꢀꢇ
Address
Read Data
ꢁ%$ꢂꢀꢐꢀꢌꢌK ꢌꢌꢌꢇK
ꢁ%$ꢂꢀꢐꢀꢌꢇK ꢏꢏꢈ(K
ꢏꢏꢑꢌꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢏꢏꢑꢇꢀꢁ:6ꢇꢏꢋ1ꢂ
ꢁ%$ꢂꢀꢐꢀꢌ)K ꢏꢏꢌꢌ
'4ꢇꢊꢀꢅꢀ'4ꢋꢀ ꢀ5HVHUYHG
'HYLFHꢀ,'ꢄꢀ:RUGꢀꢏ
'HYLFHꢀ,'ꢄꢀ:RUGꢀꢑ
ꢁ%$ꢂꢀꢐꢀꢌ(K
'4ꢈꢀꢁ)DFWRU\ꢀ/RFNꢀ%LWꢂꢆꢀꢇꢀ ꢀ/RFNHGꢄꢀꢌꢀ ꢀ1RWꢀ/RFNHG
'4ꢎꢀꢁ&XVWRPHUꢀ/RFNꢀ%LWꢂꢆꢀꢇꢀ ꢀ/RFNHGꢄꢀꢌꢀ ꢀ1RWꢀ/RFNHG
'4ꢊꢀꢁ+DQGVKDNHꢀ%LWꢂꢆꢀꢇꢀ ꢀ5HVHUYHGꢄꢀꢌꢀ ꢀ6WDQGDUGꢀ+DQGVKDNH
'4ꢍꢄꢀ'4ꢑꢀꢁ:3ꢔꢀ3URWHFWLRQꢀ%RRWꢀ&RGHꢂꢆꢀꢌꢌꢀ ꢀ:3ꢔꢀ3URWHFWVꢀERWKꢀ7RSꢀ%RRWꢀDQGꢀ
%RWWRPꢀ%RRWꢀ6HFWRUVꢃꢀꢌꢇꢄꢀꢇꢌꢄꢀꢇꢇꢀ ꢀ5HVHUYHG
,QGLFDWRUꢀ%LWVꢀ
ꢁ6HHꢀ1RWHꢂ
ꢁ%$ꢂꢀꢐꢀꢌꢑK
'4ꢏꢀ ꢀ5HVHUYHG
'4ꢇꢀꢁ'<%ꢀ3RZHUꢀXSꢀ6WDWHꢀ>/RFNꢀ5HJLVWHUꢀ'4ꢍ@ꢂꢆꢀꢇꢀ ꢀ8QORFNHGꢀꢁXVHUꢀRSWLRQꢂꢄꢀ
ꢌꢀ ꢀ/RFNHGꢀꢁGHIDXOWꢂ
'4ꢌꢀꢁ33%ꢀ(UDVHDELOLW\ꢀ>/RFNꢀ5HJLVWHUꢀ'4ꢑ@ꢂꢆꢀꢇꢀ ꢀ(UDVHꢀDOORZHGꢄꢀ
ꢌꢀ ꢀ(UDVHꢀGLVDEOHG
6HFWRUꢀ%ORFNꢀ/RFNꢒ
8QORFNꢀ
ꢁ6$ꢂꢀꢐꢀꢌꢏK ꢌꢌꢌꢇKꢀ ꢀ/RFNHGꢄꢀꢌꢌꢌꢌKꢀ ꢀ8QORFNHG
Ir)ꢂ)RUꢂ:6ꢀꢆꢑ1ꢂDQGꢂ:6ꢈꢌꢎꢄꢂ'4ꢀꢂDQGꢂ'4ꢈꢂDUHꢂUHVHUYHGꢁ
December 3, 2005 S29WS-N_m0_I0
35
P r e l i m i n a r y
Software Functions and Sample Code
Table 12.12 Autoselect Entry
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB$XWRVHOHFW(QWU\&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%$[$$$K
%$[ꢊꢊꢊK
Word Address
%$[ꢊꢊꢊK
Data
8QORFNꢀ&\FOHꢀꢇ
8QORFNꢀ&\FOHꢀꢏ
$XWRVHOHFWꢀ&RPPDQG
ꢌ[ꢌꢌ$$K
ꢌ[ꢌꢌꢊꢊK
ꢌ[ꢌꢌꢉꢌK
:ULWH
%$[ꢏ$$K
:ULWH
%$[$$$K
%$[ꢊꢊꢊK
Table 12.13 Autoselect Exit
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB$XWRVHOHFW([LW&PGꢂ
Cycle
Operation
:ULWH
Byte Address
Word Address
EDVHꢀꢐꢀ;;;K
Data
8QORFNꢀ&\FOHꢀꢇ
EDVHꢀꢐꢀ;;;K
ꢌ[ꢌꢌ)ꢌK
Ir)
ꢀꢁ $Q\ꢂRIIVHWꢂZLWKLQꢂWKHꢂGHYLFHꢂZRUNVꢁ
ꢆꢁ %$ꢂ ꢂ%DQNꢂ$GGUHVVꢁꢂ7KHꢂEDQNꢂDGGUHVVꢂLVꢂUHTXLUHGꢁ
ꢊꢁ EDVHꢂ ꢂEDVHꢂDGGUHVVꢁ
7KHꢀIROORZLQJꢀLVꢀDꢀ&ꢀVRXUFHꢀFRGHꢀH[DPSOHꢀRIꢀXVLQJꢀWKHꢀDXWRVHOHFWꢀIXQFWLRQꢀWRꢀUHDGꢀWKHꢀPDQXIDFꢅ
WXUHUꢀ,'ꢃꢀ5HIHUꢀWRꢀWKHꢀ6SDQVLRQꢂ/RZꢂ/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQG
ZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDOꢀLQIRUPDWLRQꢀRQꢀ6SDQVLRQꢀ)ODVKꢀPHPRU\ꢀVRIWZDUHꢀGHYHORSPHQW
JXLGHOLQHVꢃ
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
36
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.6 Program/Erase Operations
7KHVHꢀGHYLFHVꢀDUHꢀFDSDEOHꢀRIꢀVHYHUDOꢀPRGHVꢀRIꢀSURJUDPPLQJꢀDQGꢀRUꢀHUDVHꢀRSHUDWLRQVꢀZKLFKꢀDUH
GHVFULEHGꢀLQꢀGHWDLOꢀLQꢀWKHꢀIROORZLQJꢀVHFWLRQVꢃꢀ+RZHYHUꢄꢀSULRUꢀWRꢀDQ\ꢀSURJUDPPLQJꢀDQGꢀRUꢀHUDVH
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 12.3. Single Word Program
38
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Software Functions and Sample Code
Table 12.14. Single Word Program
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
:RUGꢀ$GGUHVV
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
:RUGꢀ$GGUHVV
Data
ꢌꢌ$$K
8QORFNꢀ&\FOHꢀꢇ
8QORFNꢀ&\FOHꢀꢏ
3URJUDPꢀ6HWXS
:ULWH
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:ULWH
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Ir)ꢂ%DVHꢂ ꢂ%DVHꢂ$GGUHVVꢁ
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/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
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S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Software Functions and Sample Code
Table 12.15. Write Buffer Program
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Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
Data
ꢌꢌ$$K
ꢇ
ꢏ
ꢑ
ꢍ
8QORFN
:ULWH
ꢌꢌꢊꢊK
:ULWHꢀ%XIIHUꢀ/RDGꢀ&RPPDQG
:ULWHꢀ:RUGꢀ&RXQW
:ULWH
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3URJUDPꢀ$GGUHVV
ꢌꢌꢏꢊK
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ꢊꢀWRꢀꢑꢎ
/DVW
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:ULWHꢀ%XIIHUꢀWRꢀ)ODVK
:ULWH
:ULWH
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6HFWRUꢀ$GGUHVV
:RUGꢀ1
ꢌꢌꢏꢉK
Ir)
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/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
UINT16 wc
= words_to_program -1;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
wc--;
goto loop;
/* done when word count equals zero */
/* decrement word count
/* do it again
*/
*/
confirm:
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
December 3, 2005 S29WS-N_m0_I0
41
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA = 0x29h
Wait 4 µs
(Recommended)
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write Buffer
Abort?
Yes
Polling Status
= Done?
No
No
Error?
Yes
FAIL. Issue reset command
to return to read array mode.
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
Figure 12.4. Write Buffer Programming Operation
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Software Functions and Sample Code
Table 12.16. Sector Erase
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Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
6HFWRUꢀ$GGUHVV
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
6HFWRUꢀ$GGUHVV
Data
ꢇ
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢋꢌK
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢑꢌK
8QORFN
:ULWH
6HWXSꢀ&RPPDQG
8QORFN
:ULWH
:ULWH
8QORFN
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/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
December 3, 2005 S29WS-N_m0_I0
43
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
(Recommended)
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
ꢁVHHꢀ)LJXUHꢀꢇꢏꢃꢎꢂ
Yes
Done?
No
No
Error condition (Exceeded Timing Limits)
DQ5 = 1?
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Ir)
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Figure 12.5. Sector Erase Operation
44
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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Software Functions and Sample Code
Table 12.17. Chip Erase
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB&KLS(UDVH&PGꢂ
Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
Data
ꢇ
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢋꢌK
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢇꢌK
8QORFN
:ULWH
6HWXSꢀ&RPPDQG
8QORFN
:ULWH
:ULWH
8QORFN
:ULWH
&KLSꢀ(UDVHꢀ&RPPDQG
:ULWH
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/RZꢂ/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDOꢀLQꢅ
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/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
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December 3, 2005 S29WS-N_m0_I0
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Software Functions and Sample Code
Table 12.18. Erase Suspend
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB(UDVH6XVSHQG&PGꢂ
Cycle
Operation
Byte Address
Word Address
Data
ꢇ
:ULWH
%DQNꢀ$GGUHVV
%DQNꢀ$GGUHVV
ꢌꢌ%ꢌK
7KHꢀIROORZLQJꢀLVꢀDꢀ&ꢀVRXUFHꢀFRGHꢀH[DPSOHꢀRIꢀXVLQJꢀWKHꢀHUDVHꢀVXVSHQGꢀIXQFWLRQꢃꢀ5HIHUꢀWRꢀWKHꢀ6SDQꢃ
VLRQꢂ/RZꢂ/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDO
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/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 12.19. Erase Resume
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB(UDVH5HVXPH&PGꢂ
Cycle
Operation
Byte Address
Word Address
%DQNꢀ$GGUHVV
Data
ꢇ
:ULWH
%DQNꢀ$GGUHVV
ꢌꢌꢑꢌK
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VLRQꢂ/RZꢂ/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDO
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/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
46
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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Software Functions and Sample Code
Table 12.20. Program Suspend
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP6XVSHQG&PGꢂ
Cycle
Operation
Byte Address
Word Address
Data
ꢇ
:ULWH
%DQNꢀ$GGUHVV
%DQNꢀ$GGUHVV
ꢌꢌ%ꢌK
7KHꢀIROORZLQJꢀLVꢀDꢀ&ꢀVRXUFHꢀFRGHꢀH[DPSOHꢀRIꢀXVLQJꢀWKHꢀSURJUDPꢀVXVSHQGꢀIXQFWLRQꢃꢀ5HIHUꢀWRꢀWKH
6SDQVLRQꢂ/RZꢂ/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRU
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/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 12.21. Program Resume
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP5HVXPH&PGꢂ
Cycle
Operation
Byte Address
Word Address
%DQNꢀ$GGUHVV
Data
ꢇ
:ULWH
%DQNꢀ$GGUHVV
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6SDQVLRQꢂ/RZꢂ/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRU
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/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
December 3, 2005 S29WS-N_m0_I0
47
P r e l i m i n a r y
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Software Functions and Sample Code
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Table 12.22. Unlock Bypass Entry
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Cycle
Description
8QORFN
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
Data
ꢇ
ꢏ
ꢑ
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢏꢌK
8QORFN
:ULWH
(QWU\ꢀ&RPPDQG
:ULWH
48
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
/* Example: Unlock Bypass Entry Command
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
*/
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
Table 12.23. Unlock Bypass Program
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB8QORFN%\SDVV3URJUDP&PGꢂ
Cycle
Description
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ[[[K
Word Address
%DVHꢀꢐ[[[K
Data
ꢇ
ꢏ
3URJUDPꢀ6HWXSꢀ&RPPDQG
3URJUDPꢀ&RPPDQG
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3URJUDPꢀ$GGUHVV
3URJUDPꢀ'DWD
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Table 12.24. Unlock Bypass Reset
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB8QORFN%\SDVV5HVHW&PGꢂ
Cycle
Description
5HVHWꢀ&\FOHꢀꢇ
5HVHWꢀ&\FOHꢀꢏ
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ[[[K
%DVHꢀꢐꢀ[[[K
Word Address
%DVHꢀꢐ[[[K
%DVHꢀꢐ[[[K
Data
ꢇ
ꢏ
ꢌꢌꢉꢌK
ꢌꢌꢌꢌK
:ULWH
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
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50
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 12.6. Write Operation Status Flowchart
December 3, 2005 S29WS-N_m0_I0
51
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52
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 12.25. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
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SHULRGꢀLVꢀFRPSOHWHꢄꢀ'4ꢑꢀVZLWFKHVꢀIURPꢀDꢀ³ꢌ´ꢀWRꢀDꢀ³ꢇꢃ´ꢀ,IꢀWKHꢀWLPHꢀEHWZHHQꢀDGGLWLRQDOꢀVHFWRUꢀHUDVH
FRPPDQGVꢀIURPꢀWKHꢀV\VWHPꢀFDQꢀEHꢀDVVXPHGꢀWRꢀEHꢀOHVVꢀWKDQꢀW6($ꢄꢀWKHꢀV\VWHPꢀQHHGꢀQRWꢀPRQLWRU
'4ꢑꢃꢀ6HHꢀ6HFWRUꢀ(UDVHꢀ&RPPDQGꢀ6HTXHQFHꢀIRUꢀPRUHꢀGHWDLOVꢃꢀ
$IWHUꢀWKHꢀVHFWRUꢀHUDVHꢀFRPPDQGꢀLVꢀZULWWHQꢄꢀWKHꢀV\VWHPꢀVKRXOGꢀUHDGꢀWKHꢀVWDWXVꢀRIꢀ'4ꢈꢀꢁ'DWDꢔ
3ROOLQJꢂꢀRUꢀ'4ꢎꢀꢁ7RJJOHꢀ%LWꢀ,ꢂꢀWRꢀHQVXUHꢀWKDWꢀWKHꢀGHYLFHꢀKDVꢀDFFHSWHGꢀWKHꢀFRPPDQGꢀVHTXHQFHꢄ
DQGꢀWKHQꢀUHDGꢀ'4ꢑꢃꢀ,Iꢀ'4ꢑꢀLVꢀ³ꢇꢄ´ꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀKDVꢀEHJXQꢕꢀDOOꢀIXUWKHUꢀFRPꢅ
PDQGVꢀꢁH[FHSWꢀ(UDVHꢀ6XVSHQGꢂꢀDUHꢀLJQRUHGꢀXQWLOꢀWKHꢀHUDVHꢀRSHUDWLRQꢀLVꢀFRPSOHWHꢃꢀ,Iꢀ'4ꢑꢀLVꢀ³ꢌꢄ´
WKHꢀGHYLFHꢀDFFHSWVꢀDGGLWLRQDOꢀVHFWRUꢀHUDVHꢀFRPPDQGVꢃꢀ7RꢀHQVXUHꢀWKHꢀFRPPDQGꢀKDVꢀEHHQꢀDFꢅ
FHSWHGꢄꢀWKHꢀV\VWHPꢀVRIWZDUHꢀVKRXOGꢀFKHFNꢀWKHꢀVWDWXVꢀRIꢀ'4ꢑꢀSULRUꢀWRꢀDQGꢀIROORZLQJꢀHDFKꢀVXEꢅ
VHTXHQWꢀVHFWRUꢀHUDVHꢀFRPPDQGꢃꢀ,Iꢀ'4ꢑꢀLVꢀKLJKꢀRQꢀWKHꢀVHFRQGꢀVWDWXVꢀFKHFNꢄꢀWKHꢀODVWꢀFRPPDQG
PLJKWꢀQRWꢀKDYHꢀEHHQꢀDFFHSWHGꢃꢀ7DEOHꢀꢇꢏꢃꢏꢎꢀVKRZVꢀWKHꢀVWDWXVꢀRIꢀ'4ꢑꢀUHODWLYHꢀWRꢀWKHꢀRWKHUꢀVWDWXV
ELWVꢃ
9R )ꢀXꢄvrꢀꢀ7ssrꢄꢀ6iꢄꢂꢀ'4ꢇꢀLQGLFDWHVꢀZKHWKHUꢀDꢀ:ULWHꢀWRꢀ%XIIHUꢀRSHUDWLRQꢀZDVꢀDERUWHGꢃ
8QGHUꢀWKHVHꢀFRQGLWLRQVꢀ'4ꢇꢀSURGXFHVꢀDꢀ³ꢇ´ꢃꢀ7KHꢀV\VWHPꢀPXVWꢀLVVXHꢀWKHꢀ:ULWHꢀWRꢀ%XIIHUꢀ$ERUW
5HVHWꢀFRPPDQGꢀVHTXHQFHꢀWRꢀUHWXUQꢀWKHꢀGHYLFHꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢃꢀ6HHꢀ:ULWHꢀ%XIIHUꢀ3URJUDPꢅ
PLQJꢀ2SHUDWLRQꢀIRUꢀPRUHꢀGHWDLOVꢃ
54
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 12.26. Write Operation Status
DQ7
DQ5
DQ2
DQ1
Status
(Note 2)
DQ6
7RJJOH
7RJJOH
,19$/,'
(Note 1)
DQ3
1ꢒ$
(Note 2)
(Note 4)
(PEHGGHGꢀ3URJUDPꢀ$OJRULWKP
(PEHGGHGꢀ(UDVHꢀ$OJRULWKP
'4ꢈꢔ
ꢌ
ꢌ
ꢌ
1RꢀWRJJOH
7RJJOH
ꢌ
6WDQGDUGꢀ
0RGH
ꢇ
1ꢒ$
,19$/,'
,19$/,'
,19$/,'
,19$/,'
,19$/,'
3URJUDPꢀ
6XVSHQGꢀ
0RGHꢀ
5HDGLQJꢀZLWKLQꢀ3URJUDPꢀ6XVSHQGHGꢀ6HFWRU
ꢏ1RWꢂ
$OORZHGꢐ
ꢏ1RWꢂ
$OORZHGꢐ
ꢏ1RWꢂ
$OORZHGꢐ
ꢏ1RWꢂ
$OORZHGꢐ
ꢏ1RWꢂ
$OORZHGꢐ
ꢏ1RWꢂ
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6HFWRU
ꢁ1RWHꢀꢑꢂ
'DWD
ꢇ
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'DWD
'DWD
ꢌ
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1ꢒ$
'DWD
7RJJOH
'DWD
'DWD
1ꢒ$
(UDVHꢀ
6XVSHQGHGꢀ6HFWRU
(UDVHꢀ
6XVSHQGꢀ
0RGH
(UDVHꢅ6XVSHQGꢅ
5HDGꢀ
1RQꢅ(UDVHꢀ6XVSHQGHGꢀ
'DWD
'DWD
'DWD
'DWD
6HFWRU
(UDVHꢅ6XVSHQGꢅ3URJUDP
%86<ꢀ6WDWH
ꢁ1RWHꢀꢎꢂ
'4ꢈꢔ
'4ꢈꢔ
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7RJJOH
7RJJOH
7RJJOH
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1ꢒ$
1ꢒ$
1ꢒ$
1ꢒ$
1ꢒ$
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1ꢒ$
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:ULWHꢀWRꢀ
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ꢁ1RWHꢀꢊꢂ
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$%257ꢀ6WDWH
ꢌ
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Ir)
ꢀꢁ '4ꢉꢂVZLWFKHVꢂWRꢂµꢀ¶ꢂZKHQꢂDQꢂ(PEHGGHGꢂ3URJUDPꢂRUꢂ(PEHGGHGꢂ(UDVHꢂRSHUDWLRQꢂKDVꢂH[FHHGHGꢂWKHꢂPD[LPXPꢂWLPLQJꢂOLPLWVꢁꢂ5HIHUꢂWRꢂWKHꢂ
VHFWLRQꢂRQꢂ'4ꢉꢂIRUꢂPRUHꢂLQIRUPDWLRQꢁ
ꢆꢁ '4ꢋꢂDQGꢂ'4ꢆꢂUHTXLUHꢂDꢂYDOLGꢂDGGUHVVꢂZKHQꢂUHDGLQJꢂVWDWXVꢂLQIRUPDWLRQꢁꢂ5HIHUꢂWRꢂWKHꢂDSSURSULDWHꢂVXEVHFWLRQꢂIRUꢂIXUWKHUꢂGHWDLOVꢁ
ꢊꢁ 'DWDꢂDUHꢂLQYDOLGꢂIRUꢂDGGUHVVHVꢂLQꢂDꢂ3URJUDPꢂ6XVSHQGHGꢂVHFWRUꢁ
ꢎꢁ '4ꢀꢂLQGLFDWHVꢂWKHꢂ:ULWHꢂWRꢂ%XIIHUꢂ$%257ꢂVWDWXVꢂGXULQJꢂ:ULWHꢂ%XIIHUꢂ3URJUDPPLQJꢂRSHUDWLRQVꢁ
ꢉꢁ 7KHꢂGDWDꢃEDUꢂSROOLQJꢂDOJRULWKPꢂVKRXOGꢂEHꢂXVHGꢂIRUꢂ:ULWHꢂ%XIIHUꢂ3URJUDPPLQJꢂRSHUDWLRQVꢁꢂ1RWHꢂWKDWꢂ'4ꢋꢅꢂGXULQJꢂ:ULWHꢂ%XIIHUꢂ3URJUDPPLQJꢂ
LQGLFDWHVꢂWKHꢂGDWDꢃEDUꢂIRUꢂ'4ꢋꢂGDWDꢂsꢄꢀurꢀG6TUꢀGP69@9ꢀXSDU@ꢅ7VAA@Sꢀ699S@TTꢀyphvꢁ
ꢌꢁ )RUꢂDQ\ꢂDGGUHVVꢂFKDQJHVꢂDIWHUꢂ&(ꢅꢂDVVHUWLRQꢄꢂUHꢃDVVHUWLRQꢂRIꢂ&(ꢅꢂPLJKWꢂEHꢂUHTXLUHGꢂDIWHUꢂWKHꢂDGGUHVVHVꢂEHFRPHꢂVWDEOHꢂIRUꢂGDWDꢂSROOLQJꢂ
GXULQJꢂWKHꢂHUDVHꢂVXVSHQGꢂRSHUDWLRQꢂXVLQJꢂ'4ꢆꢍ'4ꢌꢁ
December 3, 2005 S29WS-N_m0_I0
55
P r e l i m i n a r y
12.7 Simultaneous Read/Write
7KHꢀVLPXOWDQHRXVꢀUHDGꢒZULWHꢀIHDWXUHꢀDOORZVꢀWKHꢀKRVWꢀV\VWHPꢀWRꢀUHDGꢀGDWDꢀIURPꢀRQHꢀEDQNꢀRIꢀPHPꢅ
RU\ꢀZKLOHꢀSURJUDPPLQJꢀRUꢀHUDVLQJꢀDQRWKHUꢀEDQNꢀRIꢀPHPRU\ꢃꢀ$QꢀHUDVHꢀRSHUDWLRQꢀPD\ꢀDOVRꢀEH
VXVSHQGHGꢀWRꢀUHDGꢀIURPꢀRUꢀSURJUDPꢀDQRWKHUꢀORFDWLRQꢀZLWKLQꢀWKHꢀVDPHꢀEDQNꢀꢁH[FHSWꢀWKHꢀVHFWRU
EHLQJꢀHUDVHGꢂꢃꢀ)LJXUHꢀꢇꢎꢃꢏꢉꢄꢀ%DFNꢅWRꢅ%DFNꢀ5HDGꢒ:ULWHꢀ&\FOHꢀ7LPLQJVꢄꢀVKRZVꢀKRZꢀUHDGꢀDQGꢀZULWH
F\FOHVꢀPD\ꢀEHꢀLQLWLDWHGꢀIRUꢀVLPXOWDQHRXVꢀRSHUDWLRQꢀZLWKꢀ]HURꢀODWHQF\ꢃꢀ5HIHUꢀWRꢀWKHꢀ'&ꢀ&KDUDFWHUꢅ
LVWLFVꢀꢁ&026ꢀ&RPSDWLEOHꢂꢀWDEOHꢀIRUꢀUHDGꢅZKLOHꢅSURJUDPꢀDQGꢀUHDGꢅZKLOHꢅHUDVHꢀFXUUHQW
VSHFLILFDWLRQꢃ
12.8 Writing Commands/Command Sequences
:KHQꢀWKHꢀGHYLFHꢀLVꢀFRQILJXUHGꢀIRUꢀ$V\QFKURQRXVꢀUHDGꢄꢀRQO\ꢀ$V\QFKURQRXVꢀZULWHꢀRSHUDWLRQVꢀDUH
DOORZHGꢄꢀDQGꢀ&/.ꢀLVꢀLJQRUHGꢃꢀ:KHQꢀLQꢀWKHꢀ6\QFKURQRXVꢀUHDGꢀPRGHꢀFRQILJXUDWLRQꢄꢀWKHꢀGHYLFHꢀLV
DEOHꢀWRꢀSHUIRUPꢀERWKꢀ$V\QFKURQRXVꢀDQGꢀ6\QFKURQRXVꢀZULWHꢀRSHUDWLRQVꢃꢀ&/.ꢀDQGꢀ$9'ꢔꢀLQGXFHG
DGGUHVVꢀODWFKHVꢀDUHꢀVXSSRUWHGꢀLQꢀWKHꢀ6\QFKURQRXVꢀSURJUDPPLQJꢀPRGHꢃꢀ'XULQJꢀDꢀV\QFKURQRXV
ZULWHꢀRSHUDWLRQꢄꢀWRꢀZULWHꢀDꢀFRPPDQGꢀRUꢀFRPPDQGꢀVHTXHQFHꢀꢁZKLFKꢀLQFOXGHVꢀSURJUDPPLQJꢀGDWD
WRꢀWKHꢀGHYLFHꢀDQGꢀHUDVLQJꢀVHFWRUVꢀRIꢀPHPRU\ꢂꢄꢀWKHꢀV\VWHPꢀPXVWꢀGULYHꢀ$9'ꢔꢀDQGꢀ&(ꢔꢀWRꢀ9,/ꢄꢀDQG
2(ꢔꢀWRꢀ9,+ꢀZKHQꢀSURYLGLQJꢀDQꢀDGGUHVVꢀWRꢀWKHꢀGHYLFHꢄꢀDQGꢀGULYHꢀ:(ꢔꢀDQGꢀ&(ꢔꢀWRꢀ9,/ꢄꢀDQGꢀ2(ꢔ
WRꢀ9,+ꢀZKHQꢀZULWLQJꢀFRPPDQGVꢀRUꢀGDWDꢃꢀ'XULQJꢀDQꢀDV\QFKURQRXVꢀZULWHꢀRSHUDWLRQꢄꢀWKHꢀV\VWHP
PXVWꢀGULYHꢀ&(ꢔꢀDQGꢀ:(ꢔꢀWRꢀ9,/ꢀDQGꢀ2(ꢔꢀWRꢀ9,+ꢀZKHQꢀSURYLGLQJꢀDQꢀDGGUHVVꢄꢀFRPPDQGꢄꢀDQGꢀGDWDꢃ
$GGUHVVHVꢀDUHꢀODWFKHGꢀRQꢀWKHꢀODVWꢀIDOOLQJꢀHGJHꢀRIꢀ:(ꢔꢀRUꢀ&(ꢔꢄꢀZKLOHꢀGDWDꢀLVꢀODWFKHGꢀRQꢀWKHꢀꢇVW
ULVLQJꢀHGJHꢀRIꢀ:(ꢔꢀRUꢀ&(ꢔꢃꢀ$QꢀHUDVHꢀRSHUDWLRQꢀFDQꢀHUDVHꢀRQHꢀVHFWRUꢄꢀPXOWLSOHꢀVHFWRUVꢄꢀRUꢀWKH
HQWLUHꢀGHYLFHꢃꢀ7DEOHV ꢇꢇꢃꢇ±ꢇꢇꢃꢏꢀLQGLFDWHꢀWKHꢀDGGUHVVꢀVSDFHꢀWKDWꢀHDFKꢀVHFWRUꢀRFFXSLHVꢃꢀ7KHꢀGHYLFH
DGGUHVVꢀVSDFHꢀLVꢀGLYLGHGꢀLQWRꢀVL[WHHQꢀEDQNVꢆꢀ%DQNVꢀꢇꢀWKURXJKꢀꢇꢍꢀFRQWDLQꢀRQO\ꢀꢎꢍꢀ.ZRUGꢀVHFWRUVꢄ
ZKLOHꢀ%DQNVꢀꢌꢀDQGꢀꢇꢊꢀFRQWDLQꢀERWKꢀꢇꢎꢀ.ZRUGꢀERRWꢀVHFWRUVꢀLQꢀDGGLWLRQꢀWRꢀꢎꢍꢀ.ZRUGꢀVHFWRUVꢃꢀ$
³EDQNꢀDGGUHVV´ꢀLVꢀWKHꢀVHWꢀRIꢀDGGUHVVꢀELWVꢀUHTXLUHGꢀWRꢀXQLTXHO\ꢀVHOHFWꢀDꢀEDQNꢃꢀ6LPLODUO\ꢄꢀDꢀ³VHFWRU
DGGUHVV´ꢀLVꢀWKHꢀDGGUHVVꢀELWVꢀUHTXLUHGꢀWRꢀXQLTXHO\ꢀVHOHFWꢀDꢀVHFWRUꢃꢀ,&&ꢏꢀLQꢀ³'&ꢀ&KDUDFWHULVWLFV´ꢀUHSꢅ
UHVHQWVꢀWKHꢀDFWLYHꢀFXUUHQWꢀVSHFLILFDWLRQꢀIRUꢀWKHꢀZULWHꢀPRGHꢃꢀ³$&ꢀ&KDUDFWHULVWLFVꢅ6\QFKURQRXV´
DQGꢀ³$&ꢀ&KDUDFWHULVWLFVꢅ$V\QFKURQRXV´ꢀFRQWDLQꢀWLPLQJꢀVSHFLILFDWLRQꢀWDEOHVꢀDQGꢀWLPLQJꢀGLDJUDPV
IRUꢀZULWHꢀRSHUDWLRQVꢃꢀ
12.9 Handshaking
7KHꢀKDQGVKDNLQJꢀIHDWXUHꢀDOORZVꢀWKHꢀKRVWꢀV\VWHPꢀWRꢀGHWHFWꢀZKHQꢀGDWDꢀLVꢀUHDG\ꢀWRꢀEHꢀUHDGꢀE\ꢀVLPꢅ
SO\ꢀPRQLWRULQJꢀWKHꢀ5'<ꢀꢁ5HDG\ꢂꢀSLQꢄꢀZKLFKꢀLVꢀDꢀGHGLFDWHGꢀRXWSXWꢀDQGꢀFRQWUROOHGꢀE\ꢀ&(ꢔꢃ
:KHQꢀWKHꢀGHYLFHꢀLVꢀFRQILJXUHGꢀWRꢀRSHUDWHꢀLQꢀV\QFKURQRXVꢀPRGHꢄꢀDQGꢀ2(ꢔꢀLVꢀORZꢀꢁDFWLYHꢂꢄꢀWKHꢀLQLꢅ
WLDOꢀZRUGꢀRIꢀEXUVWꢀGDWDꢀEHFRPHVꢀDYDLODEOHꢀDIWHUꢀHLWKHUꢀWKHꢀIDOOLQJꢀRUꢀULVLQJꢀHGJHꢀRIꢀWKHꢀ5'<ꢀSLQ
ꢁGHSHQGLQJꢀRQꢀWKHꢀVHWWLQJꢀIRUꢀELWꢀꢇꢌꢀLQꢀWKHꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢂꢃꢀ,WꢀLVꢀUHFRPPHQGHGꢀWKDWꢀWKH
KRVWꢀV\VWHPꢀVHWꢀ&5ꢇꢑ±&5ꢇꢇꢀLQꢀWKHꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀWRꢀWKHꢀDSSURSULDWHꢀQXPEHUꢀRIꢀZDLW
VWDWHVꢀWRꢀHQVXUHꢀRSWLPDOꢀEXUVWꢀPRGHꢀRSHUDWLRQꢀꢁVHHꢀ7DEOHꢀꢇꢏꢃꢇꢌꢄꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢂꢃ
%LWꢀꢋꢀLQꢀWKHꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀDOORZVꢀWKHꢀKRVWꢀWRꢀVSHFLI\ꢀZKHWKHUꢀ5'<ꢀLVꢀDFWLYHꢀDWꢀWKHꢀVDPH
WLPHꢀWKDWꢀGDWDꢀLVꢀUHDG\ꢄꢀRUꢀRQHꢀF\FOHꢀEHIRUHꢀGDWDꢀLVꢀUHDG\ꢃꢀ
56
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.10 Hardware Reset
7KHꢀ5(6(7ꢔꢀLQSXWꢀSURYLGHVꢀDꢀKDUGZDUHꢀPHWKRGꢀRIꢀUHVHWWLQJꢀWKHꢀGHYLFHꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢃ
:KHQꢀ5(6(7ꢔꢀLVꢀGULYHQꢀORZꢀIRUꢀDWꢀOHDVWꢀDꢀSHULRGꢀRIꢀW53ꢄꢀWKHꢀGHYLFHꢀLPPHGLDWHO\ꢀWHUPLQDWHVꢀDQ\
RSHUDWLRQꢀLQꢀSURJUHVVꢄꢀWULVWDWHVꢀDOOꢀRXWSXWVꢄꢀUHVHWVꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUꢄꢀDQGꢀLJQRUHVꢀDOOꢀUHDGꢒ
ZULWHꢀFRPPDQGVꢀIRUꢀWKHꢀGXUDWLRQꢀRIꢀWKHꢀ5(6(7ꢔꢀSXOVHꢃꢀ7KHꢀGHYLFHꢀDOVRꢀUHVHWVꢀWKHꢀLQWHUQDOꢀVWDWH
PDFKLQHꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢃꢀ
7RꢀHQVXUHꢀGDWDꢀLQWHJULW\ꢀWKHꢀRSHUDWLRQꢀWKDWꢀZDVꢀLQWHUUXSWHGꢀVKRXOGꢀEHꢀUHLQLWLDWHGꢀRQFHꢀWKHꢀGHYLFH
LVꢀUHDG\ꢀWRꢀDFFHSWꢀDQRWKHUꢀFRPPDQGꢀVHTXHQFHꢃ
:KHQꢀ5(6(7ꢔꢀLVꢀKHOGꢀDWꢀ966ꢄꢀWKHꢀGHYLFHꢀGUDZVꢀ&026ꢀVWDQGE\ꢀFXUUHQWꢀꢁ,&&ꢍꢂꢃꢀ,Iꢀ5(6(7ꢔꢀLVꢀKHOG
DWꢀ9,/ꢄꢀEXWꢀQRWꢀDWꢀ966ꢄꢀWKHꢀVWDQGE\ꢀFXUUHQWꢀLVꢀJUHDWHUꢃꢀ
5(6(7ꢔꢀPD\ꢀEHꢀWLHGꢀWRꢀWKHꢀV\VWHPꢀUHVHWꢀFLUFXLWU\ꢀZKLFKꢀHQDEOHVꢀWKHꢀV\VWHPꢀWRꢀUHDGꢀWKHꢀERRWꢅXS
ILUPZDUHꢀIURPꢀWKHꢀ)ODVKꢀPHPRU\ꢀXSRQꢀDꢀV\VWHPꢀUHVHWꢃ
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12.11 Software Reset
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Software Functions and Sample Code
Table 12.27. Reset
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Cycle
Operation
Byte Address
Word Address
Data
5HVHWꢀ&RPPDQG
:ULWH
%DVHꢀꢐꢀ[[[K
%DVHꢀꢐꢀ[[[K
ꢌꢌ)ꢌK
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/HYHOꢂ'ULYHUꢂ8VHU¶Vꢂ*XLGHꢀꢁDYDLODEOHꢀRQꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢂꢀIRUꢀJHQHUDOꢀLQIRUPDꢅ
WLRQꢀRQꢀ6SDQVLRQꢀ)ODVKꢀPHPRU\ꢀVRIWZDUHꢀGHYHORSPHQWꢀJXLGHOLQHVꢃ
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
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58
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
13 Advanced Sector Protection/Unprotection
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Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
Password Method
(
(DQ1)
(DQ2)
WP# = V
(All boot
IL
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(DYB)6,7,8
Memory Array
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N3
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 13.1. Advanced Sector Protection/Unprotection
December 3, 2005 S29WS-N_m0_I0
59
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13.1 Lock Register
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Table 13.1 Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
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December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Yes
Wait 500 µs
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
PASS
Exit PPB
Command Set
Figure 13.2. PPB Program/Erase Algorithm
62
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
13.3 Dynamic Protection Bits
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64
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
(Recommended)
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 13.3. Lock Register Program Algorithm
December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
13.6 Advanced Sector Protection Software Examples
Table 13.2 Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
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66
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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December 3, 2005 S29WS-N_m0_I0
67
P r e l i m i n a r y
14 Power Conservation Modes
14.1 Standby Mode
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14.2 Automatic Sleep Mode
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14.3 Hardware RESET# Input Operation
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14.4 Output Disable (OE#)
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68
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
15 Secured Silicon Sector Flash Memory Region
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Table 15.1 Secured Silicon Sector Addresses
Sector
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Sector Size
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Address Range
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15.1 Factory Secured SiliconSector
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December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
15.2 Customer Secured Silicon Sector
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DYDLODEOHꢃꢀ
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15.3 Secured Silicon Sector Entry/Exit Command Sequences
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Software Functions and Sample Code
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70
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 15.2. Secured Silicon Sector Entry
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Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
Data
8QORFNꢀ&\FOHꢀꢇ
8QORFNꢀ&\FOHꢀꢏ
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢋꢋK
:ULWH
(QWU\ꢀ&\FOH
:ULWH
Ir)ꢂ%DVHꢂ ꢂ%DVHꢂ$GGUHVVꢁ
/* Example: SecSi Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 15.3. Secured Silicon Sector Program
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB3URJUDP&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
:RUGꢀ$GGUHVV
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
:RUGꢀ$GGUHVV
Data
ꢌꢌ$$K
8QORFNꢀ&\FOHꢀꢇ
8QORFNꢀ&\FOHꢀꢏ
3URJUDPꢀ6HWXS
:ULWH
ꢌꢌꢊꢊK
:ULWH
ꢌꢌ$ꢌK
3URJUDP
:ULWH
'DWDꢀ:RUG
Ir)ꢂ%DVHꢂ ꢂ%DVHꢂ$GGUHVVꢁ
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Table 15.4. Secured Silicon Sector Exit
ꢁ//'ꢀ)XQFWLRQꢀ ꢀOOGB6HF6L6HFWRU([LW&PGꢂ
Cycle
Operation
:ULWH
Byte Address
%DVHꢀꢐꢀ$$$K
%DVHꢀꢐꢀꢊꢊꢍK
%DVHꢀꢐꢀ$$$K
Word Address
%DVHꢀꢐꢀꢊꢊꢊK
%DVHꢀꢐꢀꢏ$$K
%DVHꢀꢐꢀꢊꢊꢊK
Data
8QORFNꢀ&\FOHꢀꢇ
8QORFNꢀ&\FOHꢀꢏ
ꢌꢌ$$K
ꢌꢌꢊꢊK
ꢌꢌꢉꢌK
:ULWH
([LWꢀ&\FOH
:ULWH
Ir)ꢂ%DVHꢂ ꢂ%DVHꢂ$GGUHVVꢁ
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
*/
*/
December 3, 2005 S29WS-N_m0_I0
71
P r e l i m i n a r y
16 Electrical Specifications
16.1 Absolute Maximum Ratings
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$&&ꢀꢁ1RWHꢀꢏꢂꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ±ꢌꢃꢊꢀ9ꢀWRꢀꢐꢉꢃꢊꢀ9
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Ir)
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ꢆꢁ 0LQLPXPꢂ'&ꢂLQSXWꢂYROWDJHꢂRQꢂSLQꢂ$&&ꢂLVꢂꢃꢈꢁꢉ9ꢁꢂ'XULQJꢂYROWDJHꢂWUDQVLWLRQVꢄꢂ$&&ꢂPD\ꢂ
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ꢊꢁ 1RꢂPRUHꢂWKDQꢂRQHꢂRXWSXWꢂPD\ꢂEHꢂVKRUWHGꢂWRꢂJURXQGꢂDWꢂDꢂWLPHꢁꢂ'XUDWLRQꢂRIꢂWKHꢂVKRUWꢂ
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ꢎꢁ 6WUHVVHVꢂDERYHꢂWKRVHꢂOLVWHGꢂXQGHUꢂ³$EVROXWHꢂ0D[LPXPꢂ5DWLQJV´ꢂPD\ꢂFDXVHꢂSHUPDQHQWꢂ
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WKHVHꢂRUꢂDQ\ꢂRWKHUꢂFRQGLWLRQVꢂDERYHꢂWKRVHꢂLQGLFDWHGꢂLQꢂWKHꢂRSHUDWLRQDOꢂVHFWLRQVꢂRIꢂWKLVꢂ
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IRUꢂH[WHQGHGꢂSHULRGVꢂPD\ꢂDIIHFWꢂGHYLFHꢂUHOLDELOLW\ꢁ
20 ns
20 ns
20 ns
VCC
+0.8 V
+2.0 V
VCC
+0.5 V
–0.5 V
–2.0 V
1.0 V
20 ns
20 ns
20 ns
Figure 16.1. Maximum Negative Overshoot
Waveform
Figure 16.2. Maximum Positive Overshoot
Waveform
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PHQWꢂLVꢂ3UHOLPLQDU\ꢂIRUꢂWKHꢂ6ꢆꢒ:ꢆꢉꢌ1ꢁ
72
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
16.2 Operating Ranges
:LUHOHVVꢀꢂ:ꢃꢀ'HYLFHV
$PELHQWꢀ7HPSHUDWXUHꢀꢁ7$ꢂ ꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀ ±ꢏꢊ&ꢀWRꢀꢐꢋꢊ&
6XSSO\ꢀ9ROWDJHV
9&&ꢀ6XSSO\ꢀ9ROWDJHV ꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃꢀꢃ ꢐꢇꢃꢈꢌꢀ9ꢀWRꢀꢐꢇꢃꢉꢊꢀ9
Ir) 2SHUDWLQJꢂUDQJHVꢂGHILQHꢂWKRVHꢂOLPLWVꢂEHWZHHQꢂZKLFKꢂWKHꢂIXQFWLRQDOLW\ꢂRIꢂWKHꢂGHYLFHꢂ
LVꢂJXDUDQWHHGꢁ
16.3 Test Conditions
Device
Under
Test
C
L
Figure 16.3. Test Setup
Table 16.1 Test Specifications
Test Condition
All Speed Options
Unit
2XWSXWꢀ/RDGꢀ&DSDFLWDQFHꢄꢀ&/
ꢁLQFOXGLQJꢀMLJꢀFDSDFLWDQFHꢂꢀ
ꢑꢌ
S)
ꢑꢃꢌꢀ#ꢀꢊꢍꢄꢀꢎꢎꢀ0+]
ꢏꢃꢊꢀ#ꢀꢋꢌꢀ0+]
,QSXWꢀ5LVHꢀDQGꢀ)DOOꢀ7LPHV
,QSXWꢀ3XOVHꢀ/HYHOV
QV
ꢌꢃꢌ±9&&
9&&ꢒꢏ
9
9
,QSXWꢀWLPLQJꢀPHDVXUHPHQWꢀ
UHIHUHQFHꢀOHYHOV
2XWSXWꢀWLPLQJꢀPHDVXUHPHQWꢀ
UHIHUHQFHꢀOHYHOV
9&&ꢒꢏ
9
December 3, 2005 S29WS-N_m0_I0
73
P r e l i m i n a r y
16.4 Key to Switching Waveforms
Waveform
Inputs
Outputs
6WHDG\
&KDQJLQJꢀIURPꢀ+ꢀWRꢀ/
&KDQJLQJꢀIURPꢀ/ꢀWRꢀ+
'RQ¶Wꢀ&DUHꢄꢀ$Q\ꢀ&KDQJHꢀ3HUPLWWHG
'RHVꢀ1RWꢀ$SSO\
&KDQJLQJꢄꢀ6WDWHꢀ8QNQRZQ
&HQWHUꢀ/LQHꢀLVꢀ+LJKꢀ,PSHGDQFHꢀ6WDWHꢀꢁ+LJKꢀ=ꢂꢀ
16.5 Switching Waveforms
VCC
All Inputs and Outputs
VCC/2
VCC/2
Input
Measurement Level
Output
0.0 V
Figure 16.4. Input Waveforms and Measurement Levels
16.6 VCC Power-up
Parameter
Description
Test Setup
Speed
Unit
W9&6
9&&ꢀ6HWXSꢀ7LPH
0LQ
ꢇ
PV
Ir)
ꢀꢁ $OOꢂ9 ꢂVLJQDOVꢂPXVWꢂEHꢂUDPSHGꢂVLPXOWDQHRXVO\ꢂWRꢂHQVXUHꢂFRUUHFWꢂSRZHUꢃXSꢁ
&&
ꢆꢁ 6ꢆꢒ:6ꢀꢆꢑ1ꢔꢂꢂ9 ꢂUDPSꢂUDWHꢂLVꢂ!ꢂꢀ9ꢍꢂꢀꢈꢈ VꢂDQGꢂIRUꢂ9 ꢂUDPSꢂUDWHꢂRIꢂꢕꢂꢀ 9ꢂꢍꢂ
&&
&&
ꢀꢈꢈ VꢂDꢂKDUGZDUHꢂUHVHWꢂLVꢂUHTXLUHGꢁ
tVCS
VCC
RESET#
Figure 16.5. VCC Power-up Diagram
74
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
16.7 DC Characteristics (CMOS Compatible)
3DUDPHWHU
'HVFULSWLRQꢀꢂ1RWHVꢃ
7HVWꢀ&RQGLWLRQVꢀꢂ1RWHVꢀꢄꢑꢀꢏꢃ
0LQ
7\S
0D[
ꢇ
ꢇ
ꢊꢍ
ꢎꢌ
ꢎꢎ
ꢍꢋ
ꢊꢍ
ꢎꢌ
ꢍꢏ
ꢍꢋ
ꢊꢍ
ꢑꢎ
ꢍꢏ
ꢍꢋ
ꢍꢊ
ꢏꢎ
ꢈ
8QLW
$
,
,QSXWꢀ/RDGꢀ&XUUHQW
9,1ꢀ ꢀ966ꢀWRꢀ9&&ꢄꢀ9&&ꢀ ꢀ9&&PD[
/,
,
2XWSXWꢀ/HDNDJHꢀ&XUUHQWꢀꢁꢏꢂ 9287ꢀ ꢀ966ꢀWRꢀ9&&ꢄꢀ9&&ꢀ ꢀ9&&PD[
$
/2
ꢊꢍꢀ0+]
ꢏꢈ
ꢏꢋ
ꢑꢌ
ꢏꢋ
ꢑꢌ
ꢑꢏ
ꢏꢉ
ꢑꢏ
ꢑꢍ
ꢑꢏ
ꢑꢊ
ꢑꢋ
ꢑꢍ
ꢇꢈ
ꢍ
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
$
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ
:(ꢔꢀ ꢀ9,+ꢄꢀEXUVWꢀOHQJWKꢀ ꢎꢎꢀ0+]
ꢀꢋ
ꢋꢌꢀ0+]
ꢊꢍꢀ0+]
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ
:(ꢔꢀ ꢀ9,+ꢄꢀEXUVWꢀOHQJWKꢀ ꢎꢎꢀ0+]
ꢀꢇꢎ
ꢋꢌꢀ0+]
,
9&&ꢀ$FWLYHꢀEXUVWꢀ5HDGꢀ&XUUHQW
&&%
ꢊꢍꢀ0+]
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ
:(ꢔꢀ ꢀ9,+ꢄꢀEXUVWꢀOHQJWKꢀ ꢎꢎꢀ0+]
ꢀꢑꢏ
ꢋꢌꢀ0+]
ꢊꢍꢀ0+]
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ
:(ꢔꢀ ꢀ9,+ꢄꢀEXUVWꢀOHQJWKꢀ ꢎꢎꢀ0+]
ꢀ&RQWLQXRXV
ꢋꢌꢀ0+]
ꢇꢌꢀ0+]
9&&ꢀ$FWLYHꢀ$V\QFKURQRXVꢀ
5HDGꢀ&XUUHQWꢀꢁꢑꢂ
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ
:(ꢔꢀ ꢀ9,+
,
ꢊꢀ0+]
ꢇꢀ0+]
9$&&
9&&
&&ꢇ
ꢇ
ꢊ
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ
$&&ꢀ ꢀ9,+
,
,
9&&ꢀ$FWLYHꢀ:ULWHꢀ&XUUHQWꢀꢁꢍꢂ
&&ꢏ
&&ꢑ
ꢏꢍ
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ꢊꢏꢃꢊ
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P$
$
9$&&
9&&
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9&&ꢀꢀꢌꢃꢏꢀ9
9&&ꢀ6WDQGE\ꢀ&XUUHQWꢀꢁꢊꢄꢀꢎꢂ
9&&ꢀ5HVHWꢀ&XUUHQWꢀꢁꢎꢂ
ꢏꢌ
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,
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5(6(7ꢔꢀ ꢀ9,/ꢄꢀ&/.ꢀ ꢀ9,/
$
&&ꢍ
&&ꢊ
9&&ꢀ$FWLYHꢀ&XUUHQWꢀ
ꢁ5HDGꢀ:KLOHꢀ:ULWHꢂꢀꢁꢎꢂ
&(ꢔꢀ ꢀ9,/ꢄꢀ2(ꢔꢀ ꢀ9,+ꢄꢀ$&&ꢀ ꢀ9,+ꢀ#ꢀ
ꢊ 0+]
ꢊꢌ
ꢏ
ꢎꢌ
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,
,
9&&ꢀ6OHHSꢀ&XUUHQWꢀꢁꢎꢂ
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$
P$
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9
&&ꢎ
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9&&ꢀ3DJHꢀ0RGHꢀ5HDGꢀ&XUUHQW 2(ꢔꢀ ꢀ9,+ꢄꢀ&(ꢔꢀ ꢀ9,/
9$&&
9&&
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9$&&ꢀ ꢀꢉꢃꢊꢀ9
$FFHOHUDWHGꢀ3URJUDPꢀ&XUUHQWꢀ
ꢁꢈꢂ
,
$&&
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9,/
9,+
92/
92+
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2XWSXWꢀ/RZꢀ9ROWDJH
2XWSXWꢀ+LJKꢀ9ROWDJH
9&&ꢀ ꢀꢇꢃꢋ 9
9&&ꢀ ꢀꢇꢃꢋ 9
±ꢌꢃꢊ
ꢌꢃꢍ
9&&ꢀ±ꢀꢌꢃꢍ
9&&ꢀꢐꢀꢌꢃꢍ
ꢌꢃꢇ
9
,
,
ꢀꢇꢌꢌꢀ$ꢄꢀ9&&ꢀ ꢀ9&& PLQꢀ
ꢀ
9
2/ꢀ
2+ꢀ ꢀ±ꢇꢌꢌꢀ$ꢄꢀ9&&ꢀ ꢀ9&& PLQꢀ
ꢀ
9&&ꢀ
ꢋꢃꢊ
ꢀ9
9ROWDJHꢀIRUꢀ$FFHOHUDWHGꢀ
3URJUDPꢀ
9++
9/.2
ꢉꢃꢊ
ꢇꢃꢍ
9
9
/RZꢀ9&&ꢀ/RFNꢅRXWꢀ9ROWDJH
Ir)
ꢀꢁ 0D[LPXPꢂ, ꢂVSHFLILFDWLRQVꢂDUHꢂWHVWHGꢂZLWKꢂ9 ꢂ ꢂ9 PD[ꢁ
&&
&&
&&
ꢆꢁ &(ꢅꢂPXVWꢂEHꢂVHWꢂKLJKꢂZKHQꢂPHDVXULQJꢂWKHꢂ5'<ꢂSLQꢁ
ꢊꢁ 7KHꢂ, ꢂFXUUHQWꢂOLVWHGꢂLVꢂW\SLFDOO\ꢂOHVVꢂWKDQꢂꢊꢁꢉꢂP$ꢍ0+]ꢄꢂZLWKꢂ2(ꢅꢂDWꢂ9
ꢁ
,+
&&
ꢎꢁ , ꢂDFWLYHꢂZKLOHꢂ(PEHGGHGꢂ(UDVHꢂRUꢂ(PEHGGHGꢂ3URJUDPꢂLVꢂLQꢂSURJUHVVꢁ
&&
ꢉꢁ 'HYLFHꢂHQWHUVꢂDXWRPDWLFꢂVOHHSꢂPRGHꢂZKHQꢂDGGUHVVHVꢂDUHꢂVWDEOHꢂIRUꢂW ꢂꢓꢂꢆꢈꢂQVꢁꢂ
$&&
7\SLFDOꢂVOHHSꢂPRGHꢂFXUUHQWꢂLVꢂHTXDOꢂWRꢂ,
ꢁ
&&ꢊ
ꢌꢁ 9 ꢂ ꢂ9 ꢂꢂꢈꢁꢆꢂ9ꢂDQGꢂ9 ꢂ!ꢂ±ꢈꢁꢀꢂ9ꢁ
,+
&&
,/
ꢋꢁ 7RWDOꢂFXUUHQWꢂGXULQJꢂDFFHOHUDWHGꢂSURJUDPPLQJꢂLVꢂWKHꢂVXPꢂRIꢂ9
FXUUHQWVꢁ
ꢂDQGꢂ9
ꢂ
&&
$&&
ꢑꢁ 9 ꢂ ꢂ9 ꢂRQꢂ$&&ꢂLQSXWꢁ
$&&
++
December 3, 2005 S29WS-N_m0_I0
75
P r e l i m i n a r y
16.8 AC Characteristics
ꢄꢊꢎꢏꢎꢄ &/.ꢀ&KDUDFWHUL]DWLRQ
Parameter
I&/.
Description
&/.ꢀ)UHTXHQF\
54 MHz
66 MHz
ꢎꢎ
80 MHz
ꢋꢌ
Unit
0+]
QV
0D[
0LQ
ꢊꢍ
W&/.
W&+
&/.ꢀ3HULRG
ꢇꢋꢃꢊ
ꢇꢊꢃꢇ
ꢇꢏꢃꢊ
&/.ꢀ+LJKꢀ7LPH
&/.ꢀ/RZꢀ7LPH
&/.ꢀ5LVHꢀ7LPH
&/.ꢀ)DOOꢀ7LPH
0LQ
ꢈꢃꢍ
ꢑ
ꢎꢃꢇ
ꢑ
ꢊꢃꢌ
ꢏꢃꢊ
QV
QV
W&/
W&5
0D[
W&)
Ir) 1RWꢂꢀꢈꢈꢖꢂWHVWHGꢁꢂ
t
CLK
t
t
CH
CL
CLK
t
t
CF
CR
Figure 16.6. CLK Characterization
76
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
ꢄꢊꢎꢏꢎꢈ 6\QFKURQRXVꢌ%XUVWꢀ5HDG
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz
ꢋꢌ
80 MHz
Unit
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
0+]
W,$&&
W%$&&
W$&6
W$&+
W%'+
W&5
/DWHQF\
0D[
%XUVWꢀ$FFHVVꢀ7LPHꢀ9DOLGꢀ&ORFNꢀWRꢀ2XWSXWꢀ'HOD\ 0D[
ꢇꢑꢃꢊ
ꢊ
ꢇꢇꢃꢏ
ꢉ
$GGUHVVꢀ6HWXSꢀ7LPHꢀWRꢀ&/.ꢀꢁ1RWHꢀꢇꢂ
$GGUHVVꢀ+ROGꢀ7LPHꢀIURPꢀ&/.ꢀꢁ1RWHꢀꢇꢂ
'DWDꢀ+ROGꢀ7LPHꢀIURPꢀ1H[Wꢀ&ORFNꢀ&\FOH
&KLSꢀ(QDEOHꢀWRꢀ5'<ꢀ9DOLGꢀ
2XWSXWꢀ(QDEOHꢀWRꢀ2XWSXWꢀ9DOLG
&KLSꢀ(QDEOHꢀWRꢀ+LJKꢀ=ꢀꢁ1RWHꢀꢏꢂ
2XWSXWꢀ(QDEOHꢀWRꢀ+LJKꢀ=ꢀꢁ1RWHꢀꢏꢂ
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
0LQ
0LQ
0LQ
0D[
0D[
0D[
0D[
0LQ
0LQ
0D[
0LQ
0LQ
0LQ
0LQ
0LQ
ꢍ
ꢎ
ꢑ
ꢈ
ꢍ
ꢇꢑꢃꢊ
ꢇꢑꢃꢊ
ꢇꢇꢃꢏ
ꢉ
W2(
ꢇꢇꢃꢏ
W&(=
W2(=
W&(6
W5'<6
W5$&&
W&$6
W$9&
W$9'
W$9'+
I&/.
ꢇꢌ
ꢇꢌ
ꢍ
5'<ꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
ꢊ
ꢍ
ꢑꢃꢊ
ꢋꢃꢊ
5HDG\ꢀ$FFHVVꢀ7LPHꢀIURPꢀ&/.
&(ꢔꢀ6HWXSꢀ7LPHꢀWRꢀ$9'ꢔꢀ
$9'ꢔꢀ/RZꢀWRꢀ&/.
ꢇꢑꢃꢊ
ꢇꢇꢃꢏ
ꢌ
ꢍ
$9'ꢔꢀ3XOVH
ꢈ
$9'ꢔꢀ+ROG
ꢑ
0LQLPXPꢀFORFNꢀIUHTXHQF\
ꢇ
ꢇ
ꢇ
Ir)
ꢀꢁ $GGUHVVHVꢂDUHꢂODWFKHGꢂRQꢂWKHꢂILUVWꢂULVLQJꢂHGJHꢂRIꢂ&/.ꢁ
ꢆꢁ 1RWꢂꢀꢈꢈꢖꢂWHVWHGꢁ
Table 16.2 Synchronous Wait State Requirements
0D[ꢀ)UHTXHQF\
:DLWꢀ6WDWHꢀ5HTXLUHPHQW
ꢌꢇ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢇꢍ 0+]
ꢇꢍ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢏꢈ 0+]
ꢏꢈ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢍꢌ 0+]
ꢍꢌ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢊꢍ 0+]
ꢊꢍ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢎꢈ 0+]
ꢎꢈ 0+]ꢀꢙꢀ)UHTꢃꢀ≤ꢀꢋꢌ 0+]
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢈ
December 3, 2005 S29WS-N_m0_I0
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ꢄꢊꢎꢏꢎꢅ 7LPLQJꢀ'LDJUDPV
5 cycles for initial access shown.
tCEZ
tCES
18.5 ns typ. (54 MHz)
5
CE#
1
2
3
4
6
7
CLK
tAVC
AVD#
tAVD
tAVDH
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
Da + 3
tBDH
OE#
tRACC
tOE
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
RDY (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
Ir)
ꢀꢁ )LJXUHꢂVKRZVꢂWRWDOꢂQXPEHUꢂRIꢂZDLWꢂVWDWHVꢂVHWꢂWRꢂILYHꢂF\FOHVꢁꢂ7KHꢂWRWDOꢂQXPEHUꢂRIꢂ
ZDLWꢂVWDWHVꢂFDQꢂEHꢂSURJUDPPHGꢂIURPꢂWZRꢂF\FOHVꢂWRꢂVHYHQꢂF\FOHVꢁꢂ
ꢆꢁ ,IꢂDQ\ꢂEXUVWꢂDGGUHVVꢂRFFXUVꢂDWꢂ³DGGUHVVꢂꢓꢂꢀ´ꢄꢂ³DGGUHVVꢂꢓꢂꢆ´ꢄꢂRUꢂ³DGGUHVVꢂꢓꢂꢊ´ꢄꢂ
DGGLWLRQDOꢂFORFNꢂGHOD\ꢂF\FOHVꢂDUHꢂLQVHUWHGꢄꢂDQGꢂDUHꢂLQGLFDWHGꢂE\ꢂ5'<ꢁ
ꢊꢁ 7KHꢂGHYLFHꢂLVꢂLQꢂV\QFKURQRXVꢂPRGHꢁ
Figure 16.7. CLK Synchronous Burst Mode Read
78
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
tAVDH
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Ir)
ꢀꢁ )LJXUHꢂVKRZVꢂWRWDOꢂQXPEHUꢂRIꢂZDLWꢂVWDWHVꢂVHWꢂWRꢂVHYHQꢂF\FOHVꢁꢂ7KHꢂWRWDOꢂQXPEHUꢂRIꢂZDLWꢂVWDWHVꢂFDQꢂEHꢂSURJUDPPHGꢂIURPꢂWZRꢂF\FOHVꢂWRꢂVHYHQꢂ
F\FOHVꢁ
ꢆꢁ ,IꢂDQ\ꢂEXUVWꢂDGGUHVVꢂRFFXUVꢂDWꢂ³DGGUHVVꢂꢓꢂꢀ´ꢄꢂ³DGGUHVVꢂꢓꢂꢆ´ꢄꢂRUꢂ³DGGUHVVꢂꢓꢂꢊ´ꢄꢂDGGLWLRQDOꢂFORFNꢂGHOD\ꢂF\FOHVꢂDUHꢂLQVHUWHGꢄꢂDQGꢂDUHꢂLQGLFDWHGꢂ
E\ꢂ5'<ꢁ
ꢊꢁ 7KHꢂGHYLFHꢂLVꢂLQꢂV\QFKURQRXVꢂPRGHꢂZLWKꢂZUDSꢂDURXQGꢁ
ꢎꢁ 'ꢑ±')ꢂLQꢂGDWDꢂZDYHIRUPꢂLQGLFDWHꢂWKHꢂRUGHUꢂRIꢂGDWDꢂZLWKLQꢂDꢂJLYHQꢂꢑꢃZRUGꢂDGGUHVVꢂUDQJHꢄꢂIURPꢂORZHVWꢂWRꢂKLJKHVWꢁꢂ6WDUWLQJꢂDGGUHVVꢂLQꢂILJXUHꢂ
LVꢂWKHꢂꢎWKꢂDGGUHVVꢂLQꢂUDQJHꢂꢏꢈꢃ)ꢐꢁꢂ
Figure 16.8. 8-word Linear Burst with Wrap Around
7
cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
tAVDH
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
Ir)
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Figure 16.9. 8-word Linear Burst without Wrap Around
December 3, 2005 S29WS-N_m0_I0
79
P r e l i m i n a r y
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
5
6
7
tAVC
tAVDH
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Ir)
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Figure 16.10. Linear Burst with RDY Set One Cycle Before Data
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80
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Ir) 5$ꢂ ꢂ5HDGꢂ$GGUHVVꢄꢂ5'ꢂ ꢂ5HDGꢂ'DWDꢁ
Figure 16.11. Asynchronous Mode Read
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Same Page Address
A1-A0
CE#
A0
A1
A2
A3
t
CE
t
t
COEZ
ACC
Optional
AVD#
OE#
t
OE
t
PACC
t
OEZ
WE#
Data
t
PACC
t
t
t
OEZ
OH
PACC
D0
D1
D1
D2
D3
t
t
OH
OH
Figure 16.12. Four-Word Page-Mode Operation
December 3, 2005 S29WS-N_m0_I0
81
P r e l i m i n a r y
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Parameter
JEDEC
Std.
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Description
All Speed Options
Unit
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tRH
RESET#
tRP
Figure 16.13. Reset Timings
82
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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JEDEC
Standard
Description
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66 MHz
80 MHz Unit
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December 3, 2005 S29WS-N_m0_I0
83
P r e l i m i n a r y
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
VA
VA
Addresses
Data
2AAh
555h for
chip erase
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 16.14. Chip/Sector Erase Operation Timings
84
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
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Figure 16.15. Program Operation Timing Using AVD#
December 3, 2005 S29WS-N_m0_I0
85
P r e l i m i n a r y
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
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tCAS
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VCC
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Figure 16.16. Program Operation Timing Using CLK in Relationship to AVD#
86
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IL
IH
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Figure 16.17. Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
Addresses
VA
High Z
Status Data
Status Data
Data
Ir)
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Figure 16.18. Data# Polling Timings (During Embedded Algorithm)
December 3, 2005 S29WS-N_m0_I0
87
P r e l i m i n a r y
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
Data
VA
Status Data
Status Data
Ir)
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Figure 16.19. Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Ir)
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Figure 16.20. Synchronous Data Polling Timings/Toggle Bit Timings
88
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ADDR
CE#
AVD#
OE#
Ir)ꢀ'4ꢆꢂGRHVꢂQRWꢂWRJJOHꢂFRUUHFWO\ꢂGXULQJꢂHUDVHꢂVXVSHQGꢂLIꢂ$9'ꢅꢂRUꢂ&(ꢅꢂDUHꢂKHOGꢂORZꢂDIWHUꢂYDOLGꢂ
DGGUHVVꢁ
Figure 16.21. Conditions for Incorrect DQ2 Polling During Erase Suspend
0ns
20ns
40ns
60ns
80ns
100ns 120ns 140ns 160ns 180ns 200ns
2
ADDR
CE#
AVD#
OE#
Ir)ꢀ'4ꢆꢂSROOLQJꢂGXULQJꢂHUDVHꢂVXVSHQGꢂEHKDYHVꢂQRUPDOO\ꢂLIꢂ&(ꢅꢂSXOVHVꢂORZꢂDWꢂRUꢂDIWHUꢂYDOLGꢂ$GGUHVVꢄꢂ
HYHQꢂLIꢂ$9'ꢅꢂGRHVꢂQRWꢁ
Figure 16.22. Correct DQ2 Polling during Erase Suspend #1
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns 200ns
ADDR
CE#
AVD#
OE#
Ir)ꢀ'4ꢆꢂSROOLQJꢂGXULQJꢂHUDVHꢂVXVSHQGꢂEHKDYHVꢂQRUPDOO\ꢂLIꢂ$9'ꢅꢂSXOVHVꢂORZꢂDWꢂRUꢂDIWHUꢂYDOLGꢂ$GGUHVVꢄꢂ
HYHQꢂLIꢂ&(ꢅꢂGRHVꢂQRWꢁ
Figure 16.23. Correct DQ2 Polling during Erase Suspend #2
0ns
20ns
40ns
60ns
80ns
100ns
120ns 140ns
160ns 180ns
200ns
ADDR
CE#
AVD#
OE#
Ir)ꢀ'4ꢆꢂSROOLQJꢂGXULQJꢂHUDVHꢂVXVSHQGꢂEHKDYHVꢂQRUPDOO\ꢂLIꢂERWKꢂ$9'ꢅꢂDQGꢂ&(ꢅꢂSXOVHꢂORZꢂDWꢂRUꢂDIWHUꢂ
YDOLGꢂ$GGUHVVꢁ
Figure 16.24. Correct DQ2 Polling during Erase Suspend #3
December 3, 2005 S29WS-N_m0_I0
89
P r e l i m i n a r y
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Ir)ꢀ'4ꢆꢂWRJJOHVꢂRQO\ꢂZKHQꢂUHDGꢂDWꢂDQꢂDGGUHVVꢂZLWKLQꢂDQꢂHUDVHꢃVXVSHQGHGꢂVHFWRUꢁꢂ7KHꢂV\VWHPꢂPD\ꢂXVHꢂ2(ꢅꢂRUꢂ&(ꢅꢂ
WRꢂWRJJOHꢂ'4ꢆꢂDQGꢂ'4ꢌꢁ
Figure 16.25. DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
Ir)
ꢀꢁ 5'<ꢏꢀꢐꢂDFWLYHꢂZLWKꢂGDWDꢂꢏ'ꢑꢂ ꢂꢀꢂLQꢂWKHꢂ&RQILJXUDWLRQꢂ5HJLVWHUꢐꢁ
ꢆꢁ 5'<ꢏꢆꢐꢂDFWLYHꢂRQHꢂFORFNꢂF\FOHꢂEHIRUHꢂGDWDꢂꢏ'ꢑꢂ ꢂꢈꢂLQꢂWKHꢂ&RQILJXUDWLRQꢂ5HJLVWHUꢐꢁ
ꢊꢁ &[[ꢂLQGLFDWHVꢂWKHꢂFORFNꢂWKDWꢂWULJJHUVꢂ'[[ꢂRQꢂWKHꢂRXWSXWVꢇꢂIRUꢂH[DPSOHꢄꢂ&ꢌꢈꢂWULJJHUVꢂ'ꢌꢈꢁ
ꢎꢁ )LJXUHꢂVKRZVꢂWKHꢂGHYLFHꢂQRWꢂFURVVLQJꢂDꢂEDQNꢂLQꢂWKHꢂSURFHVVꢂRIꢂSHUIRUPLQJꢂDQꢂHUDVHꢂRUꢂSURJUDPꢁ
ꢉꢁ 5'<ꢂGRHVꢂQRWꢂJRꢂORZꢂDQGꢂQRꢂDGGLWLRQDOꢂZDLWꢂVWDWHVꢂDUHꢂUHTXLUHGꢂIRUꢂ:6ꢂ≤ꢂꢉꢁ
Figure 16.26. Latency with Boundary Crossing when Frequency > 66 MHz
90
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
Ir)
ꢀꢁ 5'<ꢏꢀꢐꢂDFWLYHꢂZLWKꢂGDWDꢂꢏ'ꢑꢂ ꢂꢀꢂLQꢂWKHꢂ&RQILJXUDWLRQꢂ5HJLVWHUꢐꢁ
ꢆꢁ 5'<ꢏꢆꢐꢂDFWLYHꢂRQHꢂFORFNꢂF\FOHꢂEHIRUHꢂGDWDꢂꢏ'ꢑꢂ ꢂꢈꢂLQꢂWKHꢂ&RQILJXUDWLRQꢂ5HJLVWHUꢐꢁ
ꢊꢁ &[[ꢂLQGLFDWHVꢂWKHꢂFORFNꢂWKDWꢂWULJJHUVꢂ'[[ꢂRQꢂWKHꢂRXWSXWVꢇꢂIRUꢂH[DPSOHꢄꢂ&ꢌꢈꢂWULJJHUVꢂ'ꢌꢈꢁ
ꢎꢁ )LJXUHꢂVKRZVꢂWKHꢂGHYLFHꢂFURVVLQJꢂDꢂEDQNꢂLQꢂWKHꢂSURFHVVꢂRIꢂSHUIRUPLQJꢂDQꢂHUDVHꢂRUꢂSURJUDPꢁ
ꢉꢁ 5'<ꢂGRHVꢂQRWꢂJRꢂORZꢂDQGꢂQRꢂDGGLWLRQDOꢂZDLWꢂVWDWHVꢂDUHꢂUHTXLUHGꢂIRUꢂ:6ꢂ≤ꢂꢉꢁ
Figure 16.27. Latency with Boundary Crossing into Program/Erase Bank
December 3, 2005 S29WS-N_m0_I0
91
P r e l i m i n a r y
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
XhvꢀThrꢀ8svtꢄhvꢀSrtvrꢄꢀTr)
'ꢀꢊꢄꢂ'ꢀꢆꢄꢂ'ꢀꢀꢂ ꢂ³ꢀꢀꢀ´ꢂ⇒ꢂ5HVHUYHG
'ꢀꢊꢄꢂ'ꢀꢆꢄꢂ'ꢀꢀꢂ ꢂ³ꢀꢀꢈ´ꢂ⇒ꢂ5HVHUYHG
'ꢀꢊꢄꢂ'ꢀꢆꢄꢂ'ꢀꢀꢂ ꢂ³ꢀꢈꢀ´ꢂ⇒ꢂꢉꢂSURJUDPPHGꢄꢂꢋꢂWRWDO
'ꢀꢊꢄꢂ'ꢀꢆꢄꢂ'ꢀꢀꢂ ꢂ³ꢀꢈꢈ´ꢂ⇒ꢂꢎꢂSURJUDPPHGꢄꢂꢌꢂWRWDO
'ꢀꢊꢄꢂ'ꢀꢆꢄꢂ'ꢀꢀꢂ ꢂ³ꢈꢀꢀ´ꢂ⇒ ꢊꢂSURJUDPPHGꢄꢂꢉꢂWRWDO
Ir) )LJXUHꢂDVVXPHVꢂDGGUHVVꢂ'ꢈꢂLVꢂQRWꢂDWꢂDQꢂDGGUHVVꢂERXQGDU\ꢄꢂDQGꢂZDLWꢂVWDWHꢂLVꢂVHWꢂWRꢂ³ꢀꢈꢀ´ꢁ
Figure 16.28. Example of Wait States Insertion
92
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWrite Cycle
tWrite Cycle
tRead Cycle
tRead Cycle
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
PA/SA
tAS
RA
555h
AVD#
tAH
Ir) %UHDNSRLQWVꢂLQꢂZDYHIRUPVꢂLQGLFDWHꢂWKDWꢂV\VWHPꢂPD\ꢂDOWHUQDWHO\ꢂUHDGꢂDUUD\ꢂGDWDꢂIURPꢂWKHꢂ³QRQꢃEXV\ꢂEDQN´ꢂZKLOHꢂ
FKHFNLQJꢂWKHꢂVWDWXVꢂRIꢂWKHꢂSURJUDPꢂRUꢂHUDVHꢂRSHUDWLRQꢂLQꢂWKHꢂ³EXV\´ꢂEDQNꢁꢂ7KHꢂV\VWHPꢂVKRXOGꢂUHDGꢂVWDWXVꢂWZLFHꢂWRꢂHQVXUHꢂ
YDOLGꢂLQIRUPDWLRQꢁ
Figure 16.29. Back-to-Back Read/Write Cycle Timings
December 3, 2005 S29WS-N_m0_I0
93
P r e l i m i n a r y
ꢄꢊꢎꢏꢎꢆ (UDVHꢀDQGꢀ3URJUDPPLQJꢀ3HUIRUPDQFH
Parameter
Typ (Note 1)
ꢌꢃꢎ
Max (Note 2)
Unit
Comments
ꢎꢍꢀ.ZRUG
ꢇꢎꢀ.ZRUG
9&&
9&&
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ꢏ
6HFWRUꢀ(UDVHꢀ7LPH
V
ꢙꢌꢃꢇꢊ
([FOXGHVꢀꢌꢌKꢀ
SURJUDPPLQJꢀSULRUꢀ
WRꢀHUDVXUHꢀꢁ1RWHꢀꢍꢂ
ꢇꢊꢑꢃꢎꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢈꢈꢃꢍꢀꢁ:6ꢇꢏꢋ1ꢂ
ꢑꢌꢋꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢇꢊꢍꢀꢁ:6ꢇꢏꢋ1ꢂ
9&&
&KLSꢀ(UDVHꢀ7LPHꢀ
V
ꢇꢑꢌꢃꢎꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢎꢊꢃꢋꢀꢁ:6ꢇꢏꢋ1ꢂ
ꢏꢎꢏꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢇꢑꢏꢀꢁ:6ꢇꢏꢋ1ꢂ
$&&
9&&
$&&
9&&
$&&
9&&
$&&
ꢍꢌ
ꢏꢍ
ꢍꢌꢌ
ꢏꢍꢌ
ꢉꢍ
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ꢁ1RWHꢀꢈꢂ
V
V
V
ꢉꢃꢍ
ꢎ
(IIHFWLYHꢀ:RUGꢀ3URJUDPPLQJꢀ7LPHꢀ
XWLOL]LQJꢀ3URJUDPꢀ:ULWHꢀ%XIIHU
ꢎꢌ
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ꢇꢉꢏꢌ
7RWDOꢀꢑꢏꢅ:RUGꢀ%XIIHUꢀ3URJUDPPLQJꢀ
7LPH
ꢇꢊꢈꢃꢑꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢈꢋꢃꢎꢀꢁ:6ꢇꢏꢋ1ꢂ
ꢑꢇꢍꢃꢎꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢇꢊꢈꢃꢑꢀꢁ:6ꢇꢏꢋ1ꢂ
9&&
([FOXGHVꢀV\VWHPꢀ
OHYHOꢀRYHUKHDGꢀ
ꢁ1RWHꢀꢊꢂ
&KLSꢀ3URJUDPPLQJꢀ7LPHꢀꢁ1RWHꢀꢑꢂ
V
ꢇꢌꢌꢃꢈꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢊꢌꢃꢑꢀꢁ:6ꢇꢏꢋ1ꢂ
ꢏꢌꢇꢃꢑꢀꢁ:6ꢏꢊꢎ1ꢂ
ꢇꢌꢌꢃꢈꢀꢁ:6ꢇꢏꢋ1ꢂ
$&&
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ꢀꢁ 7\SLFDOꢂSURJUDPꢂDQGꢂHUDVHꢂWLPHVꢂDVVXPHꢂWKHꢂIROORZLQJꢂFRQGLWLRQVꢔꢂꢆꢉ°&ꢄꢂꢀꢁꢑꢂ9ꢂ9 ꢄꢂꢀꢈꢄꢈꢈꢈꢂ
&&
F\FOHVꢇꢂFKHFNHUERDUGꢂGDWDꢂSDWWHUQꢁ
ꢆꢁ 8QGHUꢂZRUVWꢂFDVHꢂFRQGLWLRQVꢂRIꢂꢒꢈ&ꢄꢂ9 ꢂ ꢂꢀꢁꢋꢈꢂ9ꢄꢂꢀꢈꢈꢄꢈꢈꢈꢂF\FOHVꢁ
&&
ꢊꢁ 7\SLFDOꢂFKLSꢂSURJUDPPLQJꢂWLPHꢂLVꢂFRQVLGHUDEO\ꢂOHVVꢂWKDQꢂWKHꢂPD[LPXPꢂFKLSꢂSURJUDPPLQJꢂ
WLPHꢂOLVWHGꢄꢂDQGꢂLVꢂEDVHGꢂRQꢂXWLOL]LQJꢂWKHꢂ:ULWHꢂ%XIIHUꢁ
ꢎꢁ ,QꢂWKHꢂSUHꢃSURJUDPPLQJꢂVWHSꢂRIꢂWKHꢂ(PEHGGHGꢂ(UDVHꢂDOJRULWKPꢄꢂDOOꢂZRUGVꢂDUHꢂSURJUDPPHGꢂ
WRꢂꢈꢈKꢂEHIRUHꢂHUDVXUHꢁ
ꢉꢁ 6\VWHPꢃOHYHOꢂRYHUKHDGꢂLVꢂWKHꢂWLPHꢂUHTXLUHGꢂWRꢂH[HFXWHꢂWKHꢂWZRꢃꢂRUꢂIRXUꢃEXVꢃF\FOHꢂVHTXHQFHꢂ
IRUꢂWKHꢂSURJUDPꢂFRPPDQGꢁꢂ6HHꢂWKHꢂ$SSHQGL[ꢂIRUꢂIXUWKHUꢂLQIRUPDWLRQꢂRQꢂFRPPDQGꢂ
GHILQLWLRQVꢁ
ꢌꢁ 5HIHUꢂWRꢂ$SSOLFDWLRQꢂ1RWHꢂ³(UDVHꢂ6XVSHQGꢍ5HVXPHꢂ7LPLQJ´ꢂIRUꢂPRUHꢂGHWDLOVꢁ
ꢋꢁ :RUGꢂSURJUDPPLQJꢂVSHFLILFDWLRQꢂLVꢂEDVHGꢂXSRQꢂDꢂVLQJOHꢂZRUGꢂSURJUDPPLQJꢂRSHUDWLRQꢂQRWꢂ
XWLOL]LQJꢂWKHꢂZULWHꢂEXIIHUꢁ
94
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
ꢄꢊꢎꢏꢎꢏ %*$ꢀ%DOOꢀ&DSDFLWDQFH
Parameter
Symbol
Parameter Description
,QSXWꢀ&DSDFLWDQFH
Test Setup
9,1ꢀ ꢀꢌ
Typ.
ꢊꢃꢑ
ꢊꢃꢋ
ꢎꢃꢑ
Max
ꢎꢃꢑ
ꢎꢃꢋ
ꢈꢃꢑ
Unit
S)
&
,1
&
2XWSXWꢀ&DSDFLWDQFH
&RQWUROꢀ3LQꢀ&DSDFLWDQFH
9287ꢀ ꢀꢌ
9,1ꢀ ꢀꢌ
S)
287
&
S)
,1ꢏ
Ir)
ꢀꢁ 6DPSOHGꢄꢂQRWꢂꢀꢈꢈꢖꢂWHVWHGꢁ
ꢆꢁ 7HVWꢂFRQGLWLRQVꢂ7 ꢂ ꢂꢆꢉ°&ꢇꢂIꢂ ꢂꢀꢁꢈꢂ0+]ꢁ
$
December 3, 2005 S29WS-N_m0_I0
95
P r e l i m i n a r y
17 Appendix
7KLVꢀVHFWLRQꢀFRQWDLQVꢀLQIRUPDWLRQꢀUHODWLQJꢀWRꢀVRIWZDUHꢀFRQWUROꢀRUꢀLQWHUIDFLQJꢀZLWKꢀWKHꢀ)ODVKꢀGHYLFHꢃ
)RUꢀDGGLWLRQDOꢀLQIRUPDWLRQꢀDQGꢀDVVLVWDQFHꢀUHJDUGLQJꢀVRIWZDUHꢄꢀVHHꢀWKHꢀ$GGLWLRQDOꢀ5HVRXUFHVꢀVHFꢅ
WLRQꢀRQꢀSDJHꢀꢏꢊꢄꢀRUꢀH[SORUHꢀWKHꢀ:HEꢀDWꢀZZZꢃDPGꢃFRPꢀDQGꢀZZZꢃIXMLWVXꢃFRPꢃꢀ
96
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 17.1 Memory Array Commands
%XVꢀ&\FOHVꢀꢂ1RWHVꢀꢄ±ꢉꢃ
7KLUGꢀ )RXUWK
$GGU $GGU 'DWD
)LUVW
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$V\QFKURQRXVꢀ5HDGꢀꢁꢎꢂ
5HVHWꢀꢁꢈꢂ
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ꢇ
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ꢍ
ꢎ
5$
;;;
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>%$@;ꢌꢌ ꢌꢌꢌꢇ
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6$
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6$
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98
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
17.1 Common Flash Memory Interface
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/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
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Table 17.3. CFI Query Identification String
Addresses
Data
Description
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Table 17.4. System Interface String
Addresses
Data
Description
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9&&ꢀ0D[ꢃꢀꢁZULWHꢒHUDVHꢂ
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9
9
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December 3, 2005 S29WS-N_m0_I0
99
P r e l i m i n a r y
Table 17.5. Device Geometry Definition
Addresses
Data
Description
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100
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 17.6. Primary Vendor-Specific Extended Query
Addresses
Data
Description
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December 3, 2005 S29WS-N_m0_I0
101
P r e l i m i n a r y
Table 17.6. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
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102
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
18 Revisions
Revision F (October 29, 2004)
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Revision G (January 27, 2005)
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December 3, 2005 S29WS-N_m0_I0
103
Mobile SDRAM Type 1
128 Mbit (8M x 16Bit) SDRAM
PRELIMINARY
Features
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Publication Number SDRAM_01 Revision A Amendment 3 Issue Date November 8, 2005
P r e l i m i n a r y
19 General Description
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
105
P r e l i m i n a r y
20 Functional Block Diagram
BA1
0
0
1
1
BA0
0
1
0
1
Bank
0
1
2
3
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
CAS#
RAS#
BANK2
BANK1
REFRESH 12
COUNTER
MODE REGISTER
12
BANK0
ROW-
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&
ROW-
ADDRESS
MUX
12
BANK0
MEMORY
ARRAY
2
2
4096
DQML,
DQMH
(4,096 x 512 x 16)
12
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
4096
16
16
DQ0-
DQ15
I/O GATING
2
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A11,
BA0, BA1
ADDRESS
REGISTER
14
DATA
INPUT
REGISTER
2
16
512
(x16)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
8
Figure 20.1 Block Diagram
106
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
21 Pin Descriptions
Symbol
Type
Description
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110
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
Address Bus
BA1 BA0 A11 A10 A9 A8
A7 A6 A5 A4
A3 A2 A1 A0
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12
9
8
6
5
4
1
11 10
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CASLatency
BT
Burst Length
Reserved**
Burst Length
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
2
4
4
8
8
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency
M6 M5 M4
Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
Reserved
Reserved
Reserved
Reserved
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
Figure 25.1 Mode Register Definition
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26 Burst Type
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27 CAS Latency
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
111
P r e l i m i n a r y
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T0
T1
T2
T3
CLK
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
Figure 27.1 CAS Latency
Table 27.1 CAS Latency
Allowable Operating Frequency MHz
CAS Latency = 2 CAS Latency = 3
Speed
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≤
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28 Operating Mode
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Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
29 Write Burst Mode
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30 Extended Mode Register
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UHIUHVKHGꢀGXULQJꢀ6HOIꢀ5HIUHVKꢃꢀ7KHꢀUHIUHVKꢀRSWLRQVꢀDUHꢀDOOꢀEDQNVꢀꢁEDQNVꢀꢌꢄꢀꢇꢄꢀꢏꢄ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
113
P r e l i m i n a r y
DQGꢀꢑꢂꢕꢀWZRꢀEDQNVꢀꢁEDQNVꢀꢌꢀDQGꢀꢇꢂꢕꢀDQGꢀRQHꢀEDQNꢀꢁEDQNꢀꢌꢂꢃꢀ$OVRꢀLQFOXGHGꢀLQꢀWKH
UHIUHVKꢀRSWLRQVꢀDUHꢀWKHꢀꢇꢒꢏꢀEDQNꢀDQGꢀꢇꢒꢍꢀEDQNꢀSDUWLDOꢀDUUD\ꢀVHOIꢀUHIUHVKꢀꢁEDQNꢀꢌꢂꢃ
:ULWHꢀDQGꢀ5HDGꢀFRPPDQGVꢀRFFXUꢀWRꢀDQ\ꢀEDQNꢀVHOHFWHGꢀGXULQJꢀVWDQGDUGꢀRSHUDWLRQꢄ
EXWꢀRQO\ꢀWKHꢀVHOHFWHGꢀEDQNVꢀLQꢀ3$65ꢀZLOOꢀEHꢀUHIUHVKHGꢀGXULQJꢀ6HOIꢀ5HIUHVKꢃꢀ,WꢀLV
LPSRUWDQWꢀWRꢀQRWHꢀWKDWꢀGDWDꢀLQꢀXQXVHGꢀEDQNVꢄꢀRUꢀSRUWLRQVꢀRIꢀEDQNVꢄꢀZLOOꢀEHꢀORVW
ZKHQꢀ3$65ꢀLVꢀXVHGꢃꢀ'DWDꢀZLOOꢀEHꢀORVWꢀLQꢀEDQNVꢀꢇꢄꢀꢏꢄꢀDQGꢀꢑꢀZKHQꢀWKHꢀRQHꢀEDQNꢀRSꢅ
WLRQꢀLVꢀXVHGꢃ
33 Driver Strength
%LWVꢀ(ꢊꢀDQGꢀ(ꢎꢀRIꢀWKHꢀH[WHQGHGꢀPRGHꢀUHJLVWHUꢀFDQꢀEHꢀXVHGꢀWRꢀVHOHFWꢀWKHꢀGULYHU
VWUHQJWKꢀRIꢀWKHꢀ'4ꢀRXWSXWVꢃꢀ7KLVꢀYDOXHꢀVKRXOGꢀEHꢀVHWꢀDFFRUGLQJꢀWRꢀWKHꢀDSSOLFDWLRQ
UHTXLUHPHQWVꢃꢀ)XOOꢀGULYHꢀVWUHQJWKꢀZDVꢀFDUULHGꢀRYHUꢀIURPꢀVWDQGDUGꢀ6'5$0ꢀDQGꢀLV
VXLWDEOHꢀWRꢀGULYHꢀKLJKHUꢀORDGꢀV\VWHPVꢃꢀ)XOOꢀGULYHꢀVWUHQJWKꢀLVꢀQRWꢀUHFRPPHQGHGꢀIRU
ORDGVꢀXQGHUꢀꢑꢌS)ꢃꢀ+DOIꢀGULYHꢀVWUHQJWKꢀLVꢀLQWHQGHGꢀIRUꢀPXOWLꢅGURSꢀV\VWHPVꢀZLWKꢀYDUꢅ
LRXVꢀORDGVꢃꢀ7KLVꢀGULYHꢀRSWLRQꢀLVꢀQRWꢀUHFRPPHQGHGꢀIRUꢀORDGVꢀXQGHUꢀꢇꢊS)ꢃꢀ4XDUWHU
GULYHꢀVWUHQJWKꢀLVꢀLQWHQGHGꢀIRUꢀOLJKWHUꢀORDGVꢀRUꢀSRLQWꢅWRꢅSRLQWꢀV\VWHPVꢃ
BA1BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
2
13 12 11 10
9
8
7
6
5
4
3
1
0
Extended Mode
Register (Ex)
1
0
All must be set to "0"
DS
TCSR
PASR
E6 E5 Driver Strength
E4 E3 Maximum Case Temp
85°C3
3
1
0
0
1
0
1
0
0
0
1
Full Strength
Half Strength
70°C
45°C
15°C
Quarter Strength
Reserved
1
1
0
1
1
0
E2
0
E1
0
E0
0
Self Refresh Coverage
Four Banks3
Two Banks (Bank 0,1)
One Bank (Bank 0)
RFU
0
0
1
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
RFU
1/2 Bank (Bank 0)4
1/4 Bank (Bank 0)5
RFU
1
1
1
Figure 33.1 Extended Mode Register
Ir)
ꢀꢁ (ꢀꢊꢂDQGꢂ(ꢀꢆꢂꢏ%$ꢀꢂDQGꢂ%$ꢈꢐꢂPXVWꢂEHꢂ³ꢀꢄꢂꢈ´ꢂWRꢂVHOHFWꢂWKHꢂH[WHQGHGꢂPRGHꢂUHJLVWHUꢂ
ꢏYVꢁꢂWKHꢂEDVHꢂPRGHꢂUHJLVWHUꢐꢁ
ꢆꢁ 5)8ꢔꢂ5HVHUYHGꢂIRUꢂIXWXUHꢂXVHꢁ
ꢊꢁ 'HIDXOWꢂ(05ꢂYDOXHVꢂDUHꢂIXOOꢂDUUD\ꢂIRUꢂ3$65ꢄꢂ)XOOꢂ'ULYHꢂ6WUHQJWKꢄꢂDQGꢂꢑꢉꢂIRUꢂ7&65ꢁ
ꢎꢁ (ꢀꢀꢂ ꢂꢈꢁ
ꢉꢁ (ꢀꢈꢄꢂ(ꢀꢀꢂ ꢂꢈꢁ
114
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
34 Commands
7DEOH ꢑꢍꢃꢇꢀSURYLGHVꢀDꢀTXLFNꢀUHIHUHQFHꢀRIꢀDYDLODEOHꢀFRPPDQGVꢃꢀ7KLVꢀLVꢀIROORZHGꢀE\
DꢀZULWWHQꢀGHVFULSWLRQꢀRIꢀHDFKꢀFRPPDQGꢃꢀ7KUHHꢀDGGLWLRQDOꢀ7UXWKꢀ7DEOHVꢀDSSHDUꢀIROꢅ
ORZLQJꢀWKHꢀ2SHUDWLRQꢀVHFWLRQꢕꢀWKHVHꢀWDEOHVꢀSURYLGHꢀFXUUHQWꢀVWDWHꢒQH[WꢀVWDWH
LQIRUPDWLRQꢃ
Table 34.1 Truth Table 1 - Commands and DQM Operation
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:ULWHꢀꢁ6HOHFWꢀEDQNꢀDQGꢀFROXPQꢄꢀDQGꢀVWDUWꢀ:ULWHꢀEXUVWꢂ
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/ꢒ+ %DQNꢒ&RO
/ꢒ+ %DQNꢒ&RO
;
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ꢁ(QWHUꢀGHHSꢀSRZHUꢀGRZQꢀPRGHꢂ
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ꢆꢁ $ꢈꢃ$ꢀꢀꢂGHILQHꢂRSꢃFRGHꢂZULWWHQꢂWRꢂPRGHꢂUHJLVWHUꢁ
ꢊꢁ $ꢈ±$ꢀꢀꢂSURYLGHꢂURZꢂDGGUHVVꢄꢂDQGꢂ%$ꢈꢄꢂ%$ꢀꢂGHWHUPLQHꢂZKLFKꢂEDQNꢂLVꢂPDGHꢂDFWLYHꢁ
ꢎꢁ $ꢀ±$ꢑꢂSURYLGHꢂFROXPQꢂDGGUHVVꢇꢂ$ꢀꢈꢂ+LJKꢂHQDEOHVꢂWKHꢂDXWRꢂSUHFKDUJHꢂIHDWXUHꢂꢏQRQꢂ
SHUVLVWHQWꢐꢄꢂZKLOHꢂ$ꢀꢈꢂ/RZꢂGLVDEOHVꢂWKHꢂDXWRꢂSUHFKDUJHꢂIHDWXUHꢇꢂ%$ꢈꢄꢂ%$ꢀꢂGHWHUꢃ
PLQHꢂZKLFKꢂEDQNꢂLVꢂEHLQJꢂUHDGꢂIURPꢂRUꢂZULWWHQꢂWRꢁ
ꢉꢁ $ꢀꢈꢂ/RZꢔꢂ%$ꢈꢄꢂ%$ꢀꢂGHWHUPLQHꢂWKHꢂEDQNꢂEHLQJꢂSUHFKDUJHGꢁꢂ$ꢀꢈꢂ+LJKꢔꢂ$OOꢂEDQNVꢂ
SUHFKDUJHGꢂDQGꢂ%$ꢈꢄꢂ%$ꢀꢂDUHꢂ³'RQ¶Wꢂ&DUHꢁ´
ꢌꢁ 7KLVꢂFRPPDQGꢂLVꢂ$XWRꢂ5HIUHVKꢂLIꢂ&.(ꢂLVꢂ+LJKꢄꢂ6HOIꢂ5HIUHVKꢂLIꢂ&.(ꢂLVꢂ/RZꢁ
ꢋꢁ ,QWHUQDOꢂUHIUHVKꢂFRXQWHUꢂFRQWUROVꢂURZꢂDGGUHVVLQJꢇꢂDOOꢂLQSXWVꢂDQGꢂ,ꢍ2VꢂDUHꢂ³'RQ¶Wꢂ
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ꢑꢁ $FWLYDWHVꢂRUꢂGHDFWLYDWHVꢂWKHꢂ'4VꢂGXULQJꢂ:ULWHVꢂꢏ]HURꢃFORFNꢂGHOD\ꢐꢂDQGꢂ5HDGVꢂꢏWZRꢃ
FORFNꢂGHOD\ꢐꢁꢂ'40/ꢂFRQWUROVꢂ'4ꢈꢃꢋꢄꢂ'40+ꢂFRQWUROVꢂ'4ꢑꢃꢀꢉꢁ
ꢒꢁ 7KLVꢂFRPPDQGꢂLVꢂ%XUVWꢂ7HUPLQDWHꢂZKHQꢂ&.(ꢂLVꢂKLJKꢂDQGꢂ'HHSꢂ3RZHUꢂ'RZQꢂZKHQꢂ
&.(ꢂLVꢂORZꢁ
ꢀꢈꢁ7KHꢂSXUSRVHꢂRIꢂWKHꢂ%XUVWꢂ7HUPLQDWHꢂFRPPDQGꢂLVꢂWRꢂVWRSꢂDꢂGDWDꢂEXUVWꢄꢂWKXVꢂWKHꢂ
FRPPDQGꢂFRXOGꢂFRLQFLGHꢂZLWKꢂGDWDꢂRQꢂWKHꢂEXVꢁꢂ+RZHYHUꢂWKHꢂ'4VꢂFROXPQꢂUHDGVꢂDꢂ
GRQ¶WꢂFDUHꢂVWDWHꢂWRꢂLOOXVWUDWHꢂWKDWꢂWKHꢂ%XUVWꢂ7HUPLQDWHꢂFRPPDQGꢂFDQꢂRFFXUꢂZKHQꢂ
WKHUHꢂLVꢂQRꢂGDWDꢂSUHVHQWꢁ
35 Command Inhibit
7KHꢀ&RPPDQGꢀ,QKLELWꢀIXQFWLRQꢀSUHYHQWVꢀQHZꢀFRPPDQGVꢀIURPꢀEHLQJꢀH[HFXWHGꢀE\
WKHꢀ6'5$0ꢄꢀUHJDUGOHVVꢀRIꢀZKHWKHUꢀWKHꢀ&/.ꢀVLJQDOꢀLVꢀHQDEOHGꢃꢀ7KHꢀ6'5$0ꢀLVꢀHIꢅ
IHFWLYHO\ꢀGHVHOHFWHGꢃꢀ2SHUDWLRQVꢀDOUHDG\ꢀLQꢀSURJUHVVꢀDUHꢀQRWꢀDIIHFWHGꢃ
36 No Operation (NOP)
7KHꢀ1Rꢀ2SHUDWLRQꢀꢁ123ꢂꢀFRPPDQGꢀLVꢀXVHGꢀWRꢀSHUIRUPꢀDꢀ123ꢀWRꢀDQꢀ6'5$0ꢀZKLFK
LVꢀVHOHFWHGꢀꢁ&6ꢔꢀLVꢀ/RZꢂꢃꢀ7KLVꢀSUHYHQWVꢀXQZDQWHGꢀFRPPDQGVꢀIURPꢀEHLQJꢀUHJLVꢅ
WHUHGꢀGXULQJꢀLGOHꢀRUꢀZDLWꢀVWDWHVꢃꢀ2SHUDWLRQVꢀDOUHDG\ꢀLQꢀSURJUHVVꢀDUHꢀQRWꢀDIIHFWHGꢃ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
115
P r e l i m i n a r y
37 Load Mode Register
7KHꢀPRGHꢀUHJLVWHUꢀLVꢀORDGHGꢀYLDꢀLQSXWVꢀ$ꢌ±$ꢇꢇꢄꢀ%$ꢌꢄꢀ%$ꢇꢃꢀ6HHꢀPRGHꢀUHJLVWHU
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WHQGHGꢀ0RGHꢀ5HJLVWHUꢀFRPPDQGVꢀFDQꢀRQO\ꢀEHꢀLVVXHGꢀZKHQꢀDOOꢀEDQNVꢀDUHꢀLGOHꢄꢀDQG
DꢀVXEVHTXHQWꢀH[HFXWDEOHꢀFRPPDQGꢀFDQQRWꢀEHꢀLVVXHGꢀXQWLOꢀW05'ꢀLVꢀPHWꢃ
7KHꢀYDOXHVꢀRIꢀWKHꢀPRGHꢀUHJLVWHUꢀDQGꢀH[WHQGHGꢀPRGHꢀUHJLVWHUꢀZLOOꢀEHꢀUHWDLQHGꢀHYHQ
ZKHQꢀH[LWLQJꢀGHHSꢀSRZHUꢅGRZQꢃ
38 Active
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RSHQꢂꢀIRUꢀDFFHVVHVꢀXQWLOꢀDꢀSUHFKDUJHꢀFRPPDQGꢀLVꢀLVVXHGꢀWRꢀWKDWꢀEDQNꢃꢀ$ꢀSUHꢅ
FKDUJHꢀFRPPDQGꢀPXVWꢀEHꢀLVVXHGꢀEHIRUHꢀRSHQLQJꢀDꢀGLIIHUHQWꢀURZꢀLQꢀWKHꢀVDPH
EDQNꢃ
39 Read
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40 Write
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WKHꢀURZꢀEHLQJꢀDFFHVVHGꢀZLOOꢀEHꢀSUHFKDUJHGꢀDWꢀWKHꢀHQGꢀRIꢀWKHꢀZULWHꢀEXUVWꢕꢀLIꢀDXWR
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116
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
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42 Auto Precharge
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
117
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47 Operation
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118
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SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
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Figure 47.1 Activating a Specific Row in a Specific Bank Register
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T4
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RCD
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Figure 47.2. Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK≤ 3
47.2 Reads
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Mobile SDRAM Type 1
119
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LQSXWꢀGDWDꢀZLOOꢀJRꢀ/RZꢅ=ꢀEHIRUHꢀWKHꢀ6'5$0ꢀ'4ꢀJRꢀ+LJKꢅ=ꢃꢀ,QꢀWKLVꢀFDVHꢄꢀDWꢀOHDVW
DꢀVLQJOHꢀF\FOHꢀGHOD\ꢀVKRXOGꢀRFFXUꢀEHWZHHQꢀWKHꢀODVWꢀUHDGꢀGDWDꢀDQGꢀWKHꢀ:ULWH
FRPPDQGꢃ
120
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
CLK
CKE
CS#
HIGH
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A8
A9, A11
A10
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,1
DON’T CARE
Figure 47.1 Read Command
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
121
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COLn
BANK,
COLb
ADDRESS
DQ
D
OUT
D
n + 1
OUT
DOUT
D
n + 3
OUT
DOUT
b
n
n + 2
CAS Latency = 2
T1
T0
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COLn
BANK,
COLb
ADDRESS
DQ
D
OUT
DOUT
D
n + 2
OUT
D
n + 3
OUT
D
OUT
n
n + 1
b
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 47.2. Consecutive Read Bursts
Ir)ꢂ(DFKꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂ/RZꢁ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COLn
BANK,
COLa
BANK,
COLx
BANK,
COLm
D
OUT
D
a
OUT
D
OUT
DOUT
n
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLa
BANK,
COLx
BANK,
COLm
D
n
OUT
D
OUT
D
OUT
DOUT
a
x
m
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 47.3. Random Read Accesses
Ir)ꢂ(DFKꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂORZꢁ
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WKHꢀ:ULWHꢀFRPPDQGꢀꢁ'40ꢀODWHQF\ꢀLVꢀWZRꢀFORFNVꢀIRUꢀRXWSXWꢀEXIIHUVꢂꢀWRꢀVXSSUHVV
122
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
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+LJKꢅ=ꢀꢁRUꢀUHPDLQꢀ+LJKꢅ=ꢂꢄꢀUHJDUGOHVVꢀRIꢀWKHꢀVWDWHꢀRIꢀWKHꢀ'40ꢀVLJQDOꢄꢀSURYLGHG
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FKDUJHꢃꢀ7KHꢀGLVDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀLVꢀWKDWꢀLWꢀUHTXLUHVꢀWKDWꢀWKH
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FRPPDQGꢕꢀWKHꢀDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀLVꢀWKDWꢀLWꢀFDQꢀEHꢀXVHGꢀWR
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T0
T1
T2
T3
T4
CLK
DQM
READ
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COLn
BANK,
COLb
t
CK
t
HZ
DOUT
n
DIN b
DQ
t
DS
Figure 47.4. Read to Write
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
123
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
CLK
DQM
READ
NOP
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COLb
BANK,
COLn
t
HZ
DOUT
n
DIN
b
DQ
t
DS
DON’T CARE
Figure 47.5. Read to Write with Extra Clock Cycle
Ir)ꢂ$ꢂ&$6ꢂODWHQF\ꢂRIꢂWKUHHꢂLVꢂXVHGꢂIRUꢂLOOXVWUDWLRQꢁꢂ7KHꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂ
DQ\ꢂEDQNꢄꢂDQGꢂWKHꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK
(a or all)
BANKa,
COLn
BANKa,
ROW
D
OUT
D
n
OUT
D
n
OUT
DOUT
n
n
+
1
+
2
+
3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 2 cycles
BANK
(a or all)
BANKa,
COLn
BANKa,
ROW
D
OUT
D
n
OUT
D
n
OUT
DOUT
n + 3
n
+
1
+
2
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 47.6. Read to Precharge
Ir)ꢂ'40ꢂLVꢂORZꢁ
124
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK,
COLn
D
OUT
D
n +
OUT
DOUT
DOUT
n + 3
n
1
n +
2
CAS Latency = 2
T1
T0
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COLn
D
OUT
D
OUT
D
n +
OUT
DOUT
n + 3
n
n
+
1
2
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 47.7. Terminating a Read Burst
Ir)ꢂ'40ꢂLVꢂORZꢁ
)XOOꢅSDJHꢀ5HDGꢀEXUVWVꢀFDQꢀEHꢀWUXQFDWHGꢀZLWKꢀWKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢄꢀDQG
IL[HGꢅOHQJWKꢀ5HDGꢀEXUVWVꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢄ
SURYLGHGꢀWKDWꢀDXWRꢀSUHFKDUJHꢀZDVꢀQRWꢀDFWLYDWHGꢃꢀ7KHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQG
VKRXOGꢀEHꢀLVVXHGꢀ[ꢀF\FOHVꢀEHIRUHꢀWKHꢀFORFNꢀHGJHꢀDWꢀZKLFKꢀWKHꢀODVWꢀGHVLUHGꢀGDWDꢀHOꢅ
HPHQWꢀLVꢀYDOLGꢄꢀZKHUHꢀ[ꢀHTXDOVꢀWKHꢀ&$6ꢀODWHQF\ꢀPLQXVꢀRQHꢃꢀ7KLVꢀLVꢀVKRZQꢀLQ
)LJXUH ꢍꢈꢃꢈꢀIRUꢀHDFKꢀSRVVLEOHꢀ&$6ꢀODWHQF\ꢕꢀGDWDꢀHOHPHQWꢀQꢂꢓꢂꢊꢀLVꢀWKHꢀODVWꢀGHVLUHG
GDWDꢀHOHPHQWꢀRIꢀDꢀORQJHUꢀEXUVWꢃ
47.3 Writes
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ZLWKꢀWKHꢀ:ULWHꢀFRPPDQGꢃꢀ6XEVHTXHQWꢀGDWDꢀHOHPHQWVꢀZLOOꢀEHꢀUHJLVWHUHGꢀRQꢀHDFK
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LQJꢀQRꢀRWKHUꢀFRPPDQGVꢀKDYHꢀEHHQꢀLQLWLDWHGꢄꢀWKHꢀ'4ꢀZLOOꢀUHPDLQꢀ+LJKꢅ=ꢀDQGꢀDQ\
DGGLWLRQDOꢀLQSXWꢀGDWDꢀZLOOꢀEHꢀLJQRUHGꢀꢁVHHꢀ)LJXUH ꢍꢈꢃꢑꢂꢃꢀ$ꢀIXOOꢅSDJHꢀEXUVWꢀZLOOꢀFRQꢅ
WLQXHꢀXQWLOꢀWHUPLQDWHGꢃꢀꢁ$WꢀWKHꢀHQGꢀRIꢀWKHꢀSDJHꢄꢀLWꢀZLOOꢀZUDSꢀWRꢀFROXPQꢀꢌꢀDQG
FRQWLQXHꢃꢂ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
125
P r e l i m i n a r y
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A8
A9, A11
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
BANK
ADDRESS
BA0,1
VALID ADDRESS
DON’T CARE
Figure 47.1 Write Command
'DWDꢀIRUꢀDQ\ꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀVXEVHTXHQWꢀ:ULWHꢀFRPPDQGꢄ
DQGꢀGDWDꢀIRUꢀDꢀIL[HGꢀOHQJWKꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀLPPHGLDWHO\ꢀIROORZHGꢀE\ꢀGDWDꢀIRU
Dꢀ:ULWHꢀFRPPDQGꢃꢀ7KHꢀQHZꢀ:ULWHꢀFRPPDQGꢀFDQꢀEHꢀLVVXHGꢀRQꢀDQ\ꢀFORFNꢀIROORZLQJ
WKHꢀSUHYLRXVꢀ:ULWHꢀFRPPDQGꢄꢀDQGꢀWKHꢀGDWDꢀSURYLGHGꢀFRLQFLGHQWꢀZLWKꢀWKHꢀQHZ
FRPPDQGꢀDSSOLHVꢀWRꢀWKHꢀQHZꢀFRPPDQGꢃꢀ$QꢀH[DPSOHꢀLVꢀVKRZQꢀLQꢀ)LJXUH ꢍꢈꢃꢍꢃ
'DWDꢀQꢂꢓꢂꢀꢀLVꢀHLWKHUꢀWKHꢀODVWꢀRIꢀDꢀEXUVWꢀRIꢀWZRꢀRUꢀWKHꢀODVWꢀGHVLUHGꢀRIꢀDꢀORQJHUꢀEXUVWꢃ
7KHꢀꢇꢏꢋ0Eꢀ6'5$0ꢀXVHVꢀDꢀSLSHOLQHGꢀDUFKLWHFWXUHꢀDQGꢀWKHUHIRUHꢀGRHVꢀQRWꢀUHTXLUH
WKHꢀꢆQꢀUXOHꢀDVVRFLDWHGꢀZLWKꢀDꢀSUHIHWFKꢀDUFKLWHFWXUHꢃꢀ$ꢀ:ULWHꢀFRPPDQGꢀFDQꢀEHꢀLQLꢅ
WLDWHGꢀRQꢀDQ\ꢀFORFNꢀF\FOHꢀIROORZLQJꢀDꢀSUHYLRXVꢀ:ULWHꢀFRPPDQGꢃꢀ)XOOꢅVSHHGꢀUDQGRP
ZULWHꢀDFFHVVHVꢀZLWKLQꢀDꢀSDJHꢀFDQꢀEHꢀSHUIRUPHGꢀWRꢀWKHꢀVDPHꢀEDQNꢄꢀDVꢀVKRZQꢀLQ
)LJXUH ꢍꢈꢃꢍꢄꢀRUꢀHDFKꢀVXEVHTXHQWꢀ:ULWHꢀPD\ꢀEHꢀSHUIRUPHGꢀWRꢀDꢀGLIIHUHQWꢀEDQNꢃ
126
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
CLK
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
DIN
n
DIN
n + 1
DON’T CARE
Figure 47.2. Write Burst
Ir)ꢂ%XUVWꢂOHQJWKꢂ ꢂꢆꢁꢂ'40ꢂLVꢂORZꢁ
T0
T1
T2
CLK
WRITE
NOP
WRITE
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLb
DIN
n
DIN
n + 1
DIN
b
DON’T CARE
Figure 47.3. Write to Write
Ir)ꢂ'40ꢂLVꢂORZꢁꢂ(DFKꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁ
'DWDꢀIRUꢀDQ\ꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀVXEVHTXHQWꢀ5HDGꢀFRPPDQGꢄ
DQGꢀGDWDꢀIRUꢀDꢀIL[HGꢀOHQJWKꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀLPPHGLDWHO\ꢀIROORZHGꢀE\ꢀDꢀ5HDG
FRPPDQGꢃꢀ2QFHꢀWKHꢀ5HDGꢀFRPPDQGꢀLVꢀUHJLVWHUHGꢄꢀWKHꢀGDWDꢀLQSXWVꢀZLOOꢀEHꢀLJQRUHGꢄ
DQGꢀZULWHVꢀZLOOꢀQRWꢀEHꢀH[HFXWHGꢃꢀ$QꢀH[DPSOHꢀLVꢀVKRZQꢀLQꢀ)LJXUH ꢍꢈꢃꢊꢃꢀ'DWDꢀQꢂꢓꢂꢀ
LVꢀHLWKHUꢀWKHꢀODVWꢀRIꢀDꢀEXUVWꢀRIꢀWZRꢀRUꢀWKHꢀODVWꢀGHVLUHGꢀRIꢀDꢀORQJHUꢀEXUVWꢃ
'DWDꢀIRUꢀDꢀIL[HGꢅOHQJWKꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀIROORZHGꢀE\ꢄꢀRUꢀWUXQFDWHGꢀZLWKꢄꢀDꢀ3UHꢅ
FKDUJHꢀFRPPDQGꢀWRꢀWKHꢀVDPHꢀEDQNꢀꢁSURYLGHGꢀWKDWꢀDXWRꢀSUHFKDUJHꢀZDVꢀQRW
DFWLYDWHGꢂꢄꢀDQGꢀDꢀIXOOꢅSDJHꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀ3UHFKDUJHꢀFRPꢅ
PDQGꢀWRꢀWKHꢀVDPHꢀEDQNꢃꢀ7KHꢀ3UHFKDUJHꢀFRPPDQGꢀVKRXOGꢀEHꢀLVVXHGꢀW:5ꢀDIWHUꢀWKH
FORFNꢀHGJHꢀDWꢀZKLFKꢀWKHꢀODVWꢀGHVLUHGꢀLQSXWꢀGDWDꢀHOHPHQWꢀLVꢀUHJLVWHUHGꢃꢀ7KHꢀDXWR
SUHFKDUJHꢀPRGHꢀUHTXLUHVꢀDꢀW:5ꢀRIꢀDWꢀOHDVWꢀRQHꢀFORFNꢀSOXVꢀWLPHꢄꢀUHJDUGOHVVꢀRI
IUHTXHQF\ꢃ
,QꢀDGGLWLRQꢄꢀZKHQꢀWUXQFDWLQJꢀDꢀ:ULWHꢀEXUVWꢄꢀWKHꢀ'40ꢀVLJQDOꢀPXVWꢀEHꢀXVHGꢀWRꢀPDVN
LQSXWꢀGDWDꢀIRUꢀWKHꢀFORFNꢀHGJHꢀSULRUꢀWRꢄꢀDQGꢀWKHꢀFORFNꢀHGJHꢀFRLQFLGHQWꢀZLWKꢄꢀWKHꢀ3UHꢅ
FKDUJHꢀFRPPDQGꢃꢀ$QꢀH[DPSOHꢀLVꢀVKRZQꢀLQꢀ)LJXUH ꢍꢈꢃꢎꢃꢀ'DWDꢀQꢂꢓꢂꢀꢀLVꢀHLWKHUꢀWKH
ODVWꢀRIꢀDꢀEXUVWꢀRIꢀWZRꢀRUꢀWKHꢀODVWꢀGHVLUHGꢀRIꢀDꢀORQJHUꢀEXUVWꢃꢀ)ROORZLQJꢀWKHꢀ3UHFKDUJH
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
127
P r e l i m i n a r y
FRPPDQGꢄꢀDꢀVXEVHTXHQWꢀFRPPDQGꢀWRꢀWKHꢀVDPHꢀEDQNꢀFDQQRWꢀEHꢀLVVXHGꢀXQWLOꢀW53
LVꢀPHWꢃ
T0
T1
T2
T3
CLK
WRITE
WRITE
WRITE
WRITE
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLa
BANK,
COLx
BANK,
COLm
D
IN
D
IN
D
IN
DIN
m
n
a
x
DON’T CARE
Figure 47.4. Random Write Cycles
Ir)ꢂ(DFKꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂORZꢁ
T0
T1
T2
T3
T4
T5
CLK
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLb
DIN
n
DIN
n + 1
D
OUT
DOUT
b + 1
b
DON’T CARE
Figure 47.5. Write to Read
Ir)ꢂ7KHꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢄꢂDQGꢂWKHꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂ
DQ\ꢂEDQNꢁꢂ'40ꢂLVꢂORZꢁꢂ&$6ꢂODWHQF\ꢂ ꢂꢆꢂIRUꢂLOOXVWUDWLRQꢁ
,QꢀWKHꢀFDVHꢀRIꢀDꢀIL[HGꢅOHQJWKꢀEXUVWꢀEHLQJꢀH[HFXWHGꢀWRꢀFRPSOHWLRQꢄꢀDꢀ3UHFKDUJH
FRPPDQGꢀLVVXHGꢀDWꢀWKHꢀRSWLPXPꢀWLPHꢀꢁDVꢀGHVFULEHGꢀDERYHꢂꢀSURYLGHVꢀWKHꢀVDPH
RSHUDWLRQꢀWKDWꢀZRXOGꢀUHVXOWꢀIURPꢀWKHꢀVDPHꢀIL[HGꢅOHQJWKꢀEXUVWꢀZLWKꢀDXWRꢀSUHꢅ
FKDUJHꢃꢀ7KHꢀGLVDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀLVꢀWKDWꢀLWꢀUHTXLUHVꢀWKDWꢀWKH
FRPPDQGꢀDQGꢀDGGUHVVꢀEXVHVꢀEHꢀDYDLODEOHꢀDWꢀWKHꢀDSSURSULDWHꢀWLPHꢀWRꢀLVVXHꢀWKH
FRPPDQGꢕꢀWKHꢀDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀLVꢀWKDWꢀLWꢀFDQꢀEHꢀXVHGꢀWR
WUXQFDWHꢀIL[HGꢅOHQJWKꢀRUꢀIXOOꢅSDJHꢀEXUVWVꢃ
)L[HGꢅOHQJWKꢀRUꢀIXOOꢅSDJHꢀ:ULWHꢀEXUVWVꢀFDQꢀEHꢀWUXQFDWHGꢀZLWKꢀWKHꢀ%XUVWꢀ7HUPLQDWH
FRPPDQGꢃꢀ:KHQꢀWUXQFDWLQJꢀDꢀ:ULWHꢀEXUVWꢄꢀWKHꢀLQSXWꢀGDWDꢀDSSOLHGꢀFRLQFLGHQWꢀZLWK
WKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢀZLOOꢀEHꢀLJQRUHGꢃꢀ7KHꢀODVWꢀGDWDꢀZULWWHQꢀꢁSURYLGHG
WKDWꢀ'40ꢀLVꢀ/RZꢀDWꢀWKDWꢀWLPHꢂꢀZLOOꢀEHꢀWKHꢀLQSXWꢀGDWDꢀDSSOLHGꢀRQHꢀFORFNꢀSUHYLRXVꢀWR
WKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢃꢀ7KLVꢀLVꢀVKRZQꢀLQꢀ)LJXUH ꢍꢈꢃꢏꢄꢀZKHUHꢀGDWDꢀQꢀLVꢀWKH
ODVWꢀGHVLUHGꢀGDWDꢀHOHPHQWꢀRIꢀDꢀORQJHUꢀEXUVWꢃ
128
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
CLK
t
t
WR@ CK 15ns
DQM
t
RP
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
D
n
IN
DIN
n + 1
DQ
t
t
WR@ CK < 15ns
DQM
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
D
n
IN
DIN
n + 1
DQ
DON’T CARE
Figure 47.6. Write to Precharge
Ir)ꢂ'40ꢂFRXOGꢂUHPDLQꢂORZꢂLQꢂWKLVꢂH[DPSOHꢂLIꢂWKHꢂ:ULWHꢂEXUVWꢂLVꢂDꢂIL[HGꢂOHQJWKꢂRIꢂWZRꢁ
47.4 Precharge
7KHꢀ3UHFKDUJHꢀFRPPDQGꢀꢁVHHꢀ)LJXUH ꢍꢈꢃꢑꢂꢀLVꢀXVHGꢀWRꢀGHDFWLYDWHꢀWKHꢀRSHQꢀURZꢀLQ
DꢀSDUWLFXODUꢀEDQNꢀRUꢀWKHꢀRSHQꢀURZꢀLQꢀDOOꢀEDQNVꢃꢀ7KHꢀEDQNꢁVꢂꢀZLOOꢀEHꢀDYDLODEOHꢀIRUꢀD
VXEVHTXHQWꢀURZꢀDFFHVVꢀVRPHꢀVSHFLILHGꢀWLPHꢀꢁW53ꢂꢀDIWHUꢀWKHꢀSUHFKDUJHꢀFRPPDQG
LVꢀLVVXHGꢃꢀ,QSXWꢀ$ꢇꢌꢀGHWHUPLQHVꢀZKHWKHUꢀRQHꢀRUꢀDOOꢀEDQNVꢀDUHꢀWRꢀEHꢀSUHFKDUJHGꢄ
DQGꢀLQꢀWKHꢀFDVHꢀZKHUHꢀRQO\ꢀRQHꢀEDQNꢀLVꢀWRꢀEHꢀSUHFKDUJHGꢄꢀLQSXWVꢀ%$ꢌꢄꢀ%$ꢇꢀVHOHFW
WKHꢀEDQNꢃꢀ:KHQꢀDOOꢀEDQNVꢀDUHꢀWRꢀEHꢀSUHFKDUJHGꢄꢀLQSXWVꢀ%$ꢌꢄꢀ%$ꢇꢀDUHꢀWUHDWHGꢀDV
³'RQ¶Wꢀ&DUHꢃ´ꢀ2QFHꢀDꢀEDQNꢀKDVꢀEHHQꢀSUHFKDUJHGꢄꢀLWꢀLVꢀLQꢀWKHꢀLGOHꢀVWDWHꢀDQGꢀPXVW
EHꢀDFWLYDWHGꢀSULRUꢀWRꢀDQ\ꢀ5HDGꢀRUꢀ:ULWHꢀFRPPDQGVꢀEHLQJꢀLVVXHGꢀWRꢀWKDWꢀEDQNꢃ
47.5 Power-down
3RZHUꢅGRZQꢀRFFXUVꢀLIꢀ&.(ꢀLVꢀUHJLVWHUHGꢀORZꢀFRLQFLGHQWꢀZLWKꢀDꢀ123ꢀRUꢀ&RPPDQG
,QKLELWꢀZKHQꢀQRꢀDFFHVVHVꢀDUHꢀLQꢀSURJUHVVꢃꢀ,IꢀSRZHUꢅGRZQꢀRFFXUVꢀZKHQꢀDOOꢀEDQNV
DUHꢀLGOHꢄꢀWKLVꢀPRGHꢀLVꢀUHIHUUHGꢀWRꢀDVꢀSUHFKDUJHꢀSRZHUꢅGRZQꢕꢀLIꢀSRZHUꢅGRZQꢀRFFXUV
ZKHQꢀWKHUHꢀLVꢀDꢀURZꢀDFWLYHꢀLQꢀDQ\ꢀEDQNꢄꢀWKLVꢀPRGHꢀLVꢀUHIHUUHGꢀWRꢀDVꢀDFWLYHꢀSRZHUꢅ
GRZQꢃꢀ(QWHULQJꢀSRZHUꢅGRZQꢀGHDFWLYDWHVꢀWKHꢀLQSXWꢀDQGꢀRXWSXWꢀEXIIHUVꢄꢀH[FOXGLQJ
&.(ꢄꢀIRUꢀPD[LPXPꢀSRZHUꢀVDYLQJVꢀZKLOHꢀLQꢀVWDQGE\ꢃꢀ7KHꢀGHYLFHꢀPD\ꢀQRWꢀUHPDLQ
LQꢀWKHꢀSRZHUꢅGRZQꢀVWDWHꢀORQJHUꢀWKDQꢀWKHꢀUHIUHVKꢀSHULRGꢀꢁꢎꢍPVꢂꢀVLQFHꢀQRꢀUHIUHVK
RSHUDWLRQVꢀDUHꢀSHUIRUPHGꢀLQꢀWKLVꢀPRGHꢃꢀ7KHꢀSRZHUꢅGRZQꢀVWDWHꢀLVꢀH[LWHGꢀE\ꢀUHJLVꢅ
WHULQJꢀDꢀ123ꢀRUꢀ&RPPDQGꢀ,QKLELWꢀDQGꢀ&.(ꢀ+LJKꢀDWꢀWKHꢀGHVLUHGꢀFORFNꢀHGJH
ꢁPHHWLQJꢀW&.6ꢂꢃꢀ6HHꢀ)LJXUH ꢍꢈꢃꢇꢃ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
129
P r e l i m i n a r y
((
))
((
))
CLK
> t
t
CKS
CKS
CKE
((
))
((
))
COMMAND
NOP
NOP
ACTIVE
((
))
t
t
t
All banks idle
RCD
RAS
RC
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
Figure 47.1. Power-Down
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
WRITE
COMMAND
ADDRESS
DQ
BANK,
COLn
(ADDRESS)
(DATA)
DIN
n
TRANSITIONING DATA
DON’T CARE
Figure 47.2. Terminating a Write Burst
Ir)ꢂ'40VꢂDUHꢂORZꢁ
CLK
CKE
CS#
HIGH
RAS#
CAS#
WE#
A0-A9, A11
A10
All Banks
Bank Selected
BANK
ADDRESS
BA0,1
VALID ADDRESS
DON’T CARE
Figure 47.3. Precharge Command
130
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
47.6 Deep Power-down
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DUUD\ꢀZLOOꢀQRWꢀEHꢀUHWDLQHGꢀRQFHꢀ'HHSꢀ3RZHUꢀ'RZQꢀPRGHꢀLVꢀH[HFXWHGꢃꢀ'HHSꢀ3RZHU
'RZQꢀPRGHꢀLVꢀHQWHUHGꢀE\ꢀKDYLQJꢀDOOꢀEDQNVꢀLGOHꢀWKHQꢀ&6ꢔꢀDQGꢀ:(ꢔꢀKHOGꢀORZꢀZLWK
5$6ꢔꢀDQGꢀ&$6ꢔꢀKLJKꢀDWꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀFORFNꢄꢀZKLOHꢀ&.(ꢀLVꢀORZꢃꢀ&.(ꢀPXVW
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UHJLVWHUꢀDQGꢀH[WHQGHGꢀPRGHꢀUHJLVWHUꢀZLOOꢀEHꢀUHWDLQHGꢀXSRQꢀH[LWLQJꢀGHHSꢀSRZHUꢅ
GRZQꢃ
47.7 Clock Suspend
7KHꢀFORFNꢀVXVSHQGꢀPRGHꢀRFFXUVꢀZKHQꢀDꢀFROXPQꢀDFFHVVꢒEXUVWꢀLVꢀLQꢀSURJUHVVꢀDQG
&.(ꢀLVꢀUHJLVWHUHGꢀORZꢃꢀ,QꢀWKHꢀFORFNꢀVXVSHQGꢀPRGHꢄꢀWKHꢀLQWHUQDOꢀFORFNꢀLVꢀGHDFWLꢅ
YDWHGꢄꢀ³IUHH]LQJ´ꢀWKHꢀV\QFKURQRXVꢀORJLFꢃ
)RUꢀHDFKꢀSRVLWLYHꢀFORFNꢀHGJHꢀRQꢀZKLFKꢀ&.(ꢀLVꢀVDPSOHGꢀ/RZꢄꢀWKHꢀQH[WꢀLQWHUQDOꢀSRVꢅ
LWLYHꢀFORFNꢀHGJHꢀLVꢀVXVSHQGHGꢃꢀ$Q\ꢀFRPPDQGꢀRUꢀGDWDꢀSUHVHQWꢀRQꢀWKHꢀLQSXWꢀSLQVꢀDW
WKHꢀWLPHꢀRIꢀDꢀVXVSHQGHGꢀLQWHUQDOꢀFORFNꢀHGJHꢀLVꢀLJQRUHGꢕꢀDQ\ꢀGDWDꢀSUHVHQWꢀRQꢀWKH
'4ꢀSLQVꢀUHPDLQVꢀGULYHQꢕꢀDQGꢀEXUVWꢀFRXQWHUVꢀDUHꢀQRWꢀLQFUHPHQWHGꢄꢀDVꢀORQJꢀDVꢀWKH
FORFNꢀLVꢀVXVSHQGHGꢃꢀꢁ6HHꢀH[DPSOHVꢀLQꢀ)LJXUH ꢍꢈꢃꢍꢄꢀDQGꢀ)LJXUH ꢍꢈꢃꢊꢃꢂ
&ORFNꢀVXVSHQGꢀPRGHꢀLVꢀH[LWHGꢀE\ꢀUHJLVWHULQJꢀ&.(ꢀ+LJKꢕꢀWKHꢀLQWHUQDOꢀFORFNꢀDQGꢀUHꢅ
ODWHGꢀRSHUDWLRQꢀZLOOꢀUHVXPHꢀRQꢀWKHꢀVXEVHTXHQWꢀSRVLWLYHꢀFORFNꢀHGJHꢃ
47.8 Burst Read/Single Write
7KHꢀEXUVWꢀUHDGꢒVLQJOHꢀZULWHꢀPRGHꢀLVꢀHQWHUHGꢀE\ꢀSURJUDPPLQJꢀWKHꢀZULWHꢀEXUVW
PRGHꢀELWꢀꢁ0ꢉꢂꢀLQꢀWKHꢀPRGHꢀUHJLVWHUꢀWRꢀDꢀORJLFꢀꢇꢃꢀ,QꢀWKLVꢀPRGHꢄꢀDOOꢀ:ULWHꢀFRPPDQGV
UHVXOWꢀLQꢀWKHꢀDFFHVVꢀRIꢀDꢀVLQJOHꢀFROXPQꢀORFDWLRQꢀꢁEXUVWꢀRIꢀRQHꢂꢄꢀUHJDUGOHVVꢀRIꢀWKH
SURJUDPPHGꢀEXUVWꢀOHQJWKꢃꢀ5HDGꢀFRPPDQGVꢀDFFHVVꢀFROXPQVꢀDFFRUGLQJꢀWRꢀWKHꢀSURꢅ
JUDPPHGꢀEXUVWꢀOHQJWKꢀDQGꢀVHTXHQFHꢄꢀMXVWꢀDVꢀLQꢀWKHꢀQRUPDOꢀPRGHꢀRIꢀRSHUDWLRQ
ꢁ0ꢉꢀ ꢀꢌꢂꢃ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
131
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
BANK,
COLn
D
n
IN
D
n + 1
IN
DIN
n + 2
DIN
DON’T CARE
Figure 47.4. Clock Suspend During Write Burst
Ir)ꢂ)RUꢂWKLVꢂH[DPSOHꢄꢂEXUVWꢂOHQJWKꢂ ꢂꢎꢂRUꢂJUHDWHUꢄꢂDQGꢂ'0ꢂLVꢂORZꢁ
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
DON’T CARE
Figure 47.5. Clock Suspend During Read Burst
Ir)ꢂ)RUꢂWKLVꢂH[DPSOHꢄꢂ&$6ꢂODWHQF\ꢂ ꢂꢆꢄꢂEXUVWꢂOHQJWKꢂ ꢂꢎꢂRUꢂJUHDWHUꢄꢂDQGꢂ'40ꢂLVꢂORZꢁ
47.9 Concurrent Auto Precharge
7KHꢀ6'5$0ꢀGHYLFHVꢀVXSSRUWꢀ&RQFXUUHQWꢀ$XWRꢀSUHFKDUJHꢄꢀZKLFKꢀDOORZVꢀDQꢀDFFHVV
FRPPDQGꢀꢁ5HDGꢀRUꢀ:ULWHꢂꢀWRꢀDQRWKHUꢀEDQNꢀZKLOHꢀDQꢀDFFHVVꢀFRPPDQGꢀZLWKꢀDXWR
SUHFKDUJHꢀHQDEOHGꢀLVꢀH[HFXWLQJꢃꢀ)RXUꢀFDVHVꢀZKHUHꢀFRQFXUUHQWꢀDXWRꢀSUHFKDUJHꢀRFꢅ
FXUVꢀDUHꢀGHILQHGꢀEHORZꢃ
ꢒꢆꢎꢐꢎꢄ 5HDGꢀZLWKꢀ$XWRꢀ3UHFKDUJH
ꢇꢃ ,QWHUUXSWHGꢀE\ꢀDꢀ5HDGꢀꢁZLWKꢀRUꢀZLWKRXWꢀDXWRꢀSUHFKDUJHꢂꢆꢀ$ꢀ5HDGꢀWRꢀEDQNꢀP
ZLOOꢀLQWHUUXSWꢀDꢀ5HDGꢀRQꢀEDQNꢀQꢄꢀWZRꢀRUꢀWKUHHꢀFORFNVꢀODWHUꢄꢀGHSHQGLQJꢀRQꢀ&$6
ODWHQF\ꢃꢀ7KHꢀSUHFKDUJHꢀWRꢀEDQNꢀQꢀZLOOꢀEHJLQꢀZKHQꢀWKHꢀ5HDGꢀWRꢀEDQNꢀPꢀLVꢀUHJꢅ
LVWHUHGꢀꢁ)LJXUH ꢍꢈꢃꢎꢂꢃ
ꢏꢃ ,QWHUUXSWHGꢀE\ꢀDꢀ:ULWHꢀꢁZLWKꢀRUꢀZLWKRXWꢀDXWRꢀSUHFKDUJHꢂꢆꢀ:KHQꢀDꢀ:ULWHꢀWR
EDQNꢀPꢀUHJLVWHUVꢄꢀDꢀ5HDGꢀRQꢀEDQNꢀQꢀZLOOꢀEHꢀLQWHUUXSWHGꢃꢀ'40ꢀVKRXOGꢀEHꢀXVHG
WZRꢀFORFNVꢀSULRUꢀWRꢀWKHꢀ:ULWHꢀFRPPDQGꢀWRꢀSUHYHQWꢀEXVꢀFRQWHQWLRQꢃꢀ7KHꢀSUHꢅ
132
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
FKDUJHꢀWRꢀEDQNꢀQꢀZLOOꢀEHJLQꢀZKHQꢀWKHꢀ:ULWHꢀWRꢀEDQNꢀPꢀLVꢀUHJLVWHUHG
ꢁ)LJXUH ꢍꢈꢃꢈꢂꢃ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANKn
READ - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
t
RP - BANKn
RP - BANKm
Internal
States
Page Active
READ with Burst of 4
Precharge
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
DQ
D
a
OUT
D
a + 1
OUT
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANKm)
DON’T CARE
Figure 47.6. Read with Auto Precharge Interrupted by a Read
Ir)ꢂ'40ꢂLVꢂORZꢁ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANKn
WRITE - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
Idle
WR -BANKm
Active
t
RP -BANK
n
Internal
States
WRITE with Burst of 4
Write-Back
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
1
DQM
D
OUT
DIN
d
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
DQ
a
CAS Latency = 3 (BANKn)
DON’T CARE
Figure 47.7. Read with Auto Precharge Interrupted by a Write
Ir)ꢂ'40ꢂLVꢂKLJKꢂDWꢂ7ꢆꢂWRꢂSUHYHQWꢂ'
ꢃDꢓꢀꢂIURPꢂFRQWHQGLQJꢂZLWKꢂ' ꢃGDWꢂ7ꢎꢁ
,1
287
47.10 Write with Auto Precharge
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EDQNꢀPꢀUHJLVWHUVꢄꢀLWꢀZLOOꢀLQWHUUXSWꢀDꢀ:ULWHꢀRQꢀEDQNꢀQꢄꢀZLWKꢀWKHꢀGDWDꢅRXWꢀDSꢅ
SHDULQJꢀꢏꢀRUꢀꢑꢀFORFNVꢀODWHUꢄꢀꢁGHSHQGLQJꢀRQꢀ&$6ꢀODWHQF\ꢂꢃꢀ7KHꢀSUHFKDUJHꢀWR
EDQNꢀQꢀZLOOꢀEHJLQꢀDIWHUꢀW:5ꢀLVꢀPHWꢄꢀZKHUHꢀW:5ꢀEHJLQVꢀZKHQꢀWKHꢀ5HDGꢀWRꢀEDQN
PꢀLVꢀUHJLVWHUHGꢃꢀ7KHꢀODVWꢀYDOLGꢀ:ULWHꢀWRꢀEDQNꢀQꢀZLOOꢀEHꢀGDWDꢅLQꢀUHJLVWHUHGꢀRQH
FORFNꢀSULRUꢀWRꢀWKHꢀ5HDGꢀWRꢀEDQNꢀPꢀꢁ)LJXUH ꢍꢈꢃꢋꢂꢃ
ꢏꢃ ,QWHUUXSWHGꢀE\ꢀDꢀ:ULWHꢀꢁZLWKꢀRUꢀZLWKRXWꢀDXWRꢀSUHFKDUJHꢂꢆꢀ:KHQꢀDꢀ:ULWHꢀWR
EDQNꢀPꢀUHJLVWHUVꢄꢀLWꢀZLOOꢀLQWHUUXSWꢀDꢀ:ULWHꢀRQꢀEDQNꢀQꢃꢀ7KHꢀSUHFKDUJHꢀWRꢀEDQN
QꢀZLOOꢀEHJLQꢀDIWHUꢀW:5ꢀLVꢀPHWꢄꢀZKHUHꢀW:5ꢀEHJLQVꢀZKHQꢀWKHꢀ:ULWHꢀWRꢀEDQNꢀPꢀLV
UHJLVWHUHGꢃꢀ7KHꢀODVWꢀYDOLGꢀGDWDꢀ:ULWHꢀWRꢀEDQNꢀQꢀZLOOꢀEHꢀGDWDꢀUHJLVWHUHGꢀRQH
FORFNꢀSULRUꢀWRꢀDꢀ:ULWHꢀWRꢀEDQNꢀPꢀꢁ)LJXUH ꢍꢈꢃꢉꢂꢃ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
133
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANKn
READ - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back Precharge
t
RP - BANKn
t
WR - BANKn
Internal
States
t
RP - BANKm
Page Active
READ with Burst of 4
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
DQ
DIN
a
D
a + 1
IN
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANKm)
DON’T CARE
Figure 47.8. Write with Auto Precharge Interrupted by a Read
Ir)ꢂ'40ꢂLVꢂORZꢁ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANKn
WRITE - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back Precharge
t
RP - BANKn
t
WR - BANKn
Internal
States
t
WR - BANKm
Write-Back
Page Active
WRITE with Burst of 4
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
DQ
DIN
a
D
a + 1
IN
D
a + 2
IN
DIN
d
D
d + 1
IN
D
d + 2
IN
D
d + 3
IN
DON’T CARE
Figure 47.9. Write with Auto Precharge Interrupted by a Write
Ir)ꢂ'40ꢂLVꢂORZꢁ
134
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
&RPPDQGꢀ,QRKZLEHLUWꢅ
'RURZ12Qꢀ3(3QWU\
P r e l i m i n a r y
Table 47.1 Truth Table 2 - CKE
&.(Qꢇꢄ
&.(Q
&XUUHQWꢀ6WDWH
3RZHUꢅ'RZQ
&RPPDQGQ
$FWLRQQ
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;
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0DLQWDLQꢀ'HHSꢀ3RZHUꢅ'RZQ
([LWꢀ3RZHUꢅ'RZQ
6HOIꢀ5HIUHVK
;
/
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3RZHUꢅ'RZQ
;
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;
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6HOIꢀ5HIUHVK
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;
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6HOIꢀ5HIUHVKꢀ(QWU\
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+
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Q
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ꢆꢁ &XUUHQWꢂVWDWHꢂLVꢂWKHꢂVWDWHꢂRIꢂWKHꢂ6'5$0ꢂLPPHGLDWHO\ꢂSULRUꢂWRꢂFORFNꢂHGJHꢂQꢁ
ꢊꢁ &RPPDQG ꢂLVꢂWKHꢂFRPPDQGꢂUHJLVWHUHGꢂDWꢂFORFNꢂHGJHꢂQꢄꢂDQGꢂ$FWLRQ ꢂLVꢂDꢂUHVXOWꢂRIꢂ
Q
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ꢎꢁ $OOꢂVWDWHVꢂDQGꢂVHTXHQFHVꢂQRWꢂVKRZQꢂDUHꢂLOOHJDOꢂRUꢂUHVHUYHGꢁ
ꢉꢁ ([LWLQJꢂSRZHUꢃGRZQꢂDWꢂFORFNꢂHGJHꢂQꢂZLOOꢂSXWꢂWKHꢂGHYLFHꢂLQꢂWKHꢂDOOꢂEDQNVꢂLGOHꢂVWDWHꢂ
LQꢂWLPHꢂIRUꢂFORFNꢂHGJHꢂQꢂꢓꢂꢀꢂꢏSURYLGHGꢂWKDWꢂW ꢂLVꢂPHWꢐꢁ
&.6
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RQFHꢂW ꢂLVꢂPHWꢁꢂ&RPPDQGꢂ,QKLELWꢂRUꢂ123ꢂFRPPDQGVꢂVKRXOGꢂEHꢂLVVXHGꢂRQꢂDQ\ꢂ
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LVꢂORZꢁ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
135
P r e l i m i n a r y
Table 47.2 Truth Table 3 - Current State Bank n, Command to Bank n
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138
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
48 Absolute Maximum Ratings
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Table 48.1 DC Electrical Characteristics and Operating Conditions
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
139
P r e l i m i n a r y
Table 48.2 AC Electrical Characteristics and Operating Conditions
Parameter
Symbol
9,+
Min
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²
Max
²
Units Notes
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Table 48.3 Electrical Characteristics and Recommended AC Operating
Conditions
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ꢀꢀꢁ'HHSꢂSRZHUꢂGRZQꢂFXUUHQWꢂLVꢂDꢂQRPLQDOꢂYDOXHꢂDWꢂꢆꢉ&ꢁꢂ7KHꢂSDUDPHWHUꢂLVꢂQRWꢂWHVWHGꢁ
Table 48.6 IDD7 - Self Refresh Current Options
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Ir)
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
143
P r e l i m i n a r y
Table 48.7 Capacitance
Parameter
Symbol
Min
ꢇꢃꢊ
ꢇꢃꢊ
ꢑꢃꢌ
Max
ꢍꢃꢌ
ꢍꢃꢌ
ꢎꢃꢌ
Units Notes
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&
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Ir)
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ꢆꢁ 3&ꢀꢈꢈꢂVSHFLILHVꢂDꢂPD[LPXPꢂRIꢂꢎS)ꢁ
ꢊꢁ 3&ꢀꢈꢈꢂVSHFLILHVꢂDꢂPD[LPXPꢂRIꢂꢉS)ꢁ
ꢎꢁ 3&ꢀꢈꢈꢂVSHFLILHVꢂDꢂPD[LPXPꢂRIꢂꢌꢁꢉS)
T1
T0
T3
T5
T7
T9
T19
T29
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CLK
t
CK
t
t
CKS CKH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CKE
COMMAND5
t
t
CMS CMH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
4
4
3
4
4
4
NOP
PRE
LMR
LMR
PRE
AR
AR
ACT
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQML, DQMU
t
t
AS AH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
A10
CODE
CODE
CODE
RA
RA
BA
ALL BANKS
ALL BANKS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
t
AS
t
AH
t
t
AH
t
t
AS
AS
AH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = H
BA0 = L,
BA1 = L
BA0, BA1
DQ
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
((
))
T = 100μs
t
t
t
t
RP
t
t
RFC
RP
MRD
MRD
RFC
Power-up:
VDD and
CLK stable
Load Extended
Mode Register
Load Mode
Register
DON’T CARE
Figure 48.1 Initialize and Load Mode Register
Ir)
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0RGHꢂ5HJLVWHUꢂꢏ/05ꢐꢂFRPPDQGꢁ
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IUHVKꢂFRPPDQGꢄꢂ$&7ꢂ ꢂ$FWLYHꢂFRPPDQGꢄꢂ5$ꢂ ꢂ5RZꢂ$GGUHVVꢄꢂ%$ꢂ ꢂ%DQNꢂ$GGUHVVꢁ
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LQꢂDQ\ꢂRUGHUꢁꢂ+RZHYHUꢄꢂDOOꢂPXVWꢂRFFXUꢂSULRUꢂWRꢂDQꢂ$FWLYHꢂFRPPDQGꢁ
ꢉꢁ 'HYLFHꢂWLPLQJꢂLVꢂꢃꢀꢈꢂZLWKꢂꢀꢈꢎꢂ0+]ꢂFORFNꢁ
144
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
Tn + 1
Tn + 2
((
))
((
))
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS
CKS
((
))
t
t
CKS CKH
t
t
CMS CMH
((
))
((
))
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
((
))
((
))
DQML, DQMU
((
))
((
))
A0-A9, A11
A10
ROW
ROW
ALL BANKS
((
))
((
))
SINGLE BANK
t
t
AS AH
((
))
((
))
BA0, BA1
DQ
BANK
BANK(S)
High-Z
((
))
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
Figure 48.2. Power Down Mode
Ir)ꢂ9LRODWLQJꢂUHIUHVKꢂUHTXLUHPHQWVꢂGXULQJꢂSRZHUꢃGRZQꢂPD\ꢂUHVXOWꢂLQꢂDꢂORVVꢂRIꢂGDWDꢁ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
145
P r e l i m i n a r y
MOBILE SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
2
COLUMNm
COLUMNe
t
AS
t
AH
A10
t
AS
t
AH
BA0, BA1
BANK
BANK
t
AC
t
AC
t
OH
t
HZ
t
DS
t
DH
DOUT
m
DOUT m + 1
DOUT
e
DOUT e + 1
DQ
t
LZ
DON’T CARE
UNDEFINED
Figure 48.3. Clock Suspend Mode
Ir)
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LVꢂGLVDEOHGꢁ
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146
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
Tn + 1
CL
To + 1
((
))
((
))
t
CLK
CKE
t
t
((
((
CK
CH
))
))
((
))
((
))
t
t
CKS
CKH
t
t
CMS
CMH
((
))
((
))
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
((
((
))
))
((
))
((
))
DQMU, DQML
((
((
))
))
((
))
((
))
((
))
((
))
A0-A9, A11
A10
ROW
ROW
ALL BANKS
((
))
((
))
((
))
((
))
SINGLE BANK
t
t
AH
AS
((
))
((
))
BA0, BA1
DQ
BANK(S)
BANK
((
((
))
))
High-Z
((
))
((
))
t
t
t
RFC
1
1
RP
RFC
Precharge all
active banks
DON’T CARE
Figure 48.4. Auto Refresh Mode
Ir)ꢂ(DFKꢂ$XWRꢂ5HIUHVKꢂFRPPDQGꢂSHUIRUPVꢂDꢂUHIUHVKꢂF\FOHꢁꢂ%DFNꢃWRꢃEDFNꢂFRPꢃ
PDQGVꢂDUHꢂQRWꢂUHTXLUHGꢁ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
147
P r e l i m i n a r y
T0
T1
T2
Tn + 1
((
To + 1
To + 2
((
))
t
CL
))
CLK
CKE
t
((
))
((
))
t
CK
CH
t
> t
CKS
RAS
((
))
((
))
((
))
t
t
CKS CKH
t
t
CMS
CMH
((
((
))
((
))
))
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
((
))
((
))
((
))
((
))
((
))
DQMU, DQML
((
))
((
))
((
))
((
))
A0-A9, A11
A10
ALL BANKS
((
))
((
))
((
))
((
))
SINGLE BANK
t
t
AS AH
((
))
((
))
((
))
((
))
BA0, BA1
DQ
BANK(S)
High-Z
((
))
((
))
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
Figure 48.5. Self Refresh Mode
Ir)ꢂ(DFKꢂ$XWRꢂ5HIUHVKꢂFRPPDQGꢂSHUIRUPVꢂDꢂUHIUHVKꢂF\FOHꢁꢂ%DFNꢃWRꢃEDFNꢂFRPꢃ
PDQGVꢂDUHꢂQRWꢂUHTXLUHGꢁ
148
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
ROW
t
t
CMS CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
ROW
COLUMNm
t
AS
t
AH
ALL BANKS
ROW
ROW
A10
SINGLE BANKS
BANK(S)
DISABLE AUTO PRECHARGE
BANK
t
AS
t
AH
BA0, BA1
BANK
BANK
t
AC
t
AC
t
AC
t
AC
t
t
t
t
OH
OH
OH
OH
DOUT
m
DOUT m+1
D
OUT m+2
DOUT m+3
DQ
t
LZ
t
HZ
t
t
RP
RCD
CAS Latency
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 48.6. Read - Without Auto Precharge
Ir)
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LVꢂIROORZHGꢂE\ꢂDꢂ³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
149
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS CMH
COMMAND
DQMU, DQML
A0-A9, A11
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
t
t
AH
AS
2
ROW
ROW
COLUMNm
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
BANK
t
t
t
AC
AC
AC
t
AC
t
t
t
t
OH
OH
OH
OH
DOUT
m
DOUT
m
+ 1
DOUT
m
+ 2
DOUT m
+ 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 48.7. Read - With Auto Precharge
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
150
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS CMH
3
3
COMMAND
PRECHARGE
ACTIVE
NOP
READ
NOP
NOP
NOP
ACTIVE
ROW
NOP
t
t
CMS CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
ROW
COLUMNm
t
t
AH
AS
ALL BANKS
ROW
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANKS
BANK(S)
t
t
AH
AS
BA0, BA1
BANK
BANK
t
t
OH
AC
D
OUT m
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 48.8. Single Read - Without Auto Precharge
Ir)
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LVꢂIROORZHGꢂE\ꢂDꢂ³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
ꢊꢁ 3UHFKDUJHꢂFRPPDQGꢂQRWꢂDOORZHGꢂRUꢂW
ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
151
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS CMH
3
3
COMMAND
DQMU, DQML
A0-A9, A11
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
t
CMS
CMH
t
t
AH
AS
2
ROW
ROW
COLUMNm
t
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
AS
t
AH
BA0, BA1
BANK
BANK
BANK
t
AC
t
OH
DOUT
m
t
DQ
t
CAS Latency
RCD
HZ
t
t
RP
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 48.9. Single Read - With Auto Precharge
Ir)
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LVꢂIROORZHGꢂE\ꢂDꢂ³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
ꢊꢁ 3UHFKDUJHꢂFRPPDQGꢂQRWꢂDOORZHGꢂRUꢂW
ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
152
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
t
CH
t
t
CKS CKH
CKE
COMMAND
t
t
CMS
CMH
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
AS
t
AH
2
2
ROW
ROW
ROW
COLUMNm
COLUMNb
t
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
ROW
A10
t
AS
t
AH
BA0, BA1
BANK 0
BANK 0
BANK 3
BANK 3
BANK 0
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
DOUT
m
DOUT m +
1
DOUT m +
2
DOUT m+
3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RCD - BANK 0
CAS Latency - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 3
CAS Latency - BANK 3
RRD
DON’T CARE
UNDEFINED
Figure 48.10. Alternating Bank Read Accesses
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
153
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
((
))
((
))
t
CL
t
CK
CLK
t
CH
t
t
CKS CKH
((
))
CKE
((
))
t
t
CMS
CMH
((
))
((
))
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
CMS
CMH
((
))
DQMU, DQML
A0-A9, A11
((
))
t
AS
t
AH
((
))
((
))
2
ROW
COLUMN m
t
AS
t
AH
((
))
((
))
ROW
A10
t
AS
t
AH
((
))
((
))
BA0, BA1
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC ((
AC
))
t
AC
t
t
t
OH
t
t
t
OH
OH
OH
OH
OH
((
))
((
))
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
DOUT
m
DOUT m+1
DQ
t
LZ
t
HZ
256 (x16) locations within same row
t
RCD
CAS Latency
Full page completed
DON’T CARE
UNDEFINED
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.3
Figure 48.11. Read - Full-Page Burst
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
ꢊꢁ 3DJHꢂOHIWꢂRSHQꢇꢂQRꢂW
ꢁ
53
154
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQMU, DQML
t
t
AS AH
2
A0-A9, A11
A10
ROW
COLUMNm
t
t
AS AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
BANK
t
t
AS AH
BA0, BA1
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
D
OUT
m
DOUT m + 2
DOUT m + 3
DQ
t
LZ
t
t
t
HZ
LZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
Figure 48.12. Read - DQM Operation
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
155
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
t
t
AH
AS
3
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
Figure 48.13. Write - Without Auto Precharge
Ir)
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³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢆꢁ ꢀꢉQVꢂLVꢂUHTXLUHGꢂEHWZHHQꢂꢕ',1ꢂPꢂꢓꢂꢊ!ꢂDQGꢂWKHꢂ3UHFKDUJHꢂFRPPDQGꢄꢂUHJDUGOHVVꢂ
RIꢂIUHTXHQF\ꢁ
ꢊꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
DQMU, DQML
A0-A9, A11
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
t
t
t
t
AH
AS
2
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
AS
AH
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
Figure 48.14. Write - With Auto Precharge
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
156
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
t
t
AH
AS
3
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
Figure 48.15. Single Write - Without Auto Precharge
Ir)
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³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢆꢁ ꢀꢉQVꢂLVꢂUHTXLUHGꢂEHWZHHQꢂꢕ',1ꢂP!ꢂDQGꢂWKHꢂ3UHFKDUJHꢂFRPPDQGꢄꢂUHJDUGOHVVꢂRIꢂ
IUHTXHQF\ꢁ
ꢊꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
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ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
157
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
3
3
3
NOP
COMMAND
NOP
ACTIVE
ACTIVE
NOP
NOP
WRITE
t
NOP
NOP
NOP
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
t
t
AH
AS
2
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
AS
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
DINm
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
Figure 48.16. Single Write with Auto Precharge
Ir)
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³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢆꢁ ꢀꢉQVꢂLVꢂUHTXLUHGꢂEHWZHHQꢂꢕ',1ꢂP!ꢂDQGꢂWKHꢂ3UHFKDUJHꢂFRPPDQGꢄꢂUHJDUGOHVVꢂRIꢂ
IUHTXHQF\ꢁ
ꢊꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
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ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
158
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
2
ROW
ROW
ROW
ROW
ROW
COLUMNm
COLUMNb
t
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
AS
t
AH
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DIN
b
DINb + 1
DINb + 2
DINb + 3
DQ
t
t
t
RCD - BANK 0
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
DON’T CARE
Figure 48.17. Alternating Bank Write Accesses
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
159
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
((
))
((
))
t
t
CK
CL
CLK
t
CH
t
t
CKS CKH
((
))
CKE
((
))
t
t
CMS
CMH
((
))
((
))
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
((
))
DQMU, DQML
A0-A9, A11
((
))
t
t
AH
AS
((
))
((
))
1
ROW
COLUMNm
t
t
AH
AS
((
))
((
))
ROW
A10
t
t
AH
AS
((
))
((
))
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH ((
DS
DH
))
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DINm- 1
DQ
((
))
t
RCD
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
512 (x16) locations within same row
Full page completed
DON’T CARE
2, 3
command to stop.
Figure 48.18. Write - Full Page Burst
Ir)
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:5
ꢊꢁ 3DJHꢂOHIWꢂRSHQꢇꢂQRꢂW
ꢁ
53
160
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQMU, DQML
t
t
AS AH
2
A0-A9, A11
ROW
COLUMNm
t
t
AS AH
ENABLE AUTO PRECHARGE
ROW
A10
t
t
DISABLE AUTO PRECHARGE
BANK
AS AH
BA0, BA1
BANK
t
t
t
t
t
t
DS DH
DS DH
DS DH
DIN m
DIN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
Figure 48.19. Write - DQM Operation
Ir)
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ꢆꢁ $ꢒꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
161
P r e l i m i n a r y
49 Revision Summary
49.1 Revision A0 (April 1, 2005)
,QLWLDOꢀ5HOHDVH
49.2 Revision A1 (April 25, 2005)
$GGHGꢀꢇꢑꢑ 0+]ꢀVSHHGꢀJUDGHꢀRSWLRQ
49.3 Revision A2 (April 25, 2005)
$GGHGꢀUHYLVLRQꢀKLVWRU\
49.4 Revision A3 (April 25, 2005)
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&RQGLWLRQVꢀWDEOHꢃ
162
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
Mobile SDRAM Type 2
2M x 16Bit x 4 Banks SDRAM
PRELIMINARY
Features
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%XUVWꢀW\SHꢀꢁ6HTXHQWLDOꢀꢓꢀ,QWHUOHDYHꢂꢃ
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3$65ꢀꢁ3DUWLDOꢀ$UUD\ꢀ6HOIꢀ5HIUHVKꢂꢃ
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([WHQGHGꢀ7HPSHUDWXUHꢀ2SHUDWLRQꢀꢂꢇꢈꢉ&ꢀaꢀꢏꢉ&ꢃ
Publication Number SDRAM_00 Revision A Amendment 0 Issue Date May 25, 2004
P r e l i m i n a r y n
50 Absolute Maximum Ratings
Parameter
9ROWDJHꢀRQꢀDQ\ꢀSLQꢀUHODWLYHꢀWRꢀ966
9ROWDJHꢀRQꢀ9''ꢀVXSSO\ꢀUHODWLYHꢀWRꢀ966
6WRUDJHꢀWHPSHUDWXUH
Symbol
9,1ꢄꢀ9287
9''ꢄꢀ9''4
767*
Value
Unit
9
ꢅꢇꢃꢌꢀaꢀꢏꢃꢎ
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9
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3'
6KRUWꢀFLUFXLWꢀFXUUHQW
,
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26
Ir)
ꢀꢁ 3HUPDQHQWꢂGHYLFHꢂGDPDJHꢂPD\ꢂRFFXUꢂLIꢂ$%62/87(ꢂ0$;,080ꢂ5$7,1*6ꢂDUHꢂH[FHHGHGꢁ
ꢆꢁ )XQFWLRQDOꢂRSHUDWLRQꢂVKRXOGꢂEHꢂUHVWULFWHGꢂWRꢂUHFRPPHQGHGꢂRSHUDWLQJꢂFRQGLWLRQꢁ
ꢊꢁ ([SRVXUHꢂWRꢂKLJKHUꢂWKDQꢂUHFRPPHQGHGꢂYROWDJHꢂIRUꢂH[WHQGHGꢂSHULRGVꢂRIꢂWLPHꢂFRXOGꢂDIIHFWꢂGHYLFHꢂ
UHOLDELOLW\ꢁ
51 DC Operating Conditions
5HFRPPHQGHGꢀRSHUDWLQJꢀFRQGLWLRQVꢀꢁ9ROWDJHꢀUHIHUHQFHGꢀWRꢀ966ꢀ ꢀꢌ9ꢄꢀ7$ꢀ ꢀꢅꢏꢊ&ꢀaꢀꢐꢋꢊ&ꢃ
Parameter
6XSSO\ꢀYROWDJH
Symbol
9''
Min
ꢇꢃꢎꢊ
Typ
ꢇꢃꢋ
ꢇꢃꢋ
ꢇꢃꢋ
ꢌ
Max
ꢇꢃꢉꢊ
ꢇꢃꢉꢊ
9''4ꢀꢐꢀꢌꢃꢑ
ꢌꢃꢑ
Unit
Note
9''4
9,+
ꢇꢃꢎꢊ
,QSXWꢀORJLFꢀKLJKꢀYROWDJH
,QSXWꢀORJLFꢀORZꢀYROWDJH
2XWSXWꢀORJLFꢀKLJKꢀYROWDJH
2XWSXWꢀORJLFꢀORZꢀYROWDJH
,QSXWꢀOHDNDJHꢀFXUUHQW
ꢌꢃꢋꢀ[ꢀ9''4
ꢅꢌꢃꢑ
ꢇ
9
9,/
ꢏ
92+
92/
9''4ꢀꢅꢌꢃꢏ
²
²
²
,
2+ꢀ ꢀꢅꢌꢃꢇP$
²
ꢌꢃꢏ
,2/ꢀ ꢀꢌꢃꢇP$
,
ꢅꢇꢌ
²
ꢇꢌ
$
/,
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ꢀꢁ 9 ꢂꢏPD[ꢐꢂ ꢂꢆꢁꢆ9ꢂ$&ꢁ7KHꢂRYHUVKRRWꢂYROWDJHꢂGXUDWLRQꢂLVꢂ≤ꢂꢊQVꢁ
,+
ꢆꢁ 9 ꢂꢏPLQꢐꢂ ꢂꢃꢀꢁꢈ9ꢂ$&ꢁꢂ7KHꢂXQGHUVKRRWꢂYROWDJHꢂGXUDWLRQꢂLVꢂ≤ꢂꢊQVꢁ
,/
ꢊꢁ $Q\ꢂLQSXWꢂꢈ9ꢂ≤ꢂ9 ꢂ≤ꢂ9
ꢁꢂ,QSXWꢂOHDNDJHꢂFXUUHQWVꢂLQFOXGHꢂ+Lꢃ=ꢂRXWSXWꢂOHDNDJHꢂIRUꢂDOOꢂELꢃGLUHFWLRQDOꢂ
EXIIHUVꢂZLWKꢂWULꢃVWDWHꢂRXWSXWVꢁ
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ꢎꢁ 'RXWꢂLVꢂGLVDEOHGꢄꢂꢈ9ꢂ≤ 9 ꢂ≤ꢂ9
ꢁ
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287
52 Capacitance
ꢁ9''ꢀ ꢀꢇꢃꢋ9ꢄꢀ7$ꢀ ꢀꢏꢑ&ꢄꢀIꢀ ꢀꢇ0+]ꢄꢀ95()ꢀ ꢌꢃꢉ9ꢀꢀꢊꢌꢀP9ꢂ
Pin
Symbol
Min
ꢏꢃꢌ
ꢏꢃꢌ
ꢏꢃꢌ
ꢑꢃꢌ
Max
ꢍꢃꢌ
ꢍꢃꢌ
ꢍꢃꢌ
ꢎꢃꢌ
Unit
Note
&ORFN
&
&/.
5$6ꢔꢄꢀ&$6ꢔꢄꢀ:(ꢔꢄꢀ&6ꢔꢄꢀ&.(ꢄꢀ'40
$GGUHVV
&
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&
287
164
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
53 DC Characteristics
Parameter
Symbol
Test Condition
Value Unit Note
%XUVWꢀOHQJWKꢀ ꢀꢇ
5&ꢀ≥ W5&ꢀꢁPLQꢂ
2ꢀ ꢀꢌꢀP$
2SHUDWLQJꢀ&XUUHQWꢀꢁ2QHꢀ%DQNꢀ$FWLYHꢂ
,
W
,
ꢑꢊ
P$
ꢇ
&&ꢇ
,
&&ꢏ3&.(ꢀ ≤ 9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀꢇꢌQV
ꢌꢃꢑ
ꢌꢃꢑ
P$
P$
3UHFKDUJHꢀ6WDQGE\ꢀ&XUUHQWꢀLQꢀSRZHUꢅ
GRZQꢀPRGH
,
&&ꢏ36 &.(ꢀꢓꢀ&/.ꢀ≤ꢀ9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀ∞
&.(ꢀ≥ꢀ9,+ꢁPLQꢂꢄꢀ&6ꢔꢀ≥ꢀ9,+ꢁPLQꢂꢄꢀW&&ꢀ ꢀꢇꢌQVꢀ,QSXWꢀ
,
&&ꢏ1
ꢇꢌ
ꢇ
P$
P$
VLJQDOVꢀDUHꢀFKDQJHGꢀRQHꢀWLPHꢀGXULQJꢀꢏꢌQV
3UHFKDUJHꢀ6WDQGE\ꢀ&XUUHQWꢀLQꢀQRQꢀ
SRZHUꢅGRZQꢀPRGH
&.(ꢀ≥ꢀ9,+ꢁPLQꢂꢄꢀ&/.ꢀ≤ꢀ9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀ∞
,QSXWꢀVLJQDOVꢀDUHꢀVWDEOH
,
&&ꢏ16
,
&&ꢑ3&.(ꢀ ≤ꢀ9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀꢇꢌQV
ꢊ
ꢇ
P$
P$
$FWLYHꢀ6WDQGE\ꢀ&XUUHQWꢀLQꢀSRZHUꢅ
GRZQꢀPRGH
,
&&ꢑ36 &.(ꢀꢓꢀ&/.ꢀ≤ꢀ9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀ∞
&.(ꢀ≥ꢀ9,+ꢁPLQꢂꢄꢀ&6ꢀ≥ꢀ9,+ꢁPLQꢂꢄꢀW&&ꢀ ꢀꢇꢌQV
,
&&ꢑ1
ꢏꢌ
ꢊ
P$
P$
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$FWLYHꢀ6WDQGE\ꢀ&XUUHQWꢀLQꢀQRQꢀSRZHUꢅ
GRZQꢀPRGHꢀꢁ2QHꢀ%DQNꢀ$FWLYHꢂ
&.(ꢀ≥ꢀ9,+ꢁPLQꢂꢄꢀ&/.ꢀ≤ꢀ9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀ∞
,QSXWꢀVLJQDOVꢀDUHꢀVWDEOH
,
&&ꢑ16
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3DJHꢀEXUVW
2SHUDWLQJꢀ&XUUHQWꢀꢁ%XUVWꢀ0RGHꢂ
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,
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&&ꢍ
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P$
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ꢏ
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W&&'ꢀ ꢀꢏ&/.V
&&ꢊ
W$5)&ꢀ≥ꢀW$5)&ꢁPLQꢂ
Internal TCSR
)XOOꢀ$UUD\
Max 40 °C
ꢇꢌꢌ
6HOIꢀ5HIUHVKꢀ&XUUHQW
,
&&ꢎ
&.(ꢀ≤ꢀꢌꢃꢏ9
ꢇꢒꢏꢀRIꢀIXOOꢀDUUD\
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ꢉꢌ
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ꢆꢁ 5HIUHVKꢂSHULRGꢂLVꢂꢌꢎPVꢁ
ꢊꢁ 8QOHVVꢂRWKHUZLVHꢂQRWHGꢄꢂLQSXWꢂVZLQJꢂ,HYH,ꢂLVꢂ&026ꢏ9 ꢂꢍ9 9
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,+
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54 AC Operating Test Conditions
9''ꢀ ꢀꢇꢃꢋ9ꢀꢀꢌꢃꢇꢊ9ꢄꢀ7$ꢀ ꢀꢅꢏꢊ&ꢀaꢀꢐꢋꢊ&
Parameter
Value
Unit
$&ꢀLQSXWꢀOHYHOVꢀꢁ9,+ꢒ9,/
ꢂ
ꢌꢃꢉꢀ[ꢀ9''4ꢀꢒꢀꢌꢃꢏ
ꢌꢃꢊꢀ[ꢀ9''4
9
,QSXWꢀWLPLQJꢀPHDVXUHPHQWꢀUHIHUHQFHꢀOHYHO
,QSXWꢀULVHꢀDQGꢀIDOOꢀWLPH
WUꢒWIꢀ ꢀꢇꢒꢇ
QV
9
2XWSXWꢀWLPLQJꢀPHDVXUHPHQWꢀUHIHUHQFHꢀOHYHO
2XWSXWꢀORDGꢀFRQGLWLRQ
ꢌꢃꢊꢀ[ꢀ9''4
6HHꢀ)LJXUHꢀꢊꢍꢃꢏ
1.8V
13.9K
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA
VOL (DC) = 0.2V, IOL = 0.1mA
Output
30pF
10.6K
Figure 54.1 DC Output Load Circuit
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
165
P r e l i m i n a r y n
Vtt=0.5 x VDDQ
50
Output
Z0=50
30pF
Figure 54.2 AC Output Load Circuit
55 Operating AC Parameter
ꢁ$&ꢀRSHUDWLQJꢀFRQGLWLRQVꢀXQOHVVꢀRWKHUZLVHꢀQRWHGꢂ
Parameter
5RZꢀDFWLYHꢀWRꢀURZꢀDFWLYHꢀGHOD\
5$6ꢔꢀWRꢀ&$6ꢔꢀGHOD\
Symbol
Value
Unit Note
W
55'ꢁPLQꢂ
5&'ꢁPLQꢂ
ꢇꢉ
W
ꢏꢋꢃꢊ
QV
ꢇ
5RZꢀSUHFKDUJHꢀWLPH
W
53ꢁPLQꢂ
5$6ꢁPLQꢂ
5$6ꢁPD[ꢂ
5&ꢁPLQꢂ
ꢏꢋꢃꢊ
W
ꢎꢌ
5RZꢀDFWLYHꢀWLPH
W
ꢇꢌꢌ
V
QV
5RZꢀF\FOHꢀWLPH
W
ꢋꢋꢃꢊ
ꢇ
ꢏ
/DVWꢀGDWDꢀLQꢀWRꢀURZꢀSUHFKDUJH
/DVWꢀGDWDꢀLQꢀWRꢀ$FWLYHꢀGHOD\
/DVWꢀGDWDꢀLQꢀWRꢀQHZꢀFROꢃꢀDGGUHVVꢀGHOD\
/DVWꢀGDWDꢀLQꢀWRꢀEXUVWꢀVWRS
W
5'/ꢁPLQꢂ
'$/ꢁPLQꢂ
&'/ꢁPLQꢂ
ꢇꢊ
QV
W
W
W5'/ꢀꢐꢀW53
²
ꢇ
ꢇ
&/.
&/.
QV
ꢏ
W%'/ꢁPLQꢂ
$XWRꢀUHIUHVKꢀF\FOHꢀWLPH
W
$5)&ꢁPLQꢂ
65);ꢁPLQꢂ
ꢋꢌ
ꢇꢏꢌ
ꢇ
([LWꢀVHOIꢀUHIUHVKꢀWRꢀDFWLYHꢀFRPPDQG
&ROꢃꢀDGGUHVVꢀWRꢀFROꢃꢀDGGUHVVꢀGHOD\
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1XPEHUꢀRIꢀYDOLGꢀRXWSXWꢀGDWD
1XPEHUꢀRIꢀYDOLGꢀRXWSXWꢀGDWD
W
QV
W
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&/.
ꢑ
ꢍ
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ꢆꢁ 0LQLPXPꢂGHOD\ꢂLVꢂUHTXLUHGꢂWRꢂFRPSOHWHꢂZULWHꢁ
ꢊꢁ $OOꢂSDUWVꢂDOORZꢂHYHU\ꢂF\FOHꢂFROXPQꢂDGGUHVVꢂFKDQJHꢁ
ꢎꢁ ,QꢂFDVHꢂRIꢂURZꢂSUHFKDUJHꢂLQWHUUXSWꢄꢂDXWRꢂSUHFKDUJHꢂDQGꢂUHDGꢂEXUVWꢂVWRSꢁ
166
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
56 AC Characteristics
ꢁ$&ꢀRSHUDWLQJꢀFRQGLWLRQVꢀXQOHVVꢀRWKHUZLVHꢀQRWHGꢂ
Parameter
Symbol
Min
ꢉꢃꢊ
ꢇꢊ
Max
Unit
Note
&/.ꢀF\FOHꢀWLPH
&$6ꢀODWHQF\ ꢑ
&$6ꢀODWHQF\ ꢏ
&$6ꢀODWHQF\ ꢇ
&$6ꢀODWHQF\ ꢑ
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&$6ꢀODWHQF\ ꢇ
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&$6ꢀODWHQF\ ꢏ
&$6ꢀODWHQF\ ꢇ
&/.ꢀF\FOHꢀWLPH
W&&
ꢇꢌꢌꢌ
QV
ꢇ
&/.ꢀF\FOHꢀWLPH
ꢏꢊ
&/.ꢀWRꢀYDOLGꢀRXWSXWꢀGHOD\
&/.ꢀWRꢀYDOLGꢀRXWSXWꢀGHOD\
&/.ꢀWRꢀYDOLGꢀRXWSXWꢀGHOD\
2XWSXWꢀGDWDꢀKROGꢀWLPH
2XWSXWꢀGDWDꢀKROGꢀWLPH
2XWSXWꢀGDWDꢀKROGꢀWLPH
&/.ꢀKLJKꢀSXOVHꢀZLGWK
&/.ꢀORZꢀSXOVHꢀZLGWK
,QSXWꢀVHWXSꢀWLPH
ꢈ
ꢋ
W6$&
QV
QV
ꢇꢄꢀꢏ
ꢏ
ꢏꢌ
W2+
ꢏꢃꢊ
ꢑꢃꢊ
W&+
W&/
ꢑ
ꢑ
ꢑ
ꢑ
ꢏ
W66
W6+
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ꢇꢃꢊ
ꢇ
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QV
&/.ꢀWRꢀRXWSXWꢀLQꢀ/RZꢅ=
&$6ꢀODWHQF\ ꢑ
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ꢆꢁ ,IꢂFORFNꢂULVLQJꢂWLPHꢂLVꢂORQJHUꢂWKDQꢂꢀQVꢄꢂꢏWUꢍꢆꢃꢈꢁꢉꢐQVꢂVKRXOGꢂEHꢂDGGHGꢂWRꢂWKHꢂSDUDPHWHUꢁ
ꢊꢁ $VVXPHGꢂLQSXWꢂULVHꢂDQGꢂIDOOꢂWLPHꢂꢏWUꢂꢗꢂWIꢐꢂ ꢂꢀQVꢁ
,IꢂWUꢂꢗꢂWIꢂLVꢂORQJHUꢂWKDQꢂꢀQVꢄꢂWUDQVLHQWꢂWLPHꢂFRPSHQVDWLRQꢂVKRXOGꢂEHꢂFRQVLGHUHGꢄ
LꢁHꢁꢄꢂ>ꢏWUꢂꢓꢂWIꢐꢍꢆꢃꢀ@QVꢂVKRXOGꢂEHꢂDGGHGꢂWRꢂWKHꢂSDUDPHWHUꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
167
P r e l i m i n a r y n
57 Simplified Truth Table
Command
CKEn-1 CKEn CS# RAS# CAS# WE# DQM BA0,1
A10/AP
A11, A9 ~ A0
Note
ꢇꢄꢀꢏ
ꢑ
5HJLVWHU
0RGHꢀ5HJLVWHUꢀ6HW
$XWRꢀ5HIUHVK
+
;
+
/
/
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;
23ꢀ&2'(
+
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+
;
;
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6HOIꢀ
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5HIUHVK
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;
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ꢑ
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+
;
;
;
;
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+
9
9
5RZꢀ$GGUHVV
/
+
/
ꢍ
ꢍꢄꢀꢊ
ꢍ
&ROXPQ
$GGUHVV
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+
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;
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;
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&ROXPQ
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&ROXPQꢀ
9
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+
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$ꢂQHZꢂFRPPDQGꢂFDQꢂEHꢂLVVXHGꢂDIWHUꢂꢆꢂ&/.ꢂF\FOHVꢂRIꢂ056ꢁ
ꢊꢁ $XWRꢂUHIUHVKꢂIXQFWLRQVꢂDUHꢂWKHꢂVDPHꢂDVꢂ&%5ꢂUHIUHVKꢂRIꢂ'5$0ꢁ
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RSHUDWLRQꢂꢏ:ULWHꢂ'40ꢂODWHQF\ꢂLVꢂꢈꢐꢄꢂEXWꢂLQꢂUHDGꢂRSHUDWLRQꢄꢂLWꢂPDNHVꢂWKHꢂGDWDꢃRXWꢂ+Lꢃ=ꢂVWDWHꢂDIWHUꢂꢆꢂ
&/.ꢂF\FOHVꢁꢂꢏ5HDGꢂ'40ꢂODWHQF\ꢂLVꢂꢆꢐꢁ
58 Mode Register Field Table to Program Modes
Address
BA0 ~ BA1
A11 ~ A10/AP
A9 (Note 2) A8
A7 A6 A5 A4
A3
A2 A1
A0
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056
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168
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
59 Normal MRS Mode
Test Mode
Type
CAS Latency
A6 A5 A4 Latency
Burst Type
Type
Burst Length
A8 A7
A3
ꢌ
A2 A1 A0
BT=0
BT=1
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
0RGHꢀ5HJLVWHUꢀ6HW
5HVHUYHG
ꢌ
ꢌ
ꢌ
ꢌ
ꢇ
ꢇ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
5HVHUYHG
ꢇ
6HTXHQWLDO
ꢌ
ꢌ
ꢌ
ꢌ
ꢇ
ꢇ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢇ
ꢏ
ꢍ
ꢋ
ꢇ
ꢏ
ꢍ
ꢋ
ꢇ
,QWHUOHDYH
5HVHUYHG
ꢏ
Mode Select
5HVHUYHG
ꢑ
BA1 BA0
Mode
Write Burst Length
Length
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG 5HVHUYHG
5HVHUYHG 5HVHUYHG
5HVHUYHG 5HVHUYHG
)XOOꢀ3DJH 5HVHUYHG
6HWWLQJ
IRUꢀ1RUPDO
056
A9
ꢌ
ꢌ
ꢌ
%XUVW
ꢇ
6LQJOHꢀ%LW
Ir)ꢂ)XOOꢂ3DJHꢂ/HQJWKꢂ[ꢂꢀꢌꢔꢂꢌꢎ0Eꢏꢆꢉꢌꢐꢄꢂꢀꢆꢑ0Eꢏꢉꢀꢆꢐꢄꢂꢆꢉꢌ0Eꢏꢉꢀꢆꢐꢄꢂꢉꢀꢆ0Eꢏꢀꢈꢆꢎꢐ
5HJLVWHUꢀ3URJUDPPHGꢀZLWKꢀ([WHQGHGꢀ056
Address
BA1
BA0
A11 ~ A10/AP
A9 A8 A7 A6 A5
'6
A4
A3
A2 A1
3$65
A0
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0RGHꢀ6HOHFW
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5)8ꢀꢁ1RWHꢀꢇꢂ
60 EMRS for PASR (Partial Array Self Ref) & DS (Driver Strength)
Mode Select
Mode
Driver Strength
A6 A5 Driver Strength
PASR
A0
BA1
ꢌ
BA0
ꢌ
A2
ꢌ
A1
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
Refreshed Area
)XOOꢀ$UUD\
1RUPDOꢀ056
5HVHUYHG
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
)XOO
ꢇꢒꢏ
ꢇꢒꢍ
ꢇꢒꢋ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇꢒꢏꢀRIꢀIXOOꢀDUUD\
ꢇꢒꢍꢀRIꢀIXOOꢀDUUD\
5HVHUYHG
ꢇ
ꢌ
(056ꢀIRUꢀ0RELOHꢀ6'5$0
5HVHUYHG
ꢌ
ꢇ
ꢇ
ꢌ
Reserved Address
A8 A7
ꢇ
5HVHUYHG
A11~A10/AP
A9
A4
A3
ꢇ
5HVHUYHG
ꢇ
5HVHUYHG
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢇ
5HVHUYHG
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ꢀꢁ 5)8ꢏ5HVHUYHGꢂIRUꢂIXWXUHꢂXVHꢐꢂVKRXOGꢂVWD\ꢂ³ꢈ´ꢂGXULQJꢂ056ꢂF\FOHꢁ
ꢆꢁ ,Iꢂ$ꢒꢂLVꢂKLJKꢂGXULQJꢂ056ꢂF\FOHꢄꢂ³%XUVWꢂ5HDGꢂ6LQJOHꢂ%LWꢂ:ULWH´ꢂIXQFWLRQꢂZLOOꢂEHꢂHQDEOHGꢁ
61 Partial Array Self Refresh
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ꢏꢃ 0RELOHꢀ6'5$0ꢀVXSSRUWVꢀꢑꢀNLQGVꢀRIꢀ3$65ꢀLQꢀVHOIꢀUHIUHVKꢀPRGHꢆꢀ)XOOꢀ$UUD\ꢄ
ꢇꢒꢏꢀRIꢀIXOOꢀDUUD\ꢄꢀDQGꢀꢇꢒꢍꢀRIꢀIXOOꢀDUUD\ꢃ
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/2 of full Array
- 1/4 of full Array
Partial Self Refresh Area
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
169
P r e l i m i n a r y n
62 Internal Temperature Compensated Self Refresh (TCSR)
Self Refresh Current (Icc 6)
Temperature Range
0D[ꢃꢀꢍꢌ&
Full Array
ꢇꢌꢌ
1/2 of full array
1/4 of full array
Unit
ꢉꢌ
ꢋꢊ
$
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ꢏꢊꢌ
ꢏꢇꢌ
ꢇꢉꢌ
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FRQWUROꢂXQLWVꢂWRꢂFRQWUROꢂWKHꢂVHOIꢂUHIUHVKꢂF\FOHꢂDXWRPDWLFDOO\ꢂDFFRUGLQJꢂWRꢂWKHꢂWZRꢂWHPSHUDWXUHꢂUDQJHVꢇꢂ
0D[ꢁꢂꢎꢈ&ꢄꢂ0D[ꢁꢂꢑꢉ&ꢁ
ꢆꢁ ,IꢂWKHꢂ(056ꢂIRUꢂH[WHUQDOꢂ7&65ꢂLVꢂLVVXHGꢂE\ꢂWKHꢂFRQWUROOHUꢄꢂWKLVꢂ(056ꢂFRGHꢂIRUꢂ7&65ꢂLVꢂLJQRUHGꢁ
63 Power Up Sequence
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ILQHGꢃ
ꢅꢀ$SSO\ꢀ9''ꢀEHIRUHꢀRUꢀDWꢀWKHꢀVDPHꢀWLPHꢀDVꢀ9''4ꢃ
ꢏꢃ 0DLQWDLQꢀVWDEOHꢀSRZHUꢄꢀVWDEOHꢀFORFNꢀDQGꢀ123ꢀLQSXWꢀFRQGLWLRQꢀIRUꢀDꢀPLQLPXPꢀRIꢀꢏꢌꢌXVꢃ
ꢑꢃ ,VVXHꢀSUHFKDUJHꢀFRPPDQGVꢀIRUꢀDOOꢀEDQNVꢀRIꢀWKHꢀGHYLFHVꢃ
ꢍꢃ ,VVXHꢀꢏꢀRUꢀPRUHꢀDXWRꢅUHIUHVKꢀFRPPDQGVꢃ
ꢊꢃ ,VVXHꢀDꢀPRGHꢀUHJLVWHUꢀVHWꢀFRPPDQGꢀWRꢀLQLWLDOL]HꢀWKHꢀPRGHꢀUHJLVWHUꢃ
ꢎꢃ ,VVXHꢀDꢀH[WHQGHGꢀPRGHꢀUHJLVWHUꢀVHWꢀFRPPDQGꢀWRꢀGHILQHꢀ'6ꢀRUꢀ3$65ꢀRSHUDWLQJꢀW\SHꢀRI
WKHꢀGHYLFHꢀDIWHUꢀQRUPDOꢀ056ꢃ
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LVꢀXVHGꢃ
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UHIUHVKHGꢃ
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)RUꢀRSHUDWLQJꢀZLWKꢀ'6ꢀRUꢀ3$65ꢄꢀVHWꢀ'6ꢀRUꢀ3$65ꢀPRGHꢀLQꢀ(056ꢀVHWWLQJꢀVWDJHꢃ
,QꢀRUGHUꢀWRꢀDGMXVWꢀDQRWKHUꢀPRGHꢀLQꢀWKHꢀVWDWHꢀRIꢀ'6ꢀRUꢀ3$65ꢀPRGHꢄꢀDGGLWLRQDOꢀ(056ꢀVHWꢀLVꢀUHTXLUHG
EXWꢀSRZHUꢀXSꢀVHTXHQFHꢀLVꢀQRWꢃ
QHHGHGꢀDJDLQꢀDWꢀWKLVꢀWLPHꢃꢀ,QꢀWKDWꢀFDVHꢄꢀDOOꢀEDQNVꢀKDYHꢀWRꢀEHꢀLQꢀLGOHꢀVWDWHꢀSULRUꢀWRꢀDGMXVWLQJꢀ(056
VHWꢃ
64 Burst Sequence
64.1 Burst Length = 4
Initial Address
A1
ꢌ
A0
ꢌ
Sequential
Interleave
ꢌ
ꢇ
ꢏ
ꢑ
ꢇ
ꢏ
ꢑ
ꢌ
ꢏ
ꢑ
ꢌ
ꢇ
ꢑ
ꢌ
ꢇ
ꢏ
ꢌ
ꢇ
ꢏ
ꢑ
ꢇ
ꢌ
ꢑ
ꢏ
ꢑ
ꢏ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢇ
170
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
64.2 Burst Length = 8
Initial Address
A2 A1
A0
ꢌ
Sequential
Interleave
ꢌ
ꢌ
ꢌ
ꢌ
ꢇ
ꢇ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢇ
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢈ
ꢇ
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢈ
ꢌ
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢈ
ꢌ
ꢇ
ꢑ
ꢍ
ꢊ
ꢎ
ꢈ
ꢌ
ꢇ
ꢏ
ꢍ
ꢊ
ꢎ
ꢈ
ꢌ
ꢇ
ꢏ
ꢑ
ꢊ
ꢎ
ꢈ
ꢌ
ꢇ
ꢏ
ꢑ
ꢍ
ꢎ
ꢈ
ꢌ
ꢇ
ꢏ
ꢑ
ꢍ
ꢊ
ꢈ
ꢌ
ꢇ
ꢏ
ꢑ
ꢍ
ꢊ
ꢎ
ꢌ
ꢇ
ꢏ
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ꢊ
ꢎ
ꢈ
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ꢏ
ꢊ
ꢍ
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ꢎ
ꢏ
ꢑ
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ꢍ
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ꢑ
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ꢇ
ꢌ
ꢈ
ꢎ
ꢊ
ꢍ
ꢍ
ꢊ
ꢎ
ꢈ
ꢌ
ꢇ
ꢏ
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ꢊ
ꢍ
ꢈ
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ꢇ
ꢌ
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ꢎ
ꢈ
ꢍ
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65 Device Operations
65.1 Addresses of 64Mb
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PHPRU\ꢀDUUD\Vꢃꢀ7KHꢀ%$ꢌꢀaꢀ%$ꢇꢀLQSXWVꢀDUHꢀODWFKHGꢀDWꢀWKHꢀWLPHꢀRIꢀDVVHUWLRQꢀRIꢀ5$6ꢔꢀDQGꢀ&$6ꢔꢀWR
VHOHFWꢀWKHꢀEDQNꢀWRꢀEHꢀXVHGꢀIRUꢀWKHꢀRSHUDWLRQꢃꢀ7KHꢀEDQNꢀDGGUHVVHVꢀ%$ꢌꢀaꢀ%$ꢇꢀDUHꢀODWFKHGꢀDWꢀEDQN
DFWLYHꢄꢀUHDGꢄꢀZULWHꢄꢀPRGHꢀUHJLVWHUꢀVHWꢀDQGꢀSUHFKDUJHꢀRSHUDWLRQVꢃ
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)ꢀDꢀphrꢀꢀ"!ꢂꢀ7KHꢀꢇꢉꢀDGGUHVVꢀELWVꢀDUHꢀUHTXLUHGꢀWRꢀGHFRGHꢀWKHꢀꢊꢏꢍꢄꢏꢋꢋꢀZRUGꢀORFDWLRQVꢀDUHꢀPXOꢅ
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65.2 Addresses of 128Mb
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
171
P r e l i m i n a r y n
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65.3 Clock
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65.4 Clock Enable (CKE)
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65.5 NOP and Device Deselect
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65.6 DQM Operation
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65.7 Mode Register Set (MRS)
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LVꢀQRWꢀGHILQHGꢄꢀWKHUHIRUHꢀWKHꢀPRGHꢀUHJLVWHUꢀPXVWꢀEHꢀZULWWHQꢀDIWHUꢀSRZHUꢀXSꢀWRꢀRSHUDWHꢀWKHꢀ6'5$0ꢃ
7KHꢀPRGHꢀUHJLVWHUꢀLVꢀZULWWHQꢀE\ꢀDVVHUWLQJꢀORZꢀRQꢀ&6ꢔꢄꢀ5$6ꢔꢄꢀ&$6ꢔꢀDQGꢀ:(ꢔꢀꢁ7KHꢀ6'5$0ꢀVKRXOG
172
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
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65.8 Extended Mode Register Set (EMRS)
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65.9 Bank Activate
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5$6ꢔꢀDQGꢀ&6ꢔꢀZLWKꢀGHVLUHGꢀURZꢀDQGꢀEDQNꢀDGGUHVVꢄꢀDꢀURZꢀDFFHVVꢀLVꢀLQLWLDWHGꢃꢀ7KHꢀUHDGꢀRUꢀZULWH
RSHUDWLRQꢀFDQꢀRFFXUꢀDIWHUꢀDꢀWLPHꢀGHOD\ꢀRIꢀW5&'ꢁPLQꢂꢀIURPꢀWKHꢀWLPHꢀRIꢀEDQNꢀDFWLYDWLRQꢃꢀW5&'ꢀLVꢀDQ
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
173
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174
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
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65.17 Basic Feature and Function Descriptions
1) Clock Suspended During Write
2) Clock Suspended During Read (BL=4)
CLK
CLK
CMD
CKE
WR
CMD
CKE
RD
Masked by CKE
Masked by CKE
Internal
CLK
Internal
CLK
D0
D0
D1
D1
D2
D2
D3
D3
DQ(CL2)
DQ(CL3)
DQ(CL2)
DQ(CL3)
Q0
Q1
Q2
Q1
Q3
Q2
Q0
Q3
Not Written
Suspended Dout
Figure 65.1 Clock Suspend
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
175
P r e l i m i n a r y n
1) Write Mask (BL=4)
CLK
2) Read Mask (BL=4)
CLK
CMD
DQM
CMD
DQM
WR
RD
Masked by CKE
Masked by CKE
Hi-Z
DQ(CL2)
DQ(CL3)
DQ(CL2)
DQ(CL3)
Q
0
Q
2
Q
Q
3
D
D
0
0
D
D
1
1
D3
Hi-Z
D3
Q
1
2
Q3
DQM to Data-in Mask = 0
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) -Note 2
CLK
CMD
RD
CKE
DQM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Q
0
Q
2
1
Q
4
Q
6
5
Q
7
Q8
DQ(CL2)
DQ(CL3)
Hi-Z
Q
Q
3
Q
Q
6
Q7
Figure 65.2 DQM Operation
Ir)
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176
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
1) Read interrupted by Read (BL=4) -Note 1
CLK
RD RD
CMD
ADD
A
B
DQ(CL2)
DQ(CL3)
QA0 QB0 QB1 QB1 QB3
QA0 QB0 QB1 QB1 QB3
Note 2
tCCD
2) Write interrupted by Write (BL=2)
CLK
3) Write interrupted by Read (BL=2)
CLK
WR RD
CMD
WR WR
CMD
*2
*2
tCCD
tCCD
ADD
A
B
A
B
ADD
DQ
DQ(CL2)
DQ(CL3)
DA0
DA0
QB0 QB1
QB0 QB1
DA0 DB0 DB1
Note 3
tCDL
Note 3
tCDL
Figure 65.3 CAS# Interrupt (1)
Ir)
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
177
P r e l i m i n a r y n
(a) CL=2, BL=4
CLK
i) CMD
RD WR
DQM
DQ
D0
D1
D2
D3
D2
ii) CMD
RD
RD
RD
WR
DQM
DQ
Hi-Z
D0
D1
D3
WR
iii) CMD
DQM
DQ
Hi-Z
D0
D1
D2
D1
D3
D2
iv) CMD
WR
DQM
DQ
Hi-Z
Note 1
Q0
D0
D3
(b) CL=3, BL=4
CLK
RD WR
i) CMD
DQM
DQ
D0
D1
D2
D3
D2
ii) CMD
RD
WR
DQM
DQ
D0
D1
D3
D2
iii) CMD
RD
RD
WR
DQM
DQ
D0
D1
D3
D2
D1
iv) CMD
WR
DQM
DQ
Hi-Z
D0
D1
D3
D2
v) CMD
RD
WR
DQM
DQ
Hi-Z
Note 1
Q0
D0
D3
Figure 65.4 CAS# Interrupt (2): Read Interrupted by Write & DQM
Ir)
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178
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
1) t
= 2CLK
RDL
CLK
Note 3
Note 2
CMD
DQM
WR
D0
PRE
D1
D2
DQ
Masked by DQM
Figure 65.5 Write Interrupted by Precharge & DQM
Ir)
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1) Normal Write
BL=4 & t
=2CLK
RDL
CLK
CMD
WR
D0
PRE
DQ
D1
D2
D3
Note 1
t
RDL
2) Normal Read (BL=4)
CLK
Note 2
RD
PRE
Q2
CMD
Note 1
Q3
Q0
Q1
Q0
Q3
Q2
DQ(CL2)
Note 2
Q1
DQ(CL3)
Figure 65.6 Precharge
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
179
P r e l i m i n a r y n
1) Normal Write (BL=4)
CLK
2) Normal Read (BL=4)
CLK
CMD
DQ
WR
ACT
CMD
RD
DQ(CL2)
DQ(CL3)
Q
0
Q
1
Q
2
Q
3
2
D0
D
1
D2
D
3
Q
0
Q
1
Q
Q3
t
=2CLK
=t
RDL
Note 4
t
+ t
DAL RDL RP
Auto Precharge Starts Note 3
Auto Precharge Starts@t
RDL
=2CLK Note 3
Figure 65.7 Auto Precharge
Ir)
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53
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1) Normal Write
BL=4 & t
=2CLK
WR
RDL
CLK
PRE
CMD
DQM
D0
D1
D2
t
DQ
Note 1
RDL
2) Write Burst Stop (BL=8)
CLK
3) Read Interrupted by Precharge (BL=4)
CLK
WR
STOP
RD
PRE
Q0
CMD
CMD
1
DQ(CL2)
Q1
Q0
DQM
DQ
2
D0
D1
D2
D3
t
Q1
DQ(CL3)
Note 2
BDL
4) Read Burst Stop (BL=4)
CLK
RD
STOP
Q0
CMD
1
Q1
Q0
DQ(CL2)
DQ(CL3)
2
Q1
Figure 65.8 Burst Stop and Interrupted by Precharge
180
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
1) Mode Register Set
CLK
Note 4
CMD
PRE
MRS
ACT
t
2CLK
RP
Figure 65.9 MRS
Ir)
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1) Clock Suspend (=Active Power Down) Exit
CLK
2) Power Down (=Precharge Power Down) Exit
CLK
CKE
CKE
t
t
SS
SS
Note 2
Note 1
Internal
Internal
CLK
CLK
RD
NOP ACT
CMD
CMD
Figure 65.10 Clock Suspend Exit and Power Down Exit
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CLK
Auto
Refresh
PRE
CMD
Command
CKE = High
tRP
tARFC(min)
Figure 65.11 Auto Refresh
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
181
P r e l i m i n a r y n
CLK
Command
CKE
Stable Clock
Self
Refresh
ACT
NOP
tSRFX(min)
tSS
tSS
Figure 65.12 Self Refresh
66 About Burst Type Control
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5DQGRPꢀ0RGH
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UHVSHFWLYHO\ꢀ8VLQJꢀEXUVWꢀVWRSꢀFRPPDQGꢄꢀDQ\ꢀEXUVWꢀOHQJWKꢀ
FRQWUROꢀLVꢀSRVVLEOHꢃ
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'40ꢄꢀYDOLGꢀ'4ꢀDIWHUꢀEXUVWꢀVWRSꢀLVꢀꢇꢄꢀꢏꢀIRUꢀ&$6ꢀODWHQF\ꢀꢏꢄꢀꢑꢀ
UHVSHFWLYHO\ꢃꢀ'XULQJꢀUHDGꢒZULWHꢀEXUVWꢀZLWKꢀDXWRꢀSUHFKDUJHꢄꢀ
5$6ꢔꢀLQWHUUXSWꢀFDQꢀQRWꢀEHꢀLVVXHGꢃ
5$6ꢔꢀ,QWHUUXSW
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3UHFKDUJHꢂ
,QWHUUXSWꢀ
0RGH
%HIRUHꢀWKHꢀHQGꢀRIꢀEXUVWꢄꢀQHZꢀUHDGꢒZULWHꢀVWRSVꢀUHDGꢒZULWHꢀEXUVWꢀ
DQGꢀVWDUWVꢀQHZꢀUHDGꢒZULWHꢀEXUVWꢃꢀ'XULQJꢀUHDGꢒZULWHꢀEXUVWꢀZLWKꢀ
DXWRꢀSUHFKDUJHꢄꢀ&$6ꢔꢀLQWHUUXSWꢀFDQꢀQRWꢀEHꢀLVVXHGꢃ
&$6ꢔꢀ,QWHUUXSW
182
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
/
$
ꢇꢌꢒ$37HUPꢀEXUVUHWꢄF
ꢑ
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ꢇꢌꢒ$37HUPꢀEXUVUHWꢄF
P r e l i m i n a r y
68 Function Truth Table (1)
Current State
CS# RAS# CAS# WE#
BA
Address
Action
Note
+
/
/
/
/
/
/
/
+
/
/
/
/
/
/
/
;
+
+
+
/
;
+
+
/
;
+
/
;
;
;
;
123
;
;
123
,//(*$/
ꢏ
;
+
/
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3,//(*$/
ꢏ
,GOH
+
+
/
5$
5RZꢀꢁꢓꢀ%DQNꢂꢀ$FWLYHꢕꢀ/DWFKꢀ5$
/
$
ꢇꢌꢒ$3123
;
ꢍ
/
+
/
$XWRꢀ5HIUHVKꢀRUꢀ6HOIꢀ5HIUHVK
ꢊ
ꢊ
/
/
23ꢀFRGH
;
23ꢀFRGH
0RGHꢀ5HJLVWHUꢀ$FFHVV
;
+
+
+
/
;
+
+
/
;
+
/
;
;
;
123
;
123
;
,//(*$/
ꢏ
ꢏ
+
/
%$
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3%HJLQꢀ5HDGꢕꢀODWFKꢀ&$ꢕꢀGHWHUPLQHꢀ$3
&$ꢄꢀ$ꢇꢌꢒ$3%HJLQꢀ5HDGꢕꢀODWFKꢀ&$ꢕꢀGHWHUPLQHꢀ$3
5RZꢀ$FWLYH
/
/
+
+
/
+
/
5$
,//(*$/
/
$ꢇꢌꢒU$H3FK3DUJH
/
;
;
;
,//(*$/
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ
$FWLYHꢂ
+
/
;
+
;
+
;
+
;
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ
$FWLYHꢂ
;
;
/
/
/
/
/
/
+
+
+
/
+
/
/
+
/
;
7HUPꢀEXUVWꢀꢅꢅ!ꢀ5RZꢀDFWLYH
5HDG
%$
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ5HDGꢄꢀ'HWHUPLQHꢀ$3
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ:ULWHꢄꢀ'HWHUPLQHꢀ$3
/
ꢑ
+
+
/
+
/
5$
,//(*$/
K3DUJHꢀWLPLQJꢀIRUꢀ5HDGV
,//(*$/
ꢏ
/
;
;
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ
$FWLYHꢂ
+
/
;
+
;
+
;
+
;
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ
$FWLYHꢂ
;
;
/
/
/
/
/
/
+
/
/
/
/
/
+
/
/
/
/
/
+
/
/
/
/
/
+
+
+
/
+
/
/
+
/
;
%$
%$
%$
%$
;
7HUPꢀEXUVWꢀꢅꢅ!ꢀ5RZꢀDFWLYH
:ULWH
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ5HDGꢄꢀ'HWHUPLQHꢀ$3
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ:ULWHꢄꢀ'HWHUPLQHꢀ$3
ꢑ
ꢑ
/
+
+
/
+
/
5$
,//(*$/
K3DUJHꢀWLPLQJꢀIRUꢀ5HDGV
,//(*$/
ꢏ
/
;
;
+
/
;
;
;
;
;
+
+
+
/
;
+
+
/
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
,//(*$/
;
;
5HDGꢀZLWKꢀ$XWRꢀ
3UHFKDUJH
;
;
;
;
+
/
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3,//(*$/
+
/
5$ꢄꢀ5$ꢇꢌ
,//(*$/
ꢏ
ꢏ
/
;
;
;
;
,//(*$/
;
+
+
+
/
;
+
+
/
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
,//(*$/
;
;
:ULWHꢀZLWKꢀ$XWRꢀ
3UHFKDUJH
;
;
;
;
+
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%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3,//(*$/
+
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5$ꢄꢀ5$ꢇꢌ
,//(*$/
/
;
;
,//(*$/
;
+
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;
+
+
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;
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW53
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW53
,//(*$/
;
;
;
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ꢏ
ꢏ
ꢍ
3UHFKDUJLQJ
;
+
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%$
%$
&$
5$
,//(*$/
+
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/
$ꢇꢌꢒ$3ꢀꢅꢅ!3ꢀ,GOHꢀDIWHUꢀW
53
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
183
P r e l i m i n a r y n
Current State
CS# RAS# CAS# WE#
BA
;
Address
Action
Note
/
+
/
/
/
/
/
/
+
/
/
/
/
+
/
/
/
/
/
;
+
+
+
/
/
;
+
+
/
;
;
+
/
;
;
,//(*$/
;
123ꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢀDIWHUꢀW5&'
123ꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢀDIWHUꢀW5&'
,//(*$/
;
;
;
;
ꢏ
ꢏ
ꢏ
5RZꢀ$FWLYDWLQJ
;
+
/
%$
%$
%$
;
&$
5$
,//(*$/
+
+
/
,//(*$/
/
$
ꢇꢌꢒ$3,//(*$/
ꢏ
/
;
;
;
;
;
;
;
+
/
;
;
;
;
;
;
;
;
;
;
;
,//(*$/
;
+
+
/
;
+
/
;
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW5&
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW5&
,//(*$/
;
5HIUHVKLQJ
;
+
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;
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/
;
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;
+
+
+
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;
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;
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀꢏꢀFORFNV
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀꢏꢀFORFNV
,//(*$/
;
0RGHꢀ5HJLVWHUꢀ
5HIUHVKLQJ
;
;
;
;
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GUHVVꢄꢂ$3ꢂ ꢂ$XWRꢂ3UHFKDUJH
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ꢆꢁ ,OOHJDOꢂWRꢂEDQNꢂLQꢂVSHFLILHGꢂVWDWHꢇꢂ)XQFWLRQꢂPD\ꢂEHꢂOHJDOꢂLQꢂWKHꢂEDQNꢂLQGLFDWHGꢂE\ꢂ%$ꢄꢂGHSHQGLQJꢂRQꢂ
WKHꢂVWDWHꢂRIꢂWKDWꢂEDQNꢁ
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ꢎꢁ 123ꢂWRꢂEDQNꢂSUHFKDUJLQJꢂRUꢂLQꢂLGOHꢂVWDWHꢁꢂ0D\ꢂSUHFKDUJHꢂEDQNꢂLQGLFDWHGꢂE\ꢂ%$ꢂꢏDQGꢂ$ ꢍ$3ꢐꢁ
ꢀꢈ
ꢉꢁ ,OOHJDOꢂLIꢂDQ\ꢂEDQNꢂLVꢂQRWꢂLGOHꢁ
184
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
69 Function Truth Table (2)
Current State CKE (n-1) CKE n CS# RAS# CAS# WE# Address
Action
Note
([LWꢀ6HOIꢀ5HIUHVKꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀ
+
/
;
+
+
;
+
/
;
;
+
;
;
+
;
;
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;
;
WV5);ꢁ$%,ꢂ
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ꢁ$%,ꢂ
ꢎ
ꢎ
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ꢁ$%,ꢂ
ꢀ
/
6HOIꢀ5HIUHVK
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/
;
;
;
;
;
+
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+
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;
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123ꢀꢁ0DLQWDLQꢀ6HOIꢀ5HIUHVKꢂ
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+
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,//(*$/
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ꢈ
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66
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ꢒꢁ 0XVWꢂEHꢂDꢂOHJDOꢂFRPPDQGꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
185
P r e l i m i n a r y n
70 AC Characteristics
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CLOCK
CKE
Hi
CS#
RAS#
CAS#
ADDR
BA0
Key
Key
RAa
BA1
A10/AP
DQ
RAa
Hi-Z
Hi-Z
WE#
DQM
High level is necessary
tRP
tARFC
tARFC
Precharge
(All Bank)
Auto
Refresh
Auto
Refresh
Normal
MRS
Extended
MRS
Row Active
(A-Bank)
: Don’t care
Figure 70.1 Power Up Sequence for Mobile SDRAM
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WKHꢂVWDWHꢂRIꢂ'6ꢂRUꢂ3$65ꢂPRGHꢄꢂDGGLWLRQDOꢂ(056ꢂVHWꢂLVꢂUHTXLUHGꢂEXWꢂSRZHUꢂXSꢂVHTXHQFHꢂLVꢂQRWꢂ
186
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
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VHWꢁ
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
tCC
tCL
HIGH
tRP
tRAS
tRC
*Note 1
tSH
CS#
tRCD
tSS
tSH
tSH
RAS#
CAS#
tSS
tSH
tSS
Ca
ADDR
BA0,BA1
A10/AP
Ra
Cb
Cc
Rb
tSS
*Note 2
BS
*Note 2,3
BS
*Note 2,3
BS
*Note 2,3 *Note 4
BS BS
*Note 2
BS
*Note 3
*Note 3
*Note 3 *Note 4
Ra
Rb
tSH
Db
tSAC
Qa
DQ
WE#
DQM
Qc
tSS
tSS tSH
tSLZ
tOH
tSS tSH
Row Active
Read
Write
Read
Row Active
Precharge
: Don’t care
Figure 70.2 Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3,
Burst Length=1
Ir)
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ꢆꢁ %DQNꢂDFWLYHꢂDQGꢂUHDGꢍZULWHꢂDUHꢂFRQWUROOHGꢂE\ꢂ%$ꢈꢄꢂ%$ꢀꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
187
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note 1
tRC
CS#
RAS#
*Note 2
CAS#
ADDR
BA0
Ra
Ca
Rb
Cb
BA1
A10/AP
CL=2
Ra
Rb
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
tSHZ
tRCD
tSAC
tOH
*Note 4
tSHZ
DQ
{
CL=3
Qa0 Qa1 Qa2 Qa3
tSAC
tRDL
*Note 4
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Figure 70.3 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
Ir)
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ꢆꢁ 5RZꢂSUHFKDUJHꢂFDQꢂLQWHUUXSWꢂEXUVWꢂRQꢂDQ\ꢂF\FOHꢁꢂ>&$6ꢂ/DWHQF\ꢂꢃꢂꢀ@ꢂQXPEHUꢂRIꢂYDOLGꢂRXWSXWꢂGDWDꢂLVꢂ
DYDLODEOHꢂDIWHUꢂ5RZꢂSUHFKDUJHꢁꢂ/DVWꢂYDOLGꢂRXWSXWꢂZLOOꢂEHꢂ+Lꢃ=ꢏW
ꢐꢂDIWHUꢂWKHꢂFORFNꢁ
6+=
ꢊꢁ 2XWSXWꢂZLOOꢂEHꢂ+Lꢃ=ꢂDIWHUꢂWKHꢂHQGꢂRIꢂEXUVWꢁꢂꢏꢀꢄꢂꢆꢄꢂꢎꢄꢂꢑꢂꢗꢂ)XOOꢂSDJHꢂELWꢂEXUVWꢐꢁ
188
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
Ra
Ca
Cb
Cc
Cd
Rb
BA1
A10/AP
CL=2
Ra
Rb
tRDL
Qa0 Qa1 Qb0 Qb1 Qb2
Dc0 Dc1 Dd0 Dd1
tRCD
tDAL
*Note 4
DQ
{
CL=3
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
tCDL
WE#
*Note 1
*Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don’t care
Figure 70.4 Page Read & Write Cycle at Same Bank @Burst Length=4,
tRDL=2CLK
Ir)
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WRꢂDYRLGꢂEXVꢂFRQWHQWLRQꢁ
ꢆꢁ 5RZꢂSUHFKDUJHꢂZLOOꢂLQWHUUXSWꢂZULWLQJꢁꢂ/DVWꢂGDWDꢂLQSXWꢄꢂW
ꢂEHIRUHꢂ5RZꢂSUHFKDUJHꢄꢂZLOOꢂEHꢂZULWWHQꢁ
5'/
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HQGꢂRIꢂEXUVWꢁꢂ,QSXWꢂGDWDꢂDIWHUꢂ5RZꢂSUHFKDUJHꢂF\FOHꢂZLOOꢂEHꢂPDVNHGꢂLQWHUQDOO\ꢁ
ꢎꢁ W
ꢄꢂODVWꢂGDWDꢂLQꢂWRꢂDFWLYHꢂGHOD\ꢄꢂLVꢂꢆ&/.ꢂꢓꢂW
ꢁ
53
'$/
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
189
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note 1
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BA1
A10/AP
CL=2
RAa
RBb
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2
QDd0 QDd1 QDd2
DQ
{
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(C-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
Precharge
(C-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
: Don’t care
Figure 70.5 Page Read Cycle at Different Bank @Burst Length=4
Ir)
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ꢆꢁ 7RꢂLQWHUUXSWꢂDꢂEXUVWꢂUHDGꢂE\ꢂURZꢂSUHFKDUJHꢄꢂERWKꢂWKHꢂUHDGꢂDQGꢂWKHꢂSUHFKDUJHꢂEDQNVꢂPXVWꢂEHꢂWKHꢂ
VDPHꢁ
190
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
RAa
RAb CAa
CBb RCc
RDd CCc
CDd
BA1
A10/AP
DQ
RAa
RBb
RCc
RDd
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
tRDL
WE#
*Note 1
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Precharge
(All Banks)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
: Don’t care
Figure 70.6 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
Ir)
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ꢆꢁ 7RꢂLQWHUUXSWꢂEXUVWꢂZULWHꢂE\ꢂ5RZꢂSUHFKDUJHꢄꢂERWKꢂWKHꢂZULWHꢂDQGꢂWKHꢂSUHFKDUJHꢂEDQNVꢂPXVWꢂEHꢂWKHꢂ
VDPHꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
191
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
RAa
CAa
RDb
CDb RBc
CBc
BA1
A10/AP
CL=2
RAa
RDb
RBc
t
CDL
*Note 1
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
QBc0 QBc1
DQ
{
CL=3
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: Don’t care
Figure 70.7 Read & Write Cycle at Different Bank @Burst Length=4
Ir)
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ꢂVKRXOGꢂEHꢂPHWꢂWRꢂFRPSOHWHꢂZULWHꢁ
&'/
192
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
RAa
RBb CAa
CBb
RAc
CAc
BA0
BA1
A10/AP
DQ CL=2
RAa
RBb
RAc
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
DAc0 DAc1
CL=3
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
WE#
DQM
Row Active
(A-Bank)
Read with Read without Auto
Auto Pre Precharge(B-Bank)
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
charge
Auto Precharge
Start Point
(A-Bank)
(A-Bank) *Note1
Row Active
(B-Bank)
: Don’t care
Figure 70.8 Read & Write Cycle with Auto Precharge 1 @Burst Length=4
Ir)
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SUHFKDUJHꢂVWDUWVꢄꢂ$ꢃ%DQNꢂDXWRꢂSUHFKDUJHꢂZLOOꢂVWDUWꢂDWꢂ%ꢃ%DQNꢂUHDGꢂFRPPDQGꢂLQSXWꢂSRLQWꢁ
ꢃꢂDQ\ꢂFRPPDQGꢂFDQꢂQRWꢂEHꢂLVVXHGꢂDWꢂ$ꢃ%DQNꢂGXULQJꢂW53ꢂDIWHUꢂ$ꢃ%DQNꢂDXWRꢂSUHFKDUJHꢂVWDUWVꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
193
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
Ra
Ca
Rb
Cb
BA1
A10/AP
DQ CL=2
Ra
Rb
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
CL=3
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
WE#
DQM
*Note1
Auto Precharge
Start Point
(B-Bank)
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
: Don’t care
Figure 70.9 Read & Write Cycle with Auto Precharge 2 @Burst Length=4
Ir)
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53
SRLQWꢁ
194
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS#
RAS#
CAS#
ADDR
BA0
Ra
Ca
Cb
Cc
BA1
A10/AP
DQ
Ra
Qa0 Qa1
Qa2
Qa3
Qb0 Qb1
tSHZ
Dc0
Dc2
tSHZ
WE#
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
DQM
Write
Clock
Suspension
: Don’t care
Figure 70.10 Clock Suspension & DQM Operation Cycle @CAS Latency=2,
Burst Length=4
Ir)
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
195
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
RAa
CAa
CAb
BA1
A10/AP
CL=2
RAa
1
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0 QAa1 QAa2 QAa3 QAa4
DQ
2
2
{
CL=3
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE#
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
: Don’t care
Figure 70.11 Read Interrupted by Precharge Command & Read Burst Stop
Cycle @Full Page Burst
Ir)
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%XWꢂDWꢂEXUVWꢂZULWHꢄꢂ%XUVWꢂVWRSꢂDQGꢂ5$6ꢅꢂLQWHUUXSWꢂVKRXOGꢂEHꢂFRPSDUHGꢂFDUHIXOO\ꢁ
5HIHUꢂWKHꢂWLPLQJꢂGLDJUDPꢂRIꢂ³)XOOꢂSDJHꢂZULWHꢂEXUVWꢂVWRSꢂF\FOH´ꢁ
ꢊꢁ %XUVWꢂVWRSꢂLVꢂYDOLGꢂDWꢂHYHU\ꢂEXUVWꢂOHQJWKꢁ
196
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
RAa
CAa
CAb
BA1
A10/AP
DQ
RAa
tBDL
tRDL
*Note 1
*Note 1,2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE#
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Figure 70.12 Write Interrupted by Precharge Command & Write Burst Stop
Cycle @ Full Page Burst, tRDL=2CLK
Ir)
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FHOOꢁꢂ,WꢂLVꢂGHILQHGꢂE\ꢂ$&ꢂSDUDPHWHUꢂRIꢂW
ꢁ
5'/
'40ꢂDWꢂZULWHꢂLQWHUUXSWHGꢂE\ꢂSUHFKDUJHꢂFRPPDQGꢂLVꢂQHHGHGꢂWRꢂSUHYHQWꢂLQYDOLGꢂZULWHꢁ
'40ꢂVKRXOGꢂPDVNꢂLQYDOLGꢂLQSXWꢂGDWDꢂRQꢂSUHFKDUJHꢂFRPPDQGꢂF\FOHꢂZKHQꢂDVVHUWLQJꢂSUHFKDUJHꢂEHIRUHꢂ
HQGꢂRIꢂEXUVWꢁꢂ,QSXWꢂGDWDꢂDIWHUꢂ5RZꢂSUHFKDUJHꢂF\FOHꢂZLOOꢂEHꢂPDVNHGꢂLQWHUQDOO\ꢁ
ꢊꢁ %XUVWꢂVWRSꢂLVꢂYDOLGꢂDWꢂHYHU\ꢂEXUVWꢂOHQJWKꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
197
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
*Note 2
CAS#
ADDR
BA0
RAa
CAa RBb CAb
RCc
CBc
CCd
BA1
A10/AP
CL=2
RAa
RBb
RCc
DAa0
QAb0 QAb1
DBc0
DBc0
QCd0 QCd1
DQ
{
CL=3
DAa0
QAb0 QAb1
QCd0 QCd1
WE#
DQM
Precharge
(C-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Write
Read with
Write with
Auto Precharge
(B-Bank)
(A-Bank) Auto Precharge
(A-Bank)
: Don’t care
Figure 70.13 Burst Read Single bit Write Cycle @Burst Length=2
Ir)
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EXUVWꢂOHQJWKꢂDWꢂZULWHꢂLVꢂIL[HGꢂWRꢂ³ꢀ´ꢂUHJDUGOHVVꢂRIꢂSURJUDPPHGꢂEXUVWꢂOHQJWKꢁ
ꢆꢁ :KHQꢂ%56:ꢂZULWHꢂFRPPDQGꢂZLWKꢂDXWRꢂSUHFKDUJHꢂLVꢂH[HFXWHGꢄꢂNHHSꢂLWꢂLQꢂPLQGꢂWKDWꢂW5$6ꢂVKRXOGꢂQRWꢂ
EHꢂYLRODWHGꢁꢂ$XWRꢂSUHFKDUJHꢂLVꢂH[HFXWHGꢂDWꢂWKHꢂEXUVWꢃHQGꢂF\FOHꢄꢂVRꢂLQꢂWKHꢂFDVHꢂRIꢂ%56:ꢂZULWHꢂ
FRPPDQGꢄꢂWKHꢂQH[WꢂF\FOHꢂVWDUWVꢂWKHꢂSUHFKDUJHꢁ
198
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
tSS
*Note 1
tSS
tSS
*Note 2
*Note 2
*Note 3
CS#
RAS#
CAS#
ADDR
BA
Ra
Ca
Ra
A10/AP
DQ
Qa0 Qa1 Qa2
tSHZ
WE#
DQM
Precharge
Power-down
Entry
Row Active
Read
Precharge
Precharge
Power-down
Exit
Active
Power-down
Entry
Active
Power-down
Exit
: Don’t care
Figure 70.14 Active/Precharge Power Down Mode @CAS Latency=2, Burst
Length=4
Ir)
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66
ꢊꢁ &DQꢂQRWꢂYLRODWHꢂPLQLPXPꢂUHIUHVKꢂVSHFLILFDWLRQꢂꢏꢌꢎPVꢐꢁ
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
199
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
*Note 2
*Note 4
tSRFX
*Note 1
*Note 6
*Note 3
tSS
CS#
RAS#
CAS#
ADDR
BA0,BA1
A10/AP
DQ
Hi-Z
Hi-Z
WE#
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don’t care
Figure 70.15 Self Refresh Entry & Exit Cycle
Ir)
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ꢎꢁ 6\VWHPꢂFORFNꢂUHVWDUWꢂDQGꢂEHꢂVWDEOHꢂEHIRUHꢂUHWXUQLQJꢂ&.(ꢂKLJKꢁ
ꢉꢁ &6ꢅꢂVWDUWVꢂIURPꢂKLJKꢁ
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ꢂLVꢂUHTXLUHGꢂDIWHUꢂ&.(ꢂJRLQJꢂKLJKꢂWRꢂFRPSOHWHꢂVHOIꢂUHIUHVKꢂH[LWꢁ
65);
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V\VWHPꢂXVHVꢂEXUVWꢂUHIUHVKꢁ
200
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
CKE
CS
HIGH
HIGH
*Note 2
tARFC
RAS
CAS
ADDR
BA0
*Note 1
*Note 3
Key
Ra
BA1
Hi-Z
Hi-Z
DQ
WE
DQM
MRS
New Command
Auto Refresh
New Command
: Don’t care
Figure 70.16 Mode Register Set Cycle and Auto Refresh Cycle
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Ir)
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ꢊꢁ 3OHDVHꢂUHIHUꢂWRꢂWKHꢂ0RGHꢂ5HJLVWHUꢂ)LHOGꢂ7DEOHꢂWRꢂ3URJUDPꢂ0RGHV
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
201
P r e l i m i n a r y n
0
1
2
3
4
5
6
CLOCK
CKE
HIGH
CS#
*Note 2
RAS#
CAS#
ADDR
BA0
*Note 1
*Note 3
Key
Ra
BA1
Hi-Z
DQ
WE#
DQM
EMRS New Command
: Don’t care
Figure 70.17 Extended Mode Register Set Cycle
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202
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SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
71 SDRAM Type 2 Revision Summary
Revision A0 (May 25, 2004)
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
203
Mobile SDRAM Type 2
256Mbit (16M x 16 bit) SDRAM
PRELIMINARY
Features
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General Description
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Publication Number SDRAM_04 Revision A Amendment 0 Issue Date May 12, 2005
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P r e l i m i n a r y
72 Address Table
16M x 16
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73 Functional Block Diagram
LWE
Data Input Register
LDQM
Bank Select
4M x 16
4M x 16
4M x 16
4M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
205
P r e l i m i n a r y
74 Absolute Maximum Ratings
Parameter
9ROWDJHꢀRQꢀDQ\ꢀSLQꢀUHODWLYHꢀWRꢀ966
9ROWDJHꢀRQꢀ9''ꢀVXSSO\ꢀUHODWLYHꢀWRꢀ966
6WRUDJHꢀWHPSHUDWXUH
Symbol
9,1ꢄꢀ9287
9''ꢄꢀ9''4
767*
Value
ꢅꢇꢃꢌꢀaꢀꢏꢃꢎ
ꢅꢇꢃꢌꢀaꢀꢏꢃꢎ
ꢅꢊꢊꢀaꢀꢐꢇꢊꢌ
ꢇꢃꢌ
Unit
9
9
&
:
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3'
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206
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
75 DC Operating Conditions
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([WHQGHGꢄꢀꢅꢏꢊ&ꢀWRꢀꢈꢌ&ꢀIRUꢀ&RPPHUFLDOꢂꢃ
Parameter
6XSSO\ꢀYROWDJH
Symbol
9''
9''4
9,+
Min
Typ
ꢇꢃꢋ
ꢇꢃꢋ
ꢇꢃꢋ
ꢌ
Max
Unit
9
Note
ꢇꢃꢈ
ꢇꢃꢉꢊ
ꢇꢃꢈ
ꢇꢃꢉꢊ
9
,QSXWꢀORJLFꢀKLJKꢀYROWDJH
,QSXWꢀORJLFꢀORZꢀYROWDJH
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2XWSXWꢀORJLFꢀORZꢀYROWDJH
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ꢌꢃꢋꢀ[ꢀ9''4
9''4ꢀꢐꢀꢌꢃꢑ
9
ꢇ
9,/
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ꢅ
9
ꢏ
92+
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287
287
76 Capacitance
ꢁ9''ꢀ ꢀꢇꢃꢋ9ꢄꢀ7$ꢀ ꢀꢏꢑ&ꢄꢀIꢀ ꢀꢇ0+]ꢄꢀ95()ꢀ ꢌꢃꢉ9ꢀꢀꢊꢌꢀP9ꢂꢃ
Pin
Symbol
Min
ꢇꢃꢊ
ꢇꢃꢊ
ꢇꢃꢊ
ꢑꢃꢌ
Max
ꢑꢃꢌ
ꢑꢃꢌ
ꢑꢃꢌ
ꢊꢃꢌ
Unit
S)
Note
&ORFN
&
&/.
5$6ꢔꢄꢀ&$6ꢔꢄꢀ:(ꢔꢄꢀ&6ꢔꢄꢀ&.(ꢄꢀ'40
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May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
207
P r e l i m i n a r y
77 DC Characteristics
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([WHQGHGꢄꢀꢅꢏꢊ&ꢀWRꢀꢈꢌ&ꢀIRUꢀ&RPPHUFLDOꢂꢃ
Parameter
Symbol
Test Condition
Value
Unit Note
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2SHUDWLQJꢀ&XUUHQW
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,
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&.(ꢀꢓꢀ&/.ꢀ≤ 9,/ꢁPD[ꢂꢄꢀW&&ꢀ ꢀ∞
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LQꢀSRZHUꢅGRZQꢀPRGH
,
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,
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Parameter
Value
Unit
9
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S73WS256N Based MCPs
208
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
9WW ꢌꢃꢊꢀ[ꢀ9''4
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Figure 78.2 AC Output Load Circuit
79 Operating AC Parameters
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Parameter
5RZꢀDFWLYHꢀWRꢀURZꢀDFWLYHꢀGHOD\
5$6ꢔꢀWRꢀ&$6ꢔꢀGHOD\
Symbol
W55'ꢁPLQꢂ
Value
Unit
QV
Note
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ꢇ
ꢇ
ꢇ
W5&'ꢁPLQꢂ
ꢏꢍ
QV
5RZꢀSUHFKDUJHꢀWLPH
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QV
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May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
209
P r e l i m i n a r y
80 AC Characteristics
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Parameter
Symbol
W&&
Min
ꢉ
Max
Unit
Note
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210
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
81 Simplified Truth Table
A12, A11,
A9 ~ A0
Command
CKEn-1
CKEn CS# RAS# CAS# WE# DQM BA0,1 A10/AP
Note
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82 Mode Register Field Table to Program Modes
Address
BA0 ~ BA1
A12 ~ A10/AP
A9*2
A8
A7
A6
A5
A4
A3
A2
A1
A0
ꢈꢀ6HWWLQJꢀIRUꢀ
1RUPDOꢀ056
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May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
211
P r e l i m i n a r y
82.1 Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Type
Burst Length
A8 A7
Type
0RGHꢀ5HJLVWHUꢀ6HW
5HVHUYHG
A6
ꢌ
A5
ꢌ
A4
ꢌ
Latency
5HVHUYHG
ꢇ
A3
ꢌ
A2
ꢌ
A1
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
ꢌ
ꢇ
ꢇ
A0
BT=0
BT=1
0
0
1
0
1
6HTXHQWLDO
,QWHUOHDYH
Mode Select
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢌ
ꢇ
ꢇ
ꢏ
ꢍ
ꢋ
ꢇ
ꢏ
ꢍ
ꢋ
ꢌ
ꢌ
ꢇ
ꢇ
ꢌ
0
1
5HVHUYHG
ꢌ
ꢇ
ꢌ
ꢏ
ꢌ
1
5HVHUYHG
ꢌ
ꢇ
ꢇ
ꢑ
BA1 BA0
Mode
ꢌ
Write Burst Length
Length
ꢇ
ꢌ
ꢌ
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
ꢇ
5HVHUYHG 5HVHUYHG
5HVHUYHG 5HVHUYHG
5HVHUYHG 5HVHUYHG
)XOOꢀ3DJH 5HVHUYHG
6HWWLQJꢀ
IRUꢀ
1RUPDOꢀ
056
A9
ꢌ
ꢇ
ꢌ
ꢇ
ꢇ
ꢌ
ꢌ
%XUVW
ꢇ
ꢇ
ꢌ
ꢇ
ꢇ
6LQJOHꢀ%LW
ꢇ
ꢇ
ꢇ
ꢇ
1RWHꢔꢂ)XOOꢂ3DJHꢂ/HQJWKꢂ[ꢂꢀꢌꢔꢂꢌꢎ0Eꢂꢏꢆꢉꢌꢐꢄꢂꢀꢆꢑ0Eꢂꢏꢉꢀꢆꢐꢄꢂꢆꢉꢌ0Eꢂꢏꢉꢀꢆꢐꢄꢂꢉꢀꢆ0Eꢂꢏꢀꢈꢆꢎꢐꢁ
Table 82.1 Register Programmed with Extended MRS
BA1
BA0
A12 ~ A10/AP
A10
Address
BA0
A9
A8
A7
A6
A5
A4
A3
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BA1
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ꢌ
A5
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ꢌ
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ꢌ
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Reserved Address
ꢇ
ꢌ
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A8
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A4
A3
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83 Partial Array Self Refresh
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212
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
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BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
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BA1=1
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- Full Array
- 1/2 of full Array
- 1/4 of full Array
Partial Self Refresh Area
Figure 83.1 Partial Array Self Refresh Areas
83.1 Internal Temperature Compensated Self Refresh (TCSR)
Self Refresh Current (Icc 6)
Temperature Range
Unit
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ꢏꢌꢌ
1/2 of Full Array
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May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
213
P r e l i m i n a r y
85 Burst Sequence
85.1 Burst Length = 4
Initial Address
Sequential
Interleave
A1
ꢌ
A0
ꢌ
ꢌ
ꢇ
ꢏ
ꢑ
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85.2 Burst Length = 8
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Sequential
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A2
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214
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
86.2 Addresses of 512Mb
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86.4 Clock Enable (CKE)
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86.5 NOP and Device Deselect
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May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
215
P r e l i m i n a r y
86.6 DQM Operation
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86.7 Mode Register Set (MRS)
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86.8 Extended Mode Register Set (EMRS)
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86.9 Bank Activate
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216
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
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86.10 Burst Read
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May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
217
P r e l i m i n a r y
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86.14 Auto Precharge
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86.15 Auto Refresh
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218
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
87 Basic Feature and Function Descriptions
87.1 Clock Suspend
CLK
CMD
CKE
WR
Masked by CKE
Internal
CLK
D0
D0
D1
D1
D2
D2
D3
D3
DQ(CL2)
DQ(CL3)
Not Written
Figure 87.1 Clock Suspend During Write
CLK
CMD
CKE
RD
Masked byCKE
Internal
CLK
D
DQ(CL2)
DQ(CL3)
Q0
Q1
Q2
Q1
Q3
Q0
Q2 Q3
Suspended Dout
Figure 87.2 Clock Suspend During Read (BL = 4)
87.2 DQM Operation
CLK
CMD
DQM
WR
Masked by CKE
D3
DQ(CL2)
DQ(CL3)
D0
D0
D1
D1
D3
DQM to Data-in Mask = 0
Figure 87.1 Write Mask (BL = 4)
CLK
CMD
DQM
RD
Masked by CKE
Hi-Z
DQ(CL2)
DQ(CL3)
Q0
Q2
Q1
Q3
Hi-Z
Q2 Q3
DQM to Data-out Mask= 2
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
219
P r e l i m i n a r y
Figure 87.2 Read Mask (BL = 4)
CLK
CMD
RD
CKE
DQM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Q0
Q2
Q1
Q4
Q3
Q6
Q5
Q7
Q6
Q8
Q7
DQ(CL2)
DQ(CL3)
Ir)
ꢀꢁ &.(ꢂWRꢂ&/.ꢂGLVDEOHꢍHQDEOHꢂ ꢂꢀ&/.ꢁ
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ꢊꢁ '40ꢂPDVNVꢂERWKꢂGDWDꢃLQꢂDQGꢂGDWDꢃRXWꢁ
Figure 87.3 DQM with CLock Suspended (Full Page Read)
87.3 CAS# Interrupt 1
CLK
RD RD
CMD
ADD
A
B
DQ(CL2)
DQ(CL3)
QA0
QB
0
QB
1
QB
1
QB
3
QA0
QB0
QB1
QB1 QB3
Note 2
tCCD
Ir)
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&&'
ꢊꢁ W
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&'/
Figure 87.4 Read Interrupted by Read (BL = 4)
CLK
WR WR
CMD
Note 2
tCCD
A
B
ADD
DQ
DA
0 DB0 DB1
Note 3
tCDL
Ir)
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&$6ꢔꢀ,QWHUUXSWꢄꢂWRꢂVWRSꢂEXUVWꢂUHDGꢍZULWHꢂE\ꢂ&$6ꢅꢂDFFHVVꢇꢂUHDGꢂDQGꢂZULWHꢁ
ꢆꢁ W
ꢔꢂ&$6ꢅꢂWRꢂ&$6ꢅꢂGHOD\ꢂꢏ ꢂꢀ&/.ꢐꢁ
&&'
ꢊꢁ W
ꢔꢂ/DVWꢂGDWDꢂLQꢂWRꢂQHZꢂFROXPQꢂDGGUHVVꢂGHOD\ꢂꢏ ꢂꢀ&/.ꢐꢁ
&'/
Figure 87.5 Write Interrupted by Write (BL = 2)
220
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
CLK
WR RD
CMD
ADD
Note 2
tCCD
A
B
DQ(CL2)
DQ(CL3)
DA0
DA0
QB0 QB1
QB0 QB1
Note 3
tCDL
Ir)
ꢀꢁ %\ꢂ,QWHUUXSWꢄꢂ,WꢂLVꢂPHDQWꢂWRꢂVWRSꢂEXUVWꢂUHDGꢍZULWHꢂE\ꢂH[WHUQDOꢂFRPPDQGꢂEHIRUHꢂWKHꢂHQGꢂRIꢂEXUVWꢁꢂ%\ꢂ
&$6ꢔꢀ,QWHUUXSWꢄꢂWRꢂVWRSꢂEXUVWꢂUHDGꢍZULWHꢂE\ꢂ&$6ꢅꢂDFFHVVꢇꢂUHDGꢂDQGꢂZULWHꢁ
ꢆꢁ W
ꢔꢂ&$6ꢅꢂWRꢂ&$6ꢅꢂGHOD\ꢂꢏ ꢂꢀ&/.ꢐꢁ
&&'
ꢊꢁ W
ꢔꢂ/DVWꢂGDWDꢂLQꢂWRꢂQHZꢂFROXPQꢂDGGUHVVꢂGHOD\ꢂꢏ ꢂꢀ&/.ꢐꢁ
&'/
Figure 87.6 Write Interrupted by Read (BL = 2)
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
221
P r e l i m i n a r y
87.4 CAS# Interrupt 2
(a) CL=2, BL=4
CLK
1)CMD
RD WR
DQM
DQ
D0
D1
D2
D3
D2
2) CMD
RD
RD
RD
WR
DQM
DQ
Hi-Z
D0
D1
D3
WR
3)CMD
DQM
DQ
Hi-Z
D0
D1
D2
D1
D3
D2
4) CMD
WR
DQM
DQ
Hi-Z
Note 1
Q0
D0
D3
(b) CL=3, BL=4
CLK
RD WR
1)CMD
DQM
DQ
D0
D1
D2
D3
D2
) CMD
2
RD
WR
DQM
DQ
D0
D1
D3
D2
3)CMD
RD
RD
WR
DQM
DQ
D0
D1
D3
D2
D1
) CMD
4
WR
DQM
DQ
Hi-Z
D0
D1
D3
D2
5)CMD
RD
WR
DQM
DQ
Hi-Z
Note 1
Q0
D0
D3
Ir)
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Figure 87.7 Read Interrupted by Write and DQM
222
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
tRDL = 2CLK
CLK
Note 3
Note 2
CMD
DQM
WR
PRE
D0
D1
D2
DQ
Masked byDQM
Ir)
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DQGꢂGDWDꢂRXWꢁ
ꢆꢁ 7RꢂLQKLELWꢂLQYDOLGꢂZULWHꢄꢂ'40ꢂVKRXOGꢂEHꢂLVVXHGꢁ
ꢊꢁ 7KLVꢂSUHFKDUJHꢂFRPPDQGꢂDQGꢂEXUVWꢂZULWHꢂFRPPDQGꢂVKRXOGꢂEHꢂRIꢂWKHꢂVDPHꢂEDQNꢄꢂRWKHUZLVHꢂLWꢂLVꢂQRWꢂ
SUHFKDUJHꢂLQWHUUXSWꢂEXWꢂRQO\ꢂDQRWKHUꢂEDQNꢂSUHFKDUJHꢂRIꢂIRXUꢂEDQNVꢂRSHUDWLRQꢁꢂ
Figure 87.8 Write Interrupted by Precharge and DQM
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
DQ
WR
D0
PRE
D1
D2
D3
Note 1
tRDL
2) Normal Read (BL=4)
CLK
Note 2
RD
PRE
CMD
1
Q0
Q1 Q2 Q3
Q0 Q1 Q2 Q3
DQ(CL2)
2
DQ(CL3)
Ir)
ꢀꢁ W
ꢂꢆꢂ&/.ꢂLVꢂVXSSRUWHGꢁ
5'/ꢂ
ꢆꢁ 1XPEHUꢂRIꢂYDOLGꢂRXWSXWꢂGDWDꢂDIWHUꢂURZꢂSUHFKDUJHꢔꢂꢀꢄꢂꢆꢂIRUꢂ&$6ꢂ/DWHQF\ꢂ ꢂꢆꢄꢂꢊꢂUHVSHFWLYHO\ꢁ
ꢊꢁ 7KHꢂURZꢂDFWLYHꢂFRPPDQGꢂRIꢂWKHꢂSUHFKDUJHꢂEDQNꢂFDQꢂEHꢂLVVXHGꢂDIWHUꢂW ꢂIURPꢂWKLVꢂSRLQWꢁꢂ7KHꢂQHZꢂ
53
UHDGꢍZULWHꢂFRPPDQGꢂRIꢂRWKHUꢂDFWLYDWHGꢂEDQNꢂFDQꢂEHꢂLVVXHGꢂIURPꢂWKLVꢂSRLQWꢁꢂ$WꢂEXUVWꢂUHDGꢍZULWHꢂZLWKꢂ
DXWRꢂSUHFKDUJHꢄꢂ&$6ꢂLQWHUUXSWꢂRIꢂWKHꢂVDPHꢂEDQNꢂLVꢂLOOHJDOꢁ
ꢎꢁ W
ꢂGHILQHGꢂ/DVWꢂGDWDꢂLQꢂWRꢂ$FWLYHꢂGHOD\ꢁꢂW
ꢂW
ꢓꢂW ꢂLVꢂVXSSRUWHGꢁ
'$/
'$/ꢂ
5'/ꢂ 53
Figure 87.9 Precharge
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
223
P r e l i m i n a r y
1) Normal Write (BL=4)
CLK
2) Nomr al Read (BL=4)
CLK
CMD
DQ
WR
D0
ACT
CMD
RD
DQ(CL2)
DQ(CL3)
Q0
Q1 Q2
Q0 Q1 Q2
Auto Precharge StartsNote 3
Q3
D1
D2
D3
tRDL=2CLK
tDAL=tRDL +tRP Note 4
Q3
Auto Precharge Starts@tRDL=2CLK *3
Ir)
ꢀꢁ W
ꢂꢆꢂ&/.ꢂLVꢂVXSSRUWHGꢁ
5'/ꢂ
ꢆꢁ 1XPEHUꢂRIꢂYDOLGꢂRXWSXWꢂGDWDꢂDIWHUꢂURZꢂSUHFKDUJHꢔꢂꢀꢄꢂꢆꢂIRUꢂ&$6ꢂ/DWHQF\ꢂ ꢂꢆꢄꢂꢊꢂUHVSHFWLYHO\ꢁ
ꢊꢁ 7KHꢂURZꢂDFWLYHꢂFRPPDQGꢂRIꢂWKHꢂSUHFKDUJHꢂEDQNꢂFDQꢂEHꢂLVVXHGꢂDIWHUꢂW ꢂIURPꢂWKLVꢂSRLQWꢁꢂ7KHꢂQHZꢂ
53
UHDGꢍZULWHꢂFRPPDQGꢂRIꢂRWKHUꢂDFWLYDWHGꢂEDQNꢂFDQꢂEHꢂLVVXHGꢂIURPꢂWKLVꢂSRLQWꢁꢂ$WꢂEXUVWꢂUHDGꢍZULWHꢂZLWKꢂ
DXWRꢂSUHFKDUJHꢄꢂ&$6ꢂLQWHUUXSWꢂRIꢂWKHꢂVDPHꢂEDQNꢂLVꢂLOOHJDOꢁ
ꢎꢁ W
ꢂGHILQHGꢂ/DVWꢂGDWDꢂLQꢂWRꢂ$FWLYHꢂGHOD\ꢁꢂW
ꢂW
ꢓꢂW ꢂLVꢂVXSSRUWHGꢁ
'$/
'$/ꢂ
5'/ꢂ 53
Figure 87.10 Auto Precharge
224
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
1) Nomr al Write
BL=4 & tRDL=2CLK
CLK
WR
D0
PRE
CMD
DQM
D1
D2
DQ
Note 1
tRDL
2) WriteBurst Stop (BL=8)
CLK
3)Read Interrupted by Precharge (BL=4)
CLK
WR
STOP
RD
PRE
Q0
CMD
CMD
1
DQ(CL2)
Q1
Q0
DQM
DQ
2
D0
D1
D2
D3
Q1
DQ(CL3)
Note 2
tBDL
4) ReadBurst Stop (BL=4)
CLK
RD
STOP
Q0
CMD
1
Q1
Q0
DQ(CL2)
2
Q1
DQ(CL3)
Ir)
ꢀꢁ W
ꢂꢆꢂ&/.ꢂLVꢂVXSSRUWHGꢁ
5'/ꢂ
ꢆꢁ W
ꢔꢂꢀꢂ&/.ꢇꢂ/DVWꢂGDWDꢂLQꢂWRꢂEXUVWꢂVWRSꢂGHOD\ꢁꢂ5HDGꢂRUꢂZULWHꢂEXUVWꢂVWRSꢂFRPPDQGꢂLVꢂYDOLGꢂDWꢂHYHU\ꢂ
%'/
EXUVWꢂOHQJWKꢁ
ꢊꢁ 1XPEHUꢂRIꢂYDOLGꢂRXWSXWꢂGDWDꢂDIWHUꢂURZꢂSUHFKDUJHꢂRUꢂEXUVWꢂVWRSꢔꢂꢀꢄꢂꢆꢂIRUꢂ&$6ꢂODWHQF\ ꢂꢆꢄꢂꢊꢂUHVSHFꢃ
WLYHO\ꢁꢂ
ꢎꢁ 35(ꢔꢂ$OOꢂEDQNVꢂSUHFKDUJHꢂLVꢂQHFHVVDU\ꢁꢂ056ꢂFDQꢂEHꢂLVVXHGꢂRQO\ꢂDWꢂDOOꢂEDQNVꢂSUHFKDUJHꢂVWDWHꢁ
Figure 87.11 Burst Stop and Interrupted by Precharge
1) Mode Register Set
CLK
Note 4
CMD
PRE
MRS
ACT
tRP
2CLK
Ir)
ꢀꢁ W
ꢂꢆꢂ&/.ꢂLVꢂVXSSRUWHGꢁ
5'/ꢂ
ꢆꢁ W
ꢔꢂꢀꢂ&/.ꢇꢂ/DVWꢂGDWDꢂLQꢂWRꢂEXUVWꢂVWRSꢂGHOD\ꢁꢂ5HDGꢂRUꢂZULWHꢂEXUVWꢂVWRSꢂFRPPDQGꢂLVꢂYDOLGꢂDWꢂHYHU\ꢂ
%'/
EXUVWꢂOHQJWKꢁ
ꢊꢁ 1XPEHUꢂRIꢂYDOLGꢂRXWSXWꢂGDWDꢂDIWHUꢂURZꢂSUHFKDUJHꢂRUꢂEXUVWꢂVWRSꢔꢂꢀꢄꢂꢆꢂIRUꢂ&$6ꢂODWHQF\ ꢂꢆꢄꢂꢊꢂUHVSHFꢃ
WLYHO\ꢁꢂ
ꢎꢁ 35(ꢔꢂ$OOꢂEDQNVꢂSUHFKDUJHꢂLVꢂQHFHVVDU\ꢁꢂ056ꢂFDQꢂEHꢂLVVXHGꢂRQO\ꢂDWꢂDOOꢂEDQNVꢂSUHFKDUJHꢂVWDWHꢁ
Figure 87.12 Mode Register Set
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
225
P r e l i m i n a r y
1) Clock Suspend (= Active Power Down) Exit
2) Power Down (= Precharge Power Down) Exit
CLK
CLK
CKE
CKE
tSS
tSS
Note 2
Note 1
Internal
CLK
Internal
CLK
RD
NOP ACT
CMD
CMD
Figure 87.13 Clock Suspend Exit and Power Down Exit
87.5 Auto Refresh
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:(ꢔꢀKLJKꢀDWꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀFORFNꢀꢁ&/.ꢂꢃꢀ$OOꢀEDQNVꢀPXVWꢀEHꢀSUHFKDUJHGꢀDQGꢀLGOHꢀIRU
W53ꢁPLQꢂꢀEHIRUHꢀWKHꢀDXWRꢀUHIUHVKꢀFRPPDQGꢀLVꢀDSSOLHGꢃꢀ1RꢀFRQWUROꢀRIꢀWKHꢀH[WHUQDOꢀDGGUHVVꢀSLQV
LVꢀUHTXLUHGꢀRQFHꢀWKLVꢀF\FOHꢀKDVꢀVWDUWHGꢀEHFDXVHꢀRIꢀWKHꢀLQWHUQDOꢀDGGUHVVꢀFRXQWHUꢃꢀ:KHQꢀWKHꢀUHꢅ
IUHVKꢀF\FOHꢀKDVꢀFRPSOHWHGꢄꢀDOOꢀEDQNVꢀZLOOꢀEHꢀLQꢀWKHꢀLGOHꢀVWDWHꢃꢀ$ꢀGHOD\ꢀEHWZHHQꢀWKHꢀDXWRꢀUHIUHVK
FRPPDQGꢀDQGꢀWKHꢀQH[WꢀDFWLYDWHꢀFRPPDQGꢀRUꢀVXEVHTXHQWꢀDXWRꢀUHIUHVKꢀFRPPDQGꢀPXVWꢀEH
JUHDWHUꢀWKDQꢀRUꢀHTXDOꢀWRꢀWKHꢀW$5)&ꢁPLQꢂ
ꢃ
CLK
Auto
Refresh
PRE
CMD
Command
CKE = High
tRP
tARFC(min)
Figure 87.14 Auto Refresh
87.6 Self Refresh
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KLJKꢀDWꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀFORFNꢃꢀ2QFHꢀWKHꢀVHOIꢀ5HIUHVKꢀFRPPDQGꢀLVꢀLQLWLDWHGꢄꢀ&.(ꢀPXVWꢀEH
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FRPPDQGꢄꢀDOOꢀRIꢀWKHꢀH[WHUQDOꢀFRQWUROꢀVLJQDOVꢀLQFOXGLQJꢀV\VWHPꢀFORFNꢀꢁ&/.ꢂꢀFDQꢀEHꢀGLVDEOHGꢀH[ꢅ
FHSWꢀ&.(ꢃꢀ7KHꢀFORFNꢀLVꢀLQWHUQDOO\ꢀGLVDEOHGꢀGXULQJꢀ6HOIꢀ5HIUHVKꢀRSHUDWLRQꢀWRꢀUHGXFHꢀSRZHUꢃꢀ7R
H[LWꢀWKHꢀ6HOIꢀ5HIUHVKꢀPRGHꢄꢀVXSSO\ꢀVWDEOHꢀFORFNꢀLQSXWꢀEHIRUHꢀUHWXUQLQJꢀ&.(ꢀKLJKꢄꢀDVVHUWꢀGHVHꢅ
OHFWꢀRUꢀ123ꢀFRPPDQGꢀDQGꢀWKHQꢀDVVHUWꢀ&.(ꢀKLJKꢃꢀ,QꢀFDVHꢀWKDWꢀWKHꢀV\VWHPꢀXVHVꢀEXUVWꢀDXWR
UHIUHVKꢀGXULQJꢀQRUPDOꢀRSHUDWLRQꢄꢀLWꢀLVꢀUHFRPPHQGHGꢀWRꢀXVHꢀEXUVWꢀDXWRꢀUHIUHVKꢀF\FOHꢀLPPHGLꢅ
DWHO\ꢀEHIRUHꢀHQWHULQJꢀVHOIꢀUHIUHVKꢀPRGHꢀDQGꢀDIWHUꢀH[LWLQJꢀLQꢀVHOIꢀUHIUHVKꢀPRGHꢃꢀ2QꢀWKHꢀRWKHU
KDQGꢄꢀLIꢀWKHꢀV\VWHPꢀXVHVꢀWKHꢀGLVWULEXWHGꢀDXWRꢀUHIUHVKꢄꢀWKHꢀV\VWHPꢀRQO\ꢀKDVꢀWRꢀNHHSꢀWKHꢀUHIUHVK
GXW\ꢀF\FOHꢃ
CLK
Stable Clock
Self
Refresh
ACT
NOP
Command
CKE
tSRFX(min)
tSS
tSS
Figure 87.15 Self Refresh
226
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
88 Burst Type Control
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6HTXHQWLDOꢀ&RXQWLQJ
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0RGH
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5DQGRP
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5DQGRPꢀ
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89 Burst Length Control
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ꢇ
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,QWHUUXSW
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%HIRUHꢀWKHꢀHQGꢀRIꢀEXUVWꢄꢀQHZꢀUHDGꢒZULWHꢀVWRSVꢀUHDGꢒZULWHꢀEXUVWꢀDQGꢀVWDUWVꢀQHZꢀ
UHDGꢒZULWHꢀEXUVWꢃ
'XULQJꢀUHDGꢒZULWHꢀEXUVWꢀZLWKꢀDXWRꢀSUHFKDUJHꢄꢀ&$6ꢔꢀLQWHUUXSWꢀFDQꢀQRWꢀEHꢀLVVXHGꢃ
&$6ꢔꢀ,QWHUUXSW
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
227
/
$ꢇꢌꢒ$37HUPꢀEXUVUWH
P r e l i m i n a r y
90 Function Truth Table 1
Current
State
CS#
RAS# CAS# WE#
BA
Address
Action
Note
+
/
/
/
/
/
/
/
+
/
/
/
/
/
/
/
+
/
/
/
/
/
/
/
+
/
/
/
/
/
/
/
+
/
/
/
/
/
+
/
/
/
/
/
+
/
/
/
/
/
;
+
+
+
/
;
+
+
/
;
+
/
;
;
;
;
;
123
123
;
,//(*$/
ꢏ
ꢏ
;
+
/
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3,//(*$/
,'/(
+
+
/
5$
5RZꢀꢁꢓꢀ%DQNꢂꢀ$FWLYHꢕꢀ/DWFKꢀ5$
/
$ꢇꢌꢒ$3123
ꢍ
ꢊ
ꢊ
/
+
/
;
$XWRꢀ5HIUHVKꢀRUꢀ6HOIꢀ5HIUHVK
/
/
23ꢀFRGH
;
23ꢀFRGH
0RGHꢀ5HJLVWHUꢀ$FFHVV
;
+
+
+
+
/
;
+
+
/
;
+
/
;
;
;
123
;
123
;
,//(*$/
ꢏ
ꢏ
+
/
%$
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3%HJLQꢀ5HDGꢕꢀODWFKꢀ&$ꢕꢀGHWHUPLQHꢀ$3
&$ꢄꢀ$ꢇꢌꢒ$3%HJLQꢀ5HDGꢕꢀODWFKꢀ&$ꢕꢀGHWHUPLQHꢀ$3
5RZ
$FWLYH
/
+
+
/
+
/
5$
,//(*$/
/
$ꢇꢌꢒU$H3F3KDUJH
/
;
;
+
/
;
;
;
;
,//(*$/
;
+
+
+
+
/
;
+
+
/
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢂ
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢂ
7HUPꢀEXUVWꢀꢅꢅ!ꢀ5RZꢀDFWLYHꢀ
;
;
+
/
%$
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ5HDGꢄꢀ'HWHUPLQHꢀ$3
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ:ULWHꢄꢀ'HWHUPLQHꢀ$3
5HDG
/
ꢑ
ꢏ
+
+
/
+
/
5$
,//(*$/
F3KDUJHꢀWLPLQJꢀIRUꢀ5HDGV
,//(*$/
/
;
;
+
/
;
;
;
;
;
+
+
+
+
/
;
+
+
/
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢂ
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢂ
7HUPꢀEXUVWꢀꢅꢅ!ꢀ5RZꢀDFWLYH
;
;
+
/
%$
%$
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀUHDGꢄꢀ'HWHUPLQHꢀ$3
&$ꢄꢀ$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀ1HZꢀ:ULWHꢄꢀ'HWHUPLQHꢀ$3
ꢑ
ꢑ
ꢏ
ꢑ
:ULWH
/
+
+
/
+
/
5$
,//(*$/
/
$ꢇꢌꢒ$37HUPꢀEXUVWꢄꢀSUHFKDUJHꢀWLPLQJꢀIRUꢀ:ULWHV
/
;
;
+
/
;
;
;
;
,//(*$/
;
+
+
+
/
;
+
+
/
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
,//(*$/
;
5HDGꢀZLWK
$XWR
3UHFKDUJH
;
;
;
;
;
+
/
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3,//(*$/
5$ꢄꢀ5$ꢇꢌ ,//(*$/
+
/
ꢏ
ꢏ
/
;
;
;
;
,//(*$/
;
+
+
+
/
;
+
+
/
;
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
123ꢀꢁ&RQWLQXHꢀ%XUVWꢀWRꢀ(QGꢀꢅꢅ!ꢀ3UHFKDUJHꢂ
,//(*$/
;
:ULWHꢀZLWK
$XWR
3UHFKDUJH
;
;
;
;
;
+
/
%$
%$
;
&$ꢄꢀ$ꢇꢌꢒ$3,//(*$/
5$ꢄꢀ5$ꢇꢌ ,//(*$/
+
/
/
;
;
,//(*$/
;
+
+
+
/
;
+
+
/
;
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW53
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW53
,//(*$/
;
;
;
;
ꢏ
ꢏ
ꢏ
ꢍ
3UHFKDUJLQJ
;
+
/
%$
%$
%$
&$
5$
,//(*$/
+
+
,//(*$/
/
$ꢇꢌꢒ$3 ꢀꢅꢅ!3 ꢀ,GOHꢀDIWHUꢀW
53
228
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
/
+
/
/
/
/
/
/
+
/
/
/
/
+
/
/
/
/
/
;
+
+
+
/
/
;
+
+
/
;
;
+
/
;
;
;
;
,//(*$/
123ꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢀDIWHUꢀW5&'
123ꢀꢅꢅ!ꢀ5RZꢀ$FWLYHꢀDIWHUꢀW5&'
,//(*$/
;
;
;
;
ꢏ
ꢏ
ꢏ
ꢏ
5RZꢀ
$FWLYDWLQJ
;
+
/
%$
%$
%$
;
&$
5$
,//(*$/
+
+
/
,//(*$/
/
$ꢇꢌꢒ$3,//(*$/
/
;
;
;
;
;
;
;
+
/
;
;
;
;
;
;
;
;
;
;
;
,//(*$/
;
+
+
/
;
+
/
;
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW5&
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀW5&
,//(*$/
;
5HIUHVKLQJ
;
+
/
;
,//(*$/
/
;
,//(*$/
;
+
+
+
/
;
+
+
/
;
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀꢏꢀFORFNV
123ꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀꢏꢀFORFNV
,//(*$/
;
0RGHꢀ
5HJLVWHU
$FFHVVLQJ
;
;
;
;
,//(*$/
;
;
,//(*$/
Grtrq)ꢂ5$ꢂ ꢂ5RZꢂ$GGUHVVꢄꢂ%$ꢂ ꢂ%DQNꢂ$GGUHVVꢄꢂ123ꢂ ꢂ1Rꢂ2SHUDWLRQꢂ&RPPDQGꢄꢂ&$ ꢂ&ROXPQꢂ$Gꢃ
GUHVVꢄꢂ$3ꢂ ꢂ$XWRꢂ3UHFKDUJH
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ꢀꢁ $OOꢂHQWULHVꢂDVVXPHꢂWKHꢂ&.(ꢂZDVꢂDFWLYHꢂꢏ+LJKꢐꢂGXULQJꢂWKHꢂSUHFKDUJHꢂFORFNꢂDQGꢂWKHꢂFXUUHQWꢂFORFNꢂF\FOHꢁ
ꢆꢁ ,OOHJDOꢂWRꢂEDQNꢂLQꢂVSHFLILHGꢂVWDWHꢇꢂ)XQFWLRQꢂPD\ꢂEHꢂOHJDOꢂLQꢂWKHꢂEDQNꢂLQGLFDWHGꢂE\ꢂ%$ꢄꢂGHSHQGLQJꢂRQꢂ
WKHꢂVWDWHꢂRIꢂWKDWꢂEDQNꢁ
ꢊꢁ 0XVWꢂVDWLVI\ꢂEXVꢂFRQWHQWLRQꢄꢂEXVꢂWXUQꢂDURXQGꢄꢂDQGꢍRUꢂZULWHꢂUHFRYHU\ꢂUHTXLUHPHQWVꢁ
ꢎꢁ 123ꢂWRꢂEDQNꢂSUHFKDUJLQJꢂRUꢂLQꢂLGOHꢂVWDWHꢁꢂ0D\ꢂSUHFKDUJHꢂEDQNꢂLQGLFDWHGꢂE\ꢂ%$ꢂꢏDQGꢂ$ꢀꢈꢍ$3ꢐꢁ
ꢉꢁ ,OOHJDOꢂLIꢂDQ\ꢂEDQNꢂLVꢂQRWꢂLGOHꢁꢂ
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
229
P r e l i m i n a r y
91 Function Truth Table 2
Current
State
CKE
(n-1)
CKE
n
CS#
RAS#
CAS#
WE#
Address
Action
Note
([LWꢀ6HOIꢀ5HIUHVKꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀ
+
/
;
+
;
+
;
;
;
;
;
;
;
;
([LWꢀ6HOIꢀ5HIUHVKꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀWV5);
ꢀ
ꢀ
ꢇ
ꢇ
([LWꢀ6HOIꢀ5HIUHVKꢀꢅꢅ!ꢀ,GOHꢀDIWHUꢀWV5);
/
/
+
+
+
+
/
/
/
+
+
+
/
+
+
/
+
/
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
5$
;
6HOI
5HIUHVK
,//(*$/
/
/
;
;
;
;
;
+
/
,//(*$/
/
/
;
;
;
;
+
+
/
,//(*$/
/
;
;
+
/
;
;
;
+
+
+
/
123ꢀꢁ0DLQWDLQꢀ6HOIꢀ5HIUHVKꢂ
,19$/,'
+
/
;
+
+
+
+
+
/
([LWꢀ3RZHUꢀ'RZQꢀꢅꢅ!ꢀ$%,
([LWꢀ3RZHUꢀ'RZQꢀꢅꢅ!ꢀ$%,
,//(*$/
$OOꢀ
%DQNVꢀ
3UHFKDUJH
3RZHUꢀ
'RZQ
/
ꢏ
ꢏ
/
/
/
/
;
;
;
;
;
+
/
,//(*$/
/
/
;
;
;
;
+
+
/
,//(*$/
/
;
;
+
/
;
;
;
+
+
+
/
123ꢀꢁ0DLQWDLQꢀ/RZꢀ3RZHUꢀ0RGHꢂ
5HIHUꢀWRꢀ)XQFWLRQꢀ7UXWKꢀ7DEOHꢀꢇ
(QWHUꢀ3RZHUꢀ'RZQ
(QWHUꢀ3RZHUꢀ'RZQ
,//(*$/
+
+
+
+
+
+
+
+
/
+
/
/
ꢑ
ꢑ
$OO
%DQNV
,GOH
/
/
/
/
;
+
+
/
,//(*$/
/
/
+
/
5RZꢀꢁꢓꢀ%DQNꢂꢀ$FWLYH
(QWHUꢀ6HOIꢀ5HIUHVK
/
/
/
ꢑ
/
/
/
/
23ꢀ&RGH 0RGHꢀ5HJLVWHUꢀ$FFHVV
/
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
123
+
+
/
+
/
5HIHUꢀWRꢀ)XQFWLRQꢀ7UXWKꢀ7DEOHꢀꢇ
%HJLQꢀ&ORFNꢀ6XVSHQGꢀQH[WꢀF\FOH
([LWꢀ&ORFNꢀ6XVSHQGꢀQH[WꢀF\FOH
0DLQWDLQꢀ&ORFNꢀ6XVSHQG
$Q\ꢀ6WDWHꢀ
RWKHUꢀ
WKDQ/LVWHGD
ERYH
ꢍ
ꢍ
+
/
/
Grtrq)ꢂ$%,ꢂ ꢂ$OOꢂ%DQNVꢂ,GOHꢄꢂ5$ꢂ ꢂ5RZꢂ$GGUHVV
Ir)
ꢀꢁ &.(ꢂORZꢂWRꢂKLJKꢂWUDQVLWLRQꢂLVꢂDV\QFKURQRXVꢁ
ꢆꢁ &.(ꢂORZꢂWRꢂKLJKꢂWUDQVLWLRQꢂLVꢂDV\QFKURQRXVꢂLIꢂUHVWDUWVꢂLQWHUQDOꢂFORFNꢁꢂ$ꢂPLQLPXPꢂVHWXSꢂWLPHꢂꢀ&/.ꢂ
ꢓꢂW ꢂPXVWꢂEHꢂVDWLVILHGꢂEHIRUHꢂDQ\ꢂFRPPDQGꢂRWKHUꢂWKDQꢂH[LWꢁ
66
ꢊꢁ 3RZHUꢂGRZQꢂDQGꢂVHOIꢂUHIUHVKꢂFDQꢂEHꢂHQWHUHGꢂRQO\ꢂIURPꢂWKHꢂDOOꢂEDQNVꢂLGOHꢂVWDWHꢁ
ꢎꢁ 0XVWꢂEHꢂDꢂOHJDOꢂFRPPDQGꢁ
230
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
92 Timing Diagrams
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CLOCK
CKE
Hi
CS#
RAS#
CAS#
ADDR
BA0
Key
Key
RAa
BA1
A10/AP
DQ
RAa
Hi-Z
Hi-Z
WE#
DQM
High level is necessary
tRP
tARFC
tARFC
Precharge
(AllBank)
Auto
Refresh
Auto
Refresh
Normal
MRS
Extended
MRS
Row Active
(A-Bank)
: Don’t care
Ir)
ꢀꢁ $SSO\ꢂSRZHUꢂDQGꢂDWWHPSWꢂWRꢂPDLQWDLQꢂ&.(ꢂDWꢂDꢂKLJKꢂVWDWHꢂDQGꢂDOOꢂRWKHUꢂLQSXWVꢂPD\ꢂEHꢂXQGHILQHGꢁ
ꢃꢂ$SSO\ꢂ9 ꢂEHIRUHꢂRUꢂDWꢂWKHꢂVDPHꢂWLPHꢂDVꢂ9
ꢁ
''4
''
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ꢊꢁ ,VVXHꢂSUHFKDUJHꢂFRPPDQGVꢂIRUꢂDOOꢂEDQNVꢂRIꢂWKHꢂGHYLFHVꢁ
ꢎꢁ ,VVXHꢂꢆꢂRUꢂPRUHꢂDXWRꢃUHIUHVKꢂFRPPDQGVꢁ
ꢉꢁ ,VVXHꢂDꢂPRGHꢂUHJLVWHUꢂVHWꢂFRPPDQGꢂWRꢂLQLWLDOL]HꢂWKHꢂPRGHꢂUHJLVWHUꢁ
ꢌꢁ ,VVXHꢂDꢂH[WHQGHGꢂPRGHꢂUHJLVWHUꢂVHWꢂFRPPDQGꢂWRꢂGHILQHꢂ'6ꢂRUꢂ3$65ꢂRSHUDWLQJꢂW\SHꢂRIꢂWKHꢂGHYLFHꢂ
DIWHUꢂQRUPDOꢂ056ꢁ
(056ꢂF\FOHꢂLVꢂQRWꢂPDQGDWRU\ꢂDQGꢂWKHꢂ(056ꢂFRPPDQGꢂQHHGVꢂWRꢂEHꢂLVVXHGꢂRQO\ꢂZKHQꢂ
'6ꢂRUꢂ3$65ꢂLVꢂXVHGꢁ
7KHꢂGHIDXOWꢂVWDWHꢂZLWKRXWꢂ(056ꢂFRPPDQGꢂLVVXHGꢂLVꢂKDOIꢂGULYHUꢂVWUHQJWKꢂDQGꢂIXOOꢂDUUD\ꢂ
UHIUHVKHGꢁ
7KHꢂGHYLFHꢂLVꢂQRZꢂUHDG\ꢂIRUꢂWKHꢂRSHUDWLRQꢂVHOHFWHGꢂE\ꢂ(056ꢁ
)RUꢂRSHUDWLQJꢂZLWKꢂ'6ꢂRUꢂ3$65ꢄꢂVHWꢂ'6ꢂRUꢂ3$65ꢂPRGHꢂLQꢂ(056ꢂVHWWLQJꢂVWDJHꢁ
,QꢂRUGHUꢂWRꢂDGMXVWꢂDQRWKHUꢂPRGHꢂLQꢂWKHꢂVWDWHꢂRIꢂ'6ꢂRUꢂ3$65ꢂPRGHꢄꢂDGGLWLRQDOꢂ(056ꢂ
VHWꢂLVꢂUHTXLUHGꢂEXWꢂSRZHUꢂXSꢂVHTXHQFHꢂLVꢂQRWꢂQHHGHGꢂDJDLQꢂDWꢂWKLVꢂWLPHꢁꢂ,QꢂWKDWꢂFDVHꢄꢂ
DOOꢂEDQNVꢂKDYHꢂWRꢂEHꢂLQꢂLGOHꢂVWDWHꢂSULRUꢂWRꢂDGMXVWLQJꢂ(056ꢂVHWꢁ
Figure 92.1 Power Up Sequence
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
231
P r e l i m i n a r y
tCH
4
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
tCC
tCL
HIGH
tRP
tRAS
tRC
*Note 1
tSH
CS#
tRCD
tSS
tSH
tSH
RAS#
CAS#
tSS
tSH
tSS
Ca
ADDR
BA0,BA1
A10/AP
Ra
Cb
Cc
Rb
tSS
*Note 2
BS
*Note 2,3
BS
*Note 2,3
BS
*Note 2,3 *Note 4
BS BS
*Note 2
BS
*Note 3
*Note 3
*Note 3 *Note 4
Ra
Rb
tSH
Db
tSAC
Qa
DQ
WE#
DQM
Qc
tSS
tSS tSH
tSLZ
tOH
tSS tSH
Row Active
Read
Write
Read
Row Active
Precharge
: Don’t care
Ir)
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ꢆꢁ %DQNꢂDFWLYHꢂꢗꢂUHDGꢍZULWHꢂDUHꢂFRQWUROOHGꢂE\ꢂ%$ꢈꢄꢂ%$ꢀꢁ
Figure 92.2 Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst
Length=1
232
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note 1
tRC
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
Ra
Ca
Rb
Cb
BA1
A10/AP
CL=2
Ra
Rb
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
tSHZ
tRCD
tSAC
tOH
*Note 4
tSHZ
DQ
CL=3
Qa0 Qa1 Qa2 Qa3
tSAC
tRDL
*Note 4
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Ir)
ꢀꢁ 0LQLPXPꢂURZꢂF\FOHꢂWLPHVꢂLVꢂUHTXLUHGꢂWRꢂFRPSOHWHꢂLQWHUQDOꢂ'5$0ꢂRSHUDWLRQꢁ
ꢆꢁ 5RZꢂSUHFKDUJHꢂFDQꢂLQWHUUXSWꢂEXUVWꢂRQꢂDQ\ꢂF\FOHꢁꢂ>&$6ꢂ/DWHQF\ꢂꢃꢂꢀ@ꢂQXPEHUꢂRIꢂYDOLGꢂRXWSXWꢂGDWDꢂLVꢂ
DYDLODEOHꢂDIWHUꢂ5RZꢂSUHFKDUJHꢁꢂ/DVWꢂYDOLGꢂRXWSXWꢂZLOOꢂEHꢂ+Lꢃ=ꢂꢏW ꢐꢂDIWHUꢂWKHꢂFORFNꢁ
6+=
ꢊꢁ 2XWSXWꢂZLOOꢂEHꢂ+Lꢃ=ꢂDIWHUꢂWKHꢂHQGꢂRIꢂEXUVWꢁꢂꢏꢀꢄꢂꢆꢄꢂꢎꢄꢂꢑꢂꢗꢂ)XOOꢂSDJHꢂELWꢂEXUVWꢐꢁ
Figure 92.3 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
233
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note 1
tRC
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
Ra
Ca
Rb
Cb
BA1
A10/AP
CL=2
Ra
Rb
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
tSHZ
tRCD
tSAC
tOH
*Note 4
tSHZ
DQ
CL=3
Qa0 Qa1 Qa2 Qa3
tSAC
tRDL
*Note 4
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Ir)
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WRꢂDYRLGꢂEXVꢂFRQWHQWLRQꢁ
ꢆꢁ 5RZꢂSUHFKDUJHꢂZLOOꢂLQWHUUXSWꢂZULWLQJꢁꢂ/DVWꢂGDWDꢂLQSXWꢄꢂW
ꢂEHIRUHꢂ5RZꢂSUHFKDUJHꢄꢂZLOOꢂEHꢂZULWWHQꢁ
5'/
ꢊꢁ '40ꢂVKRXOGꢂPDVNꢂLQYDOLGꢂLQSXWꢂGDWDꢂRQꢂSUHFKDUJHꢂFRPPDQGꢂF\FOHꢂZKHQꢂDVVHUWLQJꢂSUHFKDUJHꢂEHIRUHꢂ
HQGꢂRIꢂEXUVWꢁꢂ,QSXWꢂGDWDꢂDIWHUꢂ5RZꢂSUHFKDUJHꢂF\FOHꢂZLOOꢂEHꢂPDVNHGꢂLQWHUQDOO\ꢁꢂ
ꢎꢁ W
ꢄODVWꢂGDWDꢂLQꢂWRꢂDFWLYHꢂGHOD\ꢄꢂLVꢂꢆ&/.ꢂꢓꢂW
ꢁ
53
'$/
Figure 92.4 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
234
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note 1
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BA1
A10/AP
CL=2
RAa
RBb
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2
QDd0 QDd1 QDd2
DQ
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(C-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
Precharge
(C-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
: Don’t care
Ir)
ꢀꢁ &6ꢅꢂFDQꢂEHꢂGRQꢘWꢂFDUHGꢂZKHQꢂ5$6ꢅꢄꢂ&$6ꢅꢂDQGꢂ:(ꢅꢂDUHꢂKLJKꢂDWꢂWKHꢂFORFNꢂKLJKꢂJRLQJꢂHGJHꢁ
ꢆꢁ 7RꢂLQWHUUXSWꢂDꢂEXUVWꢂUHDGꢂE\ꢂURZꢂSUHFKDUJHꢄꢂERWKꢂWKHꢂUHDGꢂDQGꢂWKHꢂSUHFKDUJHꢂEDQNVꢂPXVWꢂEHꢂWKHꢂ
VDPHꢁ
Figure 92.5 Page Read Cycle at Different Bank @Burst Length=4
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
235
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
*Note 2
RAa
RAb CAa
CBb RCc
RDd CCc
CDd
BA1
A10/AP
DQ
RAa
RBb
RCc
RDd
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
tRDL
WE#
*Note 1
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Precharge
(All Banks)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
: Don’t care
Ir)
ꢀꢁ 7RꢂLQWHUUXSWꢂEXUVWꢂZULWHꢂE\ꢂ5RZꢂSUHFKDUJHꢄꢂ'40ꢂVKRXOGꢂEHꢂDVVHUWHGꢂWRꢂPDVNꢂLQYDOLGꢂLQSXWꢂGDWDꢁ
ꢆꢁ 7RꢂLQWHUUXSWꢂEXUVWꢂZULWHꢂE\ꢂ5RZꢂSUHFKDUJHꢄꢂERWKꢂWKHꢂZULWHꢂDQGꢂWKHꢂSUHFKDUJHꢂEDQNVꢂPXVWꢂEHꢂWKHꢂ
VDPHꢁ
Figure 92.6 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
236
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
RAa
CAa
RDb
CDb RBc
CBc
BA1
A10/AP
CL=2
RAa
RDb
RBc
tCDL
*Note 1
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
QBc0 QBc1
DQ
{
CL=3
QAa0 QAa1 QAa2 QAa3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: Don’t care
Ir)
ꢀꢁ W
ꢂVKRXOGꢂEHꢂPHWꢂWRꢂFRPSOHWHꢂZULWHꢁ
&'/
Figure 92.7 Read & Write Cycle at Different Bank @Burst Length=4
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
237
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
RAa
RBb CAa
CBb
RAc
CAc
BA1
A10/AP
DQ CL=2
RAa
RBb
RAc
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
DAc0 DAc1
CL=3
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
WE#
DQM
Row Active
(A-Bank)
Read with Read without Auto
Auto Pre Precharge(B-Bank)
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
charge
Auto Precharge
Start Point
(A-Bank)
(A-Bank) *Note1
Row Active
(B-Bank)
: Don’t care
Ir)
ꢀꢁ :KHQꢂ5HDGꢂꢏ:ULWHꢐꢂFRPPDQGꢂZLWKꢂDXWRꢂSUHFKDUJHꢂLVꢂLVVXHGꢂDWꢂ$ꢃ%DQNꢂDIWHUꢂ$ꢂDQGꢂ%ꢂ%DQNꢂDFWLYDWLRQꢁꢂ
,Iꢂ5HDGꢂꢏ:ULWHꢐꢂFRPPDQGꢂZLWKRXWꢂDXWRꢂSUHFKDUJHꢂLVꢂLVVXHGꢂDWꢂ%ꢃ%DQNꢂEHIRUHꢂ$ꢃ%DQNꢂDXWRꢂSUHFKDUJHꢂ
VWDUWVꢄꢂ$ꢃ%DQNꢂDXWRꢂSUHFKDUJHꢂZLOOꢂVWDUWꢂDWꢂ%ꢃ%DQNꢂUHDGꢂFRPPDQGꢂLQSXWꢂSRLQWꢁ
$Q\ꢂFRPPDQGꢂFDQꢂQRWꢂEHꢂLVVXHGꢂDWꢂ$ꢃ%DQNꢂGXULQJꢂW ꢂDIWHUꢂ$ꢃ%DQNꢂDXWRꢂSUHFKDUJHꢂVWDUWVꢁ
53
Figure 92.8 Read & Write Cycle with Auto Precharge I @Burst Length=4
238
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
Ra
Ca
Rb
Cb
BA1
A10/AP
DQ CL=2
Ra
Rb
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
CL=3
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
WE#
DQM
*Note1
Auto Precharge
Start Point
(B-Bank)
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
: Don’t care
Ir)
ꢀꢁ $Q\ꢂFRPPDQGꢂWRꢂ$ꢃEDQNꢂLVꢂQRWꢂDOORZHGꢂLQꢂWKLVꢂSHULRGꢁꢂW ꢂLVꢂGHWHUPLQHGꢂIURPꢂDWꢂDXWRꢂSUHFKDUJHꢂVWDUWꢂ
53
SRLQWꢁ
Figure 92.9 Read & Write Cycle with Auto Precharge 2 @Burst Length=4
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
239
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS#
RAS#
CAS#
ADDR
BA0
Ra
Ca
Cb
Cc
BA1
A10/AP
DQ
Ra
Qa0 Qa1
Qa2
Qa3
Qb0 Qb1
tSHZ
Dc0
Dc2
tSHZ
WE#
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
DQM
Write
Clock
Suspension
: Don’t care
Ir)
ꢀꢁ '40ꢂLVꢂQHHGHGꢂWRꢂSUHYHQWꢂEXVꢂFRQWHQWLRQꢁ
Figure 92.10 Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
240
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
CL=2
RAa
1
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0 QAa1 QAa2 QAa3 QAa4
DQ
2
2
{
CL=3
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE#
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
: Don’t care
Ir)
ꢀꢁ $WꢂIXOOꢂSDJHꢂPRGHꢄꢂEXUVWꢂLVꢂILQLVKHGꢂE\ꢂEXUVWꢂVWRSꢂRUꢂSUHFKDUJHꢁ
ꢆꢁ $ERXWꢂWKHꢂYDOLGꢂ'4VꢂDIWHUꢂEXUVWꢂVWRSꢄꢂLWꢂLVꢂVDPHꢂDVꢂWKHꢂFDVHꢂRIꢂ5$6ꢅꢂLQWHUUXSWꢁ
%RWKꢂFDVHVꢂDUHꢂLOOXVWUDWHGꢂDERYHꢂWLPLQJꢂGLDJUDPꢁꢂ6HHꢂWKHꢂODEHOꢂꢀꢄꢂꢆꢂRQꢂWKHPꢁꢂ
%XWꢂDWꢂEXUVWꢂZULWHꢄꢂ%XUVWꢂVWRSꢂDQGꢂ5$6ꢅꢂLQWHUUXSWꢂVKRXOGꢂEHꢂFRPSDUHGꢂFDUHIXOO\ꢁ
ꢊꢁ %XUVWꢂVWRSꢂLVꢂYDOLGꢂDWꢂHYHU\ꢂEXUVWꢂOHQJWKꢁ
Figure 92.11 Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page
Burst
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
241
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
CAS#
ADDR
BA0
RAa
CAa
CAb
BA1
A10/AP
DQ
RAa
tBDL
tRDL
*Note 1
*Note 1,2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Ir)
ꢀꢁ $WꢂIXOOꢂSDJHꢂPRGHꢄꢂEXUVWꢂLVꢂILQLVKHGꢂE\ꢂEXUVWꢂVWRSꢂRUꢂSUHFKDUJHꢁ
ꢆꢁ 'DWDꢃLQꢂDWꢂWKHꢂF\FOHꢂRIꢂLQWHUUXSWHGꢂE\ꢂSUHFKDUJHꢂFDQꢂQRWꢂEHꢂZULWWHQꢂLQWRꢂWKHꢂFRUUHVSRQGLQJꢂPHPRU\ꢂ
FHOOꢁꢂ,WꢂLVꢂGHILQHGꢂE\ꢂ$&ꢂSDUDPHWHUꢂRIꢂW ꢁꢂ'40ꢂDWꢂZULWHꢂLQWHUUXSWHGꢂE\ꢂSUHFKDUJHꢂFRPPDQGꢂLVꢂ
5'/
QHHGHGꢂWRꢂSUHYHQWꢂLQYDOLGꢂZULWHꢁꢂ'40ꢂVKRXOGꢂPDVNꢂLQYDOLGꢂLQSXWꢂGDWDꢂRQꢂSUHFKDUJHꢂFRPPDQGꢂF\FOHꢂ
ZKHQꢂDVVHUWLQJꢂSUHFKDUJHꢂEHIRUHꢂHQGꢂRIꢂEXUVWꢁꢂ,QSXWꢂGDWDꢂDIWHUꢂ5RZꢂSUHFKDUJHꢂF\FOHꢂZLOOꢂEHꢂPDVNHGꢂ
LQWHUQDOO\ꢁ
ꢊꢁ %XUVWꢂVWRSꢂLVꢂYDOLGꢂDWꢂHYHU\ꢂEXUVWꢂOHQJWKꢁ
Figure 92.12 Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full
Page Burst, tRDL=2CLK
242
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS#
RAS#
*Note 2
CAS#
ADDR
RAa
CAa RBb CAb
RCc
CBc
CCd
BA0
BA1
A10/AP
CL=2
RAa
RBb
RCc
DAa0
QAb0 QAb1
DBc0
DBc0
QCd0 QCd1
DQ
CL=3
DAa0
QAb0 QAb1
QCd0 QCd1
WE#
DQM
Precharge
(C-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Write
Read with
Write with
Auto Precharge
(B-Bank)
(A-Bank) Auto Precharge
(A-Bank)
: Don’t care
Ir)
ꢀꢁ %56:ꢂPRGHVꢂLVꢂHQDEOHGꢂE\ꢂVHWWLQJꢂ$ꢒꢂ+LJKꢂDWꢂ056ꢂꢏ0RGHꢂ5HJLVWHUꢂ6HWꢐꢁꢂ$WꢂWKHꢂ%56:ꢂ0RGHꢄꢂWKHꢂ
EXUVWꢂOHQJWKꢂDWꢂZULWHꢂLVꢂIL[HGꢂWRꢂꢇꢂUHJDUGOHVVꢂRIꢂSURJUDPPHGꢂEXUVWꢂOHQJWKꢁ
ꢆꢁ :KHQꢂ%56:ꢂZULWHꢂFRPPDQGꢂZLWKꢂDXWRꢂSUHFKDUJHꢂLVꢂH[HFXWHGꢄꢂNHHSꢂLWꢂLQꢂPLQGꢂWKDWꢂW
ꢂVKRXOGꢂQRWꢂ
5$6
EHꢂYLRODWHGꢁꢂ$XWRꢂSUHFKDUJHꢂLVꢂH[HFXWHGꢂDWꢂWKHꢂEXUVWꢃHQGꢂF\FOHꢄꢂVRꢂLQꢂWKHꢂFDVHꢂRIꢂ%56:ꢂZULWHꢂ
FRPPDQGꢄꢂWKHꢂQH[WꢂF\FOHꢂVWDUWVꢂWKHꢂSUHFKDUJHꢁꢂ
Figure 92.13 Burst Read Single bit Write Cycle @Burst Length=2
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
243
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
tSS
*Note 1
tSS
tSS
*Note 2
*Note 2
*Note 3
CS#
RAS#
CAS#
ADDR
BA
Ra
Ca
Ra
A10/AP
DQ
Qa0 Qa1 Qa2
tSHZ
WE#
DQM
Precharge
Power-down
Entry
Row Active
Read
Precharge
Precharge
Power-down
Exit
Active
Power-down
Entry
Active
Power-down
Exit
: Don’t care
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66
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Figure 92.14 Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
244
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
*Note 2
*Note 4
tSRFX
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CS#
RAS#
CAS#
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Self Refresh Entry
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Figure 92.15 Self Refresh Entry & Exit Cycle
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
245
P r e l i m i n a r y
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
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246
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SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
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Figure 92.16 Extended Mode Register Set Cycle
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
247
P r e l i m i n a r y
93 SDRAM Type 2 Revision Summary
Revision A (May 12, 2005)
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S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
A d v a n c e I n f o r m a t i o n
94 MCP Revision Summary
Revision A (October 19, 2004)
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
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December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
249
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