S75NS128NBFJWJZ0 [SPANSION]

MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface); 的MirrorBit 1.8伏特，只有同步读/写，突发模式复用闪存（ NOR接口）


型号：	S75NS128NBFJWJZ0
厂家：	SPANSION
描述：	MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) 的MirrorBit 1.8伏特，只有同步读/写，突发模式复用闪存（ NOR接口）闪存
文件：	总10页 (文件大小：317K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S75NS-N

S29NS-N: MirrorBit^™1.8 Volt-only Simultaneous Read/

Write, Burst-mode Multiplexed Flash (NOR Interface)

S30MS-P: ORNAND^™Flash (NAND interface)

Multiplexed Synchronous pSRAM

S75NS-N Cover Sheet

Data Sheet (Advance Information)

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. Each product described herein may be designated as Advance Information,

Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

Publication Number S75NS-N_00

Revision 01E

Issue Date May 3, 2006

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of

product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to verify

that they have the latest information before finalizing their design. The following descriptions of Spansion data

sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion LLC is developing one or more specific

products, but has not committed any design to production. Information presented in a document with this

designation is likely to change, and in some cases, development on the product may discontinue. Spansion

LLC therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion LLC.

The information is intended to help you evaluate this product. Do not design in this product without

contacting the factory. Spansion LLC reserves the right to change or discontinue work on this

proposed product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment

to production has taken place. This designation covers several aspects of the product life cycle, including

product qualification, initial production, and the subsequent phases in the manufacturing process that occur

before full production is achieved. Changes to the technical specifications presented in a Preliminary

document should be expected while keeping these aspects of production under consideration. Spansion

places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. The Preliminary status of this document indicates that product qualification has been

completed, and that initial production has begun. Due to the phases of the manufacturing process that

require maintaining efficiency and quality, this document may be revised by subsequent versions or

modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations

wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first

page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes

are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include

those affecting the number of ordering part numbers available, such as the addition or deletion of a speed

option, temperature range, package type, or V_IOrange. Changes may also include those needed to clarify a

description or to correct a typographical error or incorrect specification. Spansion LLC applies the following

conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion LLC deems the products to have been in sufficient production volume

such that subsequent versions of this document are not expected to change. However, typographical

or specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

S75NS-N

May 3, 2006 S75NS-N_00-01E

S75NS-N

S29NS-N: MirrorBit^™1.8 Volt-only Simultaneous Read/

Write, Burst-mode Multiplexed Flash (NOR Interface)

S30MS-P: ORNAND^™Flash (NAND interface)

Multiplexed Synchronous pSRAM

Data Sheet (Advance Information)

Features

Power supply voltage of 1.7 V to 1.95 V

Burst Speed: 66 MHz

Package - MCP BGA: 0.5 mm ball pitch

– 11 x 13 x 1.4 mm, 112 ball

Operating Temperature

– Wireless, –25°C to +85°C

General Description

The S75NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items:

S29NS-N

S30MS-P

Mux pSRAM

The products covered by this document are listed in the tables below.

pSRAM

S29NS128 +

S30MS512P

S30MS01GP

32 Mb

S75NS128NBF

S75NS128NBG

Product Selector Guide

Device

pSRAM Density

32 Mb

pSRAM Type

S75NS128NBF

S75NS128NBG

Multiplexed pSRAM Type 3

32 Mb

For detailed specifications, please refer to the individual data sheets:

Document

S29NS-N

Publication Identification Number

S29NS-N_00

S30MS-P

S30MS-P_00

32 Mb Multiplexed pSRAM Type 3

muxpsram_04

Publication Number S75NS-N_00

Revision 01E

Issue Date May 3, 2006

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design

in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

1. Ordering Information

The ordering part number is formed by a valid combination of the following:

S75NS 128

Packing Type

0 = Tray

2 = 7-inch Tape and Reel

3 = 13-inch Tape and Reel

Model Number

Refer to the Valid Combinations table below

Temperature Range

W = Wireless (-25°C to +85°C)

Package Type

J = 1.4 mm height, 0.5mm ball size, Thin Fine-Pitch Ball Grid

Array (FBGA) Lead (Pb)-free Package (LF35)

ORNAND Data Density

F = 512 Mb

G = 01 Gb

pSRAM Density

B = 32 Mb

C = 64 Mb

Process Technology

N = 110 nm MirrorBit Technology

Flash Density

256 = 256 Mb

128 = 128 Mb

Device Family

S75NS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/

Write Burst Mode Multiplexed Flash Memory + pSRAM +

ORNAND Data Storage

1.1

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local

sales office to confirm availability of specific valid combinations and to check on newly released

combinations.

Table 1.1 MCP Configurations and Valid Combinations

Base Ordering Part

Number (Note 2)

Package &

Temperature

Model

Number

Packing

Type

Flash Speed

Options

pSRAM Speed

Options

pSRAM Type

pSRAM Type 3

S75NS128NBF

S75NS128NBG

66 MHz

UJW

0, 2, 3

Notes:

1. Type 0 is standard. Specify other options as required.

2. The package marking omits the leading S and packing type designator from the ordering part number.

3. Contact factory for availability of any of the OPNs listed because RAM type availability may vary over time.

S75NS-N

S75NS-N_00_01E May 3, 2006

D a t a S h e e t

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2. Input/Output Descriptions

Table 2.1 identifies the input and output package connections provided on the device.

Table 2.1 Input/Output Descriptions

Signal

Type

(NOR)

(ORNAND)

Symbol

AMAX – A16

ADQ15 – ADQ0

Description

pSRAM

Input

I/O

Address inputs

Multiplexed Address/Data

Output Enable input. Asynchronous relative to CLK for the Burst

mode.

OE#

WE#

Input

Write Enable input.

Ground

Ready output. Indicates the status of the Burst read. The WAIT#

pin of the pSRAM is tied to RDY.

F-RDY / R-WAIT

CLK

Output

Input

Clock input. In burst mode, after the initial word is output,

subsequent active edges of CLK increment the internal address

counter. Should be at V or V while in asynchronous mode

Address Valid input. Indicates to device that the valid address is

present on the address inputs. Low = for asynchronous mode,

indicates valid address; for burst mode, causes starting address

to be latched. High = device ignores address inputs

AVD#

Input

Hardware reset input. Low = device resets and returns to reading

array data

F-RST#

F-WP#

Input

Hardware write protect input. At V , disables program and erase

functions in the four outermost sectors. Should be at V for all

other conditions.

Accelerated input. At V , accelerates programming;

automatically places device in unlock bypass mode. At V

disables all program and erase functions. Should be at V for all

other conditions.

F-ACC

F-CE#

Input

Chip-enable input for Flash. Asynchronous relative to CLK for

Burst Mode.

Power

Input

Power

Input

I/O

Flash 1.8 Volt-only single power supply

Chip-enable input for pSRAM

Control Register Enable (pSRAM)

pSRAM Power Supply

R-CE1#

R-CRE

R-V

R-UB#

Upper Byte Control (pSRAM)

Lower Byte Control (pSRAM)

Command Latch Enable

Address Latch Enable

R-LB#

N-CLE

N-ALE

N-CE#

Chip Enable input for ORNAND

Write Enable input

N-WE#

N-RE#

Read Enable input

N-IO0 - N-IO7

Data Input/Output

Hardware write protect input. At V , disables program and erase

N-WP#

Input

functions in the four outermost sectors. Should be at V for all

other conditions.

N-RY/BY#

N-PRE

Input

Ground

Power

—

Ready/Busy output

Power-On Read Enable

Ground

N-V

ORNAND 1.8 Volt-only single power supply.

Do Not Use

DNU

—

No Connect; not connected internally

S75NS-N_00_01E May 3, 2006

S75NS-N

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

3. MCP Block Diagram

Figure 3.1 MCP Block Diagram

A21-A22

A15-A0

DQ15-DQ0

CLK

A21-A22

ADQ15-ADQ0

F-RST#

RST#

F-ACC

F-WP#

F-CE#

OE#

WE#

AVD#

ACC

WP#

CE#

OE#

WE#

AVD#

CLK

F-RDY/R-WAIT

RDY

Mux

FLASH

A16-A20

MEMORY

VCC

VSS

VCCQ

VSSQ

R-UB#

R-LB#

UB#

LB#

A15-A0

DQ15-DQ0

CLK

WAIT

Mux Sync

pSRAM

MEMORY

R-CE1#

CE#

OE#

WE#

AVD#

CRE

VSS

A16-A20

R-CRE

VCC

VCCQ

VSSQ

I/O0-I/O7

N-IO0 - N-IO7

N-RY/BY#

RB#

N-PRE

N-CLE

N-CE#

N-ALE

PRE

CLE

CE#

ALE

x8 ORNAND

Flash

VSS

VCC

N-VSS

N-VCC

Memory

N-RE#

N-WP#

N-WE#

RE#

WP#

WE#

4. Connection Diagrams/Physical Dimensions

This section contains the I/O designations and package specifications for the S71NS-N.

4.1

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The

package and/or data integrity may be compromised if the package body is exposed to temperatures above

150°C for prolonged periods of time.

S75NS-N

S75NS-N_00_01E May 3, 2006

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4.2

Connection Diagrams

Legend

NOR Flash/pSRAM

Shared Only

No Connect

Do Not Use

DNU

N-IO7

DNU

A22

DNU

NOR Flash 1 Only

pSRAM Only

DNU N-RDY DNU

DNU

A21

A16

R-LB# R-UB#

N-IO5

A17

N-IO6

N-IO4

DNU

N-CE# N-RE# F-RDY/

R-WAIT

VSS

A20

CLK

VCC

WE# F-ACC

A19

A18

ORNAND Flash Only

N-VCC N-VCC VCCQ

AVD#

DNU F-RST# F-WP#

F-CE# VSSQ

DNU N-PRE

N-VSS N-VSS

VSS

A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8

OE# N-VCC N-VSS

N-CLE N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ18 VCCQ A/DQ1 A/DQ0 DNU

N-IO3

N-IO2

DNU N-WE# N-WP# DNU

R-CE# R-CRE

VSS

N-IO1

N-IO8

DNU

Note:

Addresses are shared between Flash and RAM depending on the density of the pSRAM.

MCP

Flash-Only Addresses

A22-A21

Shared Addresses

A20-A16

Shared ADQ Pins

ADQ15 – ADQ0

S75NS128NBG

S75NS128NBF

A22-A21

A20-A16

S75NS-N_00_01E May 3, 2006

S75NS-N

D a t a S h e e t

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4.2.1

Lookahead Connection Diagram

Figure 4.1 112-ball x16 MUX NOR FLASH (Bus 1) + x16 MUX pSRAM (Bus 1) + x8/x16 ORNAND (Bus2)

Legend

NOR Flash/pSRAM

Shared Only

No Connect

Do Not Use

DNU

N-IO7 N-IO15

NOR Flash 1 Only

pSRAM Only

DNU N-RDY N2-CE# F2-CE#

R-LB# R-UB#

N-IO5 N-IO13 N-IO6 N-IO14

N1-CE# N-RE# F-RDY/

R-WAIT

A21

A16

VSS

A20

CLK

VCC

WE# F-ACC

A19

A17

A22

N-IO4 N-IO12

ORNAND Flash Only

NOR Flash 2 Only

N-VCC N-VCC VCCQ

AVD#

A23 F-RST# F-WP#

A18 F1-CE# VSSQ N-IO11 N-PRE

N-VSS N-VSS

VSS

A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8

OE#

VCC

VSS

NOR Flash Shared Only

N-CLE N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 N-IO18 N-IO3

DNU N-WE# N-WP#

A24

R-CE# R-CRE

VSS

N-IO1 N-IO9 N-IO2

DNU

N-IO0 N-IO8

S75NS-N

S75NS-N_00_01E May 3, 2006

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

4.3

Physical Dimensions

Figure 4.2 MMB112—11 x 13 mm, 112-ball VFBGA

PIN A1

CORNER

PIN A1

CORNER

INDEX MARK

H G F E D C B A

0.15

(2X)

18 17 16 15 14 13 12 11 10

7 6 5 4 3 2 1

TOP VIEW

SIDE VIEW

0.15

(2X)

BOTTOM VIEW

0.20

0.08

112X

0.15

0.08

A B

NOTES:

PACKAGE

JEDEC

MMB 112

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

13.00 mm x 11.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JEP95, SECTION

4.3, SPP-010.

SYMBOL

MIN

NOM

---

MAX

NOTE

e REPRESENTS THE SOLDER BALL GRID PITCH.

---

1.40

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.20

0.94

---

BALL HEIGHT

---

1.11

BODY THICKNESS

BODY SIZE

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"

DIRECTION.

13.00 BSC

11.00 BSC

8.50 BSC

6.50 BSC

BODY SIZE

n IS THE NUMBER OF POPULTED SOLDER BALL

POSITIONS FOR MATRIX SIZE MD X ME.

MATRIX FOOTPRINT

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

SD AND SE ARE MEASURED WITH RESPECT TO

DATUMS A AND B AND DEFINE THE POSITION OF THE

CENTER SOLDER BALL IN THE OUTER ROW.

112

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS

IN THE OUTER ROW SD OR SE = 0.000.

0.25

0.30

0.35

BALL DIAMETER

0.50 BSC

0.25 BSC

BALL PITCH

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS

IN THE OUTER ROW, SD OR SE = e/2

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

8. "+" INDICATES THE THEORETICAL CENTER OF

DEPOPULATED BALLS.

1C~1M,2A,2B,2E~2K,3A,3B,3N,3P,4A,4B,4N, DEPOPULATED SOLDER BALLS

4P,5A,5B, 5C,5M,5N,5P,6A~6D,6L~6P,7A~7E,

8A~8E,8K~8P,9A~9D,9L~9P,10A~10D,

9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER

OR INK MARK, METALLIZED MARK INDENTATION OR

OTHER MEANS.

10L~10P,11A~11E,11K~11P,12A~12E,

12K~12P,13A~13D,13L~13P,14A~14C,

14M~14P,15A,15B,15N,15P,16A,16B,

16N,16P,17A,17B,17N,17P,18C~18M

3558 \ 16-038.29 \ 4.27.6

S75NS-N_00_01E May 3, 2006

S75NS-N

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

5. Revision History

5.1

Revision A (May 3, 2006)

Initial release.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as

contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under

development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this

document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,

merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any

damages of any kind arising out of the use of the information in this document.

trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.

S75NS-N

S75NS-N_00_01E May 3, 2006

S75NS128NBFJWJZ0 [SPANSION]

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