S75NS128ND0ZFWNK0 [SPANSION]
1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM; 1.8伏只，堆叠式多芯片产品（ MCP ） x16的MirrorBit闪存和DRAM
| 型号： | S75NS128ND0ZFWNK0 |
| 厂家： | 
SPANSION |
| 描述： | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| 文件： | 总211页 (文件大小：5548K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S75NS128NDE Based MCPs
1.8 Volt-only, Stacked Multi-Chip Product (MCP)
x16 MirrorBit™ Flash Memory and DRAM
128 Mb Multiplexed, Simultaneous Read/Write, Burst Mode Code Flash Memory
256 Mb Multiplexed, Burst Mode Data Flash Memory
128 Mb SDR DRAM
ADVANCE
INFORMATION
Data Sheet
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Publication Number S75NS128NDE_00 Revision A Amendment 2 Issue Date September 23, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
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S72WS-N Based MCPs
S75NS128NDE_00_A2 September23,2005
S75NS128NDE based MCPs
1.8 Volt-only, Stacked Multi-Chip Product (MCP)
x16 MirrorBit™ Flash Memory and DRAM
128 Mb Multiplexed, Simultaneous Read/Write, Burst Mode Code Flash Memory
256 Mb Multiplexed, Burst Mode Data Flash Memory
128 Mb SDR DRAM
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
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General Description
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Product Selector Guide
Device/
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Density
Data Flash
Density
DRAM
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Publication Number S75NS128NDE_00 Revision A Amendment 2 Issue Date September 23, 2005
A d v a n c e I n f o r m a t i o n
tection Mode ........................................................................................................29
S75NS128NDE Based MCPs
Hardware Data Protection Mode .................................................................29
Write Protect (WP#) ...................................................................................29
WP# Boot Sector Protection .........................................................................29
Low VCC Write Inhibit ....................................................................................30
Write Pulse “Glitch” Protection ....................................................................30
Logical Inhibit .......................................................................................................30
Power-Up Write Inhibit ...............................................................................30
Lock Register .......................................................................................................30
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Automatic Sleep Mode ...................................................................................... 31
RESET#: Hardware Reset Input ...................................................................... 31
VCC Power-up and Power-down Sequencing ........................................ 31
Output Disable Mode ........................................................................................ 31
Secured Silicon Sector Flash Memory Region ............................................ 31
Factory Locked: Factor Secured Silicon Sector Programmed and Pro-
tected At the Factory ................................................................................... 32
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Customer Secured Silicon Sector ............................................................. 32
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .............................................................. ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 1
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 10
S29NS-N MirrorBitTM Flash Module
General Description . . . . . . . . . . . . . . . . . . . . . . . 12
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 14
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Diagram of Simultaneous
Common Flash Memory Interface (CFI) . . . . . . 33
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Command Definitions . . . . . . . . . . . . . . . . . . . . . .44
Reading Array Data ...........................................................................................44
Set Configuration Register Command Sequence .....................................44
Read Configuration Register Command Sequence ..................................44
Read Mode Setting .........................................................................................45
Programmable Wait State Configuration ...............................................45
7DEOHꢀꢌꢉꢁꢀ3URJUDPPDEOHꢀ:DLWꢀ6WDWHꢀ6HWWLQJVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢑꢍ
Programmable Wait State ...........................................................................45
7DEOHꢀꢌꢊꢁꢀ:DLWꢀ6WDWHVꢀIRUꢀ+DQGVKDNLQJꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢑꢍ
Handshaking .....................................................................................................46
Burst Length Configuration .........................................................................46
7DEOHꢀꢌꢌꢁꢀ%XUVWꢀ/HQJWKꢀ&RQILJXUDWLRQꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢑꢇ
Burst Wrap Around ......................................................................................46
RDY Configuration ........................................................................................46
RDY Polarity ....................................................................................................46
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 17
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .18
7DEOHꢀꢊꢁꢀ'HYLFHꢀ%XVꢀ2SHUDWLRQVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢈ
VersatileIO™ (VIO) Control ............................................................................. 18
Requirements for Asynchronous Read Operation (Non-Burst) .......... 18
Requirements for Synchronous (Burst) Read Operation ....................... 19
Continuous Burst ............................................................................................ 19
7DEOHꢀꢌꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢏꢂꢀꢇꢂꢀDQGꢀꢍꢀ:DLWꢀ6WDWHV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢐ
7DEOHꢀꢋꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢑꢀ:DLWꢀ6WDWHVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢐ
7DEOHꢀꢑꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢋꢀ:DLWꢀ6WDWHVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢌꢉ
7DEOHꢀꢍꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢌꢀ:DLWꢀ6WDWHVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢌꢉ
7DEOHꢀꢇꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢏꢂꢀꢇꢂꢀDQGꢀꢍꢀ:DLWꢀ
6WDWHVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢌꢉ
7DEOHꢀꢏꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢑꢀ:DLWꢀ6WDWHVꢁꢀꢌꢉ
7DEOHꢀꢈꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢋꢀ:DLWꢀ6WDWHVꢀ ꢌꢉ
7DEOHꢀꢐꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢌꢀ:DLWꢀ6WDWHVꢀ ꢌꢊ
8-, 16-, and 32-Word Linear Burst with Wrap Around ...................... 21
7DEOHꢀꢊꢉꢁꢀ%XUVWꢀ$GGUHVVꢀ*URXSVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢌꢊ
8-, 16-, and 32-Word Linear Burst without Wrap Around ................ 21
Programmable Wait State ............................................................................... 22
Configuration Register ..................................................................................... 22
Configuration Register . . . . . . . . . . . . . . . . . . . . . . 47
7DEOHꢀꢌꢋꢁꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢑꢏ
Reset Command .................................................................................................47
7DEOHꢀꢌꢑꢁꢀ'HYLFHꢀ,'ꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢑꢐ
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence ....................................................................................................................49
Unlock Bypass Command Sequence ........................................................50
Program Command Sequence ........................................................................50
Program Command Sequence ....................................................................50
Program Command Sequence (Unlock Bypass Mode) .......................50
Accelerated Program ........................................................................................50
)LJXUHꢀꢊꢁꢀ3URJUDPꢀ2SHUDWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢍꢊ
Write Buffer Programming Command Sequence ......................................51
7DEOHꢀꢌꢍꢁꢀ:ULWHꢀ%XIIHUꢀ&RPPDQGꢀ6HTXHQFHꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢍꢌ
)LJXUHꢀꢌꢁꢀ:ULWHꢀ%XIIHUꢀ3URJUDPPLQJꢀ2SHUDWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢍꢋ
Chip Erase Command Sequence ................................................................... 53
Chip Erase Command Sequence ............................................................... 53
Sector Erase Command Sequence ................................................................54
Sector Erase Command Sequence ............................................................54
Accelerated Sector Erase ............................................................................ 55
Handshaking Feature ......................................................................................... 22
Simultaneous Read/Write Operations with Zero Latency ................... 22
Writing Commands/Command Sequences ................................................ 22
Accelerated Program and Erase Operations ............................................. 22
Write Buffer Programming Operation .........................................................23
Autoselect Mode ................................................................................................ 24
Advanced Sector Protection and Unprotection ....................................... 24
Sector Protection ................................................................................................25
Persistent Sector Protection ...........................................................................25
Persistent Protection Bit (PPB) ................................................................. 26
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ............................................................................................ 26
Dynamic Protection Bit (DYB) .................................................................. 26
7DEOHꢀꢊꢊꢁꢀ6HFWRUꢀ3URWHFWLRQꢀ6FKHPHVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢌꢏ
Persistent Sector Protection Mode Lock Bit .............................................27
Password Sector Protection ........................................................................... 28
64-bit Password .................................................................................................. 28
Password Mode Lock Bit ................................................................................. 28
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Pro-
2
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
)LJXUHꢀꢋꢁꢀ(UDVHꢀ2SHUDWLRQꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢍꢍ
General Description . . . . . . . . . . . . . . . . . . . . . . . .94
Erase Suspend/Erase Resume Commands ...................................................56
Program Suspend/Program Resume Commands ......................................56
Lock Register Command Set Definitions ....................................................57
Password Protection Command Set Definitions ......................................57
Non-Volatile Sector Protection Command Set Definitions ................. 58
)LJXUHꢀꢑꢁꢀ33%ꢀ3URJUDPꢒ(UDVHꢀ$OJRULWKPꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢍꢐ
Global Volatile Sector Protection Freeze Command Set .....................60
Volatile Sector Protection Command Set ..................................................60
7DEOHꢀꢌꢇꢁꢀ&RPPDQGꢀ'HILQLWLRQVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢇꢌ
Functional Block Diagram . . . . . . . . . . . . . . . . . . . 95
)LJXUHꢀꢌꢑꢁꢀ%ORFNꢀ'LDJUDP ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢐꢍ
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Functional Description . . . . . . . . . . . . . . . . . . . . . . 97
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Mode Register Definition . . . . . . . . . . . . . . . . . . . 97
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7DEOHꢀꢋꢉꢁꢀ%XUVWꢀ'HILQLWLRQꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢐꢈ
)LJXUHꢀꢌꢍꢁꢀ0RGHꢀ5HJLVWHUꢀ'HILQLWLRQꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢐꢐ
Write Operation Status . . . . . . . . . . . . . . . . . . . . 66
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DQ7: Data# Polling ........................................................................................... 66
)LJXUHꢀꢍꢁꢀ'DWDꢓꢀ3ROOLQJꢀ$OJRULWKPꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢇꢏ
DQ6: Toggle Bit I ............................................................................................... 68
DQ2: Toggle Bit II .............................................................................................. 68
)LJXUHꢀꢇꢁꢀ7RJJOHꢀ%LWꢀ$OJRULWKPꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢇꢐ
7DEOHꢀꢌꢏꢁꢀ'4ꢇꢀDQGꢀ'4ꢌꢀ,QGLFDWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢏꢉ
Reading Toggle Bits DQ6/DQ2 ..................................................................... 70
DQ5: Exceeded Timing Limits ....................................................................... 70
DQ3: Sector Erase Start Timeout State Indicator .....................................71
DQ1: Write to Buffer Abort .............................................................................71
7DEOHꢀꢌꢈꢁꢀ:ULWHꢀ2SHUDWLRQꢀ6WDWXVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢏꢌ
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .73
)LJXUHꢀꢏꢁꢀ0D[LPXPꢀ1HJDWLYHꢀ2YHUVKRRWꢀ:DYHIRUPꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢋ
)LJXUHꢀꢈꢁꢀ0D[LPXPꢀ3RVLWLYHꢀ2YHUVKRRWꢀ:DYHIRUP ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢋ
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 73
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .74
CMOS Compatible .............................................................................................74
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
)LJXUHꢀꢌꢇꢁꢀ&$6ꢀ/DWHQF\ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢉ
7DEOHꢀꢋꢊꢁꢀ&$6ꢀ/DWHQF\ꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢉꢉ
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . 100
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . 100
Extended Mode Register . . . . . . . . . . . . . . . . . . . 101
Temperature Compensated Self Refresh . . . . . 101
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . 101
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . 101
)LJXUHꢀꢌꢏꢁꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢌ
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7DEOHꢀꢋꢌꢁꢀ7UXWKꢀ7DEOHꢀꢊꢀꢃꢀ&RPPDQGVꢀDQGꢀ'40ꢀ2SHUDWLRQꢀ ꢁꢁꢁꢁꢁ ꢊꢉꢋ
Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . 103
No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . 103
Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . 103
Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . 104
Burst Terminate . . . . . . . . . . . . . . . . . . . . . . . . . 105
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . 105
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
)LJXUHꢀꢐꢁꢀ7HVWꢀ6HWXS ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢍ
7DEOHꢀꢌꢐꢁꢀ7HVWꢀ6SHFLILFDWLRQVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢏꢍ
Key to Switching Waveforms . . . . . . . . . . . . . . . 75
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 76
)LJXUHꢀꢊꢉꢁꢀ,QSXWꢀ:DYHIRUPVꢀDQGꢀ0HDVXUHPHQWꢀ/HYHOVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢇ
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .77
VCC Power-up ......................................................................................................77
)LJXUHꢀꢊꢊꢁꢀ9&&ꢀ3RZHUꢃXSꢀ'LDJUDPꢀ&/.ꢀ&KDUDFWHUL]DWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢏ
)LJXUHꢀꢊꢌꢁꢀ&/.ꢀ&KDUDFWHUL]DWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢏ
Synchronous/Burst Read .................................................................................. 78
)LJXUHꢀꢊꢋꢁꢀ%XUVWꢀ0RGHꢀ5HDGꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢏꢐ
Asynchronous Read ..........................................................................................80
)LJXUHꢀꢊꢑꢁꢀ$V\QFKURQRXVꢀ0RGHꢀ5HDGꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢉ
)LJXUHꢀꢊꢍꢁꢀ5HVHWꢀ7LPLQJVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢊ
Erase/Program Operations ............................................................................. 82
)LJXUHꢀꢊꢇꢁꢀ3URJUDPꢀ2SHUDWLRQꢀ7LPLQJV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢋ
)LJXUHꢀꢊꢏꢁꢀ&KLSꢒ6HFWRUꢀ(UDVHꢀ2SHUDWLRQV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢑ
)LJXUHꢀꢊꢈꢁꢀ$FFHOHUDWHGꢀ8QORFNꢀ%\SDVVꢀ3URJUDPPLQJꢀ7LPLQJ ꢁꢁꢁꢁꢁꢀꢈꢍ
)LJXUHꢀꢊꢐꢁꢀ'DWDꢓꢀ3ROOLQJꢀ7LPLQJVꢀ
ꢅ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢆꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢇ
)LJXUHꢀꢌꢉꢁꢀ7RJJOHꢀ%LWꢀ7LPLQJVꢀꢅ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢆꢁꢁꢁꢁꢀꢈꢇ
)LJXUHꢀꢌꢊꢁꢀꢈꢃꢂꢀꢊꢇꢃꢂꢀDQGꢀꢋꢌꢃ:RUGꢀ/LQHDUꢀ%XUVWꢀ
$GGUHVVꢀ:UDSꢀ$URXQG ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢏ
)LJXUHꢀꢌꢌꢁꢀ/DWHQF\ꢀZLWKꢀ%RXQGDU\ꢀ&URVVLQJꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢏ
)LJXUHꢀꢌꢋꢁꢀ%DFNꢃWRꢃ%DFNꢀ5HDGꢒ:ULWHꢀ&\FOHꢀ7LPLQJV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢈꢈ
Bank/Row Activation ........................................................................................106
)LJXUHꢀꢌꢈꢁꢀ$FWLYDWLQJꢀDꢀ6SHFLILFꢀ5RZꢀLQꢀDꢀ
6SHFLILFꢀ%DQNꢀ5HJLVWHUꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢇ
)LJXUHꢀꢌꢐꢁꢀ0HHWLQJꢀW5&'ꢀꢅ0,1ꢆꢀZKHQꢀꢌꢀꢔꢀW5&'ꢀꢅ0,1ꢆꢒW&.≤ꢀꢋꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢏ
Reads .....................................................................................................................107
)LJXUHꢀꢋꢉꢁꢀ5HDGꢀ&RPPDQGꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢈ
)LJXUHꢀꢋꢊꢁꢀ&RQVHFXWLYHꢀ5HDGꢀ%XUVWV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢐ
)LJXUHꢀꢋꢌꢁꢀ5DQGRPꢀ5HDGꢀ$FFHVVHVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢉꢐ
)LJXUHꢀꢋꢋꢁꢀ5HDGꢀWRꢀ:ULWHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢉ
)LJXUHꢀꢋꢑꢁꢀ5HDGꢀWRꢀ:ULWHꢀZLWKꢀ([WUDꢀ&ORFNꢀ&\FOHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢊ
)LJXUHꢀꢋꢍꢁꢀ5HDGꢀWRꢀ3UHFKDUJH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢊ
)LJXUHꢀꢋꢇꢁꢀ7HUPLQDWLQJꢀDꢀ5HDGꢀ%XUVW ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢌ
)LJXUHꢀꢋꢏꢁꢀ:ULWHꢀ&RPPDQG ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢋ
)LJXUHꢀꢋꢈꢁꢀ:ULWHꢀ%XUVWꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢑ
)LJXUHꢀꢋꢐꢁꢀ:ULWHꢀWRꢀ:ULWH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢑ
)LJXUHꢀꢑꢉꢁꢀ5DQGRPꢀ:ULWHꢀ&\FOHV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢍ
)LJXUHꢀꢑꢊꢁꢀ:ULWHꢀWRꢀ5HDGꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢍ
)LJXUHꢀꢑꢌꢁꢀ:ULWHꢀWRꢀ3UHFKDUJHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢇ
)LJXUHꢀꢑꢋꢁꢀ3RZHUꢃ'RZQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢏ
)LJXUHꢀꢑꢑꢁꢀ7HUPLQDWLQJꢀDꢀ:ULWHꢀ%XUVWꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢏ
)LJXUHꢀꢑꢍꢁꢀ3UHFKDUJHꢀ&RPPDQGꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢏ
)LJXUHꢀꢑꢇꢁꢀ&ORFNꢀ6XVSHQGꢀ'XULQJꢀ:ULWHꢀ%XUVW ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢈ
)LJXUHꢀꢑꢏꢁꢀ&ORFNꢀ6XVSHQGꢀ'XULQJꢀ5HDGꢀ%XUVWꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢊꢐ
)LJXUHꢀꢑꢈꢁꢀ5HDGꢀZLWKꢀ$XWRꢀSUHFKDUJHꢀ,QWHUUXSWHGꢀE\ꢀDꢀ5HDGꢁꢁ ꢀꢊꢊꢐ
Erase and Programming Performance . . . . . . . . 89
Device History . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Flash Module Revision Summary . . . . . . . . . . . . .90
Mobile SDRAM Type 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Speed Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
3
A d v a n c e I n f o r m a t i o n
)LJXUHꢀꢑꢐꢁꢀ5HDGꢀZLWKꢀ$XWRꢀ3UHFKDUJHꢀ,QWHUUXSWHGꢀE\ꢀDꢀ:ULWH ꢁꢁꢀꢊꢌꢉ
:DLWꢀ6WDWHVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢍꢇ
8-, 16-, and 32-Word Linear Burst with Wrap Around .....................157
7DEOHꢀꢍꢌꢁꢀ%XUVWꢀ$GGUHVVꢀ*URXSVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢍꢏ
8-, 16-, and 32-Word Linear Burst without Wrap Around ..............157
Programmable Wait State ..............................................................................157
Configuration Register .....................................................................................158
Handshaking Feature ........................................................................................158
Writing Commands/Command Sequences ...............................................158
Accelerated Program and Erase Operations ............................................158
Write Buffer Programming Operation .......................................................159
Autoselect Mode ...............................................................................................160
Sector Protection and Unprotection ..........................................................160
Sector Protection ..............................................................................................160
Dynamic Sector Protection .............................................................................161
Dynamic Protection Bit (DYB) ..................................................................161
Hardware Data Protection Mode .................................................................161
Write Protect (WP#) ..................................................................................162
WP# Boot Sector Protection ........................................................................162
Low VCC Write Inhibit ....................................................................................162
Write Pulse “Glitch” Protection ...................................................................162
Logical Inhibit ......................................................................................................162
Power-Up Write Inhibit ..............................................................................162
Lock Register ......................................................................................................162
7DEOHꢀꢍꢋꢁꢀ/RFNꢀ5HJLVWHUꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢌ
Automatic Sleep Mode ....................................................................................163
RESET#: Hardware Reset Input ....................................................................163
VCC Power-up and Power-down Sequencing ......................................163
Output Disable Mode ......................................................................................163
Secured Silicon Sector Flash Memory Region ..........................................164
Factory Locked: Factor Secured Silicon Sector
)LJXUHꢀꢍꢉꢁꢀ:ULWHꢀZLWKꢀ$XWRꢀ3UHFKDUJHꢀ,QWHUUXSWHGꢀE\ꢀDꢀ5HDG ꢁꢁꢀꢊꢌꢉ
)LJXUHꢀꢍꢊꢁꢀ:ULWHꢀZLWKꢀ$XWRꢀ3UHFKDUJHꢀ,QWHUUXSWHGꢀE\ꢀDꢀ:ULWHꢁꢁꢀꢊꢌꢊ
7DEOHꢀꢋꢋꢁꢀ7UXWKꢀ7DEOHꢀꢌ²&.(ꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢊ
7DEOHꢀꢋꢑꢁꢀ7UXWKꢀ7DEOHꢀꢋꢀ²ꢀ&XUUHQWꢀ6WDWHꢀ%DQNꢀQꢂꢀ
&RPPDQGꢀWRꢀ%DQNꢀQꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢌ
7DEOHꢀꢋꢍꢁꢀ7UXWKꢀ7DEOHꢀꢑꢀ²ꢀ&XUUHQWꢀ6WDWHꢀ%DQNꢀQꢂꢀ
&RPPDQGꢀWRꢀ%DQNꢀPꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢋ
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 125
7DEOHꢀꢋꢇꢁꢀ'&ꢀ(OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ
2SHUDWLQJꢀ&RQGLWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢍ
7DEOHꢀꢋꢏꢁꢀ$&ꢀ(OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ
2SHUDWLQJꢀ&RQGLWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢍ
7DEOHꢀꢋꢈꢁꢀ(OHFWULFDOꢀ&KDUDFWHULVWLFVꢀDQGꢀ5HFRPPHQGHGꢀ$&ꢀ
2SHUDWLQJꢀ&RQGLWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢇ
7DEOHꢀꢋꢐꢁꢀ$&ꢀ)XQFWLRQDOꢀ&KDUDFWHULVWLFVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢏ
7DEOHꢀꢑꢉꢁꢀ,''ꢀ6SHFLILFDWLRQVꢀDQGꢀ&RQGLWLRQVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢈ
7DEOHꢀꢑꢊꢁꢀ,''ꢏꢀ²ꢀ6HOIꢀ5HIUHVKꢀ&XUUHQWꢀ2SWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢌꢐ
7DEOHꢀꢑꢌꢁꢀ&DSDFLWDQFHꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢋꢉ
)LJXUHꢀꢍꢌꢁꢀ,QLWLDOL]HꢀDQGꢀ/RDGꢀ0RGHꢀ5HJLVWHU ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢉ
)LJXUHꢀꢍꢋꢁꢀ3RZHUꢀ'RZQꢀ0RGHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢊ
)LJXUHꢀꢍꢑꢁꢀ&ORFNꢀ6XVSHQGꢀ0RGHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢌ
)LJXUHꢀꢍꢍꢁꢀ$XWRꢀ5HIUHVKꢀ0RGH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢋ
)LJXUHꢀꢍꢇꢁꢀ6HOIꢀ5HIUHVKꢀ0RGH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢑ
)LJXUHꢀꢍꢏꢁꢀ5HDGꢀꢃꢀ:LWKRXWꢀ$XWRꢀ3UHFKDUJH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢍ
)LJXUHꢀꢍꢈꢁꢀ5HDGꢀꢃꢀ:LWKꢀ$XWRꢀ3UHFKDUJHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢇ
)LJXUHꢀꢍꢐꢁꢀ6LQJOHꢀ5HDGꢀꢃꢀ:LWKRXWꢀ$XWRꢀ3UHFKDUJHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢏ
)LJXUHꢀꢇꢉꢁꢀ6LQJOHꢀ5HDGꢀꢃꢀ:LWKꢀ$XWRꢀ3UHFKDUJH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢈ
)LJXUHꢀꢇꢊꢁꢀ$OWHUQDWLQJꢀ%DQNꢀ5HDGꢀ$FFHVVHVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢐ
)LJXUHꢀꢇꢌꢁꢀ5HDGꢀꢃꢀ)XOOꢃ3DJHꢀ%XUVW ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢋꢐ
)LJXUHꢀꢇꢋꢁꢀ5HDGꢀꢃꢀ'40ꢀ2SHUDWLRQꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢉ
)LJXUHꢀꢇꢑꢁꢀ:ULWHꢀꢃꢀ:LWKRXWꢀ$XWRꢀ3UHFKDUJHꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢉ
)LJXUHꢀꢇꢍꢁꢀ:ULWHꢀꢃꢀ:LWKꢀ$XWRꢀ3UHFKDUJH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢊ
)LJXUHꢀꢇꢇꢁꢀ6LQJOHꢀ:ULWHꢀꢃꢀ:LWKRXWꢀ$XWRꢀ3UHFKDUJH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢊ
)LJXUHꢀꢇꢏꢁꢀ6LQJOHꢀ:ULWHꢀZLWKꢀ$XWRꢀ3UHFKDUJH ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢌ
)LJXUHꢀꢇꢈꢁꢀ$OWHUQDWLQJꢀ%DQNꢀ:ULWHꢀ$FFHVVHV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢋ
)LJXUHꢀꢇꢐꢁꢀ:ULWHꢀꢃꢀ)XOOꢀ3DJHꢀ%XUVWꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢑ
)LJXUHꢀꢏꢉꢁꢀ:ULWHꢀꢃꢀ'40ꢀ2SHUDWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢑꢍ
Programmed and Protected At the Factory .........................................164
7DEOHꢀꢍꢑꢁꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ$GGUHVVHVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢑ
Customer Secured Silicon Sector ............................................................165
7DEOHꢀꢍꢍꢁꢀ6HFWRUꢀ$GGUHVVꢀ7DEOHꢂꢀ6ꢐꢐ.6ꢌꢍꢇ1ꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢍ
Command Definitions . . . . . . . . . . . . . . . . . . . . . 166
Reading Array Data ..........................................................................................166
Set Configuration Register Command Sequence ....................................166
Read Configuration Register Command Sequence .................................166
Read Mode Setting ........................................................................................167
Programmable Wait State Configuration ..............................................167
7DEOHꢀꢍꢇꢁꢀ3URJUDPPDEOHꢀ:DLWꢀ6WDWHꢀ6HWWLQJVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢏ
Programmable Wait State ..........................................................................167
7DEOHꢀꢍꢏꢁꢀ:DLWꢀ6WDWHVꢀIRUꢀ+DQGVKDNLQJꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢏ
Handshaking ....................................................................................................167
Burst Length Configuration ........................................................................168
7DEOHꢀꢍꢈꢁꢀ%XUVWꢀ/HQJWKꢀ&RQILJXUDWLRQꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢈ
Burst Wrap Around .....................................................................................168
RDY Configuration .......................................................................................168
RDY Polarity ...................................................................................................168
Configuration Register . . . . . . . . . . . . . . . . . . . . . 169
7DEOHꢀꢍꢐꢁꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢇꢐ
Reset Command ................................................................................................169
7DEOHꢀꢇꢉꢁꢀ'HYLFHꢀ,'ꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢏꢊ
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence .........................................................................................172
Unlock Bypass Command Sequence .......................................................172
Program Command Sequence .......................................................................172
Program Command Sequence ...................................................................172
Program Command Sequence (Unlock Bypass Mode) ......................172
Accelerated Program .......................................................................................173
)LJXUHꢀꢏꢊꢁꢀ3URJUDPꢀ2SHUDWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢏꢋ
SDRAM Revision Summary . . . . . . . . . . . . . . . . . 146
S99KS256N MirrorBit™ Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . 148
Product Selector Guide . . . . . . . . . . . . . . . . . . . 150
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Input/Output Descriptions . . . . . . . . . . . . . . . . . 152
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 153
7DEOHꢀꢑꢋꢁꢀ'HYLFHꢀ%XVꢀ2SHUDWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢑ
VersatileIO™ (VIO) Control ........................................................................... 154
Requirements for Asynchronous
Read Operation (Non-Burst) ........................................................................ 154
Requirements for Synchronous (Burst) Read Operation ..................... 154
Continuous Burst .......................................................................................... 154
7DEOHꢀꢑꢑꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢏꢂꢀꢇꢀDQGꢀꢍꢀ:DLWꢀ6WDWHVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢍ
7DEOHꢀꢑꢍꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢑꢀ:DLWꢀ6WDWHVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢍ
7DEOHꢀꢑꢇꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢋꢀ:DLWꢀ6WDWHVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢍ
7DEOHꢀꢑꢏꢁꢀ$GGUHVVꢀ/DWHQF\ꢀIRUꢀꢌꢀ:DLWꢀ6WDWHVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢇ
7DEOHꢀꢑꢈꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢏꢂꢀꢇꢂꢀ
DQGꢀꢍꢀ:DLWꢀ6WDWHVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢇ
7DEOHꢀꢑꢐꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢑꢀ
:DLWꢀ6WDWHVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢇ
7DEOHꢀꢍꢉꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢋꢀ
:DLWꢀ6WDWHVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢍꢇ
7DEOHꢀꢍꢊꢁꢀ$GGUHVVꢒ%RXQGDU\ꢀ&URVVLQJꢀ/DWHQF\ꢀIRUꢀꢌꢀ
4
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Write Buffer Programming Command Sequence ....................................173
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 193
)LJXUHꢀꢏꢈꢁꢀ7HVWꢀ6HWXSꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢐꢋ
7DEOHꢀꢇꢍꢁꢀ7HVWꢀ6SHFLILFDWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢐꢋ
7DEOHꢀꢇꢊꢁꢀ:ULWHꢀ%XIIHUꢀ&RPPDQGꢀ6HTXHQFHꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢏꢑ
)LJXUHꢀꢏꢌꢁꢀ:ULWHꢀ%XIIHUꢀ3URJUDPPLQJꢀ2SHUDWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢏꢍ
Chip Erase Command Sequence .................................................................. 176
Chip Erase Command Sequence .............................................................. 176
Sector Erase Command Sequence ............................................................... 176
Sector Erase Command Sequence .......................................................... 176
Accelerated Sector Erase ........................................................................... 177
)LJXUHꢀꢏꢋꢁꢀ(UDVHꢀ2SHUDWLRQ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢏꢏ
Erase Suspend/Erase Resume Commands ................................................. 177
Program Suspend/Program Resume Commands ....................................178
Lock Register Command Set Definitions ..................................................178
Volatile Sector Protection Command Set ................................................. 179
7DEOHꢀꢇꢌꢁꢀ&RPPDQGꢀ'HILQLWLRQVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢈꢉ
Key to Switching Waveforms . . . . . . . . . . . . . . . 193
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 193
7DEOHꢀꢇꢇꢁꢀ,QSXWꢀ:DYHIRUPVꢀDQGꢀ0HDVXUHPHQWꢀ/HYHOVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢊꢐꢋ
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 194
VCC Power-up ....................................................................................................194
)LJXUHꢀꢏꢐꢁꢀ9&&ꢀ3RZHUꢃXSꢀ'LDJUDPꢀ&/.ꢀ&KDUDFWHUL]DWLRQꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢐꢑ
)LJXUHꢀꢈꢉꢁꢀ&/.ꢀ&KDUDFWHUL]DWLRQꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢐꢑ
Synchronous/Burst Read .................................................................................195
)LJXUHꢀꢈꢊꢁꢀ%XUVWꢀ0RGHꢀ5HDG ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢐꢇ
Asynchronous Read ..........................................................................................197
)LJXUHꢀꢈꢌꢁꢀ$V\QFKURQRXVꢀ0RGHꢀ5HDGꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢐꢏ
)LJXUHꢀꢈꢋꢁꢀ5HVHWꢀ7LPLQJV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢊꢐꢈ
Erase/Program Operations .............................................................................199
)LJXUHꢀꢈꢑꢁꢀ3URJUDPꢀ2SHUDWLRQꢀ7LPLQJV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢌꢉꢉ
)LJXUHꢀꢈꢍꢁꢀ&KLSꢒ6HFWRUꢀ(UDVHꢀ2SHUDWLRQVꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢌꢉꢊ
)LJXUHꢀꢈꢇꢁꢀ$FFHOHUDWHGꢀ8QORFNꢀ%\SDVVꢀ3URJUDPPLQJꢀ7LPLQJꢁꢁꢁ ꢀꢌꢉꢌ
)LJXUHꢀꢈꢏꢁꢀ'DWDꢓꢀ3ROOLQJꢀ7LPLQJVꢀ
ꢅ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢆꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢌꢉꢋ
)LJXUHꢀꢈꢈꢁꢀ7RJJOHꢀ%LWꢀ7LPLQJVꢀꢅ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢆ ꢁ ꢀꢌꢉꢋ
)LJXUHꢀꢈꢐꢁꢀꢈꢃꢂꢀꢊꢇꢃꢂꢀDQGꢀꢋꢌꢃ:RUGꢀ/LQHDUꢀ%XUVWꢀ
$GGUHVVꢀ:UDSꢀ$URXQG ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢌꢉꢑ
)LJXUHꢀꢐꢉꢁꢀ/DWHQF\ꢀZLWKꢀ%RXQGDU\ꢀ&URVVLQJ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢌꢉꢑ
)LJXUHꢀꢐꢊꢁꢀ%DFNꢃWRꢃ%DFNꢀ5HDGꢒ:ULWHꢀ&\FOHꢀ7LPLQJV ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ꢀꢌꢉꢍ
Write Operation Status . . . . . . . . . . . . . . . . . . . 183
DQ7: Data# Polling .......................................................................................... 183
)LJXUHꢀꢏꢑꢁꢀ'DWDꢓꢀ3ROOLQJꢀ$OJRULWKP ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢈꢑ
DQ6: Toggle Bit I ..............................................................................................185
DQ2: Toggle Bit II .............................................................................................185
)LJXUHꢀꢏꢍꢁꢀ7RJJOHꢀ%LWꢀ$OJRULWKPꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢈꢇ
7DEOHꢀꢇꢋꢁꢀ'4ꢇꢀDQGꢀ'4ꢌꢀ,QGLFDWLRQVꢀ ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢈꢏ
Reading Toggle Bits DQ6/DQ2 ....................................................................187
DQ5: Exceeded Timing Limits ......................................................................187
DQ3: Sector Erase Start Timeout State Indicator ..................................188
DQ1: Write to Buffer Abort ..........................................................................188
7DEOHꢀꢇꢑꢁꢀ:ULWHꢀ2SHUDWLRQꢀ6WDWXVꢀꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢊꢈꢐ
Erase and Programming Performance . . . . . . . 206
Device History . . . . . . . . . . . . . . . . . . . . . . . . . . .207
S99KS-N Revision Summary . . . . . . . . . . . . . . . 208
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 190
)LJXUHꢀꢏꢇꢁꢀ0D[LPXPꢀ1HJDWLYHꢀ2YHUVKRRWꢀ:DYHIRUP ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢐꢉ
)LJXUHꢀꢏꢏꢁꢀ0D[LPXPꢀ3RVLWLYHꢀ2YHUVKRRWꢀ:DYHIRUPꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢀꢊꢐꢉ
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 191
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 192
CMOS Compatible ...........................................................................................192
MCP Revision Summary
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
5
A d v a n c e I n f o r m a t i o n
MCP Block Diagrams
F-RST#
F-VPP
RST#
A15-A0
ADQ15-ADQ0
DQ15-DQ0
VPP
MUX
CODE
FLASH
NSxxxN
CLK
F-CLK
F-RDY
F-WP#
F1-CE#
F-OE#
F-WE#
AVD#
WP#
CE#
RDY
OE#
WE#
AVD#
A16-Amax
A16-Amax
VCC
F-VSS
VSS
VCCQ
RST#
VPP
A15-A0
DQ15-DQ0
CLK
ADQ15-ADQ0
F-RDY
WP#
CE#
RDY
MUX
DATA
F2-CE#
OE#
WE#
AVD#
A16-Amax
FLASH
KSxxxN
VCC
F-VCC
F-VSS
VSS
VCCQ
F-VCCQ
Data Flash 1
CE#
VCC
VCCQ
F3-CE#
Data Flash 2
D-RAS#
D-CAS#
D-BA0
RAS#
CAS#
BA0
CLK
D-CLK
SDR
DRAM
MEMORY
D-BA1
BA1
D-CKE
D-LDQM
CKE
LDQM
UDQM
TEST
D-WE#
WE#
D-UDQM
D-TEST
D-Amax
- D-A0
D-DQ15 - D-DQ0
D-VSS
D-VSSQ
DQ15-DQ0
VSS
VSSQ
D-VCC
D-VCCQ
VCC
VCCQ
1RWHVꢀ
ꢀꢁ $PD[ꢂLQGLFDWHVꢂKLJKHVWꢂDGGUHVVꢂELWꢂIRUꢂPHPRU\ꢂFRPSRQHQWꢃ
Dꢁꢂ$PD[ꢂ ꢂ$ꢄꢅꢂIRUꢂ16ꢀꢄꢆ1ꢇꢂ$ꢄꢅꢂIRUꢂ.6ꢀꢄꢆ1
Eꢁꢂ$PD[ꢂ ꢂ$ꢀꢀꢂIRUꢂꢀꢄꢆꢂ0Eꢂ''5ꢂ'5$0
ꢄꢁ )RUꢂ)ODVKꢇꢂ$ꢈꢉ$ꢀꢊꢂLVꢂWLHGꢂWRꢂ'4ꢈꢂ±ꢂ'4ꢀꢊꢁ
6
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Connection Diagrams
128 Mb Code Flash + 256 Mb Data Flash +128 Mb SDR SDRAM Pinout
Legend
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DNU
DNU
D-VSSQ D-VCCQ D-DQ9
D-DQ8
D-VSS
D-VCC
D-VCC
D-DQ5
D-DQ3 D-VSSQ
DNU
DNU
Do Not Use
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
DNU
D-VSS D-DQ13
C2 C3
RFU
D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6
C5 C6 C7 C8 C9 C10
D-VCC D-VSSQ D-DQ7
D-DQ4
D-DQ1 D-VCCQ
DNU
C1
C4
C11
RFU
C12
D-DQ2
D12
C13
D-DQ0
D13
C14
D-VSS
D14
D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS
Code Flash Only
Data Flash Only
Flash Shared
DRAM Only
D1
RFU
E1
D2
NC
D3
NC
D4
INDEX
F-OE#
E12
ADQ8
E13
D-VCC
E14
E2
E3
RFU
A22
A17
ADQ9
ADQ1
ADQ0
F1
A23
F2
A19
F3
A18
F12
F-VSS
G12
F13
ADQ3
G13
F14
ADQ2
G14
G1
G2
G3
F-CE#
H1
F-WP#
H2
F-WE#
H3
F-VCCQ ADQ11
ADQ10
H14
H12
H13
F-VPP
F-VCC
F-CLK
ADQ13
ADQ12
ADQ4
J1
J2
J3
J12
J13
J14
A16
F-VSS
NC
F-VSS
F-VSS
ADQ5
K1
K2
K3
K12
K13
K14
A21
F-AVD# F2-VCC
L2 L3
F-RST# D-CE#
F2-VCC
ADQ7
ADQ6
Reserved for
Future Use
L1
A20
M1
L12
LA13
L14
ADQ14
M14
F-VCCQ ADQ15
M2
F-VSS
N2
M3
D-A3
N3
M4
D-A6
N4
M5
D-A9
N5
M6
D-CKE
N6
M7
D-VSS
N7
M8
D-WE#
N8
M9
D-A10
N9
M10
D-A1
N10
M11
RFU
M12
F2-CE#
N12
M13
F-RDY
N13
NC
F-VSS
N14
No Connect
N1
N11
DNU
P1
D-VSS
P2
D-VCC
P3
D-A5
P4
D-A8
P5
D-CAS#
P6
RFU
P7
D-BA1
P8
D-A11
P9
D-A2
P10
RFU
RFU
F-VCC
DNU
P11
P14
P12
P13
DNU
DNU
NC
D-A4
D-A7
D-RAS# D-CLK
D-VCC
D-BA0
D-A0
D-VCC
D-VSS
D-TEST
DNU
Index Location
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
7
A d v a n c e I n f o r m a t i o n
Input/Output Descriptions
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UHODWLYHꢀWRꢀ&/.ꢀIRUꢀ%XUVWꢀ0RGHꢁ
'ꢃ&/.
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'5$0ꢀ5RZꢀ$GGUHVVꢀ6WUREH
'5$0ꢀ&ROXPQꢀ$GGUHVVꢀ6WUREH
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)ODVKꢀ2XWSXWꢀ(QDEOHꢀLQSXWꢁꢀ$V\QFKURQRXVꢀUHODWLYHꢀ
WRꢀ&/.ꢀIRUꢀ%XUVWꢀPRGHꢁ
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'ꢃ:(ꢓ
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)ODVKꢀGHYLFHꢀSRZHUꢀVXSSO\ꢀꢅꢊꢁꢏꢀ9ꢀꢃꢀꢊꢁꢐꢍ9ꢆꢁ
)ODVKꢀ,QSXWꢒ2XWSXWꢀ%XIIHUꢀSRZHUꢀVXSSO\ꢁ
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'5$0ꢀ,QSXWꢒ2XWSXWꢀ%XIIHUꢀSRZHUꢀVXSSO\
'5$0ꢀGHYLFHꢀSRZHUꢀVXSSO\
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S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
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DRAM Speed
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Temperature
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Supplier
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
9
A d v a n c e I n f o r m a t i o n
Physical Dimensions
NMA133 - Thin profile Fine-pitch Ball Grid Array (BGA) MCP 11 x 10 mm
D1
D
A
A1 CORNER
eD
+0.20
-0.50
1.00
A1 ID.
0.10
C
eE
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0.50 REF
A
B
0.50 REF
C
D
E
7
SE
F
G
H
J
E
E1
K
L
M
N
P
φb
SD
B
6
7
0.10
C
φ 0.08
φ 0.15
M
C
C
TOP VIEW
M
A B
0.10
0.08
C
C
A2
C
A
A1
BOTTOM VIEW
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
JEDEC
NMA 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.00 mm x 10.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
1.20
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.10
0.20
0.90
10.9
9.90
1.30
0.30
1.02
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
0.96
BODY THICKNESS
D
11.00
11.10 BODY SIZE
10.10 BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
10.00
D1
E1
6.50 BSC.
6.50 BSC.
14
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
eD
SE / SD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
D5-D11,E4-E11,F4-F11
G4-G11, H4-H11, J4-J11
K4-K11,L4-L11
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3438 \ 16-039.22 \ 12.15.04
10
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
S29NS-N MirrorBitTM Flash Module
S29NS256N, S29NS128N
256/128 Megabit (16/8M x 16-bit), CMOS 1.8 Volt-only
Simultaneous Read/Write, Multiplexed, Burst Mode
Flash Memory
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
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S75NS128NDE based MCPs
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S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
15
A d v a n c e I n f o r m a t i o n
Block Diagram of Simultaneous Operation Circuit
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S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Input/Output Descriptions
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
17
A d v a n c e I n f o r m a t i o n
Device Bus Operations
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18
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Requirements for Synchronous (Burst) Read Operation
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Table 2. Address Latency for 7, 6, and 5 Wait States
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Table 3. Address Latency for 4 Wait States
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
19
A d v a n c e I n f o r m a t i o n
Table 4. Address Latency for 3 Wait States
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Table 5. Address Latency for 2 Wait States
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Table 6. Address/Boundary Crossing Latency for 7, 6, and 5 Wait States
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Table 7. Address/Boundary Crossing Latency for 4 Wait States
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Table 8. Address/Boundary Crossing Latency for 3 Wait States
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20
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 9. Address/Boundary Crossing Latency for 2 Wait States
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Table 10. Burst Address Groups
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
21
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22
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00_A2
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23
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S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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S75NS128NDE based MCPs
25
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26
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
27
A d v a n c e I n f o r m a t i o n
Password Sector Protection
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28
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
29
A d v a n c e I n f o r m a t i o n
Low VCC Write Inhibit
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Write Pulse “Glitch” Protection
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Logical Inhibit
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Lock Register
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Table 12. Lock Register
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30
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Standby Mode
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
31
A d v a n c e I n f o r m a t i o n
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32
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
33
A d v a n c e I n f o r m a t i o n
Table 14. CFI Query Identification String
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Table 15. System Interface String
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34
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 16. Device Geometry Definition
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Table 17. Primary Vendor-Specific Extended Query (Sheet 1 of 3)
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
35
A d v a n c e I n f o r m a t i o n
Table 17. Primary Vendor-Specific Extended Query (Sheet 2 of 3)
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36
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 17. Primary Vendor-Specific Extended Query (Sheet 3 of 3)
'DWD
$GGUHVVHV
ꢇꢍK
6ꢉꢇ16ꢉꢈꢋ1
ꢉꢉꢊꢉK
6ꢉꢇ16ꢄꢉꢊ1
ꢉꢉꢉꢈK
'HVFULSWLRQ
%DQNꢀꢊꢋꢀ5HJLRQꢀ,QIRUPDWLRQꢁꢀ;ꢀ ꢀ1XPEHUꢀRIꢀVHFWRUVꢀLQꢀEDQNꢀ
%DQNꢀꢊꢑꢀ5HJLRQꢀ,QIRUPDWLRQꢁꢀ;ꢀ ꢀ1XPEHUꢀRIꢀVHFWRUVꢀLQꢀEDQNꢀ
%DQNꢀꢊꢍꢀ5HJLRQꢀ,QIRUPDWLRQꢁꢀ;ꢀ ꢀ1XPEHUꢀRIꢀVHFWRUVꢀLQꢀEDQNꢀ
3URFHVVꢀ7HFKQRORJ\ꢁꢀꢉꢉKꢀ ꢀꢌꢋꢉꢀQPꢂꢀꢉꢊKꢀ ꢀꢊꢏꢉꢀQPꢂꢀꢉꢌKꢀ ꢀꢊꢋꢉꢀQPꢒꢊꢊꢉꢀQP
ꢇꢇK
ꢉꢉꢊꢉK
ꢉꢉꢉꢈK
ꢇꢏK
ꢉꢉꢊꢋK
ꢉꢉꢉ%K
ꢇꢈK
ꢉꢉꢉꢌK
\
Table 18. Sector Address Table, S29NS256N (Sheet 1 of 5)
%DQN
6HFWRU
6HFWRUꢀ6L]H
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
$GGUHVVꢀ5DQJH
ꢉꢉꢉꢉꢉꢉK±ꢉꢉ))))K
ꢉꢊꢉꢉꢉꢉK±ꢉꢊ))))K
ꢉꢌꢉꢉꢉꢉK±ꢉꢌ))))K
ꢉꢋꢉꢉꢉꢉK±ꢉꢋ))))K
ꢉꢑꢉꢉꢉꢉK±ꢉꢑ))))K
ꢉꢍꢉꢉꢉꢉK±ꢉꢍ))))K
ꢉꢇꢉꢉꢉꢉK±ꢉꢇ))))K
ꢉꢏꢉꢉꢉꢉK±ꢉꢏ))))K
ꢉꢈꢉꢉꢉꢉK±ꢉꢈ))))K
ꢉꢐꢉꢉꢉꢉK±ꢉꢐ))))K
ꢉ$ꢉꢉꢉꢉK±ꢉ$))))K
ꢉ%ꢉꢉꢉꢉK±ꢉ%))))K
ꢉ&ꢉꢉꢉꢉK±ꢉ&))))K
ꢉ'ꢉꢉꢉꢉK±ꢉ'))))K
ꢉ(ꢉꢉꢉꢉK±ꢉ())))K
ꢉ)ꢉꢉꢉꢉK±ꢉ)))))K
%DQN
6HFWRU
6$ꢋꢌ
6$ꢋꢋ
6$ꢋꢑ
6$ꢋꢍ
6$ꢋꢇ
6$ꢋꢏ
6$ꢋꢈ
6$ꢋꢐ
6$ꢑꢉ
6$ꢑꢊ
6$ꢑꢌ
6$ꢑꢋ
6$ꢑꢑ
6$ꢑꢍ
6$ꢑꢇ
6$ꢑꢏ
6HFWRUꢀ6L]H
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
$GGUHVVꢀ5DQJH
ꢌꢉꢉꢉꢉꢉK±ꢌꢉ))))K
ꢌꢊꢉꢉꢉꢉK±ꢌꢊ))))K
ꢌꢌꢉꢉꢉꢉK±ꢌꢌ))))K
ꢌꢋꢉꢉꢉꢉK±ꢌꢋ))))K
ꢌꢑꢉꢉꢉꢉK±ꢌꢑ))))K
ꢌꢍꢉꢉꢉꢉK±ꢌꢍ))))K
ꢌꢇꢉꢉꢉꢉK±ꢌꢇ))))K
ꢌꢏꢉꢉꢉꢉK±ꢌꢏ))))K
ꢌꢈꢉꢉꢉꢉK±ꢌꢈ))))K
ꢌꢐꢉꢉꢉꢉK±ꢌꢐ))))K
ꢌ$ꢉꢉꢉꢉK±ꢌ$))))K
ꢌ%ꢉꢉꢉꢉK±ꢌ%))))K
ꢌ&ꢉꢉꢉꢉK±ꢌ&))))K
ꢌ'ꢉꢉꢉꢉK±ꢌ'))))K
ꢌ(ꢉꢉꢉꢉK±ꢌ())))K
ꢌ)ꢉꢉꢉꢉK±ꢌ)))))K
6$ꢉ
6$ꢊ
6$ꢌ
6$ꢋ
6$ꢑ
6$ꢍ
6$ꢇ
6$ꢏ
6$ꢈ
6$ꢐ
6$ꢊꢉ
6$ꢊꢊ
6$ꢊꢌ
6$ꢊꢋ
6$ꢊꢑ
6$ꢊꢍ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
37
A d v a n c e I n f o r m a t i o n
Table 18. Sector Address Table, S29NS256N (Sheet 2 of 5)
%DQN
6HFWRU
6$ꢊꢇ
6$ꢊꢏ
6$ꢊꢈ
6$ꢊꢐ
6$ꢌꢉ
6$ꢌꢊ
6$ꢌꢌ
6$ꢌꢋ
6$ꢌꢑ
6$ꢌꢍ
6$ꢌꢇ
6$ꢌꢏ
6$ꢌꢈ
6$ꢌꢐ
6$ꢋꢉ
6$ꢋꢊ
6$ꢇꢑ
6$ꢇꢍ
6$ꢇꢇ
6$ꢇꢏ
6$ꢇꢈ
6$ꢇꢐ
6$ꢏꢉ
6$ꢏꢊ
6$ꢏꢌ
6$ꢏꢋ
6$ꢏꢑ
6$ꢏꢍ
6$ꢏꢇ
6$ꢏꢏ
6$ꢏꢈ
6$ꢏꢐ
6HFWRUꢀ6L]H
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
$GGUHVVꢀ5DQJH
ꢊꢉꢉꢉꢉꢉK±ꢊꢉ))))K
ꢊꢊꢉꢉꢉꢉK±ꢊꢊ))))K
ꢊꢌꢉꢉꢉꢉK±ꢊꢌ))))K
ꢊꢋꢉꢉꢉꢉK±ꢊꢋ))))K
ꢊꢑꢉꢉꢉꢉK±ꢊꢑ))))K
ꢊꢍꢉꢉꢉꢉK±ꢊꢍ))))K
ꢊꢇꢉꢉꢉꢉK±ꢊꢇ))))K
ꢊꢏꢉꢉꢉꢉK±ꢊꢏ))))K
ꢊꢈꢉꢉꢉꢉK±ꢊꢈ))))K
ꢊꢐꢉꢉꢉꢉK±ꢊꢐ))))K
ꢊ$ꢉꢉꢉꢉK±ꢊ$))))K
ꢊ%ꢉꢉꢉꢉK±ꢊ%))))K
ꢊ&ꢉꢉꢉꢉK±ꢊ&))))K
ꢊ'ꢉꢉꢉꢉK±ꢊ'))))K
ꢊ(ꢉꢉꢉꢉK±ꢊ())))K
ꢊ)ꢉꢉꢉꢉK±ꢊ)))))K
ꢑꢉꢉꢉꢉꢉK±ꢑꢉ))))K
ꢑꢊꢉꢉꢉꢉK±ꢑꢊ))))K
ꢑꢌꢉꢉꢉꢉK±ꢑꢌ))))K
ꢑꢋꢉꢉꢉꢉK±ꢑꢋ))))K
ꢑꢑꢉꢉꢉꢉK±ꢑꢑ))))K
ꢑꢍꢉꢉꢉꢉK±ꢑꢍ))))K
ꢑꢇꢉꢉꢉꢉK±ꢑꢇ))))K
ꢑꢏꢉꢉꢉꢉK±ꢑꢏ))))K
ꢑꢈꢉꢉꢉꢉK±ꢑꢈ))))K
ꢑꢐꢉꢉꢉꢉK±ꢑꢐ))))K
ꢑ$ꢉꢉꢉꢉK±ꢑ$))))K
ꢑ%ꢉꢉꢉꢉK±ꢑ%))))K
ꢑ&ꢉꢉꢉꢉK±ꢑ&))))K
ꢑ'ꢉꢉꢉꢉK±ꢑ'))))K
ꢑ(ꢉꢉꢉꢉK±ꢑ())))K
ꢑ)ꢉꢉꢉꢉK±ꢑ)))))K
%DQN
6HFWRU
6$ꢑꢈ
6$ꢑꢐ
6$ꢍꢉ
6$ꢍꢊ
6$ꢍꢌ
6$ꢍꢋ
6$ꢍꢑ
6$ꢍꢍ
6$ꢍꢇ
6$ꢍꢏ
6HFWRUꢀ6L]H
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
ꢇꢑꢀ.ꢀZRUGV
$GGUHVVꢀ5DQJH
ꢋꢉꢉꢉꢉꢉK±ꢋꢉ))))K
ꢋꢊꢉꢉꢉꢉK±ꢋꢊ))))K
ꢋꢌꢉꢉꢉꢉK±ꢋꢌ))))K
ꢋꢋꢉꢉꢉꢉK±ꢋꢋ))))K
ꢋꢑꢉꢉꢉꢉK±ꢋꢑ))))K
ꢋꢍꢉꢉꢉꢉK±ꢋꢍ))))K
ꢋꢇꢉꢉꢉꢉK±ꢋꢇ))))K
ꢋꢏꢉꢉꢉꢉK±ꢋꢏ))))K
ꢋꢈꢉꢉꢉꢉK±ꢋꢈ))))K
ꢋꢐꢉꢉꢉꢉK±ꢋꢐ))))K
ꢋ$ꢉꢉꢉꢉK±ꢋ$))))K
ꢋ%ꢉꢉꢉꢉK±ꢋ%))))K
ꢋ&ꢉꢉꢉꢉK±ꢋ&))))K
ꢋ'ꢉꢉꢉꢉK±ꢋ'))))K
ꢋ(ꢉꢉꢉꢉK±ꢋ())))K
ꢋ)ꢉꢉꢉꢉK±ꢋ)))))K
ꢇꢉꢉꢉꢉꢉK±ꢇꢉ))))K
ꢇꢊꢉꢉꢉꢉK±ꢇꢊ))))K
ꢇꢌꢉꢉꢉꢉK±ꢇꢌ))))K
ꢇꢋꢉꢉꢉꢉK±ꢇꢋ))))K
ꢇꢑꢉꢉꢉꢉK±ꢇꢑ))))K
ꢇꢍꢉꢉꢉꢉK±ꢇꢍ))))K
ꢇꢇꢉꢉꢉꢉK±ꢇꢇ))))K
ꢇꢏꢉꢉꢉꢉK±ꢇꢏ))))K
ꢇꢈꢉꢉꢉꢉK±ꢇꢈ))))K
ꢇꢐꢉꢉꢉꢉK±ꢇꢐ))))K
ꢇ$ꢉꢉꢉꢉK±ꢇ$))))K
ꢇ%ꢉꢉꢉꢉK±ꢇ%))))K
ꢇ&ꢉꢉꢉꢉK±ꢇ&))))K
ꢇ'ꢉꢉꢉꢉK±ꢇ'))))K
ꢇ(ꢉꢉꢉꢉK±ꢇ())))K
ꢇ)ꢉꢉꢉꢉK±ꢇ)))))K
6$ꢍꢈ
6$ꢍꢐ
6$ꢇꢉ
6$ꢇꢊ
6$ꢇꢌ
6$ꢇꢋ
6$ꢐꢇ
6$ꢐꢏ
6$ꢐꢈ
6$ꢐꢐ
6$ꢊꢉꢉ
6$ꢊꢉꢊ
6$ꢊꢉꢌ
6$ꢊꢉꢋ
6$ꢊꢉꢑ
6$ꢊꢉꢍ
6$ꢊꢉꢇ
6$ꢊꢉꢏ
6$ꢊꢉꢈ
6$ꢊꢉꢐ
6$ꢊꢊꢉ
6$ꢊꢊꢊ
38
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 18. Sector Address Table, S29NS256N (Sheet 3 of 5)
%DQN
6HFWRU
6$ꢈꢉ
6HFWRUꢀ6L]H
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
ꢇꢑꢀ.ZRUGV
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$GGUHVVꢀ5DQJH
ꢍꢉꢉꢉꢉꢉK±ꢍꢉ))))K
ꢍꢊꢉꢉꢉꢉK±ꢍꢊ))))K
ꢍꢌꢉꢉꢉꢉK±ꢍꢌ))))K
ꢍꢋꢉꢉꢉꢉK±ꢍꢋ))))K
ꢍꢑꢉꢉꢉꢉK±ꢍꢑ))))K
ꢍꢍꢉꢉꢉꢉK±ꢍꢍ))))K
ꢍꢇꢉꢉꢉꢉK±ꢍꢇ))))K
ꢍꢏꢉꢉꢉꢉK±ꢍꢏ))))K
ꢍꢈꢉꢉꢉꢉK±ꢍꢈ))))K
ꢍꢐꢉꢉꢉꢉK±ꢍꢐ))))K
ꢍ$ꢉꢉꢉꢉK±ꢍ$))))K
ꢍ%ꢉꢉꢉꢉK±ꢍ%))))K
ꢍ&ꢉꢉꢉꢉK±ꢍ&))))K
ꢍ'ꢉꢉꢉꢉK±ꢍ'))))K
ꢍ(ꢉꢉꢉꢉK±ꢍ())))K
ꢍ)ꢉꢉꢉꢉK±ꢍ)))))K
ꢈꢉꢉꢉꢉꢉK±ꢈꢉ))))K
ꢈꢊꢉꢉꢉꢉK±ꢈꢊ))))K
ꢈꢌꢉꢉꢉꢉK±ꢈꢌ))))K
ꢈꢋꢉꢉꢉꢉK±ꢈꢋ))))K
ꢈꢑꢉꢉꢉꢉK±ꢈꢑ))))K
ꢈꢍꢉꢉꢉꢉK±ꢈꢍ))))K
ꢈꢇꢉꢉꢉꢉK±ꢈꢇ))))K
ꢈꢏꢉꢉꢉꢉK±ꢈꢏ))))K
ꢈꢈꢉꢉꢉꢉK±ꢈꢈ))))K
ꢈꢐꢉꢉꢉꢉK±ꢈꢐ))))K
ꢈ$ꢉꢉꢉꢉK±ꢈ$))))K
ꢈ%ꢉꢉꢉꢉK±ꢈ%))))K
ꢈ&ꢉꢉꢉꢉK±ꢈ&))))K
ꢈ'ꢉꢉꢉꢉK±ꢈ'))))K
ꢈ(ꢉꢉꢉꢉK±ꢈ())))K
ꢈ)ꢉꢉꢉꢉK±ꢈ)))))K
%DQN
6HFWRU
6$ꢊꢊꢌ
6$ꢊꢊꢋ
6$ꢊꢊꢑ
6$ꢊꢊꢍ
6$ꢊꢊꢇ
6$ꢊꢊꢏ
6$ꢊꢊꢈ
6$ꢊꢊꢐ
6$ꢊꢌꢉ
6$ꢊꢌꢊ
6$ꢊꢌꢌ
6$ꢊꢌꢋ
6$ꢊꢌꢑ
6$ꢊꢌꢍ
6$ꢊꢌꢇ
6$ꢊꢌꢏ
6$ꢊꢇꢉ
6$ꢊꢇꢊ
6$ꢊꢇꢌ
6$ꢊꢇꢋ
6$ꢊꢇꢑ
6$ꢊꢇꢍ
6$ꢊꢇꢇ
6$ꢊꢇꢏ
6$ꢊꢇꢈ
6$ꢊꢇꢐ
6$ꢊꢏꢉ
6$ꢊꢏꢊ
6$ꢊꢏꢌ
6$ꢊꢏꢋ
6$ꢊꢏꢑ
6$ꢊꢏꢍ
6HFWRUꢀ6L]H
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ꢇꢑꢀ.ꢀZRUGV
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ꢏꢐꢉꢉꢉꢉK±ꢏꢐ))))K
ꢏ$ꢉꢉꢉꢉK±ꢏ$))))K
ꢏ%ꢉꢉꢉꢉK±ꢏ%))))K
ꢏ&ꢉꢉꢉꢉK±ꢏ&))))K
ꢏ'ꢉꢉꢉꢉK±ꢏ'))))K
ꢏ(ꢉꢉꢉꢉK±ꢏ())))K
ꢏ)ꢉꢉꢉꢉK±ꢏ)))))K
$ꢉꢉꢉꢉꢉK±$ꢉ))))K
$ꢊꢉꢉꢉꢉK±$ꢊ))))K
$ꢌꢉꢉꢉꢉK±$ꢌ))))K
$ꢋꢉꢉꢉꢉK±$ꢋ))))K
$ꢑꢉꢉꢉꢉK±$ꢑ))))K
$ꢍꢉꢉꢉꢉK±$ꢍ))))K
$ꢇꢉꢉꢉꢉK±$ꢇ))))K
$ꢏꢉꢉꢉꢉK±$ꢏ))))K
$ꢈꢉꢉꢉꢉK±$ꢈ))))K
$ꢐꢉꢉꢉꢉK±$ꢐ))))K
$$ꢉꢉꢉꢉK±$$))))K
$%ꢉꢉꢉꢉK±$%))))K
$&ꢉꢉꢉꢉK±$&))))K
$'ꢉꢉꢉꢉK±$'))))K
$(ꢉꢉꢉꢉK±$())))K
$)ꢉꢉꢉꢉK±$)))))K
6$ꢈꢊ
6$ꢈꢌ
6$ꢈꢋ
6$ꢈꢑ
6$ꢈꢍ
6$ꢈꢇ
6$ꢈꢏ
6$ꢈꢈ
6$ꢈꢐ
6$ꢐꢉ
6$ꢐꢊ
6$ꢐꢌ
6$ꢐꢋ
6$ꢐꢑ
6$ꢐꢍ
6$ꢊꢌꢈ
6$ꢊꢌꢐ
6$ꢊꢋꢉ
6$ꢊꢋꢊ
6$ꢊꢋꢌ
6$ꢊꢋꢋ
6$ꢊꢋꢑ
6$ꢊꢋꢍ
6$ꢊꢋꢇ
6$ꢊꢋꢏ
6$ꢊꢋꢈ
6$ꢊꢋꢐ
6$ꢊꢑꢉ
6$ꢊꢑꢊ
6$ꢊꢑꢌ
6$ꢊꢑꢋ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
39
A d v a n c e I n f o r m a t i o n
Table 18. Sector Address Table, S29NS256N (Sheet 4 of 5)
%DQN
6HFWRU
6$ꢊꢑꢑ
6$ꢊꢑꢍ
6$ꢊꢑꢇ
6$ꢊꢑꢏ
6$ꢊꢑꢈ
6$ꢊꢑꢐ
6$ꢊꢍꢉ
6$ꢊꢍꢊ
6$ꢊꢍꢌ
6$ꢊꢍꢋ
6$ꢊꢍꢑ
6$ꢊꢍꢍ
6$ꢊꢍꢇ
6$ꢊꢍꢏ
6$ꢊꢍꢈ
6$ꢊꢍꢐ
6$ꢊꢐꢌ
6$ꢊꢐꢋ
6$ꢊꢐꢑ
6$ꢊꢐꢍ
6$ꢊꢐꢇ
6$ꢊꢐꢏ
6$ꢊꢐꢈ
6$ꢊꢐꢐ
6$ꢌꢉꢉ
6$ꢌꢉꢊ
6$ꢌꢉꢌ
6$ꢌꢉꢋ
6$ꢌꢉꢑ
6$ꢌꢉꢍ
6$ꢌꢉꢇ
6$ꢌꢉꢏ
6HFWRUꢀ6L]H
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ꢐꢉꢉꢉꢉꢉK±ꢐꢉ))))K
ꢐꢊꢉꢉꢉꢉK±ꢐꢊ))))K
ꢐꢌꢉꢉꢉꢉK±ꢐꢌ))))K
ꢐꢋꢉꢉꢉꢉK±ꢐꢋ))))K
ꢐꢑꢉꢉꢉꢉK±ꢐꢑ))))K
ꢐꢍꢉꢉꢉꢉK±ꢐꢍ))))K
ꢐꢇꢉꢉꢉꢉK±ꢐꢇ))))K
ꢐꢏꢉꢉꢉꢉK±ꢐꢏ))))K
ꢐꢈꢉꢉꢉꢉK±ꢐꢈ))))K
ꢐꢐꢉꢉꢉꢉK±ꢐꢐ))))K
ꢐ$ꢉꢉꢉꢉK±ꢐ$))))K
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ꢐ(ꢉꢉꢉꢉK±ꢐ())))K
ꢐ)ꢉꢉꢉꢉK±ꢐ)))))K
&ꢉꢉꢉꢉꢉK±&ꢉ))))K
&ꢊꢉꢉꢉꢉK±&ꢊ))))K
&ꢌꢉꢉꢉꢉK±&ꢌ))))K
&ꢋꢉꢉꢉꢉK±&ꢋ))))K
&ꢑꢉꢉꢉꢉK±&ꢑ))))K
&ꢍꢉꢉꢉꢉK±&ꢍ))))K
&ꢇꢉꢉꢉꢉK±&ꢇ))))K
&ꢏꢉꢉꢉꢉK±&ꢏ))))K
&ꢈꢉꢉꢉꢉK±&ꢈ))))K
&ꢐꢉꢉꢉꢉK±&ꢐ))))K
&$ꢉꢉꢉꢉK±&$))))K
&%ꢉꢉꢉꢉK±&%))))K
&&ꢉꢉꢉꢉK±&&))))K
&'ꢉꢉꢉꢉK±&'))))K
&(ꢉꢉꢉꢉK±&())))K
&)ꢉꢉꢉꢉK±&)))))K
%DQN
6HFWRU
6$ꢊꢏꢇ
6$ꢊꢏꢏ
6$ꢊꢏꢈ
6$ꢊꢏꢐ
6$ꢊꢈꢉ
6$ꢊꢈꢊ
6$ꢊꢈꢌ
6$ꢊꢈꢋ
6$ꢊꢈꢑ
6$ꢊꢈꢍ
6$ꢊꢈꢇ
6$ꢊꢈꢏ
6$ꢊꢈꢈ
6$ꢊꢈꢐ
6$ꢊꢐꢉ
6$ꢊꢐꢊ
6$ꢌꢌꢑ
6$ꢌꢌꢍ
6$ꢌꢌꢇ
6$ꢌꢌꢏ
6$ꢌꢌꢈ
6$ꢌꢌꢐ
6$ꢌꢋꢉ
6$ꢌꢋꢊ
6$ꢌꢋꢌ
6$ꢌꢋꢋ
6$ꢌꢋꢑ
6$ꢌꢋꢍ
6$ꢌꢋꢇ
6$ꢌꢋꢏ
6$ꢌꢋꢈ
6$ꢌꢋꢐ
6HFWRUꢀ6L]H
ꢇꢑꢀ.ZRUGV
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(ꢊꢉꢉꢉꢉK±(ꢊ))))K
(ꢌꢉꢉꢉꢉK±(ꢌ))))K
(ꢋꢉꢉꢉꢉK±(ꢋ))))K
(ꢑꢉꢉꢉꢉK±(ꢑ))))K
(ꢍꢉꢉꢉꢉK±(ꢍ))))K
(ꢇꢉꢉꢉꢉK±(ꢇ))))K
(ꢏꢉꢉꢉꢉK±(ꢏ))))K
(ꢈꢉꢉꢉꢉK±(ꢈ))))K
(ꢐꢉꢉꢉꢉK±(ꢐ))))K
($ꢉꢉꢉꢉK±($))))K
(%ꢉꢉꢉꢉK±(%))))K
(&ꢉꢉꢉꢉK±(&))))K
('ꢉꢉꢉꢉK±('))))K
((ꢉꢉꢉꢉK±(())))K
()ꢉꢉꢉꢉK±()))))K
40
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 18. Sector Address Table, S29NS256N (Sheet 5 of 5)
%DQN
6HFWRU
6$ꢌꢉꢈ
6$ꢌꢉꢐ
6$ꢌꢊꢉ
6$ꢌꢊꢊ
6$ꢌꢊꢌ
6$ꢌꢊꢋ
6$ꢌꢊꢑ
6$ꢌꢊꢍ
6$ꢌꢊꢇ
6$ꢌꢊꢏ
6$ꢌꢊꢈ
6$ꢌꢊꢐ
6$ꢌꢌꢉ
6$ꢌꢌꢊ
6$ꢌꢌꢌ
6$ꢌꢌꢋ
6HFWRUꢀ6L]H
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'ꢋꢉꢉꢉꢉK±'ꢋ))))K
'ꢑꢉꢉꢉꢉK±'ꢑ))))K
'ꢍꢉꢉꢉꢉK±'ꢍ))))K
'ꢇꢉꢉꢉꢉK±'ꢇ))))K
'ꢏꢉꢉꢉꢉK±'ꢏ))))K
'ꢈꢉꢉꢉꢉK±'ꢈ))))K
'ꢐꢉꢉꢉꢉK±'ꢐ))))K
'$ꢉꢉꢉꢉK±'$))))K
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')ꢉꢉꢉꢉK±')))))K
%DQN
6HFWRU
6$ꢌꢑꢉ
6$ꢌꢑꢊ
6$ꢌꢑꢌ
6$ꢌꢑꢋ
6$ꢌꢑꢑ
6$ꢌꢑꢍ
6$ꢌꢑꢇ
6$ꢌꢑꢏ
6$ꢌꢑꢈ
6$ꢌꢑꢐ
6$ꢌꢍꢉ
6$ꢌꢍꢊ
6$ꢌꢍꢌ
6$ꢌꢍꢋ
6$ꢌꢍꢑ
6$ꢌꢍꢍ
6$ꢌꢍꢇ
6$ꢌꢍꢏ
6$ꢌꢍꢈ
6HFWRUꢀ6L]H
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)ꢑꢉꢉꢉꢉK±)ꢑ))))K
)ꢍꢉꢉꢉꢉK±)ꢍ))))K
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)ꢏꢉꢉꢉꢉK±)ꢏ))))K
)ꢈꢉꢉꢉꢉK±)ꢈ))))K
)ꢐꢉꢉꢉꢉK±)ꢐ))))K
)$ꢉꢉꢉꢉK±)$))))K
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))ꢈꢉꢉꢉK±))%)))K
))&ꢉꢉꢉK±))))))K
\\
Table 19. Sector Address Table, S29NS128N (Sheet 1 of 3)
%DQN
6HFWRU
6$ꢉ
6$ꢊ
6$ꢌ
6$ꢋ
6$ꢑ
6$ꢍ
6$ꢇ
6$ꢏ
6HFWRUꢀ6L]H
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ꢉꢌꢉꢉꢉꢉK±ꢉꢌ))))K
ꢉꢋꢉꢉꢉꢉK±ꢉꢋ))))K
ꢉꢑꢉꢉꢉꢉK±ꢉꢑ))))K
ꢉꢍꢉꢉꢉꢉK±ꢉꢍ))))K
ꢉꢇꢉꢉꢉꢉK±ꢉꢇ))))K
ꢉꢏꢉꢉꢉꢉK±ꢉꢏ))))K
%DQN
6HFWRU
6$ꢋꢌ
6$ꢋꢋ
6$ꢋꢑ
6$ꢋꢍ
6$ꢋꢇ
6$ꢋꢏ
6$ꢋꢈ
6$ꢋꢐ
6HFWRUꢀ6L]H
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ꢇꢑꢀ.ZRUGV
$GGUHVVꢀ5DQJH
ꢌꢉꢉꢉꢉꢉK±ꢌꢉ))))K
ꢌꢊꢉꢉꢉꢉK±ꢌꢊ))))K
ꢌꢌꢉꢉꢉꢉK±ꢌꢌ))))K
ꢌꢋꢉꢉꢉꢉK±ꢌꢋ))))K
ꢌꢑꢉꢉꢉꢉK±ꢌꢑ))))K
ꢌꢍꢉꢉꢉꢉK±ꢌꢍ))))K
ꢌꢇꢉꢉꢉꢉK±ꢌꢇ))))K
ꢌꢏꢉꢉꢉꢉK±ꢌꢏ))))K
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
41
A d v a n c e I n f o r m a t i o n
Table 19. Sector Address Table, S29NS128N (Sheet 2 of 3)
%DQN
6HFWRU
6$ꢈ
6HFWRUꢀ6L]H
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ꢉꢐꢉꢉꢉꢉK±ꢉꢐ))))K
ꢉ$ꢉꢉꢉꢉK±ꢉ$))))K
ꢉ%ꢉꢉꢉꢉK±ꢉ%))))K
ꢉ&ꢉꢉꢉꢉK±ꢉ&))))K
ꢉ'ꢉꢉꢉꢉK±ꢉ'))))K
ꢉ(ꢉꢉꢉꢉK±ꢉ())))K
ꢉ)ꢉꢉꢉꢉK±ꢉ)))))K
ꢊꢉꢉꢉꢉꢉK±ꢊꢉ))))K
ꢊꢊꢉꢉꢉꢉK±ꢊꢊ))))K
ꢊꢌꢉꢉꢉꢉK±ꢊꢌ))))K
ꢊꢋꢉꢉꢉꢉK±ꢊꢋ))))K
ꢊꢑꢉꢉꢉꢉK±ꢊꢑ))))K
ꢊꢍꢉꢉꢉꢉK±ꢊꢍ))))K
ꢊꢇꢉꢉꢉꢉK±ꢊꢇ))))K
ꢊꢏꢉꢉꢉꢉK±ꢊꢏ))))K
ꢊꢈꢉꢉꢉꢉK±ꢊꢈ))))K
ꢊꢐꢉꢉꢉꢉK±ꢊꢐ))))K
ꢊ$ꢉꢉꢉꢉK±ꢊ$))))K
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ꢊ'ꢉꢉꢉꢉK±ꢊ'))))K
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ꢑꢊꢉꢉꢉꢉK±ꢑꢊ))))K
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ꢑꢑꢉꢉꢉꢉK±ꢑꢑ))))K
ꢑꢍꢉꢉꢉꢉK±ꢑꢍ))))K
ꢑꢇꢉꢉꢉꢉK±ꢑꢇ))))K
ꢑꢏꢉꢉꢉꢉK±ꢑꢏ))))K
%DQN
6HFWRU
6$ꢑꢉ
6$ꢑꢊ
6$ꢑꢌ
6$ꢑꢋ
6$ꢑꢑ
6$ꢑꢍ
6$ꢑꢇ
6$ꢑꢏ
6$ꢑꢈ
6$ꢑꢐ
6$ꢍꢉ
6$ꢍꢊ
6$ꢍꢌ
6$ꢍꢋ
6$ꢍꢑ
6$ꢍꢍ
6$ꢍꢇ
6$ꢍꢏ
6$ꢍꢈ
6$ꢍꢐ
6$ꢇꢉ
6$ꢇꢊ
6$ꢇꢌ
6$ꢇꢋ
6$ꢐꢇ
6$ꢐꢏ
6$ꢐꢈ
6$ꢐꢐ
6$ꢊꢉꢉ
6$ꢊꢉꢊ
6$ꢊꢉꢌ
6$ꢊꢉꢋ
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ꢌ$ꢉꢉꢉꢉK±ꢌ$))))K
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ꢌ'ꢉꢉꢉꢉK±ꢌ'))))K
ꢌ(ꢉꢉꢉꢉK±ꢌ())))K
ꢌ)ꢉꢉꢉꢉK±ꢌ)))))K
ꢋꢉꢉꢉꢉꢉK±ꢋꢉ))))K
ꢋꢊꢉꢉꢉꢉK±ꢋꢊ))))K
ꢋꢌꢉꢉꢉꢉK±ꢋꢌ))))K
ꢋꢋꢉꢉꢉꢉK±ꢋꢋ))))K
ꢋꢑꢉꢉꢉꢉK±ꢋꢑ))))K
ꢋꢍꢉꢉꢉꢉK±ꢋꢍ))))K
ꢋꢇꢉꢉꢉꢉK±ꢋꢇ))))K
ꢋꢏꢉꢉꢉꢉK±ꢋꢏ))))K
ꢋꢈꢉꢉꢉꢉK±ꢋꢈ))))K
ꢋꢐꢉꢉꢉꢉK±ꢋꢐ))))K
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ꢋ%ꢉꢉꢉꢉK±ꢋ%))))K
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ꢋ'ꢉꢉꢉꢉK±ꢋ'))))K
ꢋ(ꢉꢉꢉꢉK±ꢋ())))K
ꢋ)ꢉꢉꢉꢉK±ꢋ)))))K
ꢇꢉꢉꢉꢉꢉK±ꢇꢉ))))K
ꢇꢊꢉꢉꢉꢉK±ꢇꢊ))))K
ꢇꢌꢉꢉꢉꢉK±ꢇꢌ))))K
ꢇꢋꢉꢉꢉꢉK±ꢇꢋ))))K
ꢇꢑꢉꢉꢉꢉK±ꢇꢑ))))K
ꢇꢍꢉꢉꢉꢉK±ꢇꢍ))))K
ꢇꢇꢉꢉꢉꢉK±ꢇꢇ))))K
ꢇꢏꢉꢉꢉꢉK±ꢇꢏ))))K
6$ꢐ
6$ꢊꢉ
6$ꢊꢊ
6$ꢊꢌ
6$ꢊꢋ
6$ꢊꢑ
6$ꢊꢍ
6$ꢊꢇ
6$ꢊꢏ
6$ꢊꢈ
6$ꢊꢐ
6$ꢌꢉ
6$ꢌꢊ
6$ꢌꢌ
6$ꢌꢋ
6$ꢌꢑ
6$ꢌꢍ
6$ꢌꢇ
6$ꢌꢏ
6$ꢌꢈ
6$ꢌꢐ
6$ꢋꢉ
6$ꢋꢊ
6$ꢇꢑ
6$ꢇꢍ
6$ꢇꢇ
6$ꢇꢏ
6$ꢇꢈ
6$ꢇꢐ
6$ꢏꢉ
6$ꢏꢊ
42
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 19. Sector Address Table, S29NS128N (Sheet 3 of 3)
%DQN
6HFWRU
6$ꢏꢌ
6$ꢏꢋ
6$ꢏꢑ
6$ꢏꢍ
6$ꢏꢇ
6$ꢏꢏ
6$ꢏꢈ
6$ꢏꢐ
6$ꢈꢉ
6$ꢈꢊ
6$ꢈꢌ
6$ꢈꢋ
6$ꢈꢑ
6$ꢈꢍ
6$ꢈꢇ
6$ꢈꢏ
6$ꢈꢈ
6$ꢈꢐ
6$ꢐꢉ
6$ꢐꢊ
6$ꢐꢌ
6$ꢐꢋ
6$ꢐꢑ
6$ꢐꢍ
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6$ꢊꢉꢑ
6$ꢊꢉꢍ
6$ꢊꢉꢇ
6$ꢊꢉꢏ
6$ꢊꢉꢈ
6$ꢊꢉꢐ
6$ꢊꢊꢉ
6$ꢊꢊꢊ
6$ꢊꢊꢌ
6$ꢊꢊꢋ
6$ꢊꢊꢑ
6$ꢊꢊꢍ
6$ꢊꢊꢇ
6$ꢊꢊꢏ
6$ꢊꢊꢈ
6$ꢊꢊꢐ
6$ꢊꢌꢉ
6$ꢊꢌꢊ
6$ꢊꢌꢌ
6$ꢊꢌꢋ
6$ꢊꢌꢑ
6$ꢊꢌꢍ
6$ꢊꢌꢇ
6$ꢊꢌꢏ
6$ꢊꢌꢈ
6$ꢊꢌꢐ
6$ꢊꢋꢉ
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
43
A d v a n c e I n f o r m a t i o n
Command Definitions
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Reading Array Data
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DJDLQꢀUHDGꢀDUUD\ꢀGDWDꢀZLWKꢀWKHꢀVDPHꢀH[FHSWLRQꢁꢀ6HHꢀWKHꢀ(UDVHꢀ6XVSHQGꢒ(UDVHꢀ5HVXPHꢀ&RPPDQGV
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$IWHUꢀWKHꢀGHYLFHꢀDFFHSWVꢀDꢀ3URJUDPꢀ6XVSHQGꢀFRPPDQGꢂꢀWKHꢀFRUUHVSRQGLQJꢀEDQNꢀHQWHUVꢀWKHꢀSURꢃ
JUDPꢃVXVSHQGꢃUHDGꢀPRGHꢂꢀDIWHUꢀZKLFKꢀWKHꢀV\VWHPꢀFDQꢀUHDGꢀGDWDꢀIURPꢀDQ\ꢀQRQꢃSURJUDPꢃ
VXVSHQGHGꢀVHFWRUꢀZLWKLQꢀWKHꢀVDPHꢀEDQNꢁ
7KHꢀV\VWHPꢀPXVWꢀLVVXHꢀWKHꢀUHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀDꢀEDQNꢀWRꢀWKHꢀUHDGꢀꢅRUꢀHUDVHꢃVXVSHQGꢃUHDGꢆꢀ
PRGHꢀLIꢀ'4ꢍꢀJRHVꢀKLJKꢀGXULQJꢀDQꢀDFWLYHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢂꢀRUꢀLIꢀWKHꢀEDQNꢀLVꢀLQꢀWKHꢀDXꢃ
WRVHOHFWꢀPRGHꢁ
6HHꢀDOVRꢀ9HUVDWLOH,2ꢀꢅ9,2ꢆꢀ&RQWUROꢀDQGꢀ5HTXLUHPHQWVꢀIRUꢀ6\QFKURQRXVꢀꢅ%XUVWꢆꢀ5HDGꢀ2SHUDWLRQ
LQꢀWKHꢀ'HYLFHꢀ%XVꢀ2SHUDWLRQVꢀVHFWLRQꢀIRUꢀPRUHꢀLQIRUPDWLRQꢁꢀ7KHꢀ$V\QFKURQRXVꢀ5HDGꢀDQGꢀ6\QFKURꢃ
QRXVꢒ%XUVWꢀ5HDGꢀWDEOHVꢀSURYLGHꢀWKHꢀUHDGꢀSDUDPHWHUVꢂꢀDQGꢀ)LJXUHꢀꢊꢋꢂꢀRQꢀSDJHꢀꢏꢐꢀDQGꢀ)LJXUHꢀꢊꢑꢂꢀ
RQꢀSDJHꢀꢈꢉꢀVKRZꢀWKHꢀWLPLQJVꢁ
Set Configuration Register Command Sequence
7KHꢀGHYLFHꢀXVHVꢀDꢀFRQILJXUDWLRQꢀUHJLVWHUꢀWRꢀVHWꢀWKHꢀYDULRXVꢀEXUVWꢀSDUDPHWHUVꢄꢀQXPEHUꢀRIꢀZDLWꢀ
VWDWHVꢂꢀEXUVWꢀUHDGꢀPRGHꢂꢀ5'<ꢀFRQILJXUDWLRQꢂꢀDQGꢀV\QFKURQRXVꢀPRGHꢀDFWLYHꢁꢀ7KHꢀFRQILJXUDWLRQꢀUHJꢃ
LVWHUꢀPXVWꢀEHꢀVHWꢀEHIRUHꢀWKHꢀGHYLFHꢀZLOOꢀHQWHUꢀEXUVWꢀPRGHꢁ
7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀLVꢀORDGHGꢀZLWKꢀDꢀIRXUꢃF\FOHꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀILUVWꢀWZRꢀF\FOHVꢀDUHꢀ
VWDQGDUGꢀXQORFNꢀVHTXHQFHVꢁꢀ2QꢀWKHꢀWKLUGꢀF\FOHꢂꢀWKHꢀGDWDꢀVKRXOGꢀEHꢀ'ꢉKꢀDQGꢀDGGUHVVꢀELWVꢀVKRXOGꢀ
EHꢀꢍꢍꢍKꢁꢀ'XULQJꢀWKHꢀIRXUWKꢀF\FOHꢂꢀWKHꢀFRQILJXUDWLRQꢀFRGHꢀVKRXOGꢀEHꢀHQWHUHGꢀRQWRꢀWKHꢀGDWDꢀEXVꢀZLWKꢀ
WKHꢀDGGUHVVꢀEXVꢀVHWꢀWRꢀDGGUHVVꢀꢉꢉꢉKꢁꢀ2QFHꢀWKHꢀGDWDꢀKDVꢀEHHQꢀSURJUDPPHGꢀLQWRꢀWKHꢀFRQILJXUDWLRQꢀ
UHJLVWHUꢂꢀDꢀVRIWZDUHꢀUHVHWꢀFRPPDQGꢀLVꢀUHTXLUHGꢀWRꢀVHWꢀWKHꢀGHYLFHꢀLQWRꢀWKHꢀFRUUHFWꢀVWDWHꢁꢀ7KHꢀGHYLFHꢀ
ZLOOꢀSRZHUꢀXSꢀRUꢀDIWHUꢀDꢀKDUGZDUHꢀUHVHWꢀZLWKꢀWKHꢀGHIDXOWꢀVHWWLQJꢂꢀZKLFKꢀLVꢀLQꢀDV\QFKURQRXVꢀPRGHꢁꢀ
7KHꢀUHJLVWHUꢀPXVWꢀEHꢀVHWꢀEHIRUHꢀWKHꢀGHYLFHꢀFDQꢀHQWHUꢀV\QFKURQRXVꢀPRGHꢁꢀ7KHꢀFRQILJXUDWLRQꢀUHJꢃ
LVWHUꢀFDQꢀQRWꢀEHꢀFKDQJHGꢀGXULQJꢀGHYLFHꢀRSHUDWLRQVꢀꢅSURJUDPꢂꢀHUDVHꢂꢀRUꢀVHFWRUꢀORFNꢆꢁ
Read Configuration Register Command Sequence
7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀFDQꢀEHꢀUHDGꢀZLWKꢀDꢀIRXUꢃF\FOHꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀILUVWꢀWZRꢀF\FOHVꢀ
DUHꢀVWDQGDUGꢀXQORFNꢀVHTXHQFHVꢁꢀ2QꢀWKHꢀWKLUGꢀF\FOHꢂꢀWKHꢀGDWDꢀVKRXOGꢀEHꢀ&ꢇKꢀDQGꢀDGGUHVVꢀELWVꢀ
VKRXOGꢀEHꢀꢍꢍꢍKꢁꢀ'XULQJꢀWKHꢀIRXUWKꢀF\FOHꢂꢀWKHꢀFRQILJXUDWLRQꢀFRGHꢀVKRXOGꢀEHꢀUHDGꢀRXWꢀRIꢀWKHꢀGDWDꢀ
EXVꢀZLWKꢀWKHꢀDGGUHVVꢀEXVꢀVHWꢀWRꢀDGGUHVVꢀꢉꢉꢉKꢁꢀ2QFHꢀWKHꢀGDWDꢀKDVꢀEHHQꢀUHDGꢀIURPꢀWKHꢀFRQILJXUDWLRQꢀ
UHJLVWHUꢂꢀDꢀVRIWZDUHꢀUHVHWꢀFRPPDQGꢀLVꢀUHTXLUHGꢀWRꢀVHWꢀWKHꢀGHYLFHꢀLQWRꢀWKHꢀFRUUHFWꢀVHWꢀPRGHꢁ
44
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
5HDGꢀ0RGHꢀ6HWWLQJ
2QꢀSRZHUꢃXSꢀRUꢀKDUGZDUHꢀUHVHWꢂꢀWKHꢀGHYLFHꢀLVꢀVHWꢀWRꢀEHꢀLQꢀDV\QFKURQRXVꢀUHDGꢀPRGHꢁꢀ7KLVꢀVHWWLQJꢀ
DOORZVꢀWKHꢀV\VWHPꢀWRꢀHQDEOHꢀRUꢀGLVDEOHꢀEXUVWꢀPRGHꢀGXULQJꢀV\VWHPꢀRSHUDWLRQVꢁꢀ
3URJUDPPDEOHꢀ:DLWꢀ6WDWHꢀ&RQILJXUDWLRQ
7KHꢀSURJUDPPDEOHꢀZDLWꢀVWDWHꢀIHDWXUHꢀLQIRUPVꢀWKHꢀGHYLFHꢀRIꢀWKHꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀWKDWꢀPXVWꢀ
HODSVHꢀDIWHUꢀ$9'ꢓꢀLVꢀGULYHQꢀDFWLYHꢀEHIRUHꢀGDWDꢀZLOOꢀEHꢀDYDLODEOHꢁꢀ7KLVꢀYDOXHꢀLVꢀGHWHUPLQHGꢀE\ꢀWKHꢀ
LQSXWꢀIUHTXHQF\ꢀRIꢀWKHꢀGHYLFHꢁꢀ&RQILJXUDWLRQꢀ%LWꢀ&5ꢄꢏ±&5ꢄꢄꢀGHWHUPLQHꢀWKHꢀVHWWLQJꢀꢅVHHꢀ7DEOHꢀ
ꢌꢉꢆꢁ
7KHꢀZDLWꢀVWDWHꢀFRPPDQGꢀVHTXHQFHꢀLQVWUXFWVꢀWKHꢀGHYLFHꢀWRꢀVHWꢀDꢀSDUWLFXODUꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀ
IRUꢀWKHꢀLQLWLDOꢀDFFHVVꢀLQꢀEXUVWꢀPRGHꢁꢀ7KHꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀWKDWꢀVKRXOGꢀEHꢀSURJUDPPHGꢀLQWRꢀ
WKHꢀGHYLFHꢀLVꢀGLUHFWO\ꢀUHODWHGꢀWRꢀWKHꢀFORFNꢀIUHTXHQF\ꢁ
Table 20. Programmable Wait State Settings
7RWDOꢀ,QLWLDOꢀ$FFHVVꢀ
&5ꢄꢏ
&5ꢄꢉꢀ
&5ꢄꢄ
&\FOHV
ꢉ
ꢉ
ꢉ
ꢉ
ꢊ
ꢊ
ꢊ
ꢊ
ꢉ
ꢉ
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ꢊ
ꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢊ
ꢉ
ꢊ
ꢉ
ꢊ
ꢉ
ꢊ
ꢌ
ꢋ
ꢑ
ꢍ
ꢇ
ꢏꢀꢅGHIDXOWꢆ
5HVHUYHG
5HVHUYHG
1RWHVꢀ
ꢀꢁ 8SRQꢂSRZHUꢉXSꢂRUꢂKDUGZDUHꢂUHVHWꢇꢂWKHꢂGHIDXOWꢂVHWWLQJꢂLVꢂVHYHQꢂZDLWꢂVWDWHVꢁ
ꢄꢁ 5'<ꢂZLOOꢂGHIDXOWꢂWRꢂEHLQJꢂDFWLYHꢂZLWKꢂGDWDꢂZKHQꢂWKHꢂ:DLWꢂ6WDWHꢂ6HWWLQJꢂLVꢂVHWꢂWRꢂDꢂ
WRWDOꢂLQLWLDOꢂDFFHVVꢂF\FOHꢂRIꢂꢄꢁ
,WꢀLVꢀUHFRPPHQGHGꢀWKDWꢀWKHꢀZDLWꢀVWDWHꢀFRPPDQGꢀVHTXHQFHꢀEHꢀZULWWHQꢂꢀHYHQꢀLIꢀWKHꢀGHIDXOWꢀZDLWꢀ
VWDWHꢀYDOXHꢀLVꢀGHVLUHGꢂꢀWRꢀHQVXUHꢀWKHꢀGHYLFHꢀLVꢀVHWꢀDVꢀH[SHFWHGꢁꢀ$ꢀKDUGZDUHꢀUHVHWꢀZLOOꢀVHWꢀWKHꢀZDLWꢀ
VWDWHꢀWRꢀWKHꢀGHIDXOWꢀVHWWLQJꢁ
3URJUDPPDEOHꢀ:DLWꢀ6WDWH
7KHꢀKRVWꢀV\VWHPꢀVKRXOGꢀVHWꢀ&5ꢄꢏꢒ&5ꢄꢄꢀWRꢀꢊꢉꢊꢒꢊꢉꢉꢒꢉꢊꢊꢀIRUꢀDꢀFORFNꢀIUHTXHQF\ꢀRIꢀꢈꢉꢒꢇꢇꢀ0+]ꢀIRUꢀ
WKHꢀV\VWHPꢒGHYLFHꢀWRꢀH[HFXWHꢀDWꢀPD[LPXPꢀVSHHGꢁ
7DEOHꢀꢌꢊꢀRQꢀSDJHꢀꢑꢍꢀGHVFULEHVꢀWKHꢀW\SLFDOꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀꢅZDLWꢀVWDWHVꢆꢀIRUꢀYDULRXVꢀ
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Table 21. Wait States for Handshaking
7\SLFDOꢀ1RꢅꢀRIꢀ&ORFNꢀ&\FOHVꢀDIWHUꢀ$9'ꢑꢀ/RZ
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
45
A d v a n c e I n f o r m a t i o n
+DQGVKDNLQJ
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VWDWHVꢀLQꢀWKHꢀIODVKꢀGHYLFHꢀGHSHQGLQJꢀRQꢀWKHꢀFORFNꢀIUHTXHQF\ꢁ
7KHꢀDXWRVHOHFWꢀIXQFWLRQꢀDOORZVꢀWKHꢀKRVWꢀV\VWHPꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀWKHꢀIODVKꢀGHYLFHꢀLVꢀHQDEOHGꢀ
IRUꢀKDQGVKDNLQJꢁ
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7KHꢀGHYLFHꢀVXSSRUWVꢀIRXUꢀGLIIHUHQWꢀUHDGꢀPRGHVꢄꢀFRQWLQXRXVꢀPRGHꢂꢀDQGꢀꢈꢂꢀꢊꢇꢂꢀDQGꢀꢋꢌꢀZRUGꢀOLQHDUꢀ
ZLWKꢀRUꢀZLWKRXWꢀZUDSꢀDURXQGꢀPRGHVꢁꢀ$ꢀFRQWLQXRXVꢀVHTXHQFHꢀꢅGHIDXOWꢆꢀEHJLQVꢀDWꢀWKHꢀVWDUWLQJꢀDGꢃ
GUHVVꢀDQGꢀDGYDQFHVꢀWKHꢀDGGUHVVꢀSRLQWHUꢀXQWLOꢀWKHꢀEXUVWꢀRSHUDWLRQꢀLVꢀFRPSOHWHꢁꢀ,IꢀWKHꢀKLJKHVWꢀ
DGGUHVVꢀLQꢀWKHꢀGHYLFHꢀLVꢀUHDFKHGꢀGXULQJꢀWKHꢀFRQWLQXRXVꢀEXUVWꢀUHDGꢀPRGHꢂꢀWKHꢀDGGUHVVꢀSRLQWHUꢀ
ZUDSVꢀDURXQGꢀWRꢀWKHꢀORZHVWꢀDGGUHVVꢁꢀ
)RUꢀH[DPSOHꢂꢀDQꢀHLJKWꢃZRUGꢀOLQHDUꢀUHDGꢀZLWKꢀZUDSꢀDURXQGꢀEHJLQVꢀRQꢀWKHꢀVWDUWLQJꢀDGGUHVVꢀZULWWHQꢀ
WRꢀWKHꢀGHYLFHꢀDQGꢀWKHQꢀDGYDQFHVꢀWRꢀWKHꢀQH[WꢀꢈꢀZRUGꢀERXQGDU\ꢁꢀ7KHꢀDGGUHVVꢀSRLQWHUꢀWKHQꢀUHWXUQVꢀ
WRꢀWKHꢀꢊVWꢀZRUGꢀDIWHUꢀWKHꢀSUHYLRXVꢀHLJKWꢀZRUGꢀERXQGDU\ꢂꢀZUDSSLQJꢀWKURXJKꢀWKHꢀVWDUWLQJꢀORFDWLRQꢁꢀ
7KHꢀVL[WHHQꢃꢀDQGꢀWKLUW\ꢃWZRꢀOLQHDUꢀZUDSꢀDURXQGꢀPRGHVꢀRSHUDWHꢀLQꢀDꢀIDVKLRQꢀVLPLODUꢀWRꢀWKHꢀHLJKWꢃ
ZRUGꢀPRGHꢁꢀ
7DEOHꢀꢌꢌꢀVKRZVꢀWKHꢀ&5ꢉꢒ&5ꢍꢀDQGꢀVHWWLQJVꢀIRUꢀWKHꢀIRXUꢀUHDGꢀPRGHVꢁ
Table 22. Burst Length Configuration
$GGUHVVꢀ%LWV
%XUVWꢀ0RGHV
&RQWLQXRXV
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ꢈꢃZRUGꢀOLQHDU
ꢊꢇꢃZRUGꢀOLQHDU
ꢋꢌꢃZRUGꢀOLQHDU
1RWHVꢀ
ꢀꢁ 8SRQꢂSRZHUꢉXSꢂRUꢂKDUGZDUHꢂUHVHWꢂWKHꢂGHIDXOWꢂVHWWLQJꢂLVꢂFRQWLQXRXVꢁ
ꢄꢁ $OOꢂRWKHUꢂFRQGLWLRQVꢂDUHꢂUHVHUYHGꢁ
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5'<ꢀ&RQILJXUDWLRQꢀ
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WKHꢀRXWSXWVꢁꢀ7KHꢀGHYLFHꢀFDQꢀEHꢀVHWꢀVRꢀWKDWꢀ5'<ꢀJRHVꢀDFWLYHꢀRQHꢀGDWDꢀF\FOHꢀEHIRUHꢀDFWLYHꢀGDWDꢁꢀ&5ꢊ
GHWHUPLQHVꢀWKLVꢀVHWWLQJꢕꢀ³ꢊ´ꢀIRUꢀ5'<ꢀDFWLYHꢀꢅGHIDXOWꢆꢀZLWKꢀGDWDꢂꢀ³ꢉ´ꢀIRUꢀ5'<ꢀDFWLYHꢀRQHꢀFORFNꢀF\FOHꢀ
EHIRUHꢀYDOLGꢀGDWDꢁ
5'<ꢀ3RODULW\ꢀ
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ZLWKꢀ&5ꢄꢍꢀVHWꢀWRꢀDꢀµꢊ¶ꢁꢀ,QꢀWKLVꢀFDVHꢂꢀWKHꢀ5'<ꢀSLQꢀLVꢀDFWLYHꢀKLJKꢁꢀ&KDQJLQJꢀWKHꢀ&5ꢄꢍꢀWRꢀDꢀµꢉ¶ꢀVHWVꢀ
WKHꢀ5'<ꢀSLQꢀWRꢀEHꢀDFWLYHꢀORZꢁꢀ,QꢀWKLVꢀFDVHꢂꢀWKHꢀ5'<ꢀSLQꢀZLOOꢀDOZD\VꢀLQGLFDWHꢀWKDWꢀWKHꢀGHYLFHꢀLVꢀUHDG\ꢀ
WRꢀKDQGOHꢀDꢀQHZꢀWUDQVDFWLRQꢀZKHQꢀORZꢁ
46
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Configuration Register
7DEOHꢀꢌꢋꢀVKRZVꢀWKHꢀDGGUHVVꢀELWVꢀWKDWꢀGHWHUPLQHꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀVHWWLQJVꢀ
IRUꢀYDULRXVꢀGHYLFHꢀIXQFWLRQVꢁ
Table 23. Configuration Register
&5ꢀ%,W
&5ꢊꢍ
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)XQFWLRQꢀ
5HVHUYHG
5HVHUYHG
6HWWLQJVꢀꢂ%LQDU\ꢃ
ꢉꢀ ꢀ'HIDXOW
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Reset Command
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
47
A d v a n c e I n f o r m a t i o n
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48
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Autoselect Command Sequence
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Table 24. Device ID
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Enter Secured Silicon Sector/Exit Secured Silicon Sector Command
Sequence
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
49
A d v a n c e I n f o r m a t i o n
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DGGUHVVꢀDQGꢀGDWDꢀUHTXLUHPHQWVꢀIRUꢀERWKꢀFRPPDQGꢀVHTXHQFHVꢁꢀ
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7KHꢀXQORFNꢀE\SDVVꢀIHDWXUHꢀDOORZVꢀWKHꢀV\VWHPꢀWRꢀSURJUDPꢀIDVWHUꢀWKDQꢀWKHꢀVWDQGDUGꢀSURJUDPꢀFRPꢃ
PDQGꢀVHTXHQFHꢁꢀ7KHꢀXQORFNꢀE\SDVVꢀFRPPDQGꢀVHTXHQFHꢀLVꢀLQLWLDWHGꢀE\ꢀILUVWꢀZULWLQJꢀWZRꢀXQORFNꢀ
F\FOHVꢁꢀ7KLVꢀLVꢀIROORZHGꢀE\ꢀDꢀWKLUGꢀZULWHꢀF\FOHꢀFRQWDLQLQJꢀWKHꢀXQORFNꢀE\SDVVꢀFRPPDQGꢂꢀꢌꢉKꢁꢀ7KDWꢀ
EDQNꢀWKHQꢀHQWHUVꢀWKHꢀXQORFNꢀE\SDVVꢀPRGHꢁꢀ
'XULQJꢀWKHꢀXQORFNꢀE\SDVVꢀPRGHꢀRQO\ꢀWKHꢀFRPPDQGꢀLVꢀYDOLGꢁꢀ7RꢀH[LWꢀWKHꢀXQORFNꢀE\SDVVꢀPRGHꢂꢀWKHꢀ
V\VWHPꢀPXVWꢀLVVXHꢀWKHꢀWZRꢃF\FOHꢀXQORFNꢀE\SDVVꢀUHVHWꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀILUVWꢀF\FOHꢀPXVWꢀ
FRQWDLQꢀWKHꢀEDQNꢀDGGUHVVꢀDQGꢀWKHꢀGDWDꢀꢐꢉKꢁꢀ7KHꢀVHFRQGꢀF\FOHꢀQHHGꢀRQO\ꢀFRQWDLQꢀWKHꢀGDWDꢀꢉꢉKꢁꢀ7KHꢀ
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Program Command Sequence
3URJUDPꢀ&RPPDQGꢀ6HTXHQFH
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GDWDꢀDUHꢀZULWWHQꢀQH[WꢂꢀZKLFKꢀLQꢀWXUQꢀLQLWLDWHꢀWKHꢀ(PEHGGHGꢀ3URJUDPꢀDOJRULWKPꢁꢀ7KHꢀV\VWHPꢀLVꢀQRW
UHTXLUHGꢀWRꢀSURYLGHꢀIXUWKHUꢀFRQWUROVꢀRUꢀWLPLQJVꢁꢀ7KHꢀGHYLFHꢀDXWRPDWLFDOO\ꢀSURYLGHVꢀLQWHUQDOO\ꢀJHQꢃ
HUDWHGꢀSURJUDPꢀSXOVHVꢀDQGꢀYHULILHVꢀWKHꢀSURJUDPPHGꢀFHOOꢀPDUJLQꢁꢀ7DEOHꢀꢀRQꢀSDJHꢀꢇꢌꢀVKRZVꢀWKHꢀ
DGGUHVVꢀDQGꢀGDWDꢀUHTXLUHPHQWVꢀIRUꢀWKHꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢁ
:KHQꢀWKHꢀ(PEHGGHGꢀ3URJUDPꢀDOJRULWKPꢀLVꢀFRPSOHWHꢂꢀWKDWꢀEDQNꢀWKHQꢀUHWXUQVꢀWRꢀWKHꢀUHDGꢀPRGHꢀ
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FRPPDQGꢀVHTXHQFHVꢁ
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50
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
)LJXUHꢀꢊꢀLOOXVWUDWHVꢀWKHꢀDOJRULWKPꢀIRUꢀWKHꢀSURJUDPꢀRSHUDWLRQꢁꢀ5HIHUꢀWRꢀWKHꢀ(UDVHꢒ3URJUDPꢀ2SHUDꢃ
WLRQVꢀWDEOHꢀLQꢀWKHꢀ$&ꢀ&KDUDFWHULVWLFVꢀVHFWLRQꢀIRUꢀSDUDPHWHUVꢂꢀDQGꢀ)LJXUHꢀꢊꢇꢂꢀRQꢀSDJHꢀꢈꢋꢀIRUꢀWLPLQJꢀ
GLDJUDPVꢁ
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
1RWHꢀꢁ6HHꢁ7DEOHꢁꢁIRUꢁSURJUDPꢁFRPPDQGꢁVHTXHQFHꢂ
Figure 1. Program Operation
Write Buffer Programming Command Sequence
:ULWHꢀ%XIIHUꢀ3URJUDPPLQJꢀ6HTXHQFHꢀDOORZVꢀIRUꢀIDVWHUꢀSURJUDPPLQJꢀDVꢀFRPSDUHGꢀWRꢀWKHꢀVWDQGDUGꢀ
3URJUDPꢀ&RPPDQGꢀ6HTXHQFHꢁꢀ6HHꢀ7DEOHꢀꢌꢍꢀRQꢀSDJHꢀꢍꢌꢀIRUꢀWKHꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
51
A d v a n c e I n f o r m a t i o n
Table 25. Write Buffer Command Sequence
6HTXHQFH
8QORFNꢀ&RPPDQGꢀꢊ
8QORFNꢀ&RPPDQGꢀꢌ
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52
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ15 - DQ0 at
Last Loaded Address
Yes
DQ7 and DQ15 = Data?
No
No
No
DQ1 = 1?
Yes
DQ5 and DQ13 = 1?
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
Yes
DQ7 and DQ15 = Data?
No
FAIL or ABORT
PASS
Figure 2. Write Buffer Programming Operation
Chip Erase Command Sequence
&KLSꢀ(UDVHꢀ&RPPDQGꢀ6HTXHQFH
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
53
A d v a n c e I n f o r m a t i o n
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Sector Erase Command Sequence
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54
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
55
A d v a n c e I n f o r m a t i o n
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S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
57
A d v a n c e I n f o r m a t i o n
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Non-Volatile Sector Protection Command Set Definitions
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58
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte.
Addr = SA0
Read Byte.
Addr = SA0
No
DQ6 =
Toggle?
Yes
DQ5 = 1?
Yes
Read Byte Twice.
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
Figure 4. PPB Program/Erase Algorithm
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
59
A d v a n c e I n f o r m a t i o n
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Global Volatile Sector Protection Freeze Command Set
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Volatile Sector Protection Command Set
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ꢅ'<%ꢆꢂꢀFOHDUꢀWKHꢀ'\QDPLFꢀ3URWHFWLRQꢀ%LWꢀꢅ'<%ꢆꢂꢀDQGꢀUHDGꢀWKHꢀORJLFꢀVWDWHꢀRIꢀWKHꢀ'\QDPLFꢀ3URWHFWLRQꢀ
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7KHꢀ9RODWLOHꢀ6HFWRUꢀ3URWHFWLRQꢀ&RPPDQGꢀ6HWꢀ(QWU\ꢀFRPPDQGꢀVHTXHQFHꢀPXVWꢀEHꢀLVVXHGꢀSULRUꢀ
WRꢀDQ\ꢀRIꢀWKHꢀFRPPDQGVꢀOLVWHGꢀIROORZLQJꢀWRꢀHQDEOHꢀSURSHUꢀFRPPDQGꢀH[HFXWLRQꢁ
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60
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
7KHꢀ'<%ꢀ6HWꢒ&OHDUꢀFRPPDQGꢀLVꢀXVHGꢀWRꢀVHWꢀRUꢀFOHDUꢀDꢀ'<%ꢀIRUꢀDꢀJLYHQꢀVHFWRUꢁꢀ7KHꢀKLJKꢀRUGHUꢀDGꢃ
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DVꢀWKHꢀFRGHꢀꢉꢉKꢀRUꢀꢉꢊKꢀRQꢀ'4ꢏꢃ'4ꢉꢁꢀ$OOꢀRWKHUꢀ'4ꢀGDWDꢀEXVꢀSLQVꢀDUHꢀLJQRUHGꢀGXULQJꢀWKHꢀGDWDꢀZULWHꢀ
F\FOHꢁꢀ7KHꢀ'<%VꢀDUHꢀPRGLILDEOHꢀDWꢀDQ\ꢀWLPHꢂꢀUHJDUGOHVVꢀRIꢀWKHꢀVWDWHꢀRIꢀWKHꢀ33%ꢀRUꢀ33%ꢀ/RFNꢀ%LWꢁꢀ
7KHꢀ'<%VꢀDUHꢀVHWꢀDWꢀSRZHUꢃXSꢀRUꢀKDUGZDUHꢀUHVHWꢁ
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&RPPDQGꢀWRꢀWKHꢀGHYLFHꢁ
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7KHꢀ9RODWLOHꢀ6HFWRUꢀ3URWHFWLRQꢀ&RPPDQGꢀ6HWꢀ([LWꢀFRPPDQGꢀPXVWꢀEHꢀLVVXHGꢀDIWHUꢀWKHꢀH[HFXꢃ
WLRQꢀRIꢀWKHꢀFRPPDQGVꢀOLVWHGꢀSUHYLRXVO\ꢀWRꢀUHVHWꢀWKHꢀGHYLFHꢀWRꢀUHDGꢀPRGHꢁ
1RWHꢀWKDWꢀLVVXLQJꢀWKHꢀ9RODWLOHꢀ6HFWRUꢀ3URWHFWLRQꢀ&RPPDQGꢀ6HWꢀ([LWꢀFRPPDQGꢀUHꢃHQDEOHVꢀ
UHDGVꢀDQGꢀZULWHVꢀIRUꢀWKHꢀEDQNꢀVHOHFWHGꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
61
A d v a n c e I n f o r m a t i o n
Table 26. Command Definitions (Sheet 1 of 3)
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62
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 26. Command Definitions (Sheet 2 of 3)
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
63
A d v a n c e I n f o r m a t i o n
Table 26. Command Definitions (Sheet 3 of 3)
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FKURQRXVO\ꢀZLWKꢀ'4ꢇ±'4ꢉꢀZKLOHꢀ2XWSXWꢀ(QDEOHꢀꢅ2(ꢓꢆꢀLVꢀDVVHUWHGꢀORZꢁꢀ7KDWꢀLVꢂꢀWKHꢀGHYLFHꢀPD\ꢀ
FKDQJHꢀIURPꢀSURYLGLQJꢀVWDWXVꢀLQIRUPDWLRQꢀWRꢀYDOLGꢀGDWDꢀRQꢀ'4ꢏꢁꢀ'HSHQGLQJꢀRQꢀZKHQꢀWKHꢀV\VWHPꢀ
VDPSOHVꢀWKHꢀ'4ꢏꢀRXWSXWꢂꢀLWꢀPD\ꢀUHDGꢀWKHꢀVWDWXVꢀRUꢀYDOLGꢀGDWDꢁꢀ(YHQꢀLIꢀWKHꢀGHYLFHꢀKDVꢀFRPSOHWHGꢀ
WKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢀDQGꢀ'4ꢏꢀKDVꢀYDOLGꢀGDWDꢂꢀWKHꢀGDWDꢀRXWSXWVꢀRQꢀ'4ꢇ±'4ꢉꢀPD\ꢀEHꢀ
VWLOOꢀLQYDOLGꢁꢀ9DOLGꢀGDWDꢀRQꢀ'4ꢏ±'4ꢉꢀZLOOꢀDSSHDUꢀRQꢀVXFFHVVLYHꢀUHDGꢀF\FOHVꢁ
7DEOHꢀꢌꢈꢀRQꢀSDJHꢀꢏꢌꢀVKRZVꢀWKHꢀRXWSXWVꢀIRUꢀ'DWDꢓꢀ3ROOLQJꢀRQꢀ'4ꢏꢁꢀ)LJXUHꢀꢍꢂꢀRQꢀSDJHꢀꢇꢏꢀVKRZVꢀWKHꢀ
'DWDꢓꢀ3ROOLQJꢀDOJRULWKPꢁꢀ)LJXUHꢀꢊꢐꢂꢀRQꢀSDJHꢀꢈꢇꢀLQꢀWKHꢀ$&ꢀ&KDUDFWHULVWLFVꢀVHFWLRQꢀVKRZVꢀWKHꢀ'DWDꢓꢀ
3ROOLQJꢀWLPLQJꢀGLDJUDPꢁ
66
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
1RWHVꢀ
ꢀꢁ 9$ꢂ ꢂ9DOLGꢂDGGUHVVꢂIRUꢂSURJUDPPLQJꢁꢂ'XULQJꢂDꢂ
VHFWRUꢂHUDVHꢂRSHUDWLRQꢇꢂDꢂYDOLGꢂDGGUHVVꢂLVꢂDQ\ꢂVHFWRUꢂ
DGGUHVVꢂZLWKLQꢂWKHꢂVHFWRUꢂEHLQJꢂHUDVHGꢁꢂ'XULQJꢂFKLSꢂ
HUDVHꢇꢂDꢂYDOLGꢂDGGUHVVꢂLVꢂDQ\ꢂQRQꢉSURWHFWHGꢂVHFWRUꢂ
DGGUHVVꢁ
ꢄꢁ '4ꢒꢂVKRXOGꢂEHꢂUHFKHFNHGꢂHYHQꢂLIꢂ'4ꢊꢂ ꢂ³ꢀ´ꢂEHFDXVHꢂ
'4ꢒꢂPD\ꢂFKDQJHꢂVLPXOWDQHRXVO\ꢂZLWKꢂ'4ꢊꢁ
Figure 5. Data# Polling Algorithm
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
67
A d v a n c e I n f o r m a t i o n
RDY: Ready
7KHꢀ5'<ꢀSLQꢀLVꢀDꢀGHGLFDWHGꢀVWDWXVꢀRXWSXWꢀWKDWꢀLQGLFDWHVꢀYDOLGꢀRXWSXWꢀGDWDꢀRQꢀ$ꢒ'4ꢊꢍ±$ꢒ'4ꢉꢀGXUꢃ
LQJꢀEXUVWꢀꢅV\QFKURQRXVꢆꢀUHDGVꢁꢀ:KHQꢀ5'<ꢀLVꢀDVVHUWHGꢀꢅ5'<ꢀ ꢀ92+ꢆꢂꢀWKHꢀRXWSXWꢀGDWDꢀLVꢀYDOLGꢀDQGꢀ
FDQꢀEHꢀUHDGꢁꢀ:KHQꢀ5'<ꢀLVꢀGHꢃDVVHUWHGꢀꢅ5'<ꢀ ꢀ92/ꢆꢂꢀWKHꢀV\VWHPꢀVKRXOGꢀZDLWꢀXQWLOꢀ5'<ꢀLVꢀUHꢃDVꢃ
VHUWHGꢀEHIRUHꢀH[SHFWLQJꢀWKHꢀQH[WꢀZRUGꢀRIꢀGDWDꢁ
,QꢀV\QFKURQRXVꢀꢅEXUVWꢆꢀPRGHꢀZLWKꢀ&(ꢓꢀ ꢀ2(ꢓꢀ ꢀ9,/ꢂꢀ5'<ꢀLVꢀGHꢃDVVHUWHGꢀXQGHUꢀWKHꢀIROORZLQJꢀFRQꢃ
GLWLRQVꢄꢀGXULQJꢀWKHꢀLQLWLDOꢀDFFHVVꢕꢀDIWHUꢀFURVVLQJꢀWKHꢀLQWHUQDOꢀERXQGDU\ꢀEHWZHHQꢀDGGUHVVHVꢀꢏ(KꢀDQGꢀ
ꢏ)KꢀꢅDQGꢀDGGUHVVHVꢀRIIVHWꢀIURPꢀWKHVHꢀE\ꢀDꢀPXOWLSOHꢀRIꢀꢇꢑꢆꢁꢀ7KHꢀ5'<ꢀSLQꢀZLOOꢀDOVRꢀVZLWFKꢀGXULQJꢀ
VWDWXVꢀUHDGVꢀZKHQꢀDꢀFORFNꢀVLJQDOꢀGULYHVꢀWKHꢀ&/.ꢀLQSXWꢁꢀ,QꢀDGGLWLRQꢂꢀ5'<ꢀ ꢀ92+ꢀZKHQꢀ&(ꢓꢀ ꢀ9,/
DQGꢀ2(ꢓꢀ ꢀ9,+ꢂꢀDQGꢀ5'<ꢀLVꢀ+Lꢃ=ꢀZKHQꢀ&(ꢓꢀ ꢀ9,+
,QꢀDV\QFKURQRXVꢀꢅQRQꢃEXUVWꢆꢀPRGHꢂꢀWKHꢀ5'<ꢀSLQꢀGRHVꢀQRWꢀLQGLFDWHꢀYDOLGꢀRUꢀLQYDOLGꢀRXWSXWꢀGDWDꢁꢀ
,QVWHDGꢂꢀ5'<ꢀ ꢀ92+ꢀZKHQꢀ&(ꢓꢀ ꢀ9,/ꢂꢀDQGꢀ5'<ꢀLVꢀ+Lꢃ=ꢀZKHQꢀ&(ꢓꢀ ꢀ9,+
ꢁ
ꢁ
DQ6: Toggle Bit I
7RJJOHꢀ%LWꢀ,ꢀRQꢀ'4ꢇꢀLQGLFDWHVꢀZKHWKHUꢀDQꢀ(PEHGGHGꢀ3URJUDPꢀRUꢀ(UDVHꢀDOJRULWKPꢀLVꢀLQꢀSURJUHVVꢀRUꢀ
FRPSOHWHꢂꢀRUꢀZKHWKHUꢀWKHꢀGHYLFHꢀKDVꢀHQWHUHGꢀWKHꢀ(UDVHꢀ6XVSHQGꢀPRGHꢁꢀ7RJJOHꢀ%LWꢀ,ꢀPD\ꢀEHꢀUHDGꢀ
DWꢀDQ\ꢀDGGUHVVꢀLQꢀWKHꢀVDPHꢀEDQNꢂꢀDQGꢀLVꢀYDOLGꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀWKHꢀ
FRPPDQGꢀVHTXHQFHꢀꢅSULRUꢀWRꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢆꢂꢀDQGꢀGXULQJꢀWKHꢀVHFWRUꢀHUDVHꢀWLPHꢃ
RXWꢁ
'XULQJꢀDQꢀ(PEHGGHGꢀ3URJUDPꢀRUꢀ(UDVHꢀDOJRULWKPꢀRSHUDWLRQꢂꢀVXFFHVVLYHꢀUHDGꢀF\FOHVꢀWRꢀDQ\ꢀDGꢃ
GUHVVꢀFDXVHꢀ'4ꢇꢀWRꢀWRJJOHꢁꢀ1RWHꢀWKDWꢀ2(ꢓꢀPXVWꢀEHꢀORZꢀGXULQJꢀWRJJOHꢀELWꢀVWDWXVꢀUHDGVꢁꢀ:KHQꢀWKHꢀ
RSHUDWLRQꢀLVꢀFRPSOHWHꢂꢀ'4ꢇꢀVWRSVꢀWRJJOLQJꢁ
$IWHUꢀDQꢀHUDVHꢀFRPPDQGꢀVHTXHQFHꢀLVꢀZULWWHQꢂꢀLIꢀDOOꢀVHFWRUVꢀVHOHFWHGꢀIRUꢀHUDVLQJꢀDUHꢀSURWHFWHGꢂꢀ'4ꢇꢀ
WRJJOHVꢀIRUꢀDSSUR[LPDWHO\ꢀW$63ꢂꢀDOOꢀVHFWRUVꢀSURWHFWHGꢀWRJJOHꢀWLPHꢂꢀWKHQꢀUHWXUQVꢀWRꢀUHDGLQJꢀDUUD\ꢀ
GDWDꢁꢀ,IꢀQRWꢀDOOꢀVHOHFWHGꢀVHFWRUVꢀDUHꢀSURWHFWHGꢂꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀHUDVHVꢀWKHꢀXQSURꢃ
WHFWHGꢀVHFWRUVꢂꢀDQGꢀLJQRUHVꢀWKHꢀVHOHFWHGꢀVHFWRUVꢀWKDWꢀDUHꢀSURWHFWHGꢁꢀ
7KHꢀV\VWHPꢀFDQꢀXVHꢀ'4ꢇꢀDQGꢀ'4ꢌꢀWRJHWKHUꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀDꢀVHFWRUꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀRUꢀ
LVꢀHUDVHꢃVXVSHQGHGꢁꢀ:KHQꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀꢅWKDWꢀLVꢂꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀ
LVꢀLQꢀSURJUHVVꢆꢂꢀ'4ꢇꢀWRJJOHVꢁꢀ:KHQꢀWKHꢀGHYLFHꢀHQWHUVꢀWKHꢀ(UDVHꢀ6XVSHQGꢀPRGHꢂꢀ'4ꢇꢀVWRSVꢀWRJꢃ
JOLQJꢁꢀ+RZHYHUꢂꢀWKHꢀV\VWHPꢀPXVWꢀDOVRꢀXVHꢀ'4ꢌꢀWRꢀGHWHUPLQHꢀZKLFKꢀVHFWRUVꢀDUHꢀHUDVLQJꢀRUꢀHUDVHꢃ
VXVSHQGHGꢁꢀ$OWHUQDWLYHO\ꢂꢀWKHꢀV\VWHPꢀFDQꢀXVHꢀ'4ꢏꢀꢅVHHꢀWKHꢀVXEVHFWLRQꢀRQꢀ'4ꢏꢄꢀ'DWDꢓꢀ3ROOLQJꢆꢁ
,IꢀDꢀSURJUDPꢀDGGUHVVꢀIDOOVꢀZLWKLQꢀDꢀSURWHFWHGꢀVHFWRUꢂꢀ'4ꢇꢀWRJJOHVꢀIRUꢀDSSUR[LPDWHO\ꢀW363ꢀDIWHUꢀWKHꢀ
SURJUDPꢀFRPPDQGꢀVHTXHQFHꢀLVꢀZULWWHQꢂꢀWKHQꢀUHWXUQVꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢁ
'4ꢇꢀDOVRꢀWRJJOHVꢀGXULQJꢀWKHꢀHUDVHꢃVXVSHQGꢃSURJUDPꢀPRGHꢂꢀDQGꢀVWRSVꢀWRJJOLQJꢀRQFHꢀWKHꢀ(PEHGꢃ
GHGꢀ3URJUDPꢀDOJRULWKPꢀLVꢀFRPSOHWHꢁ
6HHꢀWKHꢀIROORZLQJꢀIRUꢀDGGLWLRQDOꢀLQIRUPDWLRQꢄꢀꢅWRJJOHꢀELWꢀIORZFKDUWꢆꢂꢀ'4ꢇꢄꢀ7RJJOHꢀ%LWꢀ,ꢀꢅGHVFULSꢃ
WLRQꢆꢂꢀꢌꢉꢀꢅWRJJOHꢀELWꢀWLPLQJꢀGLDJUDPꢆꢂꢀDQGꢀ7DEOHꢀꢌꢏꢀRQꢀSDJHꢀꢏꢉꢀꢅFRPSDUHVꢀ'4ꢌꢀDQGꢀ'4ꢇꢆꢁꢀ
DQ2: Toggle Bit II
7KHꢀ³7RJJOHꢀ%LWꢀ,,´ꢀRQꢀ'4ꢌꢂꢀZKHQꢀXVHGꢀZLWKꢀ'4ꢇꢂꢀLQGLFDWHVꢀZKHWKHUꢀDꢀSDUWLFXODUꢀVHFWRUꢀLVꢀDFWLYHO\ꢀ
HUDVLQJꢀꢅWKDWꢀLVꢂꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀLVꢀLQꢀSURJUHVVꢆꢂꢀRUꢀZKHWKHUꢀWKDWꢀVHFWRUꢀLVꢀHUDVHꢃ
VXVSHQGHGꢁꢀ7RJJOHꢀ%LWꢀ,,ꢀLVꢀYDOLGꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀWKHꢀFRPPDQGꢀ
VHTXHQFHꢁ
'4ꢌꢀWRJJOHVꢀZKHQꢀWKHꢀV\VWHPꢀUHDGVꢀDWꢀDGGUHVVHVꢀZLWKLQꢀWKRVHꢀVHFWRUVꢀWKDWꢀKDYHꢀEHHQꢀVHOHFWHGꢀ
IRUꢀHUDVXUHꢁꢀ1RWHꢀWKDWꢀ2(ꢓꢀPXVWꢀEHꢀORZꢀGXULQJꢀWRJJOHꢀELWꢀVWDWXVꢀUHDGVꢁꢀ%XWꢀ'4ꢌꢀFDQQRWꢀGLVWLQJXLVKꢀ
ZKHWKHUꢀWKHꢀVHFWRUꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀRUꢀLVꢀHUDVHꢃVXVSHQGHGꢁꢀ'4ꢇꢂꢀE\ꢀFRPSDULVRQꢂꢀLQGLFDWHVꢀ
ZKHWKHUꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢂꢀRUꢀLVꢀLQꢀ(UDVHꢀ6XVSHQGꢂꢀEXWꢀFDQQRWꢀGLVWLQJXLVKꢀZKLFKꢀVHFꢃ
68
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
WRUVꢀDUHꢀVHOHFWHGꢀIRUꢀHUDVXUHꢁꢀ7KXVꢂꢀERWKꢀVWDWXVꢀELWVꢀDUHꢀUHTXLUHGꢀIRUꢀVHFWRUꢀDQGꢀPRGHꢀLQIRUPDWLRQꢁꢀ
5HIHUꢀWRꢀ7DEOHꢀꢌꢈꢀRQꢀSDJHꢀꢏꢌꢀWRꢀFRPSDUHꢀRXWSXWVꢀIRUꢀ'4ꢌꢀDQGꢀ'4ꢇꢁꢀ
6HHꢀWKHꢀIROORZLQJꢀIRUꢀDGGLWLRQDOꢀLQIRUPDWLRQꢄꢀꢅWRJJOHꢀELWꢀIORZFKDUWꢆꢂꢀ'4ꢇꢄꢀ7RJJOHꢀ%LWꢀ,ꢀꢅGHVFULSꢃ
WLRQꢆꢂꢀꢌꢉꢀꢅWRJJOHꢀELWꢀWLPLQJꢀGLDJUDPꢆꢂꢀDQGꢀ7DEOHꢀꢌꢏꢀRQꢀSDJHꢀꢏꢉꢀꢅFRPSDUHVꢀ'4ꢌꢀDQGꢀ'4ꢇꢆꢁꢀ
START
Read Byte
DQ7-DQ0
Address = VA
Read Byte
DQ7-DQ0
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
DQ7-DQ0
Adrdess = VA
No
DQ6 = Toggle?
Yes
FAIL
PASS
1RWHꢀꢁ
7KHꢂV\VWHPꢂVKRXOGꢂUHFKHFNꢂWKHꢂWRJJOHꢂELWꢂHYHQꢂLIꢂ'4ꢊꢂ ꢂ
³ꢀ´ꢂEHFDXVHꢂWKHꢂWRJJOHꢂELWꢂPD\ꢂVWRSꢂWRJJOLQJꢂDVꢂ'4ꢊꢂ
FKDQJHVꢂWRꢂ³ꢀꢁ´ꢂ6HHꢂWKHꢂVXEVHFWLRQVꢂRQꢂ'4ꢌꢂDQGꢂ'4ꢄꢂ
IRUꢂPRUHꢂLQIRUPDWLRQꢁ
Figure 6. Toggle Bit Algorithm
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
69
A d v a n c e I n f o r m a t i o n
Table 27. DQ6 and DQ2 Indications
,IꢀGHYLFHꢀLV
DQGꢀWKHꢀV\VWHPꢀUHDGV
WKHQꢀ'4ꢋ
DQGꢀ'4ꢉ
SURJUDPPLQJꢂ
DWꢀDQ\ꢀDGGUHVVꢂ
WRJJOHVꢂ
GRHVꢀQRWꢀWRJJOHꢁ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀDꢀVHFWRUꢀ
VHOHFWHGꢀIRUꢀHUDVXUHꢂ
WRJJOHVꢂ
WRJJOHVꢂ
DOVRꢀWRJJOHVꢁ
GRHVꢀQRWꢀWRJJOHꢁ
WRJJOHVꢁ
DFWLYHO\ꢀHUDVLQJꢂ
HUDVHꢀVXVSHQGHGꢂ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀVHFWRUVꢀQRWꢀ
VHOHFWHGꢀIRUꢀHUDVXUHꢂ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀDꢀVHFWRUꢀ
VHOHFWHGꢀIRUꢀHUDVXUHꢂ
GRHVꢀQRWꢀWRJJOHꢂ
UHWXUQVꢀDUUD\ꢀGDWDꢂ
WRJJOHVꢂ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀVHFWRUVꢀQRWꢀ
UHWXUQVꢀDUUD\ꢀGDWDꢁꢀ7KHꢀV\VWHPꢀFDQꢀUHDGꢀ
IURPꢀDQ\ꢀVHFWRUꢀQRWꢀVHOHFWHGꢀIRUꢀHUDVXUHꢁ
VHOHFWHGꢀIRUꢀHUDVXUHꢂ
SURJUDPPLQJꢀLQꢀ
HUDVHꢀVXVSHQG
DWꢀDQ\ꢀDGGUHVVꢂ
LVꢀQRWꢀDSSOLFDEOHꢁ
Reading Toggle Bits DQ6/DQ2
:KHQHYHUꢀWKHꢀV\VWHPꢀLQLWLDOO\ꢀEHJLQVꢀUHDGLQJꢀWRJJOHꢀELWꢀVWDWXVꢂꢀLWꢀPXVWꢀUHDGꢀ'4ꢏ±'4ꢉꢀDWꢀOHDVWꢀ
WZLFHꢀLQꢀDꢀURZꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀDꢀWRJJOHꢀELWꢀLVꢀWRJJOLQJꢁꢀ7\SLFDOO\ꢂꢀWKHꢀV\VWHPꢀZRXOGꢀQRWHꢀDQGꢀ
VWRUHꢀWKHꢀYDOXHꢀRIꢀWKHꢀWRJJOHꢀELWꢀDIWHUꢀWKHꢀILUVWꢀUHDGꢁꢀ$IWHUꢀWKHꢀVHFRQGꢀUHDGꢂꢀWKHꢀV\VWHPꢀZRXOGꢀFRPꢃ
SDUHꢀWKHꢀQHZꢀYDOXHꢀRIꢀWKHꢀWRJJOHꢀELWꢀZLWKꢀWKHꢀILUVWꢁꢀ,IꢀWKHꢀWRJJOHꢀELWꢀLVꢀQRWꢀWRJJOLQJꢂꢀWKHꢀGHYLFHꢀKDVꢀ
FRPSOHWHGꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢁꢀ7KHꢀV\VWHPꢀFDQꢀUHDGꢀDUUD\ꢀGDWDꢀRQꢀ'4ꢏ±'4ꢉꢀRQꢀWKHꢀ
IROORZLQJꢀUHDGꢀF\FOHꢁ
+RZHYHUꢂꢀLIꢀDIWHUꢀWKHꢀLQLWLDOꢀWZRꢀUHDGꢀF\FOHVꢂꢀWKHꢀV\VWHPꢀGHWHUPLQHVꢀWKDWꢀWKHꢀWRJJOHꢀELWꢀLVꢀVWLOOꢀWRJꢃ
JOLQJꢂꢀWKHꢀV\VWHPꢀDOVRꢀVKRXOGꢀQRWHꢀZKHWKHUꢀWKHꢀYDOXHꢀRIꢀ'4ꢍꢀLVꢀKLJKꢀꢅVHHꢀWKHꢀVHFWLRQꢀRQꢀ'4ꢍꢆꢁꢀ,Iꢀ
LWꢀLVꢂꢀWKHꢀV\VWHPꢀVKRXOGꢀWKHQꢀGHWHUPLQHꢀDJDLQꢀZKHWKHUꢀWKHꢀWRJJOHꢀELWꢀLVꢀWRJJOLQJꢂꢀVLQFHꢀWKHꢀWRJJOHꢀ
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LWꢀPD\ꢀFKRRVHꢀWRꢀSHUIRUPꢀRWKHUꢀV\VWHPꢀWDVNVꢁꢀ,QꢀWKLVꢀFDVHꢂꢀWKHꢀV\VWHPꢀPXVWꢀVWDUWꢀDWꢀWKHꢀEHJLQQLQJꢀ
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DQ5: Exceeded Timing Limits
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PRGHꢀꢅRUꢀWRꢀWKHꢀHUDVHꢃVXVSHQGꢃUHDGꢀPRGHꢀLIꢀDꢀEDQNꢀZDVꢀSUHYLRXVO\ꢀLQꢀWKHꢀHUDVHꢃVXVSHQGꢃSURJUDPꢀ
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70
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
DQ3: Sector Erase Start Timeout State Indicator
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RUꢀQRWꢀHUDVXUHꢀKDVꢀEHJXQꢁꢀꢅ7KHꢀVHFWRUꢀHUDVHꢀWLPHUꢀGRHVꢀQRWꢀDSSO\ꢀWRꢀWKHꢀFKLSꢀHUDVHꢀFRPPDQGꢁꢆꢀ,Iꢀ
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DQ1: Write to Buffer Abort
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
71
A d v a n c e I n f o r m a t i o n
Table 28. Write Operation Status
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1ꢒ$
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1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
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ꢊꢁ 7KHꢂGDWDꢉEDUꢂSROOLQJꢂDOJRULWKPꢂVKRXOGꢂEHꢂXVHGꢂIRUꢂ:ULWHꢂ%XIIHUꢂ3URJUDPPLQJꢂRSHUDWLRQVꢁꢂ1RWHꢂWKDWꢂ'4ꢒꢑꢂGXULQJꢂ
:ULWHꢂ%XIIHUꢂ3URJUDPPLQJꢂLQGLFDWHVꢂWKHꢂGDWDꢉEDUꢂIRUꢂ'4ꢒꢂGDWDꢂIRUꢁWKHꢁ/$67ꢁ/2$'('ꢁ:5,7(ꢃ%8))(5ꢁ$''5(66ꢁ
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72
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
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9ROWDJHꢀZLWKꢀ5HVSHFWꢀWRꢀ*URXQGꢂꢀ$OOꢀ,QSXWVꢀDQGꢀ,ꢒ2V
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9&&ꢀꢅ1RWHꢀꢊꢆ ꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁ±ꢉꢁꢍꢀ9ꢀWRꢀꢎꢌꢁꢍꢀ9
933ꢀꢅ1RWHꢀꢌꢆ ꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀ±ꢉꢁꢍꢀ9ꢀWRꢀꢎꢀꢐꢁꢍꢀ9
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SHULRGVꢂRIꢂXSꢂWRꢂꢄꢈꢂQVꢂGXULQJꢂYROWDJHꢂWUDQVLWLRQVꢂLQSXWVꢂPLJKWꢂRYHUVKRRRWꢂWRꢂ9&&ꢂꢔꢈꢁꢊꢂ9ꢂIRUꢂSHULRGVꢂXSꢂWRꢂꢄꢈꢂQVꢁꢂ6HHꢂ)LJXUHꢂ
ꢒꢁꢂ0D[LPXPꢂ'&ꢂYROWDJHꢂRQꢂRXWSXWꢂDQGꢂ,ꢓ2VꢂLVꢂ9&&ꢂꢔꢂꢈꢁꢊꢂ9ꢁꢂ'XULQJꢂYROWDJHꢂWUDQVLWLRQVꢂRXWSXWVꢂPD\ꢂRYHUVKRRWꢂWRꢂ9&&ꢂꢔꢂꢄꢁꢈꢂ9ꢂ
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ꢄꢁ 0LQLPXPꢂ'&ꢂLQSXWꢂYROWDJHꢂRQꢂ933ꢂLVꢂ±ꢈꢁꢊꢂ9ꢁꢂ'XULQJꢂYROWDJHꢂWUDQVLWLRQVꢇꢂ933ꢂPD\ꢂXQGHUVKRRWꢂ966ꢂWRꢂ±ꢄꢁꢈꢂ9ꢂIRUꢂSHULRGVꢂRIꢂXSꢂ
WRꢂꢄꢈꢂQVꢁꢂ6HHꢂ)LJXUHꢂꢒꢁꢂ0D[LPXPꢂ'&ꢂLQSXWꢂYROWDJHꢂRQꢂ933ꢂLVꢂꢔꢐꢁꢊꢂ9ꢂZKLFKꢂPD\ꢂRYHUVKRRWꢂWRꢂꢔꢀꢈꢁꢊꢂ9ꢂIRUꢂSHULRGVꢂXSꢂWRꢂꢄꢈꢂQVꢁ
ꢅꢁ 1RꢂPRUHꢂWKDQꢂRQHꢂRXWSXWꢂPD\ꢂEHꢂVKRUWHGꢂWRꢂJURXQGꢂDWꢂDꢂWLPHꢁꢂ'XUDWLRQꢂRIꢂWKHꢂVKRUWꢂFLUFXLWꢂVKRXOGꢂQRWꢂEHꢂJUHDWHUꢂWKDQꢂRQHꢂ
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76
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S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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CE#
tOE
OE#
WE#
tOEH
tCE
tOEZ
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A/DQ0
RA
tACC
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RA
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AVD#
tAAVDH
tAVDP
tAAVDS
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Figure 14. Asynchronous Mode Read
80
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
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CE#, OE#
tRH
RESET#
tRP
Figure 15. Reset Timings
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
81
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase/Program Operations
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82
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
tAS
AVD
tAH
tAVDP
Amax–A16
PA
PA
VA
VA
VA
In
A/DQ15
–
555h
Complete
A0h
PD
tDS
tDH
VA
Progress
A/DQ0
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
V
IH
CLK
VCC
V
IL
tVCS
1RWHVꢀ
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
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Figure 16. Program Operation Timings
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
83
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
tAS
AVD
tAH
tAVDP
SA
555h for
chip erase
VA
VA
VA
Amax–A16
10h for
chip erase
In
A/DQ15
–
2AAh
Complete
55h
SA
30h
VA
Progress
A/DQ0
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
V
IH
CLK
VCC
V
IL
tVCS
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Figure 17. Chip/Sector Erase Operations
84
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
CE#
ADV#
WE#
Addresses
Data
PA
Don't Care
Don't Care
A0h
PD
Don't Care
OE#
t
1 μs
VIDS
V
ACC
ID
t
VID
V
or V
IL
IH
1RWHVꢀ
1. 933 can be left high for subsequent programming pulses.
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Figure 18. Accelerated Unlock Bypass Programming Timing
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
85
A d v a n c e I n f o r m a t i o n
AC Characteristics
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
tOEH
WE#
tACC
VA
High Z
High Z
A
–A16
max
VA
A/DQ15
A/DQ0
–
Status Data
Status Data
VA
VA
1RWHVꢀ
1. All status reads are asynchronous.
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Figure 19. Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
High Z
A
–A16
max
VA
VA
VA
A/DQ15
–
Status Data
Status Data
VA
A/DQ0
1RWHVꢀ
1. All status reads are asynchronous.
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Figure 20. Toggle Bit Timings (During Embedded Algorithm)
86
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Address wraps back to beginning of address group.
Initial Access
39
CLK
39
3A
3B
3C
3D
3E
3F
38
Address (hex)
A/DQ15
–
D0
D1
D2
D3
D4
D5
D6
D7
A/DQ0
AVD#
OE#
V
IH
V
IL
V
IH
(stays low)
(stays low)
V
IL
V
CE#
IL
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Figure 21. 8-, 16-, and 32-Word Linear Burst Address Wrap Around
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
CLK
7C
83
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
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Figure 22. Latency with Boundary Crossing
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
87
A d v a n c e I n f o r m a t i o n
AC Characteristics
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
RA
A/DQ15
A/DQ0
–
RA
RA
PA/SA
PD/30h
RD
RD
555h
AAh
tSR/W
RA
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PA/SA
tAS
AVD#
tAH
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Figure 23. Back-to-Back Read/Write Cycle Timings
88
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
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Device History
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
89
A d v a n c e I n f o r m a t i o n
Flash Module Revision Summary
Revision A (April 16, 2004)
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Revision A1 (June 28, 2004)
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S75NS128NDE_00_A2 September 23, 2005
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S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
95
A d v a n c e I n f o r m a t i o n
Pin Descriptions
Symbol
Type
Description
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S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Functional Description
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S75NS128NDE based MCPs
97
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EXUVWꢀOHQJWKꢀLVꢀVHWꢀWRꢀWZRꢕꢀE\ꢀ$ꢌ±$ꢈꢀZKHQꢀWKHꢀEXUVWꢀOHQJWKꢀLVꢀVHWꢀWRꢀIRXUꢕꢀDQGꢀE\ꢀ$ꢋ±$ꢈꢀZKHQꢀWKHꢀ
EXUVWꢀOHQJWKꢀLVꢀVHWꢀWRꢀHLJKWꢁ
Table 30. Burst Definition
Order of Accesses Within A Burst
Burst Length
Starting Column Address
Type = Sequential
Type = Interleaved
$ꢉ
ꢉ
ꢌ
ꢑ
ꢉꢃꢊ
ꢊꢃꢉ
ꢉꢃꢊ
ꢊꢃꢉ
ꢊ
$ꢊ
ꢉ
$ꢉ
ꢉ
ꢉꢃꢊꢃꢌꢃꢋ
ꢊꢃꢌꢃꢋꢃꢉ
ꢌꢃꢋꢃꢉꢃꢊ
ꢋꢃꢉꢃꢊꢃꢌ
ꢉꢃꢊꢃꢌꢃꢋ
ꢊꢃꢉꢃꢋꢃꢌ
ꢌꢃꢋꢃꢉꢃꢊ
ꢋꢃꢌꢃꢊꢃꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢊ
ꢊ
$ꢌ
$ꢊ
ꢉ
$ꢉ
ꢉ
ꢉ
ꢉ
ꢉ
ꢉ
ꢊ
ꢊ
ꢊ
ꢊ
ꢉꢃꢊꢃꢌꢃꢋꢃꢑꢃꢍꢃꢇꢃꢏ
ꢊꢃꢌꢃꢋꢃꢑꢃꢍꢃꢇꢃꢏꢃꢉ
ꢌꢃꢋꢃꢑꢃꢍꢃꢇꢃꢏꢃꢉꢃꢊ
ꢋꢃꢑꢃꢍꢃꢇꢃꢏꢃꢉꢃꢊꢃꢌ
ꢑꢃꢍꢃꢇꢃꢏꢃꢉꢃꢊꢃꢌꢃꢋ
ꢍꢃꢇꢃꢏꢃꢉꢃꢊꢃꢌꢃꢋꢃꢑ
ꢇꢃꢏꢃꢉꢃꢊꢃꢌꢃꢋꢃꢑꢃꢍ
ꢏꢃꢉꢃꢊꢃꢌꢃꢋꢃꢑꢃꢍꢃꢇ
ꢉꢃꢊꢃꢌꢃꢋꢃꢑꢃꢍꢃꢇꢃꢏ
ꢊꢃꢉꢃꢋꢃꢌꢃꢍꢃꢑꢃꢏꢃꢇ
ꢌꢃꢋꢃꢉꢃꢊꢃꢇꢃꢏꢃꢑꢃꢍ
ꢋꢃꢌꢃꢊꢃꢉꢃꢏꢃꢇꢃꢍꢃꢑ
ꢑꢃꢍꢃꢇꢃꢏꢃꢉꢃꢊꢃꢌꢃꢋ
ꢍꢃꢑꢃꢏꢃꢇꢃꢊꢃꢉꢃꢋꢃꢌ
ꢇꢃꢏꢃꢑꢃꢍꢃꢌꢃꢋꢃꢉꢃꢊ
ꢏꢃꢇꢃꢍꢃꢑꢃꢋꢃꢌꢃꢊꢃꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢈ
ꢊ
ꢊ
ꢉ
ꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢊ
ꢊ
&Qꢂꢀ&Qꢎꢊꢂ
&Qꢎꢌꢂꢀ&Qꢎꢋꢂ
&Qꢎꢑꢁꢁꢁꢂꢀ«&Qꢃꢊꢂ
&Q«
)XOOꢀ3DJHꢀꢅ\ꢆ
Qꢀ ꢀ$ꢉ±$ꢈꢀꢅORFDWLRQꢀꢉꢃ\ꢆ
1RWꢀ6XSSRUWHG
1RWHVꢀ
ꢀꢁ )RUꢂIXOOꢉSDJHꢂDFFHVVHVꢃꢂ\ꢂ ꢂꢊꢀꢄꢁ
ꢄꢁ )RUꢂDꢂEXUVWꢂOHQJWKꢂRIꢂWZRꢇꢂ$ꢀ±$ꢆꢂVHOHFWꢂWKHꢂEORFNꢉRIꢉWZRꢂEXUVWꢏꢂ$ꢈꢂVHOHFWVꢂWKHꢂVWDUWLQJꢂFROXPQꢂZLWKLQꢂ
WKHꢂEORFNꢁ
ꢅꢁ )RUꢂDꢂEXUVWꢂOHQJWKꢂRIꢂIRXUꢇꢂ$ꢄ±$ꢆꢂVHOHFWꢂWKHꢂEORFNꢉRIꢉIRXUꢂEXUVWꢏꢂ$ꢈ±$ꢀꢂVHOHFWꢂWKHꢂVWDUWLQJꢂFROXPQꢂ
ZLWKLQꢂWKHꢂEORFNꢁ
ꢋꢁ )RUꢂDꢂEXUVWꢂOHQJWKꢂRIꢂHLJKWꢇꢂ$ꢅ±$ꢆꢂVHOHFWꢂWKHꢂEORFNꢉRIꢉHLJKWꢂEXUVWꢏꢂ$ꢈ±$ꢄꢂVHOHFWꢂWKHꢂVWDUWLQJꢂFROXPQꢂ
ZLWKLQꢂWKHꢂEORFNꢁ
ꢊꢁ )RUꢂDꢂIXOOꢉSDJHꢂEXUVWꢇꢂWKHꢂIXOOꢂURZꢂLVꢂVHOHFWHGꢂDQGꢂ$ꢈ±$ꢆꢂVHOHFWꢂWKHꢂVWDUWLQJꢂFROXPQꢁ
ꢌꢁ :KHQHYHUꢂDꢂERXQGDU\ꢂRIꢂWKHꢂEORFNꢂLVꢂUHDFKHGꢂZLWKLQꢂDꢂJLYHQꢂVHTXHQFHꢂDERYHꢇꢂWKHꢂIROORZLQJꢂDFFHVVꢂ
ZUDSVꢂZLWKLQꢂWKHꢂEORFNꢁ
ꢒꢁ )RUꢂDꢂEXUVWꢂOHQJWKꢂRIꢂRQHꢇꢂ$ꢈ±$ꢆꢂVHOHFWꢂWKHꢂXQLTXHꢂFROXPQꢂWRꢂEHꢂDFFHVVHGꢇꢂDQGꢂPRGHꢂUHJLVWHUꢂELWꢂ
0ꢅꢂLVꢂLJQRUHGꢁ
98
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Address Bus
BA1 BA0 A11 A10 A9 A8
A7 A6 A5 A4
A3 A2 A1 A0
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12
9
8
6
5
4
1
11 10
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CASLatency
BT
Burst Length
Reserved**
Burst Length
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
2
4
4
8
8
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency
M6 M5 M4
Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
Reserved
Reserved
Reserved
Reserved
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
Figure 25. Mode Register Definition
7KHꢀUHPDLQLQJꢀꢅOHDVWꢀVLJQLILFDQWꢆꢀDGGUHVVꢀELWꢅVꢆꢀLVꢀꢅDUHꢆꢀXVHGꢀWRꢀVHOHFWꢀWKHꢀVWDUWLQJꢀORFDWLRQꢀZLWKLQꢀ
WKHꢀEORFNꢁꢀ)XOOꢃSDJHꢀEXUVWVꢀZUDSꢀZLWKLQꢀWKHꢀSDJHꢀLIꢀWKHꢀERXQGDU\ꢀLVꢀUHDFKHGꢁ
Burst Type
$FFHVVHVꢀZLWKLQꢀDꢀJLYHQꢀEXUVWꢀPD\ꢀEHꢀSURJUDPPHGꢀWRꢀEHꢀHLWKHUꢀVHTXHQWLDOꢀRUꢀLQWHUOHDYHGꢕꢀWKLVꢀLVꢀ
UHIHUUHGꢀWRꢀDVꢀWKHꢀEXUVWꢀW\SHꢀDQGꢀLVꢀVHOHFWHGꢀYLDꢀELWꢀ0ꢋꢁ
7KHꢀRUGHULQJꢀRIꢀDFFHVVHVꢀZLWKLQꢀDꢀEXUVWꢀLVꢀGHWHUPLQHGꢀE\ꢀWKHꢀEXUVWꢀOHQJWKꢂꢀWKHꢀEXUVWꢀW\SHꢀDQGꢀWKHꢀ
VWDUWLQJꢀFROXPQꢀDGGUHVVꢂꢀDVꢀVKRZQꢀLQꢀ7DEOHꢀꢋꢉꢁ
CAS Latency
7KHꢀ&$6ꢀODWHQF\ꢀLVꢀWKHꢀGHOD\ꢂꢀLQꢀFORFNꢀF\FOHVꢂꢀEHWZHHQꢀWKHꢀUHJLVWUDWLRQꢀRIꢀDꢀ5HDGꢀFRPPDQGꢀDQGꢀ
WKHꢀDYDLODELOLW\ꢀRIꢀWKHꢀILUVWꢀSLHFHꢀRIꢀRXWSXWꢀGDWDꢁꢀ7KHꢀODWHQF\ꢀFDQꢀEHꢀVHWꢀWRꢀRQHꢂꢀWZRꢂꢀRUꢀWKUHHꢀFORFNVꢁ
,IꢀDꢀ5HDGꢀFRPPDQGꢀLVꢀUHJLVWHUHGꢀDWꢀFORFNꢀHGJHꢀQꢂꢀDQGꢀWKHꢀODWHQF\ꢀLVꢀPꢀFORFNVꢂꢀWKHꢀGDWDꢀZLOOꢀEHꢀ
DYDLODEOHꢀE\ꢀFORFNꢀHGJHꢀQꢂꢔꢂPꢁꢀ7KHꢀ'4VꢀZLOOꢀVWDUWꢀGULYLQJꢀDVꢀDꢀUHVXOWꢀRIꢀWKHꢀFORFNꢀHGJHꢀRQHꢀF\FOHꢀ
HDUOLHUꢀꢅQꢂꢔꢂPꢂꢉꢂꢀꢆꢂꢀDQGꢀSURYLGHGꢀWKDWꢀWKHꢀUHOHYDQWꢀDFFHVVꢀWLPHVꢀDUHꢀPHWꢂꢀWKHꢀGDWDꢀZLOOꢀEHꢀYDOLGꢀE\ꢀ
FORFNꢀHGJHꢀQꢂꢔꢂPꢁꢀ)RUꢀH[DPSOHꢂꢀDVVXPLQJꢀWKDWꢀWKHꢀFORFNꢀF\FOHꢀWLPHꢀLVꢀVXFKꢀWKDWꢀDOOꢀUHOHYDQWꢀDFFHVVꢀ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
99
A d v a n c e I n f o r m a t i o n
WLPHVꢀDUHꢀPHWꢂꢀLIꢀDꢀUHDGꢀFRPPDQGꢀLVꢀUHJLVWHUHGꢀDWꢀ7ꢉꢀDQGꢀWKHꢀODWHQF\ꢀLVꢀSURJUDPPHGꢀWRꢀWZRꢀ
FORFNVꢂꢀWKHꢀ'4VꢀZLOOꢀVWDUWꢀGULYLQJꢀDIWHUꢀ7ꢊꢀDQGꢀWKHꢀGDWDꢀZLOOꢀEHꢀYDOLGꢀE\ꢀ7ꢌꢂꢀDVꢀVKRZQꢀLQꢀ)LJXUHꢀꢌꢇꢂꢀ
&$6ꢀ/DWHQF\ꢁꢀ7DEOHꢀꢋꢊꢄꢀ&$6ꢀ/DWHQF\ꢂꢀLQGLFDWHVꢀWKHꢀRSHUDWLQJꢀIUHTXHQFLHVꢀDWꢀZKLFKꢀHDFKꢀ&$6ꢀODꢃ
WHQF\ꢀVHWWLQJꢀFDQꢀEHꢀXVHGꢁ
5HVHUYHGꢀVWDWHVꢀVKRXOGꢀQRWꢀEHꢀXVHGꢀDVꢀXQNQRZQꢀRSHUDWLRQꢀRUꢀLQFRPSDWLELOLW\ꢀZLWKꢀIXWXUHꢀYHUVLRQVꢀ
PD\ꢀUHVXOWꢁ
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
Figure 26. CAS Latency
Table 31. CAS Latency
Allowable Operating Frequency MHz
CAS Latency = 2 CAS Latency = 3
Speed
ꢃꢏꢍ
≤
ꢊꢉꢉ
≤
≤
ꢊꢋꢋ
ꢊꢉꢑ
ꢃꢊꢉ
≤
ꢈꢋꢁꢋ
Operating Mode
7KHꢀQRUPDOꢀRSHUDWLQJꢀPRGHꢀLVꢀVHOHFWHGꢀE\ꢀVHWWLQJꢀ0ꢏꢀDQGꢀ0ꢈꢀWRꢀ]HURꢕꢀWKHꢀRWKHUꢀFRPELQDWLRQVꢀRIꢀ
YDOXHVꢀIRUꢀ0ꢏꢀDQGꢀ0ꢈꢀDUHꢀUHVHUYHGꢀIRUꢀIXWXUHꢀXVHꢀDQGꢒRUꢀWHVWꢀPRGHVꢁꢀ7KHꢀSURJUDPPHGꢀEXUVWꢀ
OHQJWKꢀDSSOLHVꢀWRꢀERWKꢀUHDGꢀDQGꢀZULWHꢀEXUVWVꢁ
7HVWꢀPRGHVꢀDQGꢀUHVHUYHGꢀVWDWHVꢀVKRXOGꢀQRWꢀEHꢀXVHGꢀEHFDXVHꢀXQNQRZQꢀRSHUDWLRQꢀRUꢀLQFRPSDWLELOLW\ꢀ
ZLWKꢀIXWXUHꢀYHUVLRQVꢀPD\ꢀUHVXOWꢁ
Write Burst Mode
:KHQꢀ0ꢐꢀ ꢀꢉꢂꢀWKHꢀEXUVWꢀOHQJWKꢀSURJUDPPHGꢀYLDꢀ0ꢉꢃ0ꢌꢀDSSOLHVꢀWRꢀERWKꢀ5HDGꢀDQGꢀ:ULWHꢀEXUVWVꢕꢀ
ZKHQꢀ0ꢐ ꢀꢊꢂꢀWKHꢀSURJUDPPHGꢀEXUVWꢀOHQJWKꢀDSSOLHVꢀWRꢀ5HDGꢀEXUVWVꢂꢀEXWꢀZULWHꢀDFFHVVHVꢀDUHꢀVLQJOHꢃ
ORFDWLRQꢀꢅQRQEXUVWꢆꢀDFFHVVHVꢁ
100
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Extended Mode Register
7KHꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀFRQWUROVꢀWKHꢀIXQFWLRQVꢀEH\RQGꢀWKRVHꢀFRQWUROOHGꢀE\ꢀWKHꢀ0RGHꢀ5HJLVWHUꢁꢀ
7KHVHꢀDGGLWLRQDOꢀIXQFWLRQVꢀDUHꢀVSHFLDOꢀIHDWXUHVꢀRIꢀWKHꢀ0RELOHꢀGHYLFHꢁꢀ7KH\ꢀLQFOXGHꢀ7HPSHUDWXUHꢀ
&RPSHQVDWHGꢀ6HOIꢀ5HIUHVKꢀꢅ7&65ꢆꢀ&RQWUROꢂꢀ3DUWLDOꢀ$UUD\ꢀ6HOIꢀ5HIUHVKꢀꢅ3$65ꢆꢂꢀDQGꢀ2XWSXWꢀ'ULYHꢀ
6WUHQJWKꢁꢀ1RWꢀSURJUDPPLQJꢀWKHꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀXSRQꢀLQLWLDOL]DWLRQꢂꢀZLOOꢀUHVXOWꢀLQꢀGHIDXOWꢀ
VHWWLQJVꢀIRUꢀWKHꢀ/RZꢀ3RZHUꢀIHDWXUHVꢁꢀ7KHꢀ([WHQGHGꢀ0RGHꢀZLOOꢀGHIDXOWꢀWRꢀWKHꢀꢎꢈꢍ&ꢀVHWWLQJꢀIRUꢀ
7&65ꢂꢀIXOOꢀGULYHꢀVWUHQJWKꢂꢀDQGꢀIXOOꢀDUUD\ꢀUHIUHVKꢁ
7KHꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀLVꢀSURJUDPPHGꢀYLDꢀWKHꢀ0RGHꢀ5HJLVWHUꢀ6HWꢀFRPPDQGꢀꢅ%$ꢊꢀ ꢀꢊꢂꢀ%$ꢉꢀ
ꢀꢉꢆꢀDQGꢀUHWDLQVꢀWKHꢀVWRUHGꢀLQIRUPDWLRQꢀXQWLOꢀLWꢀLVꢀSURJUDPPHGꢀDJDLQꢀRUꢀWKHꢀGHYLFHꢀORVHVꢀSRZHUꢁ
7KHꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀPXVWꢀEHꢀSURJUDPPHGꢀZLWKꢀ(ꢇꢀWKURXJKꢀ(ꢊꢊꢀVHWꢀWRꢀ³ꢉ´ꢁꢀ,WꢀPXVWꢀEHꢀ
ORDGHGꢀZKHQꢀDOOꢀEDQNVꢀDUHꢀLGOHꢀDQGꢀQRꢀEXUVWVꢀDUHꢀLQꢀSURJUHVVꢂꢀDQGꢀWKHꢀFRQWUROOHUꢀPXVWꢀZDLWꢀWKHꢀ
VSHFLILHGꢀWLPHꢀEHIRUHꢀLQLWLDWLQJꢀDQ\ꢀVXEVHTXHQWꢀRSHUDWLRQꢁꢀ9LRODWLQJꢀHLWKHUꢀRIꢀWKHVHꢀUHTXLUHPHQWVꢀ
UHVXOWVꢀLQꢀXQVSHFLILHGꢀRSHUDWLRQꢁ
2QFHꢀWKHꢀYDOXHVꢀDUHꢀHQWHUHGꢀWKHꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀVHWWLQJVꢀZLOOꢀEHꢀUHWDLQHGꢀHYHQꢀDIWHUꢀH[ꢃ
LWLQJꢀ'HHSꢀ3RZHUꢃ'RZQꢁ
Temperature Compensated Self Refresh
7HPSHUDWXUHꢀ&RPSHQVDWHGꢀ6HOIꢀ5HIUHVKꢀꢅ7&65ꢆꢀDOORZVꢀWKHꢀFRQWUROOHUꢀWRꢀSURJUDPꢀWKHꢀ5HIUHVKꢀLQꢃ
WHUYDOꢀGXULQJꢀ6HOIꢀ5HIUHVKꢀPRGHꢂꢀDFFRUGLQJꢀWRꢀWKHꢀFDVHꢀWHPSHUDWXUHꢀRIꢀWKHꢀ0RELOHꢀGHYLFHꢁꢀ7KLVꢀ
DOORZVꢀJUHDWꢀSRZHUꢀVDYLQJVꢀGXULQJꢀ6HOIꢀ5HIUHVKꢀGXULQJꢀPRVWꢀRSHUDWLQJꢀWHPSHUDWXUHꢀUDQJHVꢁꢀ2QO\ꢀ
GXULQJꢀH[WUHPHꢀWHPSHUDWXUHVꢀZRXOGꢀWKHꢀFRQWUROOHUꢀKDYHꢀWRꢀVHOHFWꢀWKHꢀPD[LPXPꢀ7&65ꢀOHYHOꢁꢀ7KLVꢀ
ZRXOGꢀJXDUDQWHHꢀGDWDꢀGXULQJꢀ6HOIꢀ5HIUHVKꢁ
(YHU\ꢀFHOOꢀLQꢀWKHꢀ6'5$0ꢀUHTXLUHVꢀUHIUHVKLQJꢀGXHꢀWRꢀWKHꢀFDSDFLWRUꢀORVLQJꢀLWVꢀFKDUJHꢀRYHUꢀWLPHꢁꢀ7KHꢀ
UHIUHVKꢀUDWHꢀLVꢀGHSHQGHQWꢀRQꢀWHPSHUDWXUHꢁꢀ$WꢀKLJKHUꢀWHPSHUDWXUHVꢀDꢀFDSDFLWRUꢀORVHVꢀFKDUJHꢀ
TXLFNHUꢀWKDQꢀDWꢀORZHUꢀWHPSHUDWXUHVꢂꢀUHTXLULQJꢀWKHꢀFHOOVꢀWRꢀEHꢀUHIUHVKHGꢀPRUHꢀRIWHQꢁꢀ+LVWRULFDOO\ꢂꢀ
GXULQJꢀ6HOIꢀ5HIUHVKꢂꢀWKHꢀUHIUHVKꢀUDWHꢀKDVꢀEHHQꢀVHWꢀWRꢀDFFRPPRGDWHꢀWKHꢀZRUVWꢀFDVHꢂꢀRUꢀKLJKHVWꢀWHPꢃ
SHUDWXUHꢀUDQJHꢀH[SHFWHGꢁ
7KXVꢂꢀGXULQJꢀDPELHQWꢀWHPSHUDWXUHVꢂꢀWKHꢀSRZHUꢀFRQVXPHGꢀGXULQJꢀUHIUHVKꢀZDVꢀXQQHFHVVDULO\ꢀKLJKꢂꢀ
EHFDXVHꢀWKHꢀUHIUHVKꢀUDWHꢀZDVꢀVHWꢀWRꢀDFFRPPRGDWHꢀWKHꢀKLJKHUꢀWHPSHUDWXUHVꢁꢀ$GMXVWLQJꢀWKHꢀUHIUHVKꢀ
UDWHꢀE\ꢀVHWWLQJꢀ(ꢑꢀDQGꢀ(ꢋꢀDOORZVꢀWKHꢀ6'5$0ꢀWRꢀDFFRPPRGDWHꢀPRUHꢀVSHFLILFꢀWHPSHUDWXUHꢀUHJLRQVꢀ
GXULQJꢀ6HOIꢀ5HIUHVKꢁꢀ7KHUHꢀDUHꢀIRXUꢀWHPSHUDWXUHꢀVHWWLQJVꢂꢀZKLFKꢀZLOOꢀYDU\ꢀWKHꢀ6HOIꢀ5HIUHVKꢀFXUUHQWꢀ
DFFRUGLQJꢀWRꢀWKHꢀVHOHFWHGꢀWHPSHUDWXUHꢁꢀ7KLVꢀVHOHFWDEOHꢀUHIUHVKꢀUDWHꢀZLOOꢀVDYHꢀSRZHUꢀZKHQꢀWKHꢀ
6'5$0ꢀLVꢀRSHUDWLQJꢀDWꢀQRUPDOꢀWHPSHUDWXUHVꢁ
Partial Array Self Refresh
)RUꢀIXUWKHUꢀSRZHUꢀVDYLQJVꢀGXULQJꢀ6HOIꢀ5HIUHVKꢂꢀWKHꢀ3DUWLDOꢀ$UUD\ꢀ6HOIꢀ5HIUHVKꢀꢅ3$65ꢆꢀIHDWXUHꢀDOORZVꢀ
WKHꢀFRQWUROOHUꢀWRꢀVHOHFWꢀWKHꢀDPRXQWꢀRIꢀPHPRU\ꢀWKDWꢀZLOOꢀEHꢀUHIUHVKHGꢀGXULQJꢀ6HOIꢀ5HIUHVKꢁꢀ7KHꢀUHꢃ
IUHVKꢀRSWLRQVꢀDUHꢀDOOꢀEDQNVꢀꢅEDQNVꢀꢉꢂꢀꢊꢂꢀꢌꢂꢀDQGꢀꢋꢆꢕꢀWZRꢀEDQNVꢀꢅEDQNVꢀꢉꢀDQGꢀꢊꢆꢕꢀDQGꢀRQHꢀEDQNꢀꢅEDQNꢀ
ꢉꢆꢁꢀ$OVRꢀLQFOXGHGꢀLQꢀWKHꢀUHIUHVKꢀRSWLRQVꢀDUHꢀWKHꢀꢊꢒꢌꢀEDQNꢀDQGꢀꢊꢒꢑꢀEDQNꢀSDUWLDOꢀDUUD\ꢀVHOIꢀUHIUHVKꢀ
ꢅEDQNꢀꢉꢆꢁꢀ:ULWHꢀDQGꢀ5HDGꢀFRPPDQGVꢀRFFXUꢀWRꢀDQ\ꢀEDQNꢀVHOHFWHGꢀGXULQJꢀVWDQGDUGꢀRSHUDWLRQꢂꢀEXWꢀ
RQO\ꢀWKHꢀVHOHFWHGꢀEDQNVꢀLQꢀ3$65ꢀZLOOꢀEHꢀUHIUHVKHGꢀGXULQJꢀ6HOIꢀ5HIUHVKꢁꢀ,WꢀLVꢀLPSRUWDQWꢀWRꢀQRWHꢀWKDWꢀ
GDWDꢀLQꢀXQXVHGꢀEDQNVꢂꢀRUꢀSRUWLRQVꢀRIꢀEDQNVꢂꢀZLOOꢀEHꢀORVWꢀZKHQꢀ3$65ꢀLVꢀXVHGꢁꢀ'DWDꢀZLOOꢀEHꢀORVWꢀLQꢀ
EDQNVꢀꢊꢂꢀꢌꢂꢀDQGꢀꢋꢀZKHQꢀWKHꢀRQHꢀEDQNꢀRSWLRQꢀLVꢀXVHGꢁ
Driver Strength
%LWVꢀ(ꢍꢀDQGꢀ(ꢇꢀRIꢀWKHꢀH[WHQGHGꢀPRGHꢀUHJLVWHUꢀFDQꢀEHꢀXVHGꢀWRꢀVHOHFWꢀWKHꢀGULYHUꢀVWUHQJWKꢀRIꢀWKHꢀ'4ꢀ
RXWSXWVꢁꢀ7KLVꢀYDOXHꢀVKRXOGꢀEHꢀVHWꢀDFFRUGLQJꢀWRꢀWKHꢀDSSOLFDWLRQꢀUHTXLUHPHQWVꢁꢀ)XOOꢀGULYHꢀVWUHQJWKꢀ
ZDVꢀFDUULHGꢀRYHUꢀIURPꢀVWDQGDUGꢀ6'5$0ꢀDQGꢀLVꢀVXLWDEOHꢀWRꢀGULYHꢀKLJKHUꢀORDGꢀV\VWHPVꢁꢀ)XOOꢀGULYHꢀ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
101
A d v a n c e I n f o r m a t i o n
VWUHQJWKꢀLVꢀQRWꢀUHFRPPHQGHGꢀIRUꢀORDGVꢀXQGHUꢀꢋꢉS)ꢁꢀ+DOIꢀGULYHꢀVWUHQJWKꢀLVꢀLQWHQGHGꢀIRUꢀPXOWLꢃGURSꢀ
V\VWHPVꢀZLWKꢀYDULRXVꢀORDGVꢁꢀ7KLVꢀGULYHꢀRSWLRQꢀLVꢀQRWꢀUHFRPPHQGHGꢀIRUꢀORDGVꢀXQGHUꢀꢊꢍS)ꢁꢀ4XDUWHUꢀ
GULYHꢀVWUHQJWKꢀLVꢀLQWHQGHGꢀIRUꢀOLJKWHUꢀORDGVꢀRUꢀSRLQWꢃWRꢃSRLQWꢀV\VWHPVꢁ
BA1BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
2
13 12 11 10
9
8
7
6
5
4
3
1
0
Extended Mode
Register (Ex)
1
0
All must be set to "0"
DS
TCSR
PASR
E6 E5 Driver Strength
E4 E3 Maximum Case Temp
85°C3
3
1
0
0
1
0
1
0
0
0
1
Full Strength
Half Strength
70°C
45°C
15°C
Quarter Strength
Reserved
1
1
0
1
1
0
E2
0
E1
0
E0
0
Self Refresh Coverage
Four Banks3
Two Banks (Bank 0,1)
One Bank (Bank 0)
RFU
0
0
1
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
RFU
1/2 Bank (Bank 0)4
1/4 Bank (Bank 0)5
RFU
1
1
1
Figure 27. Extended Mode Register
1RWHVꢀ
ꢀꢁ (ꢀꢅꢂDQGꢂ(ꢀꢄꢂꢍ%$ꢀꢂDQGꢂ%$ꢈꢎꢂPXVWꢂEHꢂ³ꢀꢇꢂꢈ´ꢂWRꢂVHOHFWꢂWKHꢂH[WHQGHGꢂPRGHꢂUHJLVWHUꢂꢍYVꢁꢂWKHꢂEDVHꢂPRGHꢂ
UHJLVWHUꢎꢁ
ꢄꢁ 5)8ꢃꢂ5HVHUYHGꢂIRUꢂIXWXUHꢂXVHꢁ
ꢅꢁ 'HIDXOWꢂ(05ꢂYDOXHVꢂDUHꢂIXOOꢂDUUD\ꢂIRUꢂ3$65ꢇꢂ)XOOꢂ'ULYHꢂ6WUHQJWKꢇꢂDQGꢂꢆꢊꢂIRUꢂ7&65ꢁ
ꢋꢁ (ꢀꢀꢂ ꢂꢈꢁ
ꢊꢁ (ꢀꢈꢇꢂ(ꢀꢀꢂ ꢂꢈꢁ
Commands
7DEOHꢀꢋꢌꢀSURYLGHVꢀDꢀTXLFNꢀUHIHUHQFHꢀRIꢀDYDLODEOHꢀFRPPDQGVꢁꢀ7KLVꢀLVꢀIROORZHGꢀE\ꢀDꢀZULWWHQꢀGHVFULSꢃ
WLRQꢀRIꢀHDFKꢀFRPPDQGꢁꢀ7KUHHꢀDGGLWLRQDOꢀ7UXWKꢀ7DEOHVꢀDSSHDUꢀIROORZLQJꢀWKHꢀ2SHUDWLRQꢀVHFWLRQꢕꢀ
WKHVHꢀWDEOHVꢀSURYLGHꢀFXUUHQWꢀVWDWHꢒQH[WꢀVWDWHꢀLQIRUPDWLRQꢁ
102
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 32. Truth Table 1 - Commands and DQM Operation
Name (Function)
&RPPDQGꢀ,QKLELWꢀꢅ123ꢆ
1Rꢀ2SHUDWLRQ
+
/
;
+
;
+
;
+
;
;
;
;
;
;
%DQNꢒ
5RZ
$FWLYHꢀꢅ6HOHFWꢀEDQNꢀDQGꢀDFWLYDWHꢀURZꢆ
/
/
+
+
;
;
ꢋ
5HDGꢀꢅ6HOHFWꢀEDQNꢀDQGꢀFROXPQꢂꢀDQGꢀVWDUWꢀ5HDGꢀEXUVWꢆ
:ULWHꢀꢅ6HOHFWꢀEDQNꢀDQGꢀFROXPQꢂꢀDQGꢀVWDUWꢀ:ULWHꢀEXUVWꢆ
/
/
+
+
/
/
+
/
/ꢒ+ %DQNꢒ&RO
/ꢒ+ %DQNꢒ&RO
;
ꢑ
ꢑ
9DOLG
%XUVWꢀ7HUPLQDWHꢀRUꢀ'HHSꢀ3RZHUꢀ'RZQ
ꢅ(QWHUꢀGHHSꢀSRZHUꢀGRZQꢀPRGHꢆ
/
/
+
/
+
+
/
/
;
;
;
;
;
ꢐꢂꢀꢊꢉ
ꢍ
%DQNꢂꢀ
$ꢊꢉ
3UHFKDUJHꢀꢅ'HDFWLYDWHꢀURZꢀLQꢀEDQNꢀRUꢀEDQNVꢆ
$XWRꢀ5HIUHVKꢀRUꢀ6HOIꢀ5HIUHVKꢀꢅ(QWHUꢀVHOIꢀUHIUHVKꢀPRGHꢆ
/RDGꢀ0RGHꢀ5HJLVWHUꢒ/RDGꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHU
:ULWHꢀ(QDEOHꢒ2XWSXWꢀ(QDEOH
/
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+
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;
;
/
;
;
ꢇꢂꢀꢏ
ꢌ
2Sꢃ&RGH
;
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;
;
;
;
;
;
$FWLYH
+LJKꢃ=
ꢈ
:ULWHꢀ,QKLELWꢒ2XWSXWꢀ+LJKꢃ=
+
ꢈ
1RWHVꢀ
ꢀꢁ &.(ꢂLVꢂ+LJKꢂIRUꢂDOOꢂFRPPDQGVꢂVKRZQꢂH[FHSWꢂ6HOIꢂ5HIUHVKꢂDQGꢂ'HHSꢂ3RZHUꢂ'RZQꢁ
ꢄꢁ $ꢈꢉ$ꢀꢀꢂGHILQHꢂRSꢉFRGHꢂZULWWHQꢂWRꢂPRGHꢂUHJLVWHUꢁ
ꢅꢁ $ꢈ±$ꢀꢀꢂSURYLGHꢂURZꢂDGGUHVVꢇꢂDQGꢂ%$ꢈꢇꢂ%$ꢀꢂGHWHUPLQHꢂZKLFKꢂEDQNꢂLVꢂPDGHꢂDFWLYHꢁ
ꢋꢁ $ꢀ±$ꢆꢂSURYLGHꢂFROXPQꢂDGGUHVVꢏꢂ$ꢀꢈꢂ+LJKꢂHQDEOHVꢂWKHꢂDXWRꢂSUHFKDUJHꢂIHDWXUHꢂꢍQRQꢂSHUVLVWHQWꢎꢇꢂ
ZKLOHꢂ$ꢀꢈꢂ/RZꢂGLVDEOHVꢂWKHꢂDXWRꢂSUHFKDUJHꢂIHDWXUHꢏꢂ%$ꢈꢇꢂ%$ꢀꢂGHWHUPLQHꢂZKLFKꢂEDQNꢂLVꢂEHLQJꢂUHDGꢂ
IURPꢂRUꢂZULWWHQꢂWRꢁ
ꢊꢁ $ꢀꢈꢂ/RZꢃꢂ%$ꢈꢇꢂ%$ꢀꢂGHWHUPLQHꢂWKHꢂEDQNꢂEHLQJꢂSUHFKDUJHGꢁꢂ$ꢀꢈꢂ+LJKꢃꢂ$OOꢂEDQNVꢂSUHFKDUJHGꢂDQGꢂ%$ꢈꢇꢂ
%$ꢀꢂDUHꢂ³'RQ¶Wꢂ&DUHꢁ´
ꢌꢁ 7KLVꢂFRPPDQGꢂLVꢂ$XWRꢂ5HIUHVKꢂLIꢂ&.(ꢂLVꢂ+LJKꢇꢂ6HOIꢂ5HIUHVKꢂLIꢂ&.(ꢂLVꢂ/RZꢁ
ꢒꢁ ,QWHUQDOꢂUHIUHVKꢂFRXQWHUꢂFRQWUROVꢂURZꢂDGGUHVVLQJꢏꢂDOOꢂLQSXWVꢂDQGꢂ,ꢓ2VꢂDUHꢂ³'RQ¶Wꢂ&DUH´ꢂH[FHSWꢂIRUꢂ&.(
ꢆꢁ $FWLYDWHVꢂRUꢂGHDFWLYDWHVꢂWKHꢂ'4VꢂGXULQJꢂ:ULWHVꢂꢍ]HURꢉFORFNꢂGHOD\ꢎꢂDQGꢂ5HDGVꢂꢍWZRꢉFORFNꢂGHOD\ꢎꢁꢂ
'40/ꢂFRQWUROVꢂ'4ꢈꢉꢒꢇꢂ'40+ꢂFRQWUROVꢂ'4ꢆꢉꢀꢊꢁ
ꢐꢁ 7KLVꢂFRPPDQGꢂLVꢂ%XUVWꢂ7HUPLQDWHꢂZKHQꢂ&.(ꢂLVꢂKLJKꢂDQGꢂ'HHSꢂ3RZHUꢂ'RZQꢂZKHQꢂ&.(ꢂLVꢂORZꢁ
ꢀꢈꢁ7KHꢂSXUSRVHꢂRIꢂWKHꢂ%XUVWꢂ7HUPLQDWHꢂFRPPDQGꢂLVꢂWRꢂVWRSꢂDꢂGDWDꢂEXUVWꢇꢂWKXVꢂWKHꢂFRPPDQGꢂFRXOGꢂFRꢉ
LQFLGHꢂZLWKꢂGDWDꢂRQꢂWKHꢂEXVꢁꢂ+RZHYHUꢂWKHꢂ'4VꢂFROXPQꢂUHDGVꢂDꢂGRQ¶WꢂFDUHꢂVWDWHꢂWRꢂLOOXVWUDWHꢂWKDWꢂWKHꢂ
%XUVWꢂ7HUPLQDWHꢂFRPPDQGꢂFDQꢂRFFXUꢂZKHQꢂWKHUHꢂLVꢂQRꢂGDWDꢂSUHVHQWꢁ
Command Inhibit
7KHꢀ&RPPDQGꢀ,QKLELWꢀIXQFWLRQꢀSUHYHQWVꢀQHZꢀFRPPDQGVꢀIURPꢀEHLQJꢀH[HFXWHGꢀE\ꢀWKHꢀ6'5$0ꢂꢀUHꢃ
JDUGOHVVꢀRIꢀZKHWKHUꢀWKHꢀ&/.ꢀVLJQDOꢀLVꢀHQDEOHGꢁꢀ7KHꢀ6'5$0ꢀLVꢀHIIHFWLYHO\ꢀGHVHOHFWHGꢁꢀ2SHUDWLRQVꢀ
DOUHDG\ꢀLQꢀSURJUHVVꢀDUHꢀQRWꢀDIIHFWHGꢁ
No Operation (NOP)
7KHꢀ1Rꢀ2SHUDWLRQꢀꢅ123ꢆꢀFRPPDQGꢀLVꢀXVHGꢀWRꢀSHUIRUPꢀDꢀ123ꢀWRꢀDQꢀ6'5$0ꢀZKLFKꢀLVꢀVHOHFWHGꢀꢅ&6ꢓꢀ
LVꢀ/RZꢆꢁꢀ7KLVꢀSUHYHQWVꢀXQZDQWHGꢀFRPPDQGVꢀIURPꢀEHLQJꢀUHJLVWHUHGꢀGXULQJꢀLGOHꢀRUꢀZDLWꢀVWDWHVꢁꢀ2Sꢃ
HUDWLRQVꢀDOUHDG\ꢀLQꢀSURJUHVVꢀDUHꢀQRWꢀDIIHFWHGꢁ
Load Mode Register
7KHꢀPRGHꢀUHJLVWHUꢀLVꢀORDGHGꢀYLDꢀLQSXWVꢀ$ꢉ±$ꢊꢊꢂꢀ%$ꢉꢂꢀ%$ꢊꢁꢀ6HHꢀPRGHꢀUHJLVWHUꢀKHDGLQJꢀLQꢀWKHꢀ5HJꢃ
LVWHUꢀ'HILQLWLRQꢀVHFWLRQꢁꢀ7KHꢀ/RDGꢀ0RGHꢀ5HJLVWHUꢀDQGꢀ/RDGꢀ([WHQGHGꢀ0RGHꢀ5HJLVWHUꢀFRPPDQGVꢀFDQꢀ
RQO\ꢀEHꢀLVVXHGꢀZKHQꢀDOOꢀEDQNVꢀDUHꢀLGOHꢂꢀDQGꢀDꢀVXEVHTXHQWꢀH[HFXWDEOHꢀFRPPDQGꢀFDQQRWꢀEHꢀLVVXHGꢀ
XQWLOꢀW05'ꢀLVꢀPHWꢁ
7KHꢀYDOXHVꢀRIꢀWKHꢀPRGHꢀUHJLVWHUꢀDQGꢀH[WHQGHGꢀPRGHꢀUHJLVWHUꢀZLOOꢀEHꢀUHWDLQHGꢀHYHQꢀZKHQꢀH[LWLQJꢀ
GHHSꢀSRZHUꢃGRZQꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
103
A d v a n c e I n f o r m a t i o n
Active
Read
7KHꢀ$FWLYHꢀFRPPDQGꢀLVꢀXVHGꢀWRꢀRSHQꢀꢅRUꢀDFWLYDWHꢆꢀDꢀURZꢀLQꢀDꢀSDUWLFXODUꢀEDQNꢀIRUꢀDꢀVXEVHTXHQWꢀ
DFFHVVꢁꢀ7KHꢀYDOXHꢀRQꢀWKHꢀ%$ꢉꢂꢀ%$ꢊꢀLQSXWVꢀVHOHFWVꢀWKHꢀEDQNꢂꢀDQGꢀWKHꢀDGGUHVVꢀSURYLGHGꢀRQꢀLQSXWVꢀ
$ꢉ±$ꢊꢊꢀVHOHFWVꢀWKHꢀURZꢁꢀ7KLVꢀURZꢀUHPDLQVꢀDFWLYHꢀꢅRUꢀRSHQꢆꢀIRUꢀDFFHVVHVꢀXQWLOꢀDꢀSUHFKDUJHꢀFRPꢃ
PDQGꢀLVꢀLVVXHGꢀWRꢀWKDWꢀEDQNꢁꢀ$ꢀSUHFKDUJHꢀFRPPDQGꢀPXVWꢀEHꢀLVVXHGꢀEHIRUHꢀRSHQLQJꢀDꢀGLIIHUHQWꢀ
URZꢀLQꢀWKHꢀVDPHꢀEDQNꢁ
7KHꢀ5HDGꢀFRPPDQGꢀLVꢀXVHGꢀWRꢀLQLWLDWHꢀDꢀEXUVWꢀUHDGꢀDFFHVVꢀWRꢀDQꢀDFWLYHꢀURZꢁꢀ7KHꢀYDOXHꢀRQꢀWKHꢀ%$ꢉꢂꢀ
%$ꢊꢀLQSXWVꢀVHOHFWVꢀWKHꢀEDQNꢂꢀDQGꢀWKHꢀDGGUHVVꢀSURYLGHGꢀRQꢀLQSXWVꢀ$ꢊ±$ꢈꢀVHOHFWVꢀWKHꢀVWDUWLQJꢀFROꢃ
XPQꢀORFDWLRQꢁꢀ7KHꢀYDOXHꢀRQꢀLQSXWꢀ$ꢊꢉꢀGHWHUPLQHVꢀZKHWKHUꢀRUꢀQRWꢀDXWRꢀSUHFKDUJHꢀLVꢀXVHGꢁꢀ,IꢀDXWRꢀ
SUHFKDUJHꢀLVꢀVHOHFWHGꢂꢀWKHꢀURZꢀEHLQJꢀDFFHVVHGꢀZLOOꢀEHꢀSUHFKDUJHGꢀDWꢀWKHꢀHQGꢀRIꢀWKHꢀUHDGꢀEXUVWꢕꢀLIꢀ
DXWRꢀSUHFKDUJHꢀLVꢀQRWꢀVHOHFWHGꢂꢀWKHꢀURZꢀZLOOꢀUHPDLQꢀRSHQꢀIRUꢀVXEVHTXHQWꢀDFFHVVHVꢁꢀ5HDGꢀGDWDꢀDSꢃ
SHDUVꢀRQꢀWKHꢀ'4ꢀVXEMHFWꢀWRꢀWKHꢀORJLFꢀOHYHOꢀRQꢀWKHꢀ'40ꢀLQSXWVꢀWZRꢀFORFNVꢀHDUOLHUꢁꢀ,IꢀDꢀJLYHQꢀ'40ꢀ
VLJQDOꢀZDVꢀUHJLVWHUHGꢀ+LJKꢂꢀWKHꢀFRUUHVSRQGLQJꢀ'4ꢀZLOOꢀEHꢀ+LJKꢃ=ꢀWZRꢀFORFNVꢀODWHUꢕꢀLIꢀWKHꢀ'40ꢀVLJQDOꢀ
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104
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Burst Terminate
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
105
A d v a n c e I n f o r m a t i o n
Operation
Bank/Row Activation
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ꢁ
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
A0–A10, A11
BA0, BA1
ADDRESS
BANK
ADDRESS
DON’T CARE
Figure 28. Activating a Specific Row in a Specific Bank Register
106
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
CLK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD
DON’T CARE
Figure 29. Meeting t
when 2 < t
/t ≤ 3
RCD (MIN) CK
RCD (MIN)
Reads
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FDQꢀEHꢀDYRLGHGꢁꢀ,QꢀDꢀJLYHQꢀV\VWHPꢀGHVLJQꢂꢀWKHUHꢀPD\ꢀEHꢀDꢀSRVVLELOLW\ꢀWKDWꢀWKHꢀGHYLFHꢀGULYLQJꢀWKHꢀ
LQSXWꢀGDWDꢀZLOOꢀJRꢀ/RZꢃ=ꢀEHIRUHꢀWKHꢀ6'5$0ꢀ'4ꢀJRꢀ+LJKꢃ=ꢁꢀ,QꢀWKLVꢀFDVHꢂꢀDWꢀOHDVWꢀDꢀVLQJOHꢀF\FOHꢀGHOD\ꢀ
VKRXOGꢀRFFXUꢀEHWZHHQꢀWKHꢀODVWꢀUHDGꢀGDWDꢀDQGꢀWKHꢀ:ULWHꢀFRPPDQGꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
107
A d v a n c e I n f o r m a t i o n
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A8
A9, A11
A10
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,1
DON’T CARE
Figure 30. Read Command
108
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COLn
BANK,
COLb
ADDRESS
DQ
D
OUT
D
n +
OUT
DOUT
D
n +
OUT
DOUT
b
n
1
n +
2
3
CAS Latency = 2
T1
T0
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COLn
BANK,
COLb
ADDRESS
DQ
D
OUT
DOUT
D
n +
OUT
D
n + 3
OUT
D
OUT
n
n +
1
2
b
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 31. Consecutive Read Bursts
1RWHꢀꢂ(DFKꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂ/RZꢁ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COLn
BANK,
COLa
BANK,
COLx
BANK,
COLm
D
OUT
D
a
OUT
D
OUT
DOUT
n
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLa
BANK,
COLx
BANK,
COLm
D
n
OUT
D
OUT
D
OUT
DOUT
a
x
m
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 32. Random Read Accesses
1RWHꢀꢂ(DFKꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂORZꢁ
7KHꢀ'40ꢀLQSXWꢀLVꢀXVHGꢀWRꢀDYRLGꢀ,ꢒ2ꢀFRQWHQWLRQꢂꢀDVꢀVKRZQꢀLQꢀ)LJXUHꢀꢋꢋꢀDQGꢀ)LJXUHꢀꢋꢑꢁꢀ7KHꢀ'40ꢀ
VLJQDOꢀPXVWꢀEHꢀDVVHUWHGꢀꢅ+LJKꢆꢀDWꢀOHDVWꢀWZRꢀFORFNVꢀSULRUꢀWRꢀWKHꢀ:ULWHꢀFRPPDQGꢀꢅ'40ꢀODWHQF\ꢀLVꢀ
WZRꢀFORFNVꢀIRUꢀRXWSXWꢀEXIIHUVꢆꢀWRꢀVXSSUHVVꢀGDWDꢃRXWꢀIURPꢀWKHꢀ5HDGꢁꢀ2QFHꢀWKHꢀ:ULWHꢀFRPPDQGꢀLVꢀ
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
109
A d v a n c e I n f o r m a t i o n
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5HDGꢀFRPPDQGꢁꢀ,IꢀQRWꢂꢀWKHꢀVHFRQGꢀ:ULWHꢀZLOOꢀEHꢀDQꢀLQYDOLGꢀ:ULWHꢁꢀ)RUꢀH[DPSOHꢂꢀLIꢀ'40ꢀZDVꢀ/RZꢀ
GXULQJꢀ7ꢑꢀLQꢀ)LJXUHꢀꢋꢍꢂꢀWKHQꢀWKHꢀ:ULWHVꢀDWꢀ7ꢍꢀDQGꢀ7ꢏꢀZRXOGꢀEHꢀYDOLGꢂꢀZKLOHꢀWKHꢀ:ULWHꢀDWꢀ7ꢇꢀZRXOGꢀ
EHꢀLQYDOLGꢁ
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WKHꢀVDPHꢀIL[HGꢃOHQJWKꢀEXUVWꢀZLWKꢀDXWRꢀSUHFKDUJHꢁꢀ7KHꢀGLVDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀ
LVꢀWKDWꢀLWꢀUHTXLUHVꢀWKDWꢀWKHꢀFRPPDQGꢀDQGꢀDGGUHVVꢀEXVHVꢀEHꢀDYDLODEOHꢀDWꢀWKHꢀDSSURSULDWHꢀWLPHꢀWRꢀ
LVVXHꢀWKHꢀFRPPDQGꢕꢀWKHꢀDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀLVꢀWKDWꢀLWꢀFDQꢀEHꢀXVHGꢀWRꢀWUXQFDWHꢀ
IL[HGꢃOHQJWKꢀRUꢀIXOOꢃSDJHꢀEXUVWVꢁ
T0
T1
T2
T3
T4
CLK
DQM
READ
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COLn
BANK,
COLb
t
CK
t
HZ
DOUT
n
DIN b
DQ
t
DS
Figure 33. Read to Write
110
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
CLK
DQM
READ
NOP
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COLb
BANK,
COLn
t
HZ
DOUT
n
DIN
b
DQ
t
DS
DON’T CARE
Figure 34. Read to Write with Extra Clock Cycle
1RWHꢀꢂ$ꢂ&$6ꢂODWHQF\ꢂRIꢂWKUHHꢂLVꢂXVHGꢂIRUꢂLOOXVWUDWLRQꢁꢂ7KHꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢇꢂDQGꢂWKHꢂ
:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK
(a or all)
BANKa,
COLn
BANKa,
ROW
D
OUT
D
n +
OUT
D
n +
OUT
DOUT
n +
n
1
2
3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 2 cycles
BANK
(a or all)
BANKa,
COLn
BANKa,
ROW
D
OUT
D
n +
OUT
D
n +
OUT
DOUT
n + 3
n
1
2
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 35. Read to Precharge
1RWHꢀꢂ'40ꢂLVꢂORZꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
111
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK,
COLn
D
OUT
D
n +
OUT
DOUT
DOUT
n + 3
n
1
n +
2
CAS Latency = 2
T1
T0
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COLn
D
OUT
D
OUT
D
n +
OUT
DOUT
n + 3
n
n +
1
2
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 36. Terminating a Read Burst
1RWHꢀꢂ'40ꢂLVꢂORZꢁ
)XOOꢃSDJHꢀ5HDGꢀEXUVWVꢀFDQꢀEHꢀWUXQFDWHGꢀZLWKꢀWKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢂꢀDQGꢀIL[HGꢃOHQJWKꢀ
5HDGꢀEXUVWVꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢂꢀSURYLGHGꢀWKDWꢀDXWRꢀSUHFKDUJHꢀ
ZDVꢀQRWꢀDFWLYDWHGꢁꢀ7KHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢀVKRXOGꢀEHꢀLVVXHGꢀ[ꢀF\FOHVꢀEHIRUHꢀWKHꢀFORFNꢀHGJHꢀ
DWꢀZKLFKꢀWKHꢀODVWꢀGHVLUHGꢀGDWDꢀHOHPHQWꢀLVꢀYDOLGꢂꢀZKHUHꢀ[ꢀHTXDOVꢀWKHꢀ&$6ꢀODWHQF\ꢀPLQXVꢀRQHꢁꢀ7KLVꢀ
LVꢀVKRZQꢀLQꢀ)LJXUHꢀꢋꢇꢀIRUꢀHDFKꢀSRVVLEOHꢀ&$6ꢀODWHQF\ꢕꢀGDWDꢀHOHPHQWꢀQꢂꢔꢂꢅꢀLVꢀWKHꢀODVWꢀGHVLUHGꢀGDWDꢀ
HOHPHQWꢀRIꢀDꢀORQJHUꢀEXUVWꢁ
Writes
:ULWHꢀEXUVWVꢀDUHꢀLQLWLDWHGꢀZLWKꢀDꢀ:ULWHꢀFRPPDQGꢂꢀDVꢀVKRZQꢀLQꢀ)LJXUHꢀꢋꢏꢁ
7KHꢀVWDUWLQJꢀFROXPQꢀDQGꢀEDQNꢀDGGUHVVHVꢀDUHꢀSURYLGHGꢀZLWKꢀWKHꢀ:ULWHꢀFRPPDQGꢂꢀDQGꢀDXWRꢀSUHꢃ
FKDUJHꢀLVꢀHLWKHUꢀHQDEOHGꢀRUꢀGLVDEOHGꢀIRUꢀWKDWꢀDFFHVVꢁꢀ,IꢀDXWRꢀSUHFKDUJHꢀLVꢀHQDEOHGꢂꢀWKHꢀURZꢀEHLQJꢀ
DFFHVVHGꢀLVꢀSUHFKDUJHGꢀDWꢀWKHꢀFRPSOHWLRQꢀRIꢀWKHꢀEXUVWꢁꢀ)RUꢀWKHꢀJHQHULFꢀ:ULWHꢀFRPPDQGVꢀXVHGꢀLQꢀ
WKHꢀIROORZLQJꢀLOOXVWUDWLRQVꢂꢀDXWRꢀSUHFKDUJHꢀLVꢀGLVDEOHGꢁ
'XULQJꢀ:ULWHꢀEXUVWVꢂꢀWKHꢀILUVWꢀYDOLGꢀGDWDꢃLQꢀHOHPHQWꢀZLOOꢀEHꢀUHJLVWHUHGꢀFRLQFLGHQWꢀZLWKꢀWKHꢀ:ULWHꢀ
FRPPDQGꢁꢀ6XEVHTXHQWꢀGDWDꢀHOHPHQWVꢀZLOOꢀEHꢀUHJLVWHUHGꢀRQꢀHDFKꢀVXFFHVVLYHꢀSRVLWLYHꢀFORFNꢀHGJHꢁꢀ
8SRQꢀFRPSOHWLRQꢀRIꢀDꢀIL[HGꢃOHQJWKꢀEXUVWꢂꢀDVVXPLQJꢀQRꢀRWKHUꢀFRPPDQGVꢀKDYHꢀEHHQꢀLQLWLDWHGꢂꢀWKHꢀ
'4ꢀZLOOꢀUHPDLQꢀ+LJKꢃ=ꢀDQGꢀDQ\ꢀDGGLWLRQDOꢀLQSXWꢀGDWDꢀZLOOꢀEHꢀLJQRUHGꢀꢅVHHꢀ)LJXUHꢀꢋꢐꢆꢁꢀ$ꢀIXOOꢃSDJHꢀ
EXUVWꢀZLOOꢀFRQWLQXHꢀXQWLOꢀWHUPLQDWHGꢁꢀꢅ$WꢀWKHꢀHQGꢀRIꢀWKHꢀSDJHꢂꢀLWꢀZLOOꢀZUDSꢀWRꢀFROXPQꢀꢉꢀDQGꢀ
FRQWLQXHꢁꢆ
112
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A8
A9, A11
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
BANK
ADDRESS
BA0,1
VALID ADDRESS
DON’T CARE
Figure 37. Write Command
'DWDꢀIRUꢀDQ\ꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀVXEVHTXHQWꢀ:ULWHꢀFRPPDQGꢂꢀDQGꢀGDWDꢀIRUꢀDꢀ
IL[HGꢀOHQJWKꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀLPPHGLDWHO\ꢀIROORZHGꢀE\ꢀGDWDꢀIRUꢀDꢀ:ULWHꢀFRPPDQGꢁꢀ7KHꢀQHZꢀ
:ULWHꢀFRPPDQGꢀFDQꢀEHꢀLVVXHGꢀRQꢀDQ\ꢀFORFNꢀIROORZLQJꢀWKHꢀSUHYLRXVꢀ:ULWHꢀFRPPDQGꢂꢀDQGꢀWKHꢀGDWDꢀ
SURYLGHGꢀFRLQFLGHQWꢀZLWKꢀWKHꢀQHZꢀFRPPDQGꢀDSSOLHVꢀWRꢀWKHꢀQHZꢀFRPPDQGꢁꢀ$QꢀH[DPSOHꢀLVꢀVKRZQꢀ
LQꢀ)LJXUHꢀꢑꢉꢁꢀ'DWDꢀQꢂꢔꢂꢀꢀLVꢀHLWKHUꢀWKHꢀODVWꢀRIꢀDꢀEXUVWꢀRIꢀWZRꢀRUꢀWKHꢀODVWꢀGHVLUHGꢀRIꢀDꢀORQJHUꢀEXUVWꢁꢀ
7KHꢀꢊꢌꢈ0Eꢀ6'5$0ꢀXVHVꢀDꢀSLSHOLQHGꢀDUFKLWHFWXUHꢀDQGꢀWKHUHIRUHꢀGRHVꢀQRWꢀUHTXLUHꢀWKHꢀꢄQꢀUXOHꢀDVꢃ
VRFLDWHGꢀZLWKꢀDꢀSUHIHWFKꢀDUFKLWHFWXUHꢁꢀ$ꢀ:ULWHꢀFRPPDQGꢀFDQꢀEHꢀLQLWLDWHGꢀRQꢀDQ\ꢀFORFNꢀF\FOHꢀ
IROORZLQJꢀDꢀSUHYLRXVꢀ:ULWHꢀFRPPDQGꢁꢀ)XOOꢃVSHHGꢀUDQGRPꢀZULWHꢀDFFHVVHVꢀZLWKLQꢀDꢀSDJHꢀFDQꢀEHꢀSHUꢃ
IRUPHGꢀWRꢀWKHꢀVDPHꢀEDQNꢂꢀDVꢀVKRZQꢀLQꢀ)LJXUHꢀꢑꢉꢂꢀRUꢀHDFKꢀVXEVHTXHQWꢀ:ULWHꢀPD\ꢀEHꢀSHUIRUPHGꢀWRꢀ
DꢀGLIIHUHQWꢀEDQNꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
113
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
CLK
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
DIN
n
DIN
n + 1
DON’T CARE
Figure 38. Write Burst
1RWHꢀꢂ%XUVWꢂOHQJWKꢂ ꢂꢄꢁꢂ'40ꢂLVꢂORZꢁ
T0
T1
T2
CLK
WRITE
NOP
WRITE
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLb
DIN
n
DIN
n + 1
DIN
b
DON’T CARE
Figure 39. Write to Write
1RWHꢀꢂ'40ꢂLVꢂORZꢁꢂ(DFKꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁ
'DWDꢀIRUꢀDQ\ꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀVXEVHTXHQWꢀ5HDGꢀFRPPDQGꢂꢀDQGꢀGDWDꢀIRUꢀDꢀIL[HGꢀ
OHQJWKꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀLPPHGLDWHO\ꢀIROORZHGꢀE\ꢀDꢀ5HDGꢀFRPPDQGꢁꢀ2QFHꢀWKHꢀ5HDGꢀFRPPDQGꢀ
LVꢀUHJLVWHUHGꢂꢀWKHꢀGDWDꢀLQSXWVꢀZLOOꢀEHꢀLJQRUHGꢂꢀDQGꢀZULWHVꢀZLOOꢀQRWꢀEHꢀH[HFXWHGꢁꢀ$QꢀH[DPSOHꢀLVꢀVKRZQꢀ
LQꢀ)LJXUHꢀꢑꢊꢁꢀ'DWDꢀQꢂꢔꢂꢀꢀLVꢀHLWKHUꢀWKHꢀODVWꢀRIꢀDꢀEXUVWꢀRIꢀWZRꢀRUꢀWKHꢀODVWꢀGHVLUHGꢀRIꢀDꢀORQJHUꢀEXUVWꢁ
'DWDꢀIRUꢀDꢀIL[HGꢃOHQJWKꢀ:ULWHꢀEXUVWꢀPD\ꢀEHꢀIROORZHGꢀE\ꢂꢀRUꢀWUXQFDWHGꢀZLWKꢂꢀDꢀ3UHFKDUJHꢀFRPPDQGꢀ
WRꢀWKHꢀVDPHꢀEDQNꢀꢅSURYLGHGꢀWKDWꢀDXWRꢀSUHFKDUJHꢀZDVꢀQRWꢀDFWLYDWHGꢆꢂꢀDQGꢀDꢀIXOOꢃSDJHꢀ:ULWHꢀEXUVWꢀ
PD\ꢀEHꢀWUXQFDWHGꢀZLWKꢀDꢀ3UHFKDUJHꢀFRPPDQGꢀWRꢀWKHꢀVDPHꢀEDQNꢁꢀ7KHꢀ3UHFKDUJHꢀFRPPDQGꢀVKRXOGꢀ
EHꢀLVVXHGꢀW:5ꢀDIWHUꢀWKHꢀFORFNꢀHGJHꢀDWꢀZKLFKꢀWKHꢀODVWꢀGHVLUHGꢀLQSXWꢀGDWDꢀHOHPHQWꢀLVꢀUHJLVWHUHGꢁꢀ7KHꢀ
DXWRꢀSUHFKDUJHꢀPRGHꢀUHTXLUHVꢀDꢀW:5ꢀRIꢀDWꢀOHDVWꢀRQHꢀFORFNꢀSOXVꢀWLPHꢂꢀUHJDUGOHVVꢀRIꢀIUHTXHQF\ꢁ
,QꢀDGGLWLRQꢂꢀZKHQꢀWUXQFDWLQJꢀDꢀ:ULWHꢀEXUVWꢂꢀWKHꢀ'40ꢀVLJQDOꢀPXVWꢀEHꢀXVHGꢀWRꢀPDVNꢀLQSXWꢀGDWDꢀIRUꢀ
WKHꢀFORFNꢀHGJHꢀSULRUꢀWRꢂꢀDQGꢀWKHꢀFORFNꢀHGJHꢀFRLQFLGHQWꢀZLWKꢂꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢁꢀ$QꢀH[DPSOHꢀ
LVꢀVKRZQꢀLQꢀ)LJXUHꢀꢑꢌꢁꢀ'DWDꢀQꢂꢔꢂꢀꢀLVꢀHLWKHUꢀWKHꢀODVWꢀRIꢀDꢀEXUVWꢀRIꢀWZRꢀRUꢀWKHꢀODVWꢀGHVLUHGꢀRIꢀDꢀORQJHUꢀ
EXUVWꢁꢀ)ROORZLQJꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢂꢀDꢀVXEVHTXHQWꢀFRPPDQGꢀWRꢀWKHꢀVDPHꢀEDQNꢀFDQQRWꢀEHꢀ
LVVXHGꢀXQWLOꢀW53ꢀLVꢀPHWꢁ
114
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
CLK
WRITE
WRITE
WRITE
WRITE
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLa
BANK,
COLx
BANK,
COLm
D
IN
D
IN
D
IN
DIN
m
n
a
x
DON’T CARE
Figure 40. Random Write Cycles
1RWHꢀꢂ(DFKꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂORZꢁ
T0
T1
T2
T3
T4
T5
CLK
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
BANK,
COLb
DIN
n
DIN
n + 1
D
OUT
DOUT
b + 1
b
DON’T CARE
Figure 41. Write to Read
1RWHꢀꢂ7KHꢂ:ULWHꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢇꢂDQGꢂWKHꢂ5HDGꢂFRPPDQGꢂPD\ꢂEHꢂWRꢂDQ\ꢂEDQNꢁꢂ'40ꢂLVꢂ
ORZꢁꢂ&$6ꢂODWHQF\ꢂ ꢂꢄꢂIRUꢂLOOXVWUDWLRQꢁ
,QꢀWKHꢀFDVHꢀRIꢀDꢀIL[HGꢃOHQJWKꢀEXUVWꢀEHLQJꢀH[HFXWHGꢀWRꢀFRPSOHWLRQꢂꢀDꢀ3UHFKDUJHꢀFRPPDQGꢀLVVXHGꢀ
DWꢀWKHꢀRSWLPXPꢀWLPHꢀꢅDVꢀGHVFULEHGꢀDERYHꢆꢀSURYLGHVꢀWKHꢀVDPHꢀRSHUDWLRQꢀWKDWꢀZRXOGꢀUHVXOWꢀIURPꢀ
WKHꢀVDPHꢀIL[HGꢃOHQJWKꢀEXUVWꢀZLWKꢀDXWRꢀSUHFKDUJHꢁꢀ7KHꢀGLVDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀ
LVꢀWKDWꢀLWꢀUHTXLUHVꢀWKDWꢀWKHꢀFRPPDQGꢀDQGꢀDGGUHVVꢀEXVHVꢀEHꢀDYDLODEOHꢀDWꢀWKHꢀDSSURSULDWHꢀWLPHꢀWRꢀ
LVVXHꢀWKHꢀFRPPDQGꢕꢀWKHꢀDGYDQWDJHꢀRIꢀWKHꢀ3UHFKDUJHꢀFRPPDQGꢀLVꢀWKDWꢀLWꢀFDQꢀEHꢀXVHGꢀWRꢀWUXQFDWHꢀ
IL[HGꢃOHQJWKꢀRUꢀIXOOꢃSDJHꢀEXUVWVꢁ
)L[HGꢃOHQJWKꢀRUꢀIXOOꢃSDJHꢀ:ULWHꢀEXUVWVꢀFDQꢀEHꢀWUXQFDWHGꢀZLWKꢀWKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢁꢀ:KHQꢀ
WUXQFDWLQJꢀDꢀ:ULWHꢀEXUVWꢂꢀWKHꢀLQSXWꢀGDWDꢀDSSOLHGꢀFRLQFLGHQWꢀZLWKꢀWKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢀZLOOꢀ
EHꢀLJQRUHGꢁꢀ7KHꢀODVWꢀGDWDꢀZULWWHQꢀꢅSURYLGHGꢀWKDWꢀ'40ꢀLVꢀ/RZꢀDWꢀWKDWꢀWLPHꢆꢀZLOOꢀEHꢀWKHꢀLQSXWꢀGDWDꢀ
DSSOLHGꢀRQHꢀFORFNꢀSUHYLRXVꢀWRꢀWKHꢀ%XUVWꢀ7HUPLQDWHꢀFRPPDQGꢁꢀ7KLVꢀLVꢀVKRZQꢀLQꢀ)LJXUHꢀꢑꢑꢂꢀZKHUHꢀ
GDWDꢀQꢀLVꢀWKHꢀODVWꢀGHVLUHGꢀGDWDꢀHOHPHQWꢀRIꢀDꢀORQJHUꢀEXUVWꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
115
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
CLK
t
t
WR@ CK 15ns
DQM
t
RP
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
DIN
n
DIN
DQ
n
+ 1
t
t
WR@ CK < 15ns
DQM
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
DIN
n
DIN
+ 1
DQ
n
DON’T CARE
Figure 42. Write to Precharge
1RWHꢀꢂ'40ꢂFRXOGꢂUHPDLQꢂORZꢂLQꢂWKLVꢂH[DPSOHꢂLIꢂWKHꢂ:ULWHꢂEXUVWꢂLVꢂDꢂIL[HGꢂOHQJWKꢂRIꢂWZRꢁ
Precharge
7KHꢀ3UHFKDUJHꢀFRPPDQGꢀꢅVHHꢀ)LJXUHꢀꢑꢍꢆꢀLVꢀXVHGꢀWRꢀGHDFWLYDWHꢀWKHꢀRSHQꢀURZꢀLQꢀDꢀSDUWLFXODUꢀEDQNꢀ
RUꢀWKHꢀRSHQꢀURZꢀLQꢀDOOꢀEDQNVꢁꢀ7KHꢀEDQNꢅVꢆꢀZLOOꢀEHꢀDYDLODEOHꢀIRUꢀDꢀVXEVHTXHQWꢀURZꢀDFFHVVꢀVRPHꢀVSHFꢃ
LILHGꢀWLPHꢀꢅW53ꢆꢀDIWHUꢀWKHꢀSUHFKDUJHꢀFRPPDQGꢀLVꢀLVVXHGꢁꢀ,QSXWꢀ$ꢊꢉꢀGHWHUPLQHVꢀZKHWKHUꢀRQHꢀRUꢀDOOꢀ
EDQNVꢀDUHꢀWRꢀEHꢀSUHFKDUJHGꢂꢀDQGꢀLQꢀWKHꢀFDVHꢀZKHUHꢀRQO\ꢀRQHꢀEDQNꢀLVꢀWRꢀEHꢀSUHFKDUJHGꢂꢀLQSXWVꢀ%$ꢉꢂꢀ
%$ꢊꢀVHOHFWꢀWKHꢀEDQNꢁꢀ:KHQꢀDOOꢀEDQNVꢀDUHꢀWRꢀEHꢀSUHFKDUJHGꢂꢀLQSXWVꢀ%$ꢉꢂꢀ%$ꢊꢀDUHꢀWUHDWHGꢀDVꢀ³'RQ¶Wꢀ
&DUHꢁ´ꢀ2QFHꢀDꢀEDQNꢀKDVꢀEHHQꢀSUHFKDUJHGꢂꢀLWꢀLVꢀLQꢀWKHꢀLGOHꢀVWDWHꢀDQGꢀPXVWꢀEHꢀDFWLYDWHGꢀSULRUꢀWRꢀDQ\ꢀ
5HDGꢀRUꢀ:ULWHꢀFRPPDQGVꢀEHLQJꢀLVVXHGꢀWRꢀWKDWꢀEDQNꢁ
Power-down
3RZHUꢃGRZQꢀRFFXUVꢀLIꢀ&.(ꢀLVꢀUHJLVWHUHGꢀORZꢀFRLQFLGHQWꢀZLWKꢀDꢀ123ꢀRUꢀ&RPPDQGꢀ,QKLELWꢀZKHQꢀQRꢀ
DFFHVVHVꢀDUHꢀLQꢀSURJUHVVꢁꢀ,IꢀSRZHUꢃGRZQꢀRFFXUVꢀZKHQꢀDOOꢀEDQNVꢀDUHꢀLGOHꢂꢀWKLVꢀPRGHꢀLVꢀUHIHUUHGꢀWRꢀ
DVꢀSUHFKDUJHꢀSRZHUꢃGRZQꢕꢀLIꢀSRZHUꢃGRZQꢀRFFXUVꢀZKHQꢀWKHUHꢀLVꢀDꢀURZꢀDFWLYHꢀLQꢀDQ\ꢀEDQNꢂꢀWKLVꢀ
PRGHꢀLVꢀUHIHUUHGꢀWRꢀDVꢀDFWLYHꢀSRZHUꢃGRZQꢁꢀ(QWHULQJꢀSRZHUꢃGRZQꢀGHDFWLYDWHVꢀWKHꢀLQSXWꢀDQGꢀRXWSXWꢀ
EXIIHUVꢂꢀH[FOXGLQJꢀ&.(ꢂꢀIRUꢀPD[LPXPꢀSRZHUꢀVDYLQJVꢀZKLOHꢀLQꢀVWDQGE\ꢁꢀ7KHꢀGHYLFHꢀPD\ꢀQRWꢀUHPDLQꢀ
LQꢀWKHꢀSRZHUꢃGRZQꢀVWDWHꢀORQJHUꢀWKDQꢀWKHꢀUHIUHVKꢀSHULRGꢀꢅꢇꢑPVꢆꢀVLQFHꢀQRꢀUHIUHVKꢀRSHUDWLRQVꢀDUHꢀ
SHUIRUPHGꢀLQꢀWKLVꢀPRGHꢁꢀ7KHꢀSRZHUꢃGRZQꢀVWDWHꢀLVꢀH[LWHGꢀE\ꢀUHJLVWHULQJꢀDꢀ123ꢀRUꢀ&RPPDQGꢀ,QKLELWꢀ
DQGꢀ&.(ꢀ+LJKꢀDWꢀWKHꢀGHVLUHGꢀFORFNꢀHGJHꢀꢅPHHWLQJꢀW&.6ꢆꢁꢀ6HHꢀ)LJXUHꢀꢑꢋꢁ
116
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
((
))
((
))
CLK
> t
t
CKS
CKS
CKE
((
))
((
))
((
))
COMMAND
NOP
NOP
ACTIVE
t
t
t
All banks idle
RCD
RAS
RC
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
Figure 43. Power-Down
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
WRITE
COMMAND
ADDRESS
DQ
BANK,
COLn
(ADDRESS)
(DATA)
DIN
n
TRANSITIONING DATA
DON’T CARE
Figure 44. Terminating a Write Burst
1RWHꢀꢂ'40VꢂDUHꢂORZꢁ
CLK
CKE
CS#
HIGH
RAS#
CAS#
WE#
A0-A9, A11
A10
All Banks
Bank Selected
BANK
ADDRESS
BA0,1
VALID ADDRESS
DON’T CARE
Figure 45. Precharge Command
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
117
A d v a n c e I n f o r m a t i o n
Deep Power-down
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T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
BANK,
COLn
D
n
IN
D
n + 1
IN
DIN
n + 2
DIN
DON’T CARE
Figure 46. Clock Suspend During Write Burst
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118
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COLn
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
DON’T CARE
Figure 47. Clock Suspend During Read Burst
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Concurrent Auto Precharge
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T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANKn
READ - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
t
RP - BANKn
RP - BANKm
Internal
States
Page Active
READ with Burst of 4
Precharge
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
DQ
D
a
OUT
D
a + 1
OUT
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANKm)
DON’T CARE
Figure 48. Read with Auto precharge Interrupted by a Read
1RWHꢀꢂ'40ꢂLVꢂORZꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
119
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANKn
WRITE - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
Idle
WR -BANKm
Active
t
RP -BANK
n
Internal
States
WRITE with Burst of 4
Write-Back
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
1
DQM
D
OUT
DIN
d
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
DQ
a
CAS Latency = 3 (BANKn)
DON’T CARE
Figure 49. Read with Auto Precharge Interrupted by a Write
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287
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T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANKn
READ - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back Precharge
t
RP - BANKn
t
WR - BANKn
Internal
States
t
RP - BANKm
Page Active
READ with Burst of 4
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
DQ
DIN
a
D
a + 1
IN
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANKm)
DON’T CARE
Figure 50. Write with Auto Precharge Interrupted by a Read
1RWHꢀꢂ'40ꢂLVꢂORZꢁ
120
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
&RPPDQGꢀ,QRKZLEHLUWꢃ
'RURZ12Qꢀ3(3QWU\
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANKn
WRITE - AP
BANKm
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
BANKn
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back Precharge
t
RP - BANKn
t
WR - BANKn
Internal
States
t
WR - BANKm
Write-Back
Page Active
WRITE with Burst of 4
BANKm
BANKn,
COLa
BANKm,
COLd
ADDRESS
DQ
DIN
a
D
a + 1
IN
D
a + 2
IN
DIN
d
D
d + 1
IN
D
d + 2
IN
D
d + 3
IN
DON’T CARE
Figure 51. Write with Auto Precharge Interrupted by a Write
1RWHꢀꢂ'40ꢂLVꢂORZꢁ
Table 33. Truth Table 2—CKE
CKE
CKE
Current State
3RZHUꢃ'RZQ
Command
Action
n
Notes
n-1
n
n
;
;
;
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S75NS128NDE based MCPs
121
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Table 34. Truth Table 3 — Current State Bank n, Command to Bank n
Current State
CS# RAS# CAS# WE#
Command (Action)
Notes
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S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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Table 35. Truth Table 4 — Current State Bank n, Command to Bank m
Current State
CS# RAS# CAS# WE#
Command (Action)
Notes
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
123
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ꢀꢌꢁ)RUꢂDꢂ:ULWHꢂZLWKꢂDXWRꢂSUHFKDUJHꢂLQWHUUXSWHGꢂE\ꢂDꢂ5HDGꢂꢍZLWKꢂRUꢂZLWKRXWꢂDXWRꢂSUHFKDUJHꢎꢇꢂWKHꢂ5HDGꢂ
WRꢂEDQNꢂPꢂZLOOꢂLQWHUUXSWꢂWKHꢂ:ULWHꢂRQꢂEDQNꢂQꢂZKHQꢂUHJLVWHUHGꢇꢂZLWKꢂWKHꢂGDWDꢉRXWꢂDSSHDULQJꢂ&$6ꢂODꢉ
WHQF\ꢂODWHUꢂꢍ)LJXUHꢂꢊꢈꢎꢁꢂ7KHꢂ3UHFKDUJHꢂWRꢂEDQNꢂQꢂZLOOꢂEHJLQꢂDIWHUꢂW ꢂLVꢂPHWꢇꢂZKHUHꢂW ꢂEHJLQVꢂZKHQꢂ
:5
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SULRUꢂWRꢂWKHꢂ5HDGꢂWRꢂEDQNꢂPꢁ
ꢀꢒꢁ)RUꢂDꢂ:ULWHꢂZLWKꢂDXWRꢂSUHFKDUJHꢂLQWHUUXSWHGꢂE\ꢂDꢂ:ULWHꢂꢍZLWKꢂRUꢂZLWKRXWꢂDXWRꢂSUHFKDUJHꢎꢇꢂWKHꢂ:ULWHꢂ
WRꢂEDQNꢂPꢂZLOOꢂLQWHUUXSWꢂWKHꢂ:ULWHꢂRQꢂEDQNꢂQꢂZKHQꢂUHJLVWHUHGꢁꢂ7KHꢂ3UHFKDUJHꢂWRꢂEDQNꢂQꢂZLOOꢂEHJLQꢂ
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124
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
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9ROWDJHꢀRQꢀ9''ꢒ9''4ꢀ6XSSO\ꢀ5HODWLYHꢀWRꢀ966 ꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀ ꢃꢉꢁꢋꢍ9ꢀWRꢀꢎꢌꢁꢈ9
9ROWDJHꢀRQꢀ,QSXWVꢂꢀ1&ꢀRUꢀ,ꢒ2ꢀ3LQVꢀ5HODWLYHꢀWRꢀ966ꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁ ꢃꢉꢁꢋꢍ9ꢀWRꢀꢎꢌꢁꢈ9
2SHUDWLQJꢀ7HPSHUDWXUHꢀ7$ꢀꢅ([WHQGHGꢆ ꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀ ꢃꢌꢍ&ꢀWRꢀꢎꢈꢍ&
6WRUDJHꢀ7HPSHUDWXUHꢀꢅSODVWLFꢆ ꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀ ꢃꢍꢍ&ꢀWRꢀꢎꢊꢍꢉ&
Table 36. DC Electrical Characteristics and Operating Conditions
-75
-10
Parameter
Symbol
Units
Notes
Min
ꢊꢁꢏ
Max
ꢊꢁꢐꢍ
ꢊꢁꢐꢍ
Min
ꢊꢁꢏ
ꢊꢁꢏ
Max
ꢊꢁꢐ
ꢊꢁꢐ
6XSSO\ꢀ9ROWDJH
9
''
,ꢒ2ꢀ6XSSO\ꢀ9ROWDJH
9
ꢊꢁꢏ
''4
,QSXWꢀ+LJKꢀ9ROWDJHꢄꢀ/RJLFꢀꢊꢕꢀ$OOꢀLQSXWV
,QSXWꢀ/RZꢀ9ROWDJHꢄꢀ/RJLFꢀꢉꢕꢀ$OOꢀLQSXWV
2XWSXWꢀ+LJKꢀ9ROWDJHꢄꢀ$OOꢀLQSXWV
2XWSXWꢀ/RZꢀ9ROWDJHꢄꢀ$OOꢀLQSXWV
,QSXWꢀ/HDNDJHꢀ&XUUHQWꢄ
9
ꢉꢁꢈꢀ[ꢀ9
9
ꢀꢎꢀꢉꢁꢋ ꢉꢁꢈꢀ[ꢀ9
9 ꢀꢎꢀꢉꢁꢋ
''
ꢑ
ꢑ
,+
''4
''
''4
9
9
ꢃꢉꢁꢋ
ꢎꢉꢁꢋ
ꢃꢉꢁꢋ
ꢎꢉꢁꢋ
,/
9
ꢉꢁꢐꢀ[ꢀ9
²
²
ꢉꢁꢐꢀ[ꢀ9
²
²
2+
''4
''4
9
ꢉꢁꢌ
ꢉꢁꢌ
2/
$Q\ꢀLQSXWꢀꢉ9ꢀ≤ꢀ9 ꢀ≤ 9
ꢀ
,
ꢃꢊꢁꢉ
ꢃꢊꢁꢍ
ꢊꢁꢉ
ꢊꢁꢍ
ꢃꢊꢁꢉ
ꢃꢊꢁꢍ
ꢊꢁꢉ
$
$
,1
''
,
ꢅ$OOꢀRWKHUꢀSLQVꢀQRWꢀXQGHUꢀWHVWꢀ ꢀꢉ9ꢆ
2XWSXWꢀ/HDNDJHꢀ&XUUHQWꢄꢀ'4ꢀGLVDEOHGꢕꢀ
,
ꢊꢁꢍ
2=
ꢉ9ꢀ≤ꢀ9
ꢀ≤ 9
287
''4
1RWHVꢀ
ꢀꢁ $OOꢂYROWDJHVꢂUHIHUHQFHGꢂWRꢂ9 ꢁꢂ9 ꢂ ꢂ9 ꢂ ꢂꢔꢀꢁꢆ9ꢂꢈꢁꢀ9ꢁ
''4
66
''
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IXOOꢂWHPSHUDWXUHꢂUDQJHꢂꢍꢉꢄꢊ&ꢂ≤ꢂ7 ꢂ≤ꢂꢔꢆꢊ&ꢂIRUꢂVWDQGDUGꢂSDUWVꢏꢂꢉꢋꢈ&ꢂ≤ꢂ7 ꢂ≤ꢂꢔꢆꢊ&ꢂIRUꢂ,7ꢂSDUWVꢎꢂLVꢂ
$
$
HQVXUHGꢁ
ꢅꢁ $QꢂLQLWLDOꢂSDXVHꢂRIꢂꢀꢈꢈVꢂLVꢂUHTXLUHGꢂDIWHUꢂSRZHUꢂXSꢇꢂIROORZHGꢂE\ꢂWZRꢂ$XWRꢂ5HIUHVKꢂFRPPDQGVꢇꢂEHꢉ
IRUHꢂSURSHUꢂGHYLFHꢂRSHUDWLRQꢂLVꢂHQVXUHGꢁꢂꢍ9 ꢂDQGꢂ9 ꢂPXVWꢂEHꢂSRZHUHGꢂXSꢂVLPXOWDQHRXVO\ꢁꢂ9
ꢂ
66
''
''4
DQGꢂ9
ꢂPXVWꢂEHꢂDWꢂVDPHꢂSRWHQWLDOꢁꢎꢂ7KHꢂWZRꢂ$XWRꢂ5HIUHVKꢂFRPPDQGꢂZDNHꢉXSVꢂVKRXOGꢂEHꢂUHSHDWHGꢂ
664
DQ\ꢂWLPHꢂWKHꢂW
ꢂUHIUHVKꢂUHTXLUHPHQWꢂLVꢂH[FHHGHGꢁ
5()
ꢋꢁ 9 ꢂRYHUVKRRWꢃꢂ9
ꢂ ꢂ9
ꢂꢔꢂꢄ9ꢂIRUꢂDꢂSXOVHꢂZLGWKꢂ≤ꢂꢅQVꢇꢂDQGꢂWKHꢂSXOVHꢂZLGWKꢂFDQQRWꢂEHꢂJUHDWHUꢂ
''4
,+
,+ꢂꢍ0$;ꢎ
WKDQꢂRQHꢂWKLUGꢂRIꢂWKHꢂF\FOHꢂUDWHꢁꢂ9 ꢂXQGHUVKRRWꢃꢂ9
ꢂ ꢂꢉꢄ9ꢂIRUꢂDꢂSXOVHꢂZLGWKꢂ≤ꢂꢅQVꢁ
,/
,/ꢂꢍ0,1ꢎ
Table 37. AC Electrical Characteristics and Operating Conditions
Parameter
Symbol
9,+
Min
ꢊꢁꢑ
²
Max
²
Units Notes
,QSXWꢀ+LJKꢀ9ROWDJHꢄꢀ/RJLFꢀꢊꢕꢀ$OOꢀLQSXWV
,QSXWꢀ/RZꢀ9ROWDJHꢄꢀ/RJLFꢀꢉꢕꢀ$OOꢀLQSXWV
9
9
9,/
ꢎꢉꢁꢑ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
125
A d v a n c e I n f o r m a t i o n
Table 38. Electrical Characteristics and Recommended AC Operating Conditions
AC Characteristics
-75
-10
Units Notes
Parameter
Symbol
Min
Max
ꢍꢁꢑ
ꢇ
Min
Max
ꢏ
&/ ꢋ
&/ ꢌ
W
W
ꢀꢅꢋꢆ
ꢀꢅꢌꢆ
ꢌꢏ
$FFHVVꢀWLPHꢀIURPꢀ&/.ꢀꢅSRVꢁꢀ
HGJHꢆ
$&
$&
ꢈ
$GGUHVVꢀKROGꢀWLPH
$GGUHVVꢀVHWXSꢀWLPH
&/.ꢀKLJKꢃOHYHOꢀZLGWK
&/.ꢀORZꢃOHYHOꢀZLGWK
W
ꢊ
ꢊ
ꢌꢁꢍ
ꢋ
$+
W
ꢌꢁꢍ
ꢌꢁꢍ
ꢌꢁꢍ
ꢏꢁꢍ
ꢊꢉ
$6
&+
W
W
ꢋ
&/
&/ ꢋ
&/ ꢌ
W
W
ꢀꢅꢋꢆ
ꢀꢅꢌꢆ
ꢊꢉꢉ
ꢊꢉꢉ
ꢐꢁꢇ
ꢊꢌ
ꢊ
ꢊꢉꢉ
ꢊꢉꢉ
ꢇ
ꢇ
&.
&.
&ORFNꢀF\FOHꢀWLPH
&.(ꢀKROGꢀWLPH
&.(ꢀVHWXSꢀWLPH
W
ꢊ
&.+
W
ꢌꢁꢍ
ꢌꢁꢍ
&.6
&6ꢓꢂꢀ5$6ꢓꢂꢀ&$6ꢓꢂꢀ:(ꢓꢂꢀ'40ꢀKROGꢀ
WLPH
W
ꢊ
ꢊ
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Table 39. AC Functional Characteristics
Parameter
5HDGꢒ:ULWHꢀFRPPDQGꢀWRꢀ5HDGꢒ:ULWHꢀFRPPDQG
&.(ꢀWRꢀFORFNꢀGLVDEOHꢀRUꢀSRZHUꢃGRZQꢀHQWU\ꢀPRGH
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'40ꢀWRꢀLQSXWꢀGDWDꢀGHOD\
Symbol
-75 & -10
Units
Notes
W
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Table 40. IDD Specifications and Conditions
-75
-10
Parameter/Condition
Symbol
Units
Notes
Max
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ꢐꢁ )RUꢂꢉꢀꢈꢇꢂ&/ꢂ ꢂꢅꢂDQGꢂW ꢂ ꢂꢐꢁꢌQVꢁ
&.
ꢀꢈꢁ&.(ꢂLVꢂ+LJKꢂGXULQJꢂUHIUHVKꢂFRPPDQGꢂSHULRGꢂW
ꢂHOVHꢂ&.(ꢂLVꢂ/RZꢁꢂ7KHꢂ,
ꢂOLPLWꢂLVꢂDFWXDOO\ꢂDꢂ
''ꢌ
5)&ꢂꢍ0,1ꢎ
QRPLQDOꢂYDOXHꢂDQGꢂGRHVꢂQRWꢂUHVXOWꢂLQꢂDꢂIDLOꢂYDOXHꢁ
ꢀꢀꢁ'HHSꢂSRZHUꢂGRZQꢂFXUUHQWꢂLVꢂDꢂQRPLQDOꢂYDOXHꢂDWꢂꢄꢊ&ꢁꢂ7KHꢂSDUDPHWHUꢂLVꢂQRWꢂWHVWHGꢁ
Table 41.
I
— Self Refresh Current Options
DD7
Temperature Compensated Self Refresh
Parameter/Condition
Max
Temperature
-75
-10
Units
Notes
ꢈꢍ&
ꢏꢉ&
ꢑꢍ&
ꢊꢍ&
ꢈꢍ&
ꢏꢉ&
ꢑꢍ&
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ꢈꢍ&
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ꢑꢍ&
ꢊꢍ&
ꢌꢌꢉ
ꢊꢏꢍ
ꢊꢍꢉ
ꢊꢌꢍ
ꢊꢇꢉ
ꢊꢌꢍ
ꢊꢌꢍ
ꢈꢍ
ꢌꢉꢉ
ꢊꢇꢉ
ꢊꢑꢉ
ꢊꢌꢉ
ꢊꢇꢉ
ꢊꢋꢉ
ꢊꢌꢉ
ꢊꢊꢉ
ꢊꢋꢉ
ꢊꢌꢉ
ꢊꢊꢉ
ꢊꢉꢉ
ꢊꢌꢉ
ꢊꢊꢉ
ꢊꢉꢉ
ꢐꢉ
6HOIꢀ5HIUHVKꢀ&XUUHQWꢄ
&.(ꢀꢔꢀꢉꢁꢌ9ꢀ±ꢀꢑꢀ%DQNVꢀ2SHQ
6HOIꢀ5HIUHVKꢀ&XUUHQWꢄ
&.(ꢀꢔꢀꢉꢁꢌ9ꢀ±ꢀꢌꢀ%DQNVꢀ2SHQ
ꢊꢋꢉ
ꢊꢉꢍ
ꢐꢉ
6HOIꢀ5HIUHVKꢀ&XUUHQWꢄ
&.(ꢀꢔꢀꢉꢁꢌ9ꢀ±ꢀꢊꢀ%DQNꢀ2SHQ
$
ꢌ
ꢏꢍ
7%'
7%'
7%'
7%'
7%'
7%'
7%'
7%'
6HOIꢀ5HIUHVKꢀ&XUUHQWꢄ
&.(ꢀꢔꢀꢉꢁꢌ9ꢀ±ꢀꢊꢒꢌꢀ%DQNꢀ2SHQ
ꢊꢊꢍ
ꢊꢉꢍ
ꢐꢍ
6HOIꢀ5HIUHVKꢀ&XUUHQWꢄ
&.(ꢀꢔꢀꢉꢁꢌ9ꢀ±ꢀꢊꢒꢑꢀ%DQNꢀ2SHQ
ꢐꢉ
1RWHVꢀ
ꢀꢁ 9 ꢂ ꢂ9
ꢂ ꢂꢔꢀꢁꢆ9ꢂꢈꢁꢀ9ꢁ
''4
''
ꢄꢁ (QDEOHVꢂRQꢉFKLSꢂUHIUHVKꢂDQGꢂDGGUHVVꢂFRXQWHUVꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
129
A d v a n c e I n f o r m a t i o n
Table 42. Capacitance
Parameter
Symbol
Min
ꢊꢁꢍ
ꢊꢁꢍ
ꢋꢁꢉ
Max
ꢑꢁꢉ
ꢑꢁꢉ
ꢇꢁꢉ
Units Notes
,QSXWꢀ&DSDFLWDQFHꢄꢀ&/.
&
&
S)
S)
S)
ꢌꢌꢐ
ꢋ
,ꢊ
,ꢌ
,2
,QSXWꢀ&DSDFLWDQFHꢄꢀ$OOꢀRWKHUꢀLQSXWꢃRQO\ꢀSLQV
,QSXWꢒ2XWSXWꢀ&DSDFLWDQFHꢄꢀ'4
&
ꢑ
1RWHVꢀ
ꢀꢁ 7KLVꢂSDUDPHWHUꢂLVꢂVDPSOHGꢁꢂ9 ꢇꢂ9
ꢂ ꢂꢔꢀꢁꢆ9ꢏꢂ7$ꢂ ꢂꢄꢊ&ꢏꢂSLQꢂXQGHUꢂWHVWꢂELDVHGꢂDWꢂꢀꢁꢋ9ꢁꢂIꢂ ꢂꢀꢂ
''4
''
0+]ꢁ
ꢄꢁ 3&ꢀꢈꢈꢂVSHFLILHVꢂDꢂPD[LPXPꢂRIꢂꢋS)ꢁ
ꢅꢁ 3&ꢀꢈꢈꢂVSHFLILHVꢂDꢂPD[LPXPꢂRIꢂꢊS)ꢁ
ꢋꢁ 3&ꢀꢈꢈꢂVSHFLILHVꢂDꢂPD[LPXPꢂRIꢂꢌꢁꢊS)
T1
T0
T3
T5
T7
T9
T19
T29
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CLK
t
CK
t
t
CKS CKH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CKE
COMMAND5
t
t
CMS CMH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
4
4
3
4
4
4
NOP
PRE
LMR
LMR
PRE
AR
AR
ACT
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQML, DQMU
t
t
AS AH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
A10
CODE
CODE
CODE
RA
RA
BA
ALL BANKS
ALL BANKS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
t
AS
t
AH
t
t
AH
t
AH
t
AS
AS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = H
BA0 = L,
BA1 = L
BA0, BA1
DQ
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
((
))
T = 100μs
t
t
t
t
RP
t
t
RFC
RP
MRD
MRD
RFC
Power-up:
VDD and
CLK stable
Load Extended
Mode Register
Load Mode
Register
DON’T CARE
Figure 52. Initialize and Load Mode Register
1RWHVꢀ
ꢀꢁ 7KHꢂWZRꢂ$XWRꢂ5HIUHVKꢂFRPPDQGVꢂDWꢂ7ꢐꢂDQGꢂ7ꢀꢐꢂPD\ꢂEHꢂDSSOLHGꢂEHIRUHꢂHLWKHUꢂ/RDGꢂ0RGHꢂ5HJLVWHUꢂ
ꢍ/05ꢎꢂFRPPDQGꢁ
ꢄꢁ 35(ꢂ ꢂ3UHFKDUJHꢂFRPPDQGꢇꢂ/05ꢂ ꢂ/RDGꢂ0RGHꢂ5HJLVWHUꢂFRPPDQGꢇꢂ$5ꢂ ꢂ$XWRꢂ5HIUHVKꢂFRPPDQGꢇꢂ
$&7ꢂ ꢂ$FWLYHꢂFRPPDQGꢇꢂ5$ꢂ ꢂ5RZꢂ$GGUHVVꢇꢂ%$ꢂ ꢂ%DQNꢂ$GGUHVVꢁ
ꢅꢁ 2SWLRQDOꢂUHIUHVKꢂFRPPDQGꢁ
ꢋꢁ 7KHꢂ/RDGꢂ0RGHꢂ5HJLVWHUꢂIRUꢂERWKꢂ05ꢓ(05ꢂDQGꢂꢄꢂ$XWRꢂ5HIUHVKꢂFRPPDQGVꢂFDQꢂEHꢂLQꢂDQ\ꢂRUGHUꢁꢂ+RZꢉ
HYHUꢇꢂDOOꢂPXVWꢂRFFXUꢂSULRUꢂWRꢂDQꢂ$FWLYHꢂFRPPDQGꢁ
ꢊꢁ 'HYLFHꢂWLPLQJꢂLVꢂꢉꢀꢈꢂZLWKꢂꢀꢈꢋꢂ0+]ꢂFORFNꢁ
130
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
Tn + 1
Tn + 2
((
))
((
))
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS
CKS
((
))
t
t
CKS CKH
t
t
CMS CMH
((
))
((
))
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
((
))
((
))
DQML, DQMU
((
))
((
))
A0-A9, A11
A10
ROW
ROW
ALL BANKS
((
))
((
))
SINGLE BANK
t
t
AS AH
((
))
((
))
BA0, BA1
DQ
BANK
BANK(S)
High-Z
((
))
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
Figure 53. Power Down Mode
1RWHꢀꢂ9LRODWLQJꢂUHIUHVKꢂUHTXLUHPHQWVꢂGXULQJꢂSRZHUꢉGRZQꢂPD\ꢂUHVXOWꢂLQꢂDꢂORVVꢂRIꢂGDWDꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
131
A d v a n c e I n f o r m a t i o n
MOBILE SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
2
COLUMNm
COLUMNe
t
t
AH
AS
A10
t
t
AS
AH
BA0, BA1
BANK
BANK
t
AC
t
AC
t
OH
t
HZ
t
DS
t
DH
DOUT
m
DOUT m +
1
DOUT
e
DOUT e + 1
DQ
t
LZ
DON’T CARE
UNDEFINED
Figure 54. Clock Suspend Mode
1RWHVꢀ
ꢀꢁ )RUꢂWKLVꢂH[DPSOHꢇꢂWKHꢂEXUVWꢂOHQJWKꢂ ꢂꢄꢇꢂWKHꢂ&$6ꢂODWHQF\ꢂ ꢂꢅꢇꢂDQGꢂDXWRꢂSUHFKDUJHꢂLVꢂGLVDEOHGꢁ
ꢄꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
132
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
Tn + 1
CL
To + 1
((
))
((
))
t
CLK
CKE
t
t
((
((
CK
CH
))
))
((
))
((
))
t
t
CKS
CKH
t
t
CMS
CMH
((
))
((
))
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
((
((
))
))
((
))
((
))
DQMU, DQML
((
((
))
))
((
))
((
))
((
))
((
))
A0-A9, A11
A10
ROW
ROW
ALL BANKS
((
))
((
))
((
))
((
))
SINGLE BANK
t
t
AH
AS
((
))
((
))
BA0, BA1
DQ
BANK(S)
BANK
((
((
))
))
High-Z
((
))
((
))
t
t
t
RFC
1
1
RP
RFC
Precharge all
active banks
DON’T CARE
Figure 55. Auto Refresh Mode
1RWHꢀꢂ(DFKꢂ$XWRꢂ5HIUHVKꢂFRPPDQGꢂSHUIRUPVꢂDꢂUHIUHVKꢂF\FOHꢁꢂ%DFNꢉWRꢉEDFNꢂFRPPDQGVꢂDUHꢂQRWꢂUHꢉ
TXLUHGꢁ
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
133
A d v a n c e I n f o r m a t i o n
T0
T1
T2
Tn + 1
To + 1
To + 2
((
))
((
))
t
CL
CLK
CKE
t
((
))
((
))
t
CK
CH
t
> t
CKS
RAS
((
))
((
))
((
))
t
t
CKS CKH
t
t
CMS
CMH
((
))
((
))
((
))
((
))
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
((
))
((
))
((
))
((
))
DQMU, DQML
((
))
((
))
((
))
((
))
A0-A9, A11
A10
ALL BANKS
((
))
((
))
((
))
((
))
SINGLE BANK
t
t
AS AH
((
))
((
))
((
))
((
))
BA0, BA1
DQ
BANK(S)
High-Z
((
))
((
))
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
Figure 56. Self Refresh Mode
1RWHꢀꢂ(DFKꢂ$XWRꢂ5HIUHVKꢂFRPPDQGꢂSHUIRUPVꢂDꢂUHIUHVKꢂF\FOHꢁꢂ%DFNꢉWRꢉEDFNꢂFRPPDQGVꢂDUHꢂQRWꢂUHꢉ
TXLUHGꢁ
134
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
ROW
t
t
CMS CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
ROW
COLUMNm
t
t
AH
AS
ALL BANKS
ROW
ROW
A10
SINGLE BANKS
BANK(S)
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
DOUT m+1
D
OUT m+2
DOUT m+3
DQ
t
LZ
t
HZ
t
t
RP
RCD
CAS Latency
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 57. Read - Without Auto Precharge
1RWHVꢀ
ꢀꢁ )RUꢂWKLVꢂH[DPSOHꢇꢂWKHꢂEXUVWꢂOHQJWKꢂ ꢂꢋꢇꢂWKHꢂ&$6ꢂODWHQF\ꢂ ꢂꢄꢇꢂDQGꢂWKHꢂ5HDGꢂEXUVWꢂLVꢂIROORZHGꢂE\ꢂDꢂ
³PDQXDO´ꢂ3UHFKDUJHꢁ
ꢄꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
135
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS CMH
COMMAND
DQMU, DQML
A0-A9, A11
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
t
t
AH
AS
2
ROW
ROW
COLUMNm
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
BANK
t
t
t
AC
AC
AC
t
AC
t
t
t
t
OH
OH
OH
OH
DOUT
m
DOUT
m
+ 1
DOUT
m
+ 2
DOUT m
+ 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 58. Read - With Auto Precharge
1RWHVꢀ
ꢀꢁ )RUꢂWKLVꢂH[DPSOHꢇꢂWKHꢂEXUVWꢂOHQJWKꢂ ꢂꢋꢇꢂWKHꢂ&$6ꢂODWHQF\ꢂ ꢂꢄꢁ
ꢄꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
136
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS CMH
3
3
COMMAND
PRECHARGE
ACTIVE
NOP
READ
NOP
NOP
NOP
ACTIVE
ROW
NOP
t
t
CMS CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
ROW
COLUMNm
t
t
AH
AS
ALL BANKS
ROW
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANKS
BANK(S)
t
t
AH
AS
BA0, BA1
BANK
BANK
t
t
OH
AC
D
OUT m
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 59. Single Read - Without Auto Precharge
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³PDQXDO´ꢂ3UHFKDUJHꢁ
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ꢅꢁ 3UHFKDUJHꢂFRPPDQGꢂQRWꢂDOORZHGꢂRUꢂW
ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
137
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS CMH
3
3
COMMAND
DQMU, DQML
A0-A9, A11
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
t
CMS
CMH
t
t
AH
AS
2
ROW
ROW
COLUMNm
t
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
AS
t
AH
BA0, BA1
BANK
BANK
BANK
t
AC
t
OH
DOUT
m
t
DQ
t
CAS Latency
RCD
HZ
t
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
Figure 60. Single Read - With Auto Precharge
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³PDQXDO´ꢂ3UHFKDUJHꢁ
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ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
138
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
t
CH
t
t
CKS CKH
CKE
COMMAND
t
t
CMS
CMH
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
AS
t
AH
2
2
ROW
ROW
ROW
COLUMNm
COLUMNb
t
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
ROW
A10
t
AS
t
AH
BA0, BA1
BANK 0
BANK 0
BANK 3
BANK 3
BANK 0
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
DOUT
m
DOUT m +
1
DOUT m +
2
DOUT m+
3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RCD - BANK 0
CAS Latency - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 3
CAS Latency - BANK 3
RRD
DON’T CARE
UNDEFINED
Figure 61. Alternating Bank Read Accesses
1RWHVꢀ
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ꢄꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
((
))
((
))
t
CL
t
CK
CLK
t
CH
t
t
CKS CKH
((
))
CKE
((
))
t
t
CMS
CMH
((
))
((
))
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
CMS
CMH
((
))
DQMU, DQML
A0-A9, A11
((
))
t
AS
t
AH
((
))
((
))
2
ROW
COLUMN m
t
AS
t
AH
((
))
((
))
ROW
A10
t
AS
t
AH
((
))
((
))
BA0, BA1
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC ((
AC
))
t
AC
t
t
t
OH
t
t
t
OH
OH
OH
OH
OH
((
))
((
))
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
D
OUT
m
DOUT m+1
DQ
t
LZ
t
HZ
256 (x16) locations within same row
Full page completed
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
3
Figure 62. Read - Full-Page Burst
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ꢅꢁ 3DJHꢂOHIWꢂRSHQꢏꢂQRꢂW
ꢁ
53
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
139
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQMU, DQML
t
t
AS AH
2
A0-A9, A11
A10
ROW
COLUMNm
t
t
AS AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
BANK
t
t
AS AH
BA0, BA1
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
D
OUT
m
DOUT m + 2
DOUT m + 3
DQ
t
LZ
t
t
t
HZ
LZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
Figure 63. Read - DQM Operation
1RWHVꢀ
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
t
t
AH
AS
3
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
Figure 64. Write - Without Auto Precharge
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ꢄꢁ ꢀꢊQVꢂLVꢂUHTXLUHGꢂEHWZHHQꢂꢖ',1ꢂPꢂꢔꢂꢅ!ꢂDQGꢂWKHꢂ3UHFKDUJHꢂFRPPDQGꢇꢂUHJDUGOHVVꢂRIꢂIUHTXHQF\ꢁ
ꢅꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
140
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
DQMU, DQML
A0-A9, A11
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
t
t
t
t
AH
AS
2
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
AS
AH
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
Figure 65. Write - With Auto Precharge
1RWHVꢀ
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ꢄꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
t
t
AH
AS
3
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
Figure 66. Single Write - Without Auto Precharge
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ꢄꢁ ꢀꢊQVꢂLVꢂUHTXLUHGꢂEHWZHHQꢂꢖ',1ꢂP!ꢂDQGꢂWKHꢂ3UHFKDUJHꢂFRPPDQGꢇꢂUHJDUGOHVVꢂRIꢂIUHTXHQF\ꢁ
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ꢋꢁ 3UHFKDUJHꢂFRPPDQGꢂQRWꢂDOORZHGꢂHOVHꢂW
ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
141
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
3
3
3
NOP
COMMAND
NOP
ACTIVE
ACTIVE
NOP
NOP
WRITE
t
NOP
NOP
NOP
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
t
t
AH
AS
2
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
AS
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
DINm
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
Figure 67. Single Write with Auto Precharge
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ꢄꢁ ꢀꢊQVꢂLVꢂUHTXLUHGꢂEHWZHHQꢂꢖ',1ꢂP!ꢂDQGꢂWKHꢂ3UHFKDUJHꢂFRPPDQGꢇꢂUHJDUGOHVVꢂRIꢂIUHTXHQF\ꢁ
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ꢂZRXOGꢂEHꢂYLRODWHGꢁ
5$6
142
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
2
ROW
ROW
ROW
ROW
ROW
COLUMNm
COLUMNb
t
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
AS
t
AH
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DIN
b
DINb + 1
DINb + 2
DINb + 3
DQ
t
t
t
RCD - BANK 0
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
DON’T CARE
Figure 68. Alternating Bank Write Accesses
1RWHVꢀ
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ꢄꢁ $ꢐꢂDQGꢂ$ꢀꢀꢂ ꢂ³'RQ¶Wꢂ&DUHꢁ´
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
143
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
((
))
((
))
t
t
CK
CL
CLK
t
CH
t
t
CKS CKH
((
))
CKE
((
))
t
t
CMS
CMH
((
))
((
))
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
((
))
DQMU, DQML
A0-A9, A11
((
))
t
t
AH
AS
((
))
((
))
1
ROW
COLUMNm
t
t
AH
AS
((
))
((
))
ROW
A10
t
t
AH
AS
((
))
((
))
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH ((
DS
DH
))
DIN
m
DINm+ 1
DINm+ 2
DINm+ 3
DINm- 1
DQ
((
))
t
RCD
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
512 (x16) locations within same row
Full page completed
DON’T CARE
2, 3
command to stop.
Figure 69. Write - Full Page Burst
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ꢄꢁ W ꢂPXVWꢂEHꢂVDWLVILHGꢂSULRUꢂWRꢂ3UHFKDUJHꢂFRPPDQGꢁ
:5
ꢅꢁ 3DJHꢂOHIWꢂRSHQꢏꢂQRꢂW
ꢁ
53
144
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQMU, DQML
t
t
AS AH
2
A0-A9, A11
ROW
COLUMNm
t
t
AS AH
ENABLE AUTO PRECHARGE
ROW
A10
t
t
DISABLE AUTO PRECHARGE
BANK
AS AH
BA0, BA1
BANK
t
t
t
t
t
t
DS DH
DS DH
DS DH
DIN m
DIN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
Figure 70. Write - DQM Operation
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September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
145
A d v a n c e I n f o r m a t i o n
SDRAM Revision Summary
Revision A0 (August 8, 2004)
,QLWLDOꢀ5HOHDVH
Revision A1 (April 1, 2005)
&DVꢀ/DWHQF\ꢀVHFWLRQꢀXSGDWHG
%DQNꢒ5RZꢀ$FWLYDWLRQꢀVHFWLRQꢀXSGDWHG
Revision A2 (April 25, 2005)
$GGHGꢀꢊꢋꢋꢀ0+]ꢀVSHHGꢀJUDGHꢀRSWLRQ
146
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
S99KS256N MirrorBit™ Flash Family
256 Megabit (16 Mb x 16-bit), CMOS 1.8 Volt-only
Data Storage, Multiplexed, Burst Mode Flash Memory
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
²
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VHFWRUVꢀDQGꢀꢈꢉꢉꢀPVꢀVHFWRUꢀHUDVHꢀWLPHꢀIRUꢀꢇꢑꢀ.ZRUGꢀ
VHFWRUV
6LQJOHꢀꢄꢅꢊꢀYROWꢀUHDGꢌꢀSURJUDPꢀDQGꢀHUDVHꢀ
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9HUVDWLOH,2ꢀ)HDWXUH
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A d v a n c e I n f o r m a t i o n
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WRPDWLFDOO\ꢀHQDEOHGꢀIRUꢀEXUVWꢀPRGHꢀDQGꢀDGGUHVVHVꢀDUHꢀODWFKHGꢀRQꢀWKHꢀILUVWꢀULVLQJꢀHGJHꢀRIꢀ&/.ꢀLQSXWꢂꢀ
ZKLOHꢀ$9'ꢓꢀLVꢀKHOGꢀORZꢀIRUꢀRQHꢀFORFNꢀF\FOHꢁ
154
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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IRUꢀWKHꢀLQLWLDOꢀZRUGꢀꢅW,$&&ꢆꢀRIꢀHDFKꢀEXUVWꢀVHVVLRQꢁꢀ7KHꢀV\VWHPꢀZRXOGꢀWKHQꢀZULWHꢀWKHꢀ6HWꢀ&RQILJXUDꢃ
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7KHꢀLQLWLDOꢀZRUGꢀLVꢀRXWSXWꢀW,$&&ꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILUVWꢀ&/.ꢀF\FOHꢁꢀ6XEVHTXHQWꢀZRUGVꢀDUHꢀ
RXWSXWꢀW%$&&ꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀHDFKꢀVXFFHVVLYHꢀFORFNꢀF\FOHꢂꢀZKLFKꢀDXWRPDWLFDOO\ꢀLQFUHPHQWVꢀ
WKHꢀLQWHUQDOꢀDGGUHVVꢀFRXQWHUꢁꢀ1RWHꢀWKDWꢀWKHꢀGHYLFHꢀKDVꢀDꢀIL[HGꢀLQWHUQDOꢀDGGUHVVꢀERXQGDU\ꢀ
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ꢊꢌꢈꢀZRUGVꢆꢀIRUꢀIUHTXHQFLHVꢀHTXDOꢀWRꢀRUꢀORZHUꢀWKDQꢀꢇꢇꢀ0K]ꢁꢀ)RUꢀIUHTXHQFLHVꢀKLJKHUꢀWKDQꢀꢇꢇꢀ0K]ꢂꢀ
WKHUHꢀLVꢀDꢀODWHQF\ꢀRIꢀꢊꢀF\FOHꢁ
'XULQJꢀWKHꢀWLPHꢀWKHꢀGHYLFHꢀLVꢀRXWSXWWLQJꢀGDWDꢀZLWKꢀWKHꢀVWDUWLQJꢀEXUVWꢀDGGUHVVꢀQRWꢀGLYLVLEOHꢀE\ꢀIRXUꢂꢀ
DGGLWLRQDOꢀZDLWVꢀDUHꢀUHTXLUHGꢁꢀ7KHꢀ5'<ꢀRXWSXWꢀLQGLFDWHVꢀWKLVꢀFRQGLWLRQꢀWRꢀWKHꢀV\VWHPꢀE\ꢀ
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Table 44. Address Latency for 7, 6 and 5 Wait States
:RUG
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Table 45. Address Latency for 4 Wait States
:RUG
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Table 46. Address Latency for 3 Wait States
:RUG
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
155
A d v a n c e I n f o r m a t i o n
Table 47. Address Latency for 2 Wait States
:RUG
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7DEOHVꢀꢑꢈꢀ±ꢀꢍꢊꢀVKRZꢀWKHꢀDGGUHVVꢒERXQGDU\ꢀFURVVLQJꢀODWHQF\ꢀIRUꢀYDULDEOHꢀZDLWꢀVWDWHꢀLIꢀDꢀERXQGDU\ꢀ
FURVVLQJꢀRFFXUVꢀGXULQJꢀLQLWLDOꢀDFFHVVꢁ
Table 48. Address/Boundary Crossing Latency for 7, 6, and 5 Wait States
:RUG
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Table 49. Address/Boundary Crossing Latency for 4 Wait States
:RUG
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Table 50. Address/Boundary Crossing Latency for 3 Wait States
:RUG
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Table 51. Address/Boundary Crossing Latency for 2 Wait States
:RUG
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156
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
7KHꢀGHYLFHꢀFRQWLQXHVꢀWRꢀRXWSXWꢀFRQWLQXRXVꢂꢀVHTXHQWLDOꢀEXUVWꢀGDWDꢂꢀZUDSSLQJꢀDURXQGꢀWRꢀDGGUHVVꢀ
ꢉꢉꢉꢉꢉꢉKꢀDIWHUꢀLWꢀUHDFKHVꢀWKHꢀKLJKHVWꢀDGGUHVVDEOHꢀPHPRU\ꢀORFDWLRQꢂꢀXQWLOꢀWKHꢀV\VWHPꢀDVVHUWVꢀ&(ꢓꢀ
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LVꢀQRWꢀSURJUDPPLQJꢀRUꢀHUDVLQJꢂꢀQRꢀDGGLWLRQDOꢀODWHQF\ꢀRFFXUVꢀDVꢀGHVFULEHGꢀDERYHꢁꢀ,IꢀWKHꢀKRVWꢀV\Vꢃ
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UHDGVꢂꢀRUꢀWKHꢀGHYLFHꢀKDVꢀFRPSOHWHGꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢂꢀWKHꢀKRVWꢀFDQꢀUHVWDUWꢀDꢀEXUVWꢀ
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QXPEHUꢀRIꢀZRUGVꢀUHDGꢀLQꢀDꢀVLQJOHꢀEXUVWꢀVHTXHQFHꢀIRUꢀDꢀJLYHQꢀPRGHꢀꢅVHHꢀ7DEOHꢀꢍꢌꢁꢆ
Table 52. Burst Address Groups
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WKHꢀEXUVWꢀVHTXHQFHꢀZRXOGꢀEHꢀꢋ$ꢃꢋ%ꢃꢋ&ꢃꢋ'ꢃꢋ(ꢃꢋ)ꢃꢑꢉꢃꢑꢊKꢂꢀDQGꢀWKHꢀUHDGꢀRSHUDWLRQꢀLVꢀWHUPLQDWHGꢀ
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WLQXRXVO\ꢀUHDGꢀWRꢀWKHꢀSUHGHILQHGꢀꢊꢇꢀRUꢀꢋꢌꢀZRUGVꢀDFFRUGLQJO\ꢁꢀ1RWHꢁꢀ,QꢀWKLVꢀEXUVWꢀUHDGꢀPRGHꢌꢀ
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S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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S75NS128NDE based MCPs
159
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A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
163
A d v a n c e I n f o r m a t i o n
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164
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S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
165
A d v a n c e I n f o r m a t i o n
Command Definitions
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166
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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7KHꢀZDLWꢀVWDWHꢀFRPPDQGꢀVHTXHQFHꢀLQVWUXFWVꢀWKHꢀGHYLFHꢀWRꢀVHWꢀDꢀSDUWLFXODUꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀ
IRUꢀWKHꢀLQLWLDOꢀDFFHVVꢀLQꢀEXUVWꢀPRGHꢁꢀ7KHꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀWKDWꢀVKRXOGꢀEHꢀSURJUDPPHGꢀLQWRꢀ
WKHꢀGHYLFHꢀLVꢀGLUHFWO\ꢀUHODWHGꢀWRꢀWKHꢀFORFNꢀIUHTXHQF\ꢁ
Table 56. Programmable Wait State Settings
7RWDOꢀ,QLWLDO
&5ꢄꢏ
&5ꢄꢉꢀ
&5ꢄꢄ
$FFHVVꢀ&\FOHV
ꢉ
ꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢊ
ꢉ
ꢊ
ꢉ
ꢊ
ꢉ
ꢊ
ꢌ
ꢉ
ꢋ
ꢉ
ꢑ
ꢍ
ꢉ
ꢊ
ꢇ
ꢊ
ꢏꢀꢅGHIDXOWꢆ
5HVHUYHG
5HVHUYHG
ꢊ
ꢊ
1RWHVꢀ
ꢀꢁ 8SRQꢂSRZHUꢉXSꢂRUꢂKDUGZDUHꢂUHVHWꢇꢂWKHꢂGHIDXOWꢂVHWWLQJꢂLVꢂVHYHQꢂZDLWꢂVWDWHVꢁ
ꢄꢁ 5'<ꢂGHIDXOWVꢂWRꢂEHLQJꢂDFWLYHꢂZLWKꢂGDWDꢂZKHQꢂWKHꢂ:DLWꢂ6WDWHꢂ6HWWLQJꢂLVꢂVHWꢂWRꢂDꢂWRWDOꢂLQLWLDOꢂDFFHVVꢂ
F\FOHꢂRIꢂꢄꢁ
,WꢀLVꢀUHFRPPHQGHGꢀWKDWꢀWKHꢀZDLWꢀVWDWHꢀFRPPDQGꢀVHTXHQFHꢀEHꢀZULWWHQꢂꢀHYHQꢀLIꢀWKHꢀGHIDXOWꢀZDLWꢀ
VWDWHꢀYDOXHꢀLVꢀGHVLUHGꢂꢀWRꢀHQVXUHꢀWKHꢀGHYLFHꢀLVꢀVHWꢀDVꢀH[SHFWHGꢁꢀ$ꢀKDUGZDUHꢀUHVHWꢀVHWVꢀWKHꢀZDLWꢀ
VWDWHꢀWRꢀWKHꢀGHIDXOWꢀVHWWLQJꢁ
3URJUDPPDEOHꢀ:DLWꢀ6WDWH
7KHꢀKRVWꢀV\VWHPꢀVKRXOGꢀVHWꢀ&5ꢄꢏꢒ&5ꢄꢄꢀWRꢀꢊꢉꢊꢒꢊꢉꢉꢒꢉꢊꢊꢀIRUꢀDꢀFORFNꢀIUHTXHQF\ꢀRIꢀꢈꢉꢀꢒꢀꢇꢇꢀꢀ0+]ꢀ
IRUꢀWKHꢀV\VWHPꢒGHYLFHꢀWRꢀH[HFXWHꢀDWꢀPD[LPXPꢀVSHHGꢁ
7DEOHꢀꢍꢏꢀGHVFULEHVꢀWKHꢀW\SLFDOꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀꢅZDLWꢀVWDWHVꢆꢀIRUꢀYDULRXVꢀFRQGLWLRQVꢁ
Table 57. Wait States for Handshaking
7\SLFDOꢀ1RꢅꢀRIꢀ&ORFNꢀ&\FOHVꢀDIWHUꢀ$9'ꢑꢀ/RZ
&RQGLWLRQVꢀDWꢀ$GGUHVV
ꢊꢍꢀ0+]
ꢋꢋꢀ0+]
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ꢇ
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VWDWHVꢀLQꢀWKHꢀIODVKꢀGHYLFHꢀGHSHQGLQJꢀRQꢀWKHꢀFORFNꢀIUHTXHQF\ꢁ
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
167
A d v a n c e I n f o r m a t i o n
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7KHꢀGHYLFHꢀVXSSRUWVꢀIRXUꢀGLIIHUHQWꢀUHDGꢀPRGHVꢄꢀFRQWLQXRXVꢀPRGHꢂꢀDQGꢀꢈꢂꢀꢊꢇꢂꢀDQGꢀꢋꢌꢀZRUGꢀOLQHDUꢀ
ZLWKꢀRUꢀZLWKRXWꢀZUDSꢃDURXQGꢀPRGHVꢁꢀ$ꢀFRQWLQXRXVꢀVHTXHQFHꢀꢅGHIDXOWꢆꢀEHJLQVꢀDWꢀWKHꢀVWDUWLQJꢀDGꢃ
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Table 58. Burst Length Configuration
$GGUHVVꢀ%LWV
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5'<ꢀSLQꢀWRꢀEHꢀDFWLYHꢀORZꢁꢀ,QꢀWKLVꢀFDVHꢂꢀWKHꢀ5'<ꢀSLQꢀDOZD\VꢀLQGLFDWHVꢀWKDWꢀWKHꢀGHYLFHꢀLVꢀUHDG\ꢀWRꢀ
KDQGOHꢀDꢀQHZꢀWUDQVDFWLRQꢀZKHQꢀORZꢁ
168
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Configuration Register
7DEOHꢀꢍꢐꢀVKRZVꢀWKHꢀDGGUHVVꢀELWVꢀWKDWꢀGHWHUPLQHꢀWKHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀVHWWLQJVꢀIRUꢀYDULRXVꢀGHꢃ
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Table 59. Configuration Register
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Reset Command
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SURJUDPPLQJꢀEHJLQVꢌꢀKRZHYHUꢌꢀWKHꢀGHYLFHꢀLJQRUHVꢀUHVHWꢀFRPPDQGVꢀXQWLOꢀWKHꢀRSHUDWLRQꢀ
LVꢀFRPSOHWHꢁ
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
169
A d v a n c e I n f o r m a t i o n
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170
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Autoselect Command Sequence
7KHꢀDXWRVHOHFWꢀFRPPDQGꢀVHTXHQFHꢀDOORZVꢀWKHꢀKRVWꢀV\VWHPꢀWRꢀDFFHVVꢀWKHꢀPDQXIDFWXUHUꢀDQGꢀGHYLFHꢀ
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Table 60. Device ID
'HVFULSWLRQ
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
171
A d v a n c e I n f o r m a t i o n
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
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HOHFWURQLFꢀVHULDOꢀQXPEHUꢀꢅ(61ꢆꢁꢀ7KHꢀV\VWHPꢀFDQꢀDFFHVVꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀUHJLRQꢀE\ꢀLVꢃ
VXLQJꢀWKHꢀWKUHHꢃF\FOHꢀ(QWHUꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀGHYLFHꢀFRQWLQXHVꢀWRꢀ
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FRQꢀ6HFWRUꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀ([LWꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀFRPPDQGꢀVHTXHQFHꢀUHWXUQVꢀWKHꢀ
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FXWLQJꢀDQꢀ(PEHGGHGꢀ3URJUDPꢀRUꢀHPEHGGHGꢀ(UDVHꢀDOJRULWKPꢁꢀ7DEOHꢀꢇꢌꢀVKRZVꢀWKHꢀDGGUHVVꢀDQGꢀGDWDꢀ
UHTXLUHPHQWVꢀIRUꢀERWKꢀFRPPDQGꢀVHTXHQFHVꢁ
8QORFNꢀ%\SDVVꢀ&RPPDQGꢀ6HTXHQFH
7KHꢀXQORFNꢀE\SDVVꢀIHDWXUHꢀDOORZVꢀWKHꢀV\VWHPꢀWRꢀSURJUDPꢀIDVWHUꢀWKDQꢀWKHꢀVWDQGDUGꢀSURJUDPꢀFRPꢃ
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V\VWHPꢀPXVWꢀLVVXHꢀWKHꢀWZRꢃF\FOHꢀXQORFNꢀE\SDVVꢀUHVHWꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀILUVWꢀF\FOHꢀPXVWꢀ
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7KHꢀUHJLRQꢀWKHQꢀUHWXUQVꢀWRꢀWKHꢀUHDGꢀPRGHꢁ
Program Command Sequence
3URJUDPꢀ&RPPDQGꢀ6HTXHQFH
3URJUDPPLQJꢀLVꢀDꢀIRXUꢃEXVꢃF\FOHꢀRSHUDWLRQꢁꢀ7KHꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢀLVꢀLQLWLDWHGꢀE\ꢀZULWꢃ
LQJꢀWZRꢀXQORFNꢀZULWHꢀF\FOHVꢂꢀIROORZHGꢀE\ꢀWKHꢀSURJUDPꢀVHWꢃXSꢀFRPPDQGꢁꢀ7KHꢀSURJUDPꢀDGGUHVVꢀDQGꢀ
GDWDꢀDUHꢀZULWWHQꢀQH[WꢂꢀZKLFKꢀLQꢀWXUQꢀLQLWLDWHꢀWKHꢀ(PEHGGHGꢀ3URJUDPꢀDOJRULWKPꢁꢀ7KHꢀV\VWHPꢀLVꢀQRW
UHTXLUHGꢀWRꢀSURYLGHꢀIXUWKHUꢀFRQWUROVꢀRUꢀWLPLQJVꢁꢀ7KHꢀGHYLFHꢀDXWRPDWLFDOO\ꢀSURYLGHVꢀLQWHUQDOO\ꢀJHQꢃ
HUDWHGꢀSURJUDPꢀSXOVHVꢀDQGꢀYHULILHVꢀWKHꢀSURJUDPPHGꢀFHOOꢀPDUJLQꢁꢀ7DEOHꢀꢇꢌꢀVKRZVꢀWKHꢀDGGUHVVꢀDQGꢀ
GDWDꢀUHTXLUHPHQWVꢀIRUꢀWKHꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢁ
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DQGꢀDGGUHVVHVꢀDUHꢀQRꢀORQJHUꢀODWFKHGꢁꢀ7KHꢀV\VWHPꢀFDQꢀGHWHUPLQHꢀWKHꢀVWDWXVꢀRIꢀWKHꢀSURJUDPꢀRSHUꢃ
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JUDPPHGꢀIURPꢀ³ꢍ´ꢀEDFNꢀWRꢀDꢀ³ꢄꢅ´ꢀ$WWHPSWLQJꢀWRꢀGRꢀVRꢀPD\ꢀFDXVHVꢀWKDWꢀUHJLRQꢀWRꢀVHWꢀ'4ꢍꢀ ꢀ
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FRQWDLQVꢀWKHꢀXQORFNꢀE\SDVVꢀSURJUDPꢀFRPPDQGꢂꢀ$ꢉKꢕꢀWKHꢀVHFRQGꢀF\FOHꢀFRQWDLQVꢀWKHꢀSURJUDPꢀDGꢃ
GUHVVꢀDQGꢀGDWDꢁꢀ$GGLWLRQDOꢀGDWDꢀLVꢀSURJUDPPHGꢀLQꢀWKHꢀVDPHꢀPDQQHUꢁꢀ7KLVꢀPRGHꢀGLVSHQVHVꢀZLWKꢀ
WKHꢀLQLWLDOꢀWZRꢀXQORFNꢀF\FOHVꢀUHTXLUHGꢀLQꢀWKHꢀVWDQGDUGꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢂꢀUHVXOWLQJꢀLQꢀ
IDVWHUꢀWRWDOꢀSURJUDPPLQJꢀWLPHꢁꢀ7DEOHꢀꢇꢌꢀVKRZVꢀWKHꢀUHTXLUHPHQWVꢀIRUꢀWKHꢀXQORFNꢀE\SDVVꢀFRPPDQGꢀ
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172
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Accelerated Program
7KHꢀGHYLFHꢀRIIHUVꢀDFFHOHUDWHGꢀSURJUDPꢀRSHUDWLRQVꢀWKURXJKꢀWKHꢀ933ꢀLQSXWꢁꢀ:KHQꢀWKHꢀV\VWHPꢀDVVHUWVꢀ
33ꢀRQꢀWKLVꢀLQSXWꢂꢀWKHꢀGHYLFHꢀDXWRPDWLFDOO\ꢀHQWHUVꢀWKHꢀ8QORFNꢀ%\SDVVꢀPRGHꢁꢀ7KHꢀV\VWHPꢀPD\ꢀWKHQꢀ
9
ZULWHꢀWKHꢀWZRꢃF\FOHꢀ8QORFNꢀ%\SDVVꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢁꢀ7KHꢀGHYLFHꢀXVHVꢀWKHꢀKLJKHUꢀYROWꢃ
DJHꢀRQꢀWKHꢀ933ꢀLQSXWꢀWRꢀDFFHOHUDWHꢀWKHꢀRSHUDWLRQꢁ
)LJXUHꢀꢏꢊꢀLOOXVWUDWHVꢀWKHꢀDOJRULWKPꢀIRUꢀWKHꢀSURJUDPꢀRSHUDWLRQꢁꢀ6HHꢀWKHꢀ(UDVHꢒ3URJUDPꢀ2SHUDWLRQV
WDEOHꢀLQꢀ$&ꢀ&KDUDFWHULVWLFVꢀIRUꢀSDUDPHWHUVꢂꢀDQGꢀ)LJXUHꢀꢈꢑꢀIRUꢀWLPLQJꢀGLDJUDPVꢁ
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
1RWHꢀꢂ6HHꢂ7DEOHꢂꢌꢄꢂIRUꢂSURJUDPꢂFRPPDQGꢂVHTXHQFH
Figure 71. Program Operation
Write Buffer Programming Command Sequence
:ULWHꢀ%XIIHUꢀ3URJUDPPLQJꢀ6HTXHQFHꢀDOORZVꢀIRUꢀIDVWHUꢀSURJUDPPLQJꢀDVꢀFRPSDUHGꢀWRꢀWKHꢀVWDQGDUGꢀ
3URJUDPꢀ&RPPDQGꢀ6HTXHQFHꢁꢀ6HHꢀ7DEOHꢀꢇꢊꢀIRUꢀWKHꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢁ
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
173
A d v a n c e I n f o r m a t i o n
Table 61. Write Buffer Command Sequence
6HTXHQFH
8QORFNꢀ&RPPDQGꢀꢊ
8QORFNꢀ&RPPDQGꢀꢌ
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6DPHꢀDVꢀDERYH
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ꢉꢉꢌꢍK
6SHFLI\ꢀWKHꢀ1XPEHUꢀRI
3URJUDPꢀ/RFDWLRQV
6WDUWLQJꢀ
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$OOꢀDGGUHVVHVꢀPXVWꢀEHꢀZLWKLQ
6WDUWLQJꢀ
$GGUHVV
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3URJUDPꢀ'DWD
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EXWꢀGRꢀQRWꢀKDYHꢀWRꢀEHꢀORDGHGꢀLQꢀDQ\ꢀRUGHU
:ULWHꢀ%XIIHUꢀ
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ꢁꢁꢁ
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6DPHꢀDVꢀDERYH
6DPHꢀDVꢀDERYH
ꢁꢁꢁ
:ULWHꢀ%XIIHUꢀ
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ꢉꢉꢌꢐK
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6WDWXVꢀPRQLWRULQJꢀWKURXJK
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/DVWꢀ/RDGHGꢀ$GGUHVVꢆ
1RWHꢀꢂ:ULWHꢂEXIIHUꢂDGGUHVVHVꢂPXVWꢂEHꢂORDGHGꢂLQꢂVHTXHQWLDOꢂRUGHUꢁ
174
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ15 - DQ0 at
Last Loaded Address
Yes
DQ7 and DQ15 = Data?
No
No
No
DQ1 = 1?
Yes
DQ5 and DQ13 = 1?
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
Yes
DQ7 and DQ15 = Data?
No
FAIL or ABORT
PASS
Figure 72. Write Buffer Programming Operation
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
175
A d v a n c e I n f o r m a t i o n
Chip Erase Command Sequence
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176
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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Write Erase
Command Sequence
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Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Figure 73. Erase Operation
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Erase Suspend/Erase Resume Commands
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
177
A d v a n c e I n f o r m a t i o n
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Program Suspend/Program Resume Commands
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Lock Register Command Set Definitions
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178
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
179
A d v a n c e I n f o r m a t i o n
Table 62. Command Definitions (Sheet 1 of 2)
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180
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 62. Command Definitions (Sheet 2 of 2)
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S75NS128NDE based MCPs
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ꢄꢁ '4ꢒꢂVKRXOGꢂEHꢂUHFKHFNHGꢂHYHQꢂLIꢂ'4ꢊꢂ ꢂ³ꢀ´ꢂEHFDXVHꢂ'4ꢒꢂPD\ꢂFKDQJHꢂVLPXOWDQHRXVO\ꢂZLWKꢂ'4ꢊ
Figure 74. Data# Polling Algorithm
184
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
RDY: Ready
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LQJꢀEXUVWꢀꢅV\QFKURQRXVꢆꢀUHDGVꢁꢀ:KHQꢀ5'<ꢀLVꢀDVVHUWHGꢀꢅ5'<ꢀ ꢀ92+ꢆꢂꢀWKHꢀRXWSXWꢀGDWDꢀLVꢀYDOLGꢀDQGꢀ
FDQꢀEHꢀUHDGꢁꢀ:KHQꢀ5'<ꢀLVꢀGHꢃDVVHUWHGꢀꢅ5'<ꢀ ꢀ92/ꢆꢂꢀWKHꢀV\VWHPꢀVKRXOGꢀZDLWꢀXQWLOꢀ5'<ꢀLVꢀUHꢃDVꢃ
VHUWHGꢀEHIRUHꢀH[SHFWLQJꢀWKHꢀQH[WꢀZRUGꢀRIꢀGDWDꢁ
,QꢀV\QFKURQRXVꢀꢅEXUVWꢆꢀPRGHꢀZLWKꢀ&(ꢓꢀ ꢀ2(ꢓꢀ ꢀ9,/ꢂꢀ5'<ꢀLVꢀGHꢃDVVHUWHGꢀXQGHUꢀWKHꢀIROORZLQJꢀFRQꢃ
GLWLRQVꢄꢀGXULQJꢀWKHꢀLQLWLDOꢀDFFHVVꢕꢀDIWHUꢀFURVVLQJꢀWKHꢀLQWHUQDOꢀERXQGDU\ꢀEHWZHHQꢀDGGUHVVHVꢀꢏ(KꢀDQGꢀ
ꢏ)KꢀꢅDQGꢀDGGUHVVHVꢀRIIVHWꢀIURPꢀWKHVHꢀE\ꢀDꢀPXOWLSOHꢀRIꢀꢇꢑꢆꢁꢀ7KHꢀ5'<ꢀSLQꢀDOVRꢀVZLWFKHVꢀGXULQJꢀVWDWXVꢀ
UHDGVꢀZKHQꢀDꢀFORFNꢀVLJQDOꢀGULYHVꢀWKHꢀ&/.ꢀLQSXWꢁꢀ,QꢀDGGLWLRQꢂꢀ5'<ꢀ ꢀ92+ꢀZKHQꢀ&(ꢓꢀ ꢀ9,/ꢀDQGꢀ2(ꢓꢀ
ꢀ9,+ꢂꢀDQGꢀ5'<ꢀLVꢀ+Lꢃ=ꢀZKHQꢀ&(ꢓꢀ ꢀ9,+
,QꢀDV\QFKURQRXVꢀꢅQRQꢃEXUVWꢆꢀPRGHꢂꢀWKHꢀ5'<ꢀSLQꢀGRHVꢀQRWꢀLQGLFDWHꢀYDOLGꢀRUꢀLQYDOLGꢀRXWSXWꢀGDWDꢁꢀ
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DQ6: Toggle Bit I
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FRPSOHWHꢂꢀRUꢀZKHWKHUꢀWKHꢀGHYLFHꢀKDVꢀHQWHUHGꢀWKHꢀ(UDVHꢀ6XVSHQGꢀPRGHꢁꢀ7RJJOHꢀ%LWꢀ,ꢀPD\ꢀEHꢀUHDGꢀ
DWꢀDQ\ꢀDGGUHVVꢀLQꢀWKHꢀVDPHꢀUHJLRQꢂꢀDQGꢀLVꢀYDOLGꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀWKHꢀ
FRPPDQGꢀVHTXHQFHꢀꢅSULRUꢀWRꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢆꢂꢀDQGꢀGXULQJꢀWKHꢀVHFWRUꢀHUDVHꢀWLPHꢃ
RXWꢁ
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GUHVVꢀFDXVHꢀ'4ꢇꢀWRꢀWRJJOHꢁꢀ1RWHꢀWKDWꢀ2(ꢓꢀPXVWꢀEHꢀORZꢀGXULQJꢀWRJJOHꢀELWꢀVWDWXVꢀUHDGVꢁꢀ:KHQꢀWKHꢀ
RSHUDWLRQꢀLVꢀFRPSOHWHꢂꢀ'4ꢇꢀVWRSVꢀWRJJOLQJꢁ
$IWHUꢀDQꢀHUDVHꢀFRPPDQGꢀVHTXHQFHꢀLVꢀZULWWHQꢂꢀLIꢀDOOꢀVHFWRUVꢀVHOHFWHGꢀIRUꢀHUDVLQJꢀDUHꢀSURWHFWHGꢂꢀ'4ꢇꢀ
WRJJOHVꢀIRUꢀDSSUR[LPDWHO\ꢀW$63ꢂꢀDOOꢀVHFWRUVꢀSURWHFWHGꢀWRJJOHꢀWLPHꢂꢀWKHQꢀUHWXUQVꢀWRꢀUHDGLQJꢀDUUD\ꢀ
GDWDꢁꢀ,IꢀQRWꢀDOOꢀVHOHFWHGꢀVHFWRUVꢀDUHꢀSURWHFWHGꢂꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀHUDVHVꢀWKHꢀXQSURꢃ
WHFWHGꢀVHFWRUVꢂꢀDQGꢀLJQRUHVꢀWKHꢀVHOHFWHGꢀVHFWRUVꢀWKDWꢀDUHꢀSURWHFWHGꢁꢀ
7KHꢀV\VWHPꢀFDQꢀXVHꢀ'4ꢇꢀDQGꢀ'4ꢌꢀWRJHWKHUꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀDꢀVHFWRUꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀRUꢀ
LVꢀHUDVHꢃVXVSHQGHGꢁꢀ:KHQꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀꢅWKDWꢀLVꢂꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀ
LVꢀLQꢀSURJUHVVꢆꢂꢀ'4ꢇꢀWRJJOHVꢁꢀ:KHQꢀWKHꢀGHYLFHꢀHQWHUVꢀWKHꢀ(UDVHꢀ6XVSHQGꢀPRGHꢂꢀ'4ꢇꢀVWRSVꢀWRJꢃ
JOLQJꢁꢀ+RZHYHUꢂꢀWKHꢀV\VWHPꢀPXVWꢀDOVRꢀXVHꢀ'4ꢌꢀWRꢀGHWHUPLQHꢀZKLFKꢀVHFWRUVꢀDUHꢀHUDVLQJꢀRUꢀHUDVHꢃ
VXVSHQGHGꢁꢀ$OWHUQDWLYHO\ꢂꢀWKHꢀV\VWHPꢀFDQꢀXVHꢀ'4ꢏꢀꢅVHHꢀ'4ꢏꢄꢀ'DWDꢓꢀ3ROOLQJꢆꢁ
,IꢀDꢀSURJUDPꢀDGGUHVVꢀIDOOVꢀZLWKLQꢀDꢀSURWHFWHGꢀVHFWRUꢂꢀ'4ꢇꢀWRJJOHVꢀIRUꢀDSSUR[LPDWHO\ꢀW363ꢀDIWHUꢀWKHꢀ
SURJUDPꢀFRPPDQGꢀVHTXHQFHꢀLVꢀZULWWHQꢂꢀWKHQꢀUHWXUQVꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢁ
'4ꢇꢀDOVRꢀWRJJOHVꢀGXULQJꢀWKHꢀHUDVHꢃVXVSHQGꢃSURJUDPꢀPRGHꢂꢀDQGꢀVWRSVꢀWRJJOLQJꢀRQFHꢀWKHꢀ(PEHGꢃ
GHGꢀ3URJUDPꢀDOJRULWKPꢀLVꢀFRPSOHWHꢁ
6HHꢀWKHꢀIROORZLQJꢀIRUꢀDGGLWLRQDOꢀLQIRUPDWLRQꢄꢀꢅWRJJOHꢀELWꢀIORZFKDUWꢆꢂꢀ'4ꢇꢄꢀ7RJJOHꢀ%LWꢀ,ꢀꢅGHVFULSꢃ
WLRQꢆꢂꢀ)LJXUHꢀꢈꢈꢀꢅWRJJOHꢀELWꢀWLPLQJꢀGLDJUDPꢆꢂꢀDQGꢀ7DEOHꢀꢇꢋꢀꢅFRPSDUHVꢀ'4ꢌꢀDQGꢀ'4ꢇꢆꢁꢀ
DQ2: Toggle Bit II
7KHꢀ³7RJJOHꢀ%LWꢀ,,´ꢀRQꢀ'4ꢌꢂꢀZKHQꢀXVHGꢀZLWKꢀ'4ꢇꢂꢀLQGLFDWHVꢀZKHWKHUꢀDꢀSDUWLFXODUꢀVHFWRUꢀLVꢀDFWLYHO\ꢀ
HUDVLQJꢀꢅWKDWꢀLVꢂꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀLVꢀLQꢀSURJUHVVꢆꢂꢀRUꢀZKHWKHUꢀWKDWꢀVHFWRUꢀLVꢀHUDVHꢃ
VXVSHQGHGꢁꢀ7RJJOHꢀ%LWꢀ,,ꢀLVꢀYDOLGꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀWKHꢀFRPPDQGꢀ
VHTXHQFHꢁ
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
185
A d v a n c e I n f o r m a t i o n
'4ꢌꢀWRJJOHVꢀZKHQꢀWKHꢀV\VWHPꢀUHDGVꢀDWꢀDGGUHVVHVꢀZLWKLQꢀWKRVHꢀVHFWRUVꢀWKDWꢀKDYHꢀEHHQꢀVHOHFWHGꢀ
IRUꢀHUDVXUHꢁꢀ1RWHꢀWKDWꢀ2(ꢓꢀPXVWꢀEHꢀORZꢀGXULQJꢀWRJJOHꢀELWꢀVWDWXVꢀUHDGVꢁꢀ%XWꢀ'4ꢌꢀFDQQRWꢀGLVWLQJXLVKꢀ
ZKHWKHUꢀWKHꢀVHFWRUꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀRUꢀLVꢀHUDVHꢃVXVSHQGHGꢁꢀ'4ꢇꢂꢀE\ꢀFRPSDULVRQꢂꢀLQGLFDWHVꢀ
ZKHWKHUꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢂꢀRUꢀLVꢀLQꢀ(UDVHꢀ6XVSHQGꢂꢀEXWꢀFDQQRWꢀGLVWLQJXLVKꢀZKLFKꢀVHFꢃ
WRUVꢀDUHꢀVHOHFWHGꢀIRUꢀHUDVXUHꢁꢀ7KXVꢂꢀERWKꢀVWDWXVꢀELWVꢀDUHꢀUHTXLUHGꢀIRUꢀVHFWRUꢀDQGꢀPRGHꢀLQIRUPDWLRQꢁꢀ
5HIHUꢀWRꢀ7DEOHꢀꢇꢑꢀWRꢀFRPSDUHꢀRXWSXWVꢀIRUꢀ'4ꢌꢀDQGꢀ'4ꢇꢁꢀ
6HHꢀWKHꢀIROORZLQJꢀIRUꢀDGGLWLRQDOꢀLQIRUPDWLRQꢄꢀꢅWRJJOHꢀELWꢀIORZFKDUWꢆꢂꢀ'4ꢇꢄꢀ7RJJOHꢀ%LWꢀ,ꢀꢅGHVFULSꢃ
WLRQꢆꢂꢀ)LJXUHꢀꢈꢈꢀꢅWRJJOHꢀELWꢀWLPLQJꢀGLDJUDPꢆꢂꢀDQGꢀ7DEOHꢀꢇꢋꢀꢅFRPSDUHVꢀ'4ꢌꢀDQGꢀ'4ꢇꢆꢁꢀ
START
Read Byte
DQ7-DQ0
Address = VA
Read Byte
DQ7-DQ0
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
DQ7-DQ0
Adrdess = VA
No
DQ6 = Toggle?
Yes
FAIL
PASS
Note:
7KHꢂV\VWHPꢂVKRXOGꢂUHFKHFNꢂWKHꢂWRJJOHꢂELWꢂHYHQꢂLIꢂ'4ꢊꢂ ꢂ³ꢀ´ꢂEHFDXVHꢂWKHꢂWRJJOHꢂELWꢂPD\ꢂVWRSꢂ
WRJJOLQJꢂDVꢂ'4ꢊꢂFKDQJHVꢂWRꢂ³ꢀꢁ´ꢂ6HHꢂ'4ꢌꢃꢂ7RJJOHꢂ%LWꢂ,ꢂDQGꢂ'4ꢄꢃꢂ7RJJOHꢂ%LWꢂ,,IRUꢂPRUHꢂLQIRUꢉ
PDWLRQ
Figure 75. Toggle Bit Algorithm
186
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 63. DQ6 and DQ2 Indications
,IꢀGHYLFHꢀLV
DQGꢀWKHꢀV\VWHPꢀUHDGV
DWꢀDQ\ꢀDGGUHVVꢂ
WKHQꢀ'4ꢋ
WRJJOHVꢂ
DQGꢀ'4ꢉ
GRHVꢀQRWꢀWRJJOHꢁ
SURJUDPPLQJꢂ
DWꢀDQꢀDGGUHVVꢀZLWKLQ
DꢀVHFWRUꢀVHOHFWHGꢀIRUꢀHUDVXUHꢂ
WRJJOHVꢂ
DOVRꢀWRJJOHVꢁ
GRHVꢀQRWꢀWRJJOHꢁ
WRJJOHVꢁ
DFWLYHO\ꢀHUDVLQJꢂ
HUDVHꢀVXVSHQGHGꢂ
DWꢀDQꢀDGGUHVVꢀZLWKLQ
VHFWRUVꢀQRWꢀVHOHFWHGꢀIRUꢀHUDVXUHꢂ
WRJJOHVꢂ
DWꢀDQꢀDGGUHVVꢀZLWKLQ
DꢀVHFWRUꢀVHOHFWHGꢀIRUꢀHUDVXUHꢂ
GRHVꢀQRWꢀWRJJOHꢂ
UHWXUQVꢀDUUD\ꢀGDWDꢁ
7KHꢀV\VWHPꢀFDQꢀUHDGꢀIURPꢀDQ\
VHFWRUꢀQRWꢀVHOHFWHGꢀIRUꢀHUDVXUHꢁ
DWꢀDQꢀDGGUHVVꢀZLWKLQ
UHWXUQVꢀDUUD\ꢀGDWDꢂ
WRJJOHVꢂ
VHFWRUVꢀQRWꢀVHOHFWHGꢀIRUꢀHUDVXUHꢂ
SURJUDPPLQJꢀLQ
HUDVHꢀVXVSHQG
DWꢀDQ\ꢀDGGUHVVꢂ
LVꢀQRWꢀDSSOLFDEOHꢁ
Reading Toggle Bits DQ6/DQ2
:KHQHYHUꢀWKHꢀV\VWHPꢀLQLWLDOO\ꢀEHJLQVꢀUHDGLQJꢀWRJJOHꢀELWꢀVWDWXVꢂꢀLWꢀPXVWꢀUHDGꢀ'4ꢏ±'4ꢉꢀDWꢀOHDVWꢀ
WZLFHꢀLQꢀDꢀURZꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀDꢀWRJJOHꢀELWꢀLVꢀWRJJOLQJꢁꢀ7\SLFDOO\ꢂꢀWKHꢀV\VWHPꢀZRXOGꢀQRWHꢀDQGꢀ
VWRUHꢀWKHꢀYDOXHꢀRIꢀWKHꢀWRJJOHꢀELWꢀDIWHUꢀWKHꢀILUVWꢀUHDGꢁꢀ$IWHUꢀWKHꢀVHFRQGꢀUHDGꢂꢀWKHꢀV\VWHPꢀZRXOGꢀFRPꢃ
SDUHꢀWKHꢀQHZꢀYDOXHꢀRIꢀWKHꢀWRJJOHꢀELWꢀZLWKꢀWKHꢀILUVWꢁꢀ,IꢀWKHꢀWRJJOHꢀELWꢀLVꢀQRWꢀWRJJOLQJꢂꢀWKHꢀGHYLFHꢀKDVꢀ
FRPSOHWHGꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢁꢀ7KHꢀV\VWHPꢀFDQꢀUHDGꢀDUUD\ꢀGDWDꢀRQꢀ'4ꢏ±'4ꢉꢀRQꢀWKHꢀ
IROORZLQJꢀUHDGꢀF\FOHꢁ
+RZHYHUꢂꢀLIꢀDIWHUꢀWKHꢀLQLWLDOꢀWZRꢀUHDGꢀF\FOHVꢂꢀWKHꢀV\VWHPꢀGHWHUPLQHVꢀWKDWꢀWKHꢀWRJJOHꢀELWꢀLVꢀVWLOOꢀWRJꢃ
JOLQJꢂꢀWKHꢀV\VWHPꢀDOVRꢀVKRXOGꢀQRWHꢀZKHWKHUꢀWKHꢀYDOXHꢀRIꢀ'4ꢍꢀLVꢀKLJKꢀꢅVHHꢀ'4ꢍꢄꢀ([FHHGHGꢀ7LPLQJꢀ
/LPLWVꢆꢁꢀ,IꢀLWꢀLVꢂꢀWKHꢀV\VWHPꢀVKRXOGꢀWKHQꢀGHWHUPLQHꢀDJDLQꢀZKHWKHUꢀWKHꢀWRJJOHꢀELWꢀLVꢀWRJJOLQJꢂꢀVLQFHꢀ
WKHꢀWRJJOHꢀELWꢀPD\ꢀKDYHꢀVWRSSHGꢀWRJJOLQJꢀMXVWꢀDVꢀ'4ꢍꢀZHQWꢀKLJKꢁꢀ,IꢀWKHꢀWRJJOHꢀELWꢀLVꢀQRꢀORQJHUꢀ
WRJJOLQJꢂꢀWKHꢀGHYLFHꢀKDVꢀVXFFHVVIXOO\ꢀFRPSOHWHGꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQꢁꢀ,IꢀLWꢀLVꢀVWLOOꢀWRJꢃ
JOLQJꢂꢀWKHꢀGHYLFHꢀGLGꢀQRWꢀFRPSOHWHGꢀWKHꢀRSHUDWLRQꢀVXFFHVVIXOO\ꢂꢀDQGꢀWKHꢀV\VWHPꢀPXVWꢀZULWHꢀWKHꢀ
UHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢁꢀ
7KHꢀUHPDLQLQJꢀVFHQDULRꢀLVꢀWKDWꢀWKHꢀV\VWHPꢀLQLWLDOO\ꢀGHWHUPLQHVꢀWKDWꢀWKHꢀWRJJOHꢀELWꢀLVꢀWRJJOLQJꢀDQGꢀ
'4ꢍꢀKDVꢀQRWꢀJRQHꢀKLJKꢁꢀ7KHꢀV\VWHPꢀPD\ꢀFRQWLQXHꢀWRꢀPRQLWRUꢀWKHꢀWRJJOHꢀELWꢀDQGꢀ'4ꢍꢀWKURXJKꢀVXFꢃ
FHVVLYHꢀUHDGꢀF\FOHVꢂꢀGHWHUPLQLQJꢀWKHꢀVWDWXVꢀDVꢀGHVFULEHGꢀLQꢀWKHꢀSUHYLRXVꢀSDUDJUDSKꢁꢀ$OWHUQDWLYHO\ꢂꢀ
LWꢀPD\ꢀFKRRVHꢀWRꢀSHUIRUPꢀRWKHUꢀV\VWHPꢀWDVNVꢁꢀ,QꢀWKLVꢀFDVHꢂꢀWKHꢀV\VWHPꢀPXVWꢀVWDUWꢀDWꢀWKHꢀEHJLQQLQJꢀ
RIꢀWKHꢀDOJRULWKPꢀZKHQꢀLWꢀUHWXUQVꢀWRꢀGHWHUPLQHꢀWKHꢀVWDWXVꢀRIꢀWKHꢀRSHUDWLRQꢁ
DQ5: Exceeded Timing Limits
'4ꢍꢀLQGLFDWHVꢀZKHWKHUꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀWLPHꢀKDVꢀH[FHHGHGꢀDꢀVSHFLILHGꢀLQWHUQDOꢀSXOVHꢀFRXQWꢀ
OLPLWꢁꢀ8QGHUꢀWKHVHꢀFRQGLWLRQVꢀ'4ꢍꢀSURGXFHVꢀDꢀ³ꢊꢂ´ꢀLQGLFDWLQJꢀWKDWꢀWKHꢀSURJUDPꢀRUꢀHUDVHꢀF\FOHꢀZDVꢀ
QRWꢀVXFFHVVIXOO\ꢀFRPSOHWHGꢁ
7KHꢀGHYLFHꢀPD\ꢀRXWSXWꢀDꢀ³ꢊ´ꢀRQꢀ'4ꢍꢀLIꢀWKHꢀV\VWHPꢀWULHVꢀWRꢀSURJUDPꢀDꢀ³ꢊ´ꢀWRꢀDꢀORFDWLRQꢀWKDWꢀZDVꢀ
SUHYLRXVO\ꢀSURJUDPPHGꢀWRꢀ³ꢉꢁ´ꢀ2QO\ꢀDQꢀHUDVHꢀRSHUDWLRQꢀFDQꢀFKDQJHꢀDꢀ³ꢍ´ꢀEDFNꢀWRꢀDꢀ³ꢄꢅ´
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
187
A d v a n c e I n f o r m a t i o n
DQ3: Sector Erase Start Timeout State Indicator
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188
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S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
Table 64. Write Operation Status
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
189
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
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66
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Figure 77. Maximum Positive Overshoot Waveform
190
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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A d v a n c e I n f o r m a t i o n
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September 23, 2005 S75NS128NDE_00 A2
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193
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September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
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S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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S75NS128NDE based MCPs
199
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AC Characteristics
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Read Status Data
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200
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
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chip erase
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Figure 85. Chip/Sector Erase Operations
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
201
A d v a n c e I n f o r m a t i o n
AC Characteristics
CE#
AVD#
WE#
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PA
A/DQ15
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Figure 86. Accelerated Unlock Bypass Programming Timing
202
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
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High Z
A
– A16
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Figure 87. Data# Polling Timings
(During Embedded Algorithm)
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tOEZ
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High Z
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Figure 88. Toggle Bit Timings (During Embedded Algorithm)
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
203
A d v a n c e I n f o r m a t i o n
AC Characteristics
Address wraps back to beginning of address group.
Initial Access
CLK
39
39
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3B
3C
3D
3E
3F
38
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D2
D3
D4
D5
D6
D7
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204
S75NS128NDE based MCPs
S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in the same memory
region and/or array data from other region
Begin another
write or program
command sequence
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tRC
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tOEH
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tAH
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system should read the status twice to ensure valid information.
Figure 91. Back-to-Back Read/Write Cycle Timings
September 23, 2005 S75NS128NDE_00 A2
S75NS128NDE based MCPs
205
A d v a n c e I n f o r m a t i o n
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S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
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207
A d v a n c e I n f o r m a t i o n
S99KS-N Revision Summary
Revision A0 (December 14, 2004)
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S75NS128NDE_00 A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
MCP Revision Summary
Revision A0 (December 24, 2004)
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is with-
out warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-
party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the
information in this document.
Copyright © 2004-2005 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Span-
sion. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
September 23, 2005 S75NS128NDE_00_A2
S75NS128NDE based MCPs
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