CY2SSTU32864_技术文档

CY2SSTU32864

1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register

The device monitors both DCS# and CSR# inputs and will gate

the Qn outputs from changing states when both DCS# and

Features

• Operating frequency: DC to 500 MHz

• Supports DDRII SDRAM

CSR# inputs are high. If either DCS# or CSR# input is low, the

Qn outputs will function normally. The RESET input has priority

over the DCS# and CSR# control and will force the outputs

low. If the DCS#-control functionality is not desired, the CSR#

input can be hardwired to ground, in which case the set-up

time requirement for DCS# would be the same as for the other

D data inputs.

• Two operations modes: 25 bit (1:1) and 14 bit (1:2)

• 1.8V operation

• Fully JEDEC-compliant (JESD82-7A)

• 96-ball FBGA

The device supports low-power standby operation. When the

reset input (RESET#) is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference

voltage (VREF) inputs are allowed. In addition, when RESET#

is low, all registers are reset and all outputs are forced low. The

LVCMOS RESET# and Cn inputs must always be held at a

valid logic high or low level. To ensure defined outputs from the

register before a stable clock has been supplied, RESET#

must be held in the low state during power-up.

Functional Description

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8V CMOS drivers that have been optimized to

drive the DDR-II DIMM load. The CY2SSTU32864 operates

from a differential clock (CK and CK#). Data are registered at

the crossing of CK going high, and CK# going low.

In the DDR-II RDIMM application, RESET# is specified to be

completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between

the two. When entering reset, the register will be cleared and

the outputs will be driven low quickly, relative to the time to

disable the differential input receivers. However, when coming

out of reset, the register will become active quickly, relative to

the time to enable the differential input receivers.

The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when low) to B configuration (when

high). The C1 input controls the pinout configuration from

25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and

C1 = 0 is not allowed and it will default to the C0 = C1 = 0 state.

Pin Configurations

1

2

3

4

5

6

1

2

3

4

5

6

1

2

3

4

5

6

A

B

C

D

DCKE NC

VREF VDD QCKEA QCKEB

A

B

C

D

DCKE NC

VREF VDD QCKE NC

A

B

C

D

E

F

D1

D2

D3

D4

D5

D6

NC

CK

NC

VREF VDD Q1A

GND GND Q2A

VDD VDD Q3A

GND GND Q4A

VDD VDD Q5A

GND GND Q6A

Q1B

D2

D3

NC

GND GND Q2A

VDD VDD Q3A

Q2B

Q3B

Q2B

Q3B

Q4B

Q5B

Q6B

C0

D2

D3

D15

D16

GND GND Q2

VDD VDD Q3

Q15

Q16

DODT NC

GND GND QODTA QODTB

DODT NC

GND GND QODT NC

E

F

G

H

J

D5

NC

VDD VDD Q5A

GND GND Q6A

Q5B

Q6B

C0

E

F

G

H

J

D5

D17

D18

VDD VDD Q5

GND GND Q6

Q17

Q18

C0

D6

NC

CK

RST# VDD VDD C1

G

H

J

RST# VDD VDD C1

NC

CK

RST# VDD VDD C1

DCS# GND GND QCSA# QCSB#

CSR# VDD VDD ZOH ZOL

DCS# GND GND QCSA# QCSB#

CSR# VDD VDD ZOH ZOL

DCS# GND GND QCS# NC

CSR# VDD VDD ZOH ZOL

CK#

D8

CK#

D8

CK#

D8

K

L

NC

GND GND Q8A

VDD VDD Q9A

Q8B

Q9B

K

L

NC

GND GND Q8A

VDD VDD Q9A

Q8B

Q9B

K

L

D19

D20

D21

D22

D23

D24

D25

GND GND Q8

VDD VDD Q9

GND GND Q10

VDD VDD Q11

GND GND Q12

VDD VDD Q13

VREF VDD Q14

Q19

Q20

Q21

Q22

Q23

Q24

Q25

D9

M

N

P

R

T

D10

D11

D12

D13

D14

GND GND Q10A Q10B

VDD VDD Q11A Q11B

GND GND Q12A Q12B

VDD VDD Q13A Q13B

VREF VDD Q14A Q14B

M

N

D10

GND GND Q10A Q10B

VDD VDD QODTA QODTB

M

N

P

R

T

D10

D11

D12

D13

D14

DODT NC

P

R

T

D12

D13

NC

GND GND Q12A Q12B

VDD VDD Q13A Q13B

VREF VDD QCKEA QCKEB

DCKE NC

1

2

3

4

5

6

1

2

3

4

5

6

2

3

4

5

6

1:2 Register A C0 = 0, C1 = 1

1:2 Register B C0 = 1, C1 = 1

1:1 Register C0 = 0, C1 = 0

Rev 1.0, November 25, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 9

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

CY2SSTU32864

Pin Definitions

Pin Number

(C0 = 0, C1 = 0)

Pin Number

(C0 = 0, C1 = 1)

Pin Number

(C0 = 1, C1 = 1)

Pin Name

GND

Description

B3, B4, D3, D4, F3, F4, B3,B4,D3,D4,F3, B3,B4,D3,D4,F3, Ground

H3, H4, K3, K4, M3, M4, F4,H3,H4,K3,K4, F4,H3,H4,K3,K4,

P3, P4

M3, M4, P3, P4

VDD

A4, C3, C4, E3, E4, G3, A4, C3, C4, E3, A4, C3, C4, E3,

G4, J3, J4, L3, L4, N3, E4, G3, G4, J3, J4, E4, G3, G4, J3, J4,

Power Supply Voltage

N4, R3, R4, T4

L3, L4, N3, N4, R3, L3, L4, N3, N4, R3,

R4, T4

A3, T3

J5

R4, T4

A3, T3

J5

VREF

ZOH

ZOL

CK

A3, T3

J5

Input Reference Voltage

Reserved

J6

Reserved

H1

Positive Master Clock

Negative Master Clock

Configuration Control Input

CK#

C0

J1

G6

G5

G2

G6

C1

G5

RESET#

G2

Asynchronous Reset – resets registers and

disables Vref data and clock differential input

receivers

CSR#

DCS#

D1

J2

ChipSelect–DisablesD1-D24whenbothCSR#

and DCS# are High (VDD)

H2

ChipSelect–DisablesD1-D24whenbothCSR#

and DCS# are High (VDD)

A1

Data Input – clocked in on the crossing points of

CK and CK#

D2-3

D4

B1, C1

D1

Data Input – clocked in on the crossing points of

CK and CK#

Data Input – clocked in on the crossing points of

CK and CK#

D5, 6, 8, 9, E1, F1, K1, L1, M1

10

E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data Input – clocked in on the crossing points of

CK and CK#

D11

N1

Data Input – clocked in on the crossing points of

CK and CK#

D12, 13

D14

P1, R1

T1

P1, R1

T1

P1, R1

Data Input – clocked in on the crossing points of

CK and CK#

Data Input – clocked in on the crossing points of

CK and CK#

D15-25

DODT

DCKE

Q1A

B2, C2, E2, F2, K2, L2,

M2, N2, P2, R2, T2

Data Input – clocked in on the crossing points of

CK and CK#

D1

A1

N1

The outputs of this register bit will not be

suspended by the DCS# and CSR# Control

A1

T1

The outputs of this register bit will not be

suspended by the DCS# and CSR# Control

A5

Data Outputs that are suspended by the DCS#

and CSR# control

Q2A–3A

Q4A

B5, C5

D5

Data Outputs that are suspended by the DCS#

and CSR# control

Data Outputs that are suspended by the DCS#

and CSR# control

Q5A,6A,8A, E5, F5, K5, L5, M5

9A, 10A

E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#

and CSR# control

Q11A

N5

Rev 1.0,November 25, 2006

Page 2 of 9

CY2SSTU32864

Pin Definitions (continued)

Pin Number

(C0 = 0, C1 = 0)

Pin Number

(C0 = 0, C1 = 1)

Pin Number

(C0 = 1, C1 = 1)

Pin Name

Description

Q12A, Q13A P5, R5

P5, R5

T5

P5, R5

Q14A

Q1B

T5

Data Outputs that are suspended by the DCS#

and CSR# control

A6

Data Outputs that are suspended by the DCS#

and CSR# control

Q2B-3B

Q4B

B6, C6

D6

Data Outputs that are suspended by the DCS#

and CSR# control

Data Outputs that are suspended by the DCS#

and CSR# control

Q5B,6B,8B,

9B, 10B,

E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#

and CSR# control

Q11B

N6

Data Outputs that are suspended by the DCS#

and CSR# control

Q12B, 13B

Q14B

P6, R6

T6

P6, R6

Data Outputs that are suspended by the DCS#

and CSR# control

Data Outputs that are suspended by the DCS#

and CSR# control

Q15–25

QCSA#

QCSB#

QODTA

QODTB

QCKEA

QCKEB

NC

B6, C6, E6, F6, K6, L6,

M6, N6, P6, R6, T6

Data Outputs that are suspended by the DCS#

and CSR# control

H5

D5

A5

H5

H6

D5

D6

A5

A6

H5

Data outputs that will not be suspended by the

DCS# and CSR# control

H6

Data outputs that will not be suspended by the

DCS# and CSR# control

N5

Data outputs that will not be suspended by the

DCS# and CSR# control

N6

Data outputs that will not be suspended by the

DCS# and CSR# control

T5

Data outputs that will not be suspended by the

DCS# and CSR# control

T6

Data outputs that will not be suspended by the

DCS# and CSR# control

A2, A6, D2, D6, G1, H6 A2, B2, C2, D2,

A2, B2, C2, D2,

No Connect Pins

E2, F2, G1, K2, L2, E2, F2, G1, K2, L2,

M2, N2, P2, R2, T2 M2, N2, P2, R2, T2

Rev 1.0,November 25, 2006

Page 3 of 9

CY2SSTU32864

Table 1. Flip Flop Function Table

Inputs

CK

Outputs

RESET#

DCS#

CSR#

CK#

Dn, DODT, DCKE

Qn

QCS# QODT, QCKE

H

L

H

L

H

L

L or H

X

Q0

L

Q0

L

Q0

L

H

L

H

L

H

L

X

Q0

L

Q0

H

Q0

L

H

L

H

L

X

Q0

L

Q0

H

Q0

L

H

L

H

X

H

Q0

L

Q0

L

X or Floating X or Floating X or Floating X or Floating

X or Floating

Rev 1.0,November 25, 2006

Page 4 of 9

CY2SSTU32864

Absolute Maximum Conditions ^[1]

Parameter

Description

Input Voltage Range^{[2, 3]}

Output Voltage Range^{[2, 3]}

Storage Temperature

Condition

Min.

–0.5

–65

Max.

V_DD+ 0.5

150

Unit

V

V_IN

V_OUT

T_S

V

°C

V

V_CC

I_IK

I_OK

I_O

Supply Voltage Range

–0.5

–50

2.5

Input Clamp Current

V_O< 0 or V_O> V_DD

V_O= 0 to V_DD

50

mA

Output Clamp Current

–50

50

Continuous Output Current

Continuous Current through VDD/GND

–50

50

–100

100

DC Electrical Specifications

Parameter

T_A

Description

Ambient Operating Temp

Operating Voltage

Conditions

Min.

0

Max.

70

Unit

C

V_DD

1.7

1.9

V

V_ICR

Input Differential Common CK, CK#

Mode Voltage Range

0.675

1.125

V

V_ID

V_REF

V_TT

V_I

Input Differential Voltage CK, CK#

Voltage Reference

600

–

mV

V

0.49*V_DD

0.51*V_DD

Terminating Voltage

V_REF– 40 mV V_REF+ 40 mV

V

Input Voltage

0

V_DD

V

I_I

Input Current

V_I= V_DDor GND

–5

5

PA

V

V_IL

AC Input Low Voltage

DC Input Low Voltage

AC Input High Voltage

DC Input High Voltage

Output Low Voltage

Data Inputs

–

V_REF– 250 mV

–

V

_REF– 125mV

V

V_IH

V_REF+ 250 mV

–

V

V_REF+ 125 mV

V

V_OL

I_OL= 100 PA, V_CC= 1.7V to 1.9V

_OL= 6 mA, V_CC= 1.7V

I_OH= –100 PA, V_CC= 1.7V to 1.9V

_OH= –6 mA, V_CC= 1.7V

–

0.2

0.5

–

V

I

–

V

V_OH

Output High Voltage

V_DD– 0.2

V

I

1.2

–

V

I_OH

I_OL

I_DD

Output High Current

Output Low Current

–8

8

mA

PA

–

Static Standby Power

Supply Current

RESET# = G_ND, IO = 0, V_DD= 1.9V

100

Static Operating Power

Supply Current

RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC)

IO = 0, V_DD= 1.9V

,

40

mA

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stresses ratings only and functional

operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 2.5V (max.)

Rev 1.0,November 25, 2006

Page 5 of 9

CY2SSTU32864

DC Electrical Specifications (continued)

Parameter

Description

Conditions

Min.

Max.

Unit

I_DDD

Power Supply Current

Dynamic Operating Clock CK# switching 50% duty cycle,

RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC), CK,

28 (typical)

18 (typical)

36 (typical)

27 (typical)

2 (typical)

PA/MHz

Only

V_DD= 1.8V

Dynamic Operating per

each Data Input

RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC), CK,

CK# switching 50% duty cycle,

PA/MHz

V_DD= 1.8V, 1 IO switching 1:1 configuration

RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC), CK,

CK# switching 50% duty cycle,

V_DD= 1.8V, 1 IO switching 1:2 configuration

Low Power Active Mode, RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC), CK,

CLK only CK# switching 50% duty cycle,

_DD= 1.8V, CS Enabled

V

Low Power Active Mode RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC), CK,

per each Data Input

CK# switching 50% duty cycle,

_DD= 1.8V, 1 IO switching 1:1 configuration,

CS Enabled

V

RESET# = V_DD, V_I= V_IH(AC)or V_IL(AC), CK,

CK# switching 50% duty cycle,

V_DD= 1.8V, 1 IO switching 1:2 configuration;

CS Enabled

2 (typical)

PA/MHz

C_IN

Ci (Data)

V_I= V_REF250 mV

2.5

2

3.5

3

pF

Ci (CK and CK#)

Ci (RESET#)

V

_IX= 0.9V, V_ID= 600 mV

V_I= V_DDor GND

2.5

AC Timing Specifications

Parameter

Description

Clock Frequency

Pulse Duration

Conditions

Min.

–

Max.

Unit

MHz

ns

F_CLK

T_W

500

–

CK,CK# H or L

1

[4,5]

T_ACT

Differential Input Active Time

Differential Input Inactive Time

Set up Time

–

10

15

–

ns

[4,5]

T_INACT

T_SU

–

ns

DCS#beforecrossingCK,CK#,

CSR = H, CK going high

0.7

ns

DCS#beforecrossingCK,CK#,

CSR = L, CK going high

0.5

–

ns

CSR, ODT, CKE and data

before crossing CK,CK#, CK

going high

T_H

Hold Time

DCS#, CSRT#, ODT, CKE and

dataaftercrossingCK,CK#,CK

going high

0.5

–

ns

T_PDM

Propagation Delay without Switching

Propagation Delay with Switching

From CK, CK# to Q

1.86

1.87

ns

T_PDMS

From CK, CK# to Q –

simultaneous switching

T_rPHL

S_LR

Propagation Delay from High to Low

Slew Rate Rising

RESET# Start to Q Low

dv/dt_r (20 to 80%)

dv/dt_f (20 to 80%)

3

4

1

ns

1

–

V/ns

Slew Rate Falling

ꢀdv/dt '

Notes:

Delta between Rising/Falling Rates

4. Data and V

5. Data, V

REF

inputs must be low a minimum time of T max, after RESET# is taken high.

and clock inputs must be held at valid levels (not floating) a minimum time of T

REF

ACT

max after RESET# is taken low.

INACT

Rev 1.0,November 25, 2006

Page 6 of 9

CY2SSTU32864

VDD

R_L= 1000:

DUT

T_L= 350ps, 50:

C_L= 30pF

CK

Test Point

CK Inputs

OUT

Test Point

R_L= 1000:

R_L= 100:

Test Point

Note: C includes probe and jig capacitance

L

Figure 1. Test Load for Timing Measurements #1

VDD

DUT

R_L= 50:

Test Point

OUT

C_L= 10pF

Figure 2. Slew Rate Measurement Load High to Low

DUT

Test Point

OUT

C_L= 10pF

Figure 3. Slew Rate Measurement Load Low to High

RESET

VDD/2

Input

D

50%

t_inact

t_act

Figure 4. Active and Inactive Times

t_w

VID

V_ICR

Input

V_ICR

Figure 5. Pulse Duration

Rev 1.0,November 25, 2006

Page 7 of 9

CY2SSTU32864

CK

V_ICR

t_h

VID

t_su

VIH

V_REF

Input

V_REF

VIL

Figure 6. Set-up and Hold Times

CK

V

ICR

VID

ICR

CK

t_PLH

t_PHL

V

VOH

VOL

V

TT

Output

TT

Figure 7. Propagation Delay

RESET#

VIH

VDD/2

VIL

t_RPHL

V_TT

VOH

VOL

Output

Figure 8. Propagation Delay after RESET#

Rev 1.0,November 25, 2006

Page 8 of 9

CY2SSTU32864

Ordering Information

Part Number

CY2SSTU32864BFXC

CY2SSTU32864BFXCT

Package Type

Product Flow

96-pin FBGA

96-pin FBGA– Tape and Reel

Commercial, 0° to 85°C

Package Drawing and Dimensions

Ø0.05 M C

96 FBGA (5.5 x 13.5 x 1.2 mm) BA96A

Ø0.25 M C A B

Ø0.50 0.05ꢀ(96X

BOTTOM VIEW

TOP VIEW

A1 CORNER

1

2

3

4

5

9

5

4

3

2

1

A

B

A

B

C

D

C

D

E

F

G

H

J

G

H

J

DIMENSIONS IN MILLIMETERS

REFERENCE JEDEC MO-205

PKG. WEIGHT: 0.23 gms

K

L

K

L

M

PART #

N

P

R

T

N

P

R

T

BF(9A STANDARD PKG.

BP(9A LEAD FREE PKG.

2.00

A

0.80

B

5.50 0.10

4.00

B

5.50 0.10

0.15ꢀ46X

SEATING PLANE

C

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, November 25, 2006

Page 9 of 9


型号：	CY2SSTU32864
厂家：	SPECTRALINEAR INC
描述：	1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register 1.8V， 25位（1： 1）或14位（1： 2）的JEDEC兼容的数据寄存器
文件：	总9页 (文件大小：98K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY2SSTU32864 [SPECTRALINEAR]

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