SC660E [SPECTRALINEAR]

SMBus System Clock Buffer for Mobile Applications; SMBus的系统时钟缓冲器，用于移动应用程序


型号：	SC660E
厂家：	SPECTRALINEAR INC
描述：	SMBus System Clock Buffer for Mobile Applications SMBus的系统时钟缓冲器，用于移动应用程序时钟
文件：	总5页 (文件大小：70K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC660E

SMBus System Clock Buffer for Mobile Applications

Product Description

Features

• 10 output buffers for high clock fanout applications

The device is a high fanout system clock distributor. Its

primary application is to create the large quantity of clocks

needed to support a wide range of clock loads that are refer-

enced to a single existing clock. Loads of up to 30 pF are

supported. Primary application of this component is where

long traces are used to transport clocks from their generating

devices to their loads. The creation of EMI and the degra-

dation of waveform rise and fall times is greatly reduced by

running a single reference clock trace to this device and then

using it to regenerate the clock that drives shorter traces by

using the SC660 to generate the clocks at the target devices

EMI is therefore minimized and board real estate is saved.

• Each output can be internally disabled for EMI and power

consumption reduction.

• Separate power supply for each group of 2 clock outputs

for mixed voltage application.

• < 250ps skew between output clocks.

• 28-pin SSOP package for minimum board space

• Single output Tristate pin for testability

Block Diagram

Pin Configuration

VDDB

SDRAM(0:1)

VDDB

SDRAM0

SDRAM1

VSS

VDDB

SDRAM9

SDRAM8

VSS

SDRAM(2:3)

VDDB

SDRAM7

SDRAM6

VSS

SDRAM2

SDRAM3

VSS

SDRAM4

FIN

SDRAM5

VDDB

SDRAM5

VSS

SDRAM4

VSS

VDD

SDRAM(6:7)

VDD

VSS

SDATA

SCLOCK

SDATA

I2C

SCLOCK

SDRAM(8:9)

Rev 1.0, December 06, 2006

Page 1 of 5

www.SpectraLinear.com

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

SC660E

Pin Description

Pin No.

Name

PWR

I/O

Type

Description

FIN

PAD This pin is connected to the input reference clock. This clock

must be in the range of 10.0 to 100.0 Mhz.

2,3,6,7,11,18,22,23

,26,27

Sdram(0:9)

VddB

BUF1 Low skew output clocks.

PAD Buffer Output Enable pin. This pin is low it is used to place

all output clocks (CLK1:10) in a tri state condition. This

feature facilitates in production board level testing to be

easily implemented for the clocks that this device produces.

Has internal pull-up resistor.

Sdata

Vdd

I/O

PAD Serial Data for SMBus control interface. This pin receives

data streams from the SMBus bus and outputs an

acknowledge for valid data.

Sclock

Vss

PAD Serial Clock for SMBus control interface.

4, 8, 12, 16, 17, 21,

PWR

Ground pins for clock output buffers. These pins must be

returned to the same potential to reduce output clock skew.

1, 5, 10, 19, 24, 28

VddB

Vdd

PWR

Power for output clock buffers.

Pin for device core logic.

Maximum Ratings^[1]

Input Voltage Relative to VSS:................................VSS-0.3V

Input Voltage Relative to VDDQ or AVDD: ........... VDD+0.3V

Storage Temperature: .................................-65qC to + 150qC

Operating Temperature:.................................... 0qC to +85qC

Maximum Power Supply:................................................3.5V

This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precau-

tions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper

operation, Vin and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).

Note:

1. The voltage on any input or I/O pin cannot exceed the power pin during the power-up. Power supply sequencing is NOT required.

Rev 1.0,December 06, 2006

Page 2 of 5

SC660E

The device will respond to writes to 10 bytes (max) of data to

address D2 by generating the acknowledge (low) signal on the

SDATA wire following reception of each byte. The device will

not respond to any other control interface conditions. Previ-

ously set control registers are retained.

2-Wire SMBus Control Interface

The 2-wire control interface implements a write only slave

interface. The device cannot be read back. Sub-addressing is

not supported, thus all preceding bytes must be sent in order

to change one of the control bytes. The 2-wire control

interface allows each clock output to be individually enabled

or disabled.

Serial Control Registers

Following the acknowledge of the Address Byte, two additional

bytes must be sent:

During normal data transfer, the SDATA signal only changes

when the SDCLK signal is low, and is stable when SDCLK is

high. There are two exceptions to this. A high to low transition

on SDATA while SDCLK is high is used to indicate the start of

a data transfer cycle. A low to high transition on SDATA while

SDCLK is high indicates the end of a data transfer cycle. Data

is always sent as complete 8-bit bytes, after which an

acknowledge is generated. The first byte of a transfer cycle is

a 7-bit address with a Read/Write bit as the LSB. Data is

transferred MSB first.

1. “Command Code “ byte, and

2. “Byte Count” byte.

Although the data (bits) in the command is considered “don’t

care”; it must be sent and will be acknowledged.

After the Command Code and the Byte Count have been

acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)

described below will be valid and acknowledged.

Byte 0: Function Select Register (1 = enable, 0 = Stopped)

Bit

@Pup

Pin#

Description

reserved

SDRAM3 (Active = 1, Forced low = 0)

SDRAM2 (Active = 1, Forced low = 0)

SDRAM1 (Active = 1, Forced low = 0)

SDRAM0 (Active = 1, Forced low = 0)

Byte 1: Clock Register (1 = enable, 0 = Stopped)

Bit

@Pup

Pin#

Description

SDRAM9 (Active = 1, Forced low = 0)

SDRAM8 (Active = 1, Forced low = 0)

SDRAM7 (Active = 1, Forced low = 0)

SDRAM6 (Active = 1, Forced low = 0)

reserved

Byte 2: Clock Register ( 1 = enable, 0 = Stopped )

Bit

@Pup

Pin#

Description

SDRAM5 (Active = 1, Forced low = 0)

SDRAM4 (Active = 1, Forced low = 0)

Not Used

Rev 1.0,December 06, 2006

Page 3 of 5

SC660E

Electrical Characteristics

Parameter

Description

Input Low Voltage

Min.

Typ.

Max.

Units

Conditions

VIL

0.8

Vdc

VIH

IIL

Input High Voltage

Input Low Current

Input High Current

2.0

-66

Vdc

µA

IIH

0.4

µA

VOL

Output Low Voltage

IOL = 40mA

Vdc All Outputs (see buffer spec)

VOH

Output High Voltage

IOH = 30mA

2.4

Vdc All Outputs Using 3.3V Power

(see buffer spec)

Ioz

Tri-State leakage Current

Dynamic Supply Current

µA

Idd₆₆

160

Input frequency = 66 Mhz - All outputs on

and at 30 pF load

Idd₁₀₀

220

Input frequency 100 Mhz - All outputs on

and at 30 pF load

Isdd

ISC

TIR

Static Supply Current

Short Circuit Current

Input Rise Time

All outputs disabled no input clock

1 output at a time - 30 seconds

.8 to 2.4 volts

2.4

VDD = VDD1 thru VDD5 =3.3V r5%, , TA = -40ºC to +85ºC

Switching Characteristics

Parameter

Description

Output Duty Cycle

Min.

Typ.

Max.

Units

Conditions

Measured at 1.5V (50/50 in)

35 pF Load Measured at 1.5V

Buffer out/out Skew All Buffer

Outputs

250

tSKEW

TJCC

Buffer input to output Skew

Jitter Cycle to Cycle ^[2]

Jitter Absolute (Peak to Peak)^[2]

2.0

4.0

5.0

@ 35 pF loading

150

VDD = VDD1 thru VDD5 =3.3V r5%, , TA = -40ºC to +85ºC

TB40_ Type Buffer Characteristics (All Clock Outputs)

Parameter

IOH_min

IOH_max

IOL_min

IOL_max

Description

Pull-Up Current Min

Min.

Typ.

Max.

Units

Conditions

Vout = VDD - .5V

Pull-Up Current Max

109

Vout = 1.5V

Vout = 0.4

Vout = 1.2V

Pull-Down Current Min

Pull-Down Current Max

Dynamic Output Impedance

103

Ohms 66 and 100 MHz

TRF_min

Rise/Fall Time Min

Between 0.4 V and 2.4 V

1.33

30 pF Load

TRF_max

Rise/Fall Time Max

Between 0.4 V and 2.4 V

1.33

30 pF Load

VDD = VDD1 thru VDD5 =3.3V r5%, , TA = -40ºC to +85ºC

Note:

2. This jitter is additive to the input clock’s jitter.

Rev 1.0,December 06, 2006

Page 4 of 5

SC660E

Ordering Information

Part Number

Package Type

Product Flow

Commercial,–40q to 85qC

SC660EYB

28-pin SSOP

Package Diagrams

28-Lead (5.3 mm) Shrunk Small Outline Package O28

1.14 DIA.

PIN 1 ID.

1.14

7.50

8.10

DIMENSIONS IN MILLIMETERS MIN.

MAX.

10.00

10.40

SEATING PLANE

.235 MIN.

GAUGE PLANE

0° MIN.

0.65 BSC.

2.00

MAX.

1.65

1.85

0.25

0.10

5.00

5.60

0.05

0.21

0°-8°

0.22

0.38

1.25 REF.

0.55

0.95

51-85079-*C

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, December 06, 2006

Page 5 of 5

SC660E [SPECTRALINEAR]

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