SL23EP04 [SPECTRALINEAR]
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer(ZDB); 低抖动和偏斜10到220兆赫零延迟缓冲器（ ZDB ）
| 型号： | SL23EP04 |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer(ZDB) |
| 文件： | 总14页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
SL23EP04
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
Description
The SL23EP04 is a low skew, low jitter and low power
Zero Delay Buffer (ZDB) designed to produce up to four
(4) clock outputs from one (1) reference input clock, for
high speed clock distribution applications.
x
x
x
10 to 220 MHz operating frequency range
Low output clock skew: 60ps-typ
Low output clock Jitter:
- 35 ps-typ at 166MHz, CL=15pF and VDD=3.3V
- 45 ps-typ at 166MHz, CL=15pF and VDD=2.5V
Low part-to-part output skew: 150 ps-typ
3.3V to 2.5V power supply range
Low power dissipation:
The product has an on-chip PLL and a feedback pin
(FBK) which can be used to obtain feedback from any
one of the 4 output clocks. The SL23EP04 offers X/2,1X
and 2X frequency options at the output with respect to
input reference clock. Refer to the “Product Configuration
Table” for the details of these options.
x
x
x
x
x
- 12 mA-typ at 66MHz and VDD=3.3V
- 10 mA-typ at 66MHz and VDD=2.5V
One input drives 4 outputs
The SL23EP04-1H and -2H High Drive version operates
up to 220 MHz and 200MHz at 3.3 and 2.5V power
supplies respectively. The standard versions -1 and -2
operate up to 167MHz and 135MHz at 3.3V and 2.5V
power supplies respectively with CL=15pF output load.
x
x
x
x
x
Multiple configurations and drive options
SpreadThru™ PLL that allows use of SSCG
Available in 8-pin SOIC package
The SL23EP04 enter into Power Down (PD) mode if the
input at CLKIN is DC (GND to VDD). In this state all 4
output clocks are tri-stated and the PLL is turned off,
leading to 8ȝA-typ power supply current draw.
Available in Commercial and Industrial grades
Applications
Benefits
x
x
x
x
x
Printers, MFPs and Digital Copiers
PCs and Work Stations
x
x
Up to four (4) distribution of input clock
Routers, Switchers and Servers
Datacom and Telecom
Standard and High-Drive levels to control
impedance level, frequency range and EMI
x
Low skew, jitter and power dissipation
High-Speed Digital Embeded Systems
Block Diagram
Rev 1.1, May 25, 2007
Page 1 of 14
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com
SL23EP04
Pin Configuration
8-Pin SOIC
Pin Description
Pin
Number
Pin Name
Pin Type
Pin Description
1
CLKIN
Input
Reference Frequency Clock Input. Weak pull-down (250kȍ).
2
3
4
5
6
7
8
CLKA1
CLKA2
GND
Output
Output
Power
Output
Output
Power
Input
Buffered Clock Output Weak pull-down (250kȍ).
Buffered Clock Output. Weak pull-down (250kȍ).
Power Ground.
CLKB1
CLKB2
VDD
Buffered Clock Output. Weak pull-down (250kȍ).
Buffered Clock Output. Weak pull-down (250kȍ).
2.5V to 3.3V Power Supply.
FBK
PLL Feedback Input. This pin must be connected to one of the clock outputs.
Rev 1.1, May 25, 2007
Page 2 of 14
SL23EP04
General Description
High and Low-Drive Product Options
The SL23EP04 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
All SL23EP04 products are offered with the high drive
“-1H” and “-2H” as well as the standard drive “-1” and “-2”
options. These drive options enable the user to control
load levels, frequency range and EMI levels. Refer to the
electrical tables for the details of the drive levels.
The product includes an on-chip high performance PLL
that locks into the input reference clock and produces
four (4) output clock drivers tracking the input reference
clock for systems requiring clock distribution.
Skew and Zero Delay
in addition to FBK pin used for internal PLL feedback,
there are two (2) banks with two (2) outputs in each bank,
bringing the number of total available output clocks to
four (4).
All outputs should drive the similar load to achieve output-
to-output skew and input-to-output delay specifications as
given in the switching electrical tables. However, the delay
between input and outputs can be adjusted by changing
the load at FBK pin relative to the banks A and B clocks
since FBK pin is the feedback to the internal PLL.
Input and output Frequency Range
The input and output frequency is the same (1x) for
SL23EP04-1 and -1H versions. For SL23EP04-2 and -
2H versions, the output frequency is 1/2x, 1x or 2x of
the CLKIN as given in the “Available SL23EP04
Configurations” Table 1. But, the frequency range
depends on VDD, drive levels and CL (Load
Capacitance) as given in the electrical specifications
tables.
In addition, the input reference clock rise and fall time
should be similar to the output rise and fall time to obtain
the best skew results.
Power Supply Range (VDD)
The SL23EP04 is designed to operate from 3.3V (3.63V-
max) to 2.5V (2.25V-min) VDD power supply range. An
internal on-chip voltage regulator is used to provide to
PLL constant power supply of 1.8V internally. This leads
to a consistent and stable PLL electrical performance in
terms of skew, jitter and power dissipation. The
When the input clock frequency is DC (from GND to
VDD), this input state is detected by an input level
detection circuitry and all four (4) clock outputs are forced
to Hi-Z. The PLL is shutdown to save power. In this
shutdown state, the product draws less than 12 ȝA
(8 ȝA –typ) supply current.
SL23EP04 I/O is powered by using VDD.
Contact SLI for 1.8V power supply ZDB called
SL23EPL04.
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as
an input clock, the SL23EP04 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from
its reference CLKIN input to the output clocks. The
same spread spectrum characteristics at the input are
passed through the PLL and drivers without any
degradation in spread percent (%), spread profile and
modulation frequency.
Device
Feedback From
Bank-A or Bank-B
Bank-A
Bank-A Frequency
Reference
Bank-B Frequency
Reference
SL23EP04-1 and 1H
SL23EP04-2 and -2H
SL23EP04-2 and -2H
Reference
Reference / 2
Reference
Bank-B
2 x Reference
Table 1. Available SL23EP04 Configurations
Rev 1.1, May 25, 2007
Page 3 of 14
SL23EP04
Absolute Maximum Ratings (All Products)
Description
Supply voltage, VDD
Condition
Min
-0.5
-0.5
0
Max
4.6
Unit
V
V
All Inputs and Outputs
VDD+0.5
70
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
In operation, C-Grade
In operation, I-Grade
°C
°C
°C
°C
°C
V
-40
-65
-
85
No power is applied
150
125
260
-
Junction Temperature
In operation, power is applied
Soldering Temperature
-
ESD Rating (Human Body Model)
MIL-STD-883, Method 3015
2000
Operating Conditions (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Operating Voltage
Symbol
VDD
TA
Condition
VDD+/-10%
Min
2.97
0
Typ
3.3
-
Max
3.63
70
Unit
V
Operating Temperature
Input Capacitance
Ambient Temperature
Pins 1 and 8
°C
VIH
-
5
7
pF
DC Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Input LOW Voltage
Symbol
VINL
Condition
CLKIN and FBK
Min
–
Typ
–
Max
0.8
Unit
V
Input HIGH Voltage
Input LOW Current
VINH
CLKIN and FBK
2.0
–
VDD+0.3
V
0 < VIN < 0.8V
CLKIN and FBK
IINL
IINH
–
–
20
20
50
50
µA
µA
2.4V < VIN < VDD
CLKIN and FBK
Input HIGH Current
Input LOW Voltage
Input HIGH Voltage
VINL
VINH
CLKIN and FBK
CLKIN and FBK
–
–
–
0.8
V
V
2.0
VDD+0.3
0 < VIN < 0.8V
CLKIN and FBK
Input LOW Current
Input HIGH Current
IINL
IINH
–
–
20
20
50
50
µA
µA
2.4V < VIN < VDD
CLKIN and FBK
IOL = 8 mA ( -1, -2 drives)
–
–
–
–
0.4
0.4
V
V
Output LOW Voltage
VOL
IOL = 12 mA (-1H, -2H drives)
Rev 1.1, May 25, 2007
Page 4 of 14
SL23EP04
DC Electrical Characteristics (C-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
Condition
Min
2.4
Typ
–
Max
Unit
IOH = –8 mA (-1, -2 drives)
IOH = –12 mA (-1H, -2H drives)
–
–
V
V
Output HIGH Voltage
VOH
2.4
–
Power Down Supply
Current
Measured when CLKIN= GND to VDD
or floating
IDDPD
IDD1
IDD2
IDD3
–
–
–
–
8
12
14
17
20
µA
mA
mA
mA
All Outputs CL=0, 33.3 MHz CLKIN
All versions
Power Supply Current
Power Supply Current
Power Supply Current
10
12
14
All Outputs CL=0, 66.6 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLKIN
All versions
All Outputs CL=0, 166.6 MHz CLKIN
All versions
Power Supply Current
Pull-down Resistors
IDD4
RPD
–
16
23
mA
Pin-1, 2, 3, 5, and 6
150
250
350
kȍ
Switching Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
FOUT1
FOUT2
FOUT3
FOUT4
FOUT5
FOUT6
DC1
Condition
Min
10
10
10
10
10
10
30
Typ
Max
220
200
135
200
135
100
70
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
CL=30pf, -1H and -2H versions
CL=15pf, -1, and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
Measured at VDD/2, all versions
-
-
-
Output Frequency Range
-
-
-
Input Duty Cycle
50
CL=30pF, Fout=66 MHz, all versions
Measured at 1.4V
Output Duty Cycle
DC2
DC3
DC4
DC5
40
45
45
45
50
50
50
50
60
55
55
55
%
%
%
%
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
tr/f1
tr/f2
tr/f3
CL=15pF, -1 and -2 versions
CL=15pF, -1 and -2 versions
CL=30pF -1H and -2H version
-
-
-
-
-
-
2.2
1.5
1.5
ns
ns
ns
Rev 1.1, May 25, 2007
Page 5 of 14
SL23EP04
Switching Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Output Rise/Fall Time
tr/f4
CL=15pF -1H and -2H version
-
-
-
1.2
ns
Output-to-Output Skew
on Same Bank
-1 and -2 measured at VDD/2
and outputs are equally loaded
SKW1
70
150
ps
ps
ps
Output-to-Output Skew
on Same Bank
-1H and -2H measured at VDD/2
and outputs are equally loaded
SKW2
SKW3
-
-
60
125
250
Output-to-Output Skew
Between Bank A and B
-1 and -2 measured at VDD/2
and outputs are equally loaded
110
Output-to-Output Skew
Between Bank A and B
-1H and -2H measured at VDD/2
and outputs are equally loaded
SKW4
SKW5
-
-
90
200
400
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
150
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Dt
-200
+/-70
200
ps
Fout=66.6 MHz and CL=15pF
Fout=66.6MHz and CL=30PF
Fout=133.3MHz and CL=15pF
Fout=66.6 MHz and CL=15pF
Fout=66.6MHz and CL=30PF
Fout=166.6MHz and CL=15pF
-
-
-
-
-
-
50
70
40
40
60
35
100
150
80
ps
ps
ps
ps
ps
ps
Cycle-to-Cycle Jitter
(-1 and, -2 Versions)
CCJ1
80
Cycle-to-Cycle Jitter
CCJ2
130
70
(-1H and -2H Versions)
From 0.95VDD and valid clock
presented at CLKIN
PLL Lock Time
tLOCK
-
-
1.0
ms
Operating Conditions (I-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Operating Voltage
Symbol
VDD
TA
Condition
VDD+/-10%
Min
2.97
-40
-
Typ
3.3
-
Max
3.63
85
Unit
V
Operating Temperature
Input Capacitance
Ambient Temperature
Pins 1 and 8
°C
VIH
5
8
pF
Rev 1.1, May 25, 2007
Page 6 of 14
SL23EP04
DC Electrical Characteristics (I-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°
Description
Input LOW Voltage
Input HIGH Voltage
Symbol
VINL
Condition
CLKIN and FBK
Min
–
Typ
–
Max
0.8
Unit
V
V
VINH
CLKIN and FBK
2.0
–
VDD+0.3
0 < VIN < 0.8V
CLKIN and FBK
Input LOW Current
Input HIGH Current
IINL
IINH
–
–
25
25
50
50
µA
µA
2.4V < VIN < VDD
CLKIN and FBK
IOL = 8 mA ( -1, -2 drives)
–
–
–
–
–
0.4
0.4
–
V
V
V
V
Output LOW Voltage
Output HIGH Voltage
VOL
VOH
IOL = 12 mA ( -1H, -2H drives)
IOH = –8 mA (-1, -2 drives)
IOH = –12 mA ( -1H, -2H drives)
–
2.4
2.4
–
Power Down Supply
Current
Measured when CLKIN= GND to VDD
or floating
IDDPD
IDD1
IDD2
IDD3
–
–
–
–
12
12
14
16
18
17
20
22
µA
mA
mA
mA
All Outputs CL=0, 33.3 MHz CLKIN
All versions
Power Supply Current
Power Supply Current
Power Supply Current
All Outputs CL=0, 66.6 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLKIN
All versions
All Outputs CL=0, 166.6 MHz CLKIN
All versions
Power Supply Current
Pull-down Resistors
IDD4
RPD
–
18
25
mA
Pin-1, 2, 3, 5 and 6
125
250
375
kȍ
Rev 1.1, May 25, 2007
Page 7 of 14
SL23EP04
DC Electrical Characteristics (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Input LOW Voltage
Input HIGH Voltage
Symbol
VINL
Condition
CLKIN and FBK
Min
–
Typ
–
Max
0.7
Unit
V
V
VINH
CLKIN and FBK
1.7
–
VDD+0.3
0 < VIN < 0.8V
CLKIN and FBK
Input LOW Current
Input HIGH Current
IINL
IINH
–
–
20
20
50
50
µA
µA
2.4V < VIN < VDD
CLKIN and FBK
IOL = 6 mA, -1 and -2 versions
IOL = 8 mA, -1H and -2H versions
IOH = –6 mA, -1 and -2 versions
IOH = –8 mA, -1H and -2H versions
–
–
–
–
–
0.3
0.3
–
V
V
V
V
Output LOW Voltage
Output HIGH Voltage
VOL
VOH
–
2.0
2.0
–
Power Down Supply
Current
Measured when CLKIN= GND to VDD
or floating
IDDPD
–
10
18
µA
All Outputs CL=0, 33.3 MHz CLKIN
All versions
Power Supply Current
Power Supply Current
Power Supply Current
IDD1
IDD2
IDD3
–
–
–
8
11
14
17
mA
All Outputs CL=0, 66.6 MHz CLKIN
All versions
10
12
mA
mA
All Outputs CL=0, 133.3 MHz CLKIN
All versions
All Outputs CL=0, 166.6 MHz CLKIN
All versions
Power Supply Current
Pull-down Resistors
IDD4
RPD
–
14
20
mA
Pin-1, 2, 3, 5 and 6
150
250
350
kȍ
Switching Electrical Characteristics (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
FOUT1
FOUT2
Condition
Min
10
Typ
Max
175
Unit
MHz
MHz
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
-
-
10
135
FOUT1
FOUT4
FOUT5
FOUT6
CL=30pf, -1H and -2H versions
CL=15pf, -1 and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
10
10
10
10
-
-
-
-
100
135
100
75
MHz
MHz
MHz
MHz
Output Frequency Range
Rev 1.1, May 25, 2007
Page 8 of 14
SL23EP04
Input Duty Cycle
DC1
DC2
Measured at VDD/2, all versions
40
45
50
50
60
55
%
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Duty Cycle
%
%
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
Output Duty Cycle
DC3
DC4
45
40
-
50
50
-
55
60
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
Output Duty Cycle
%
CL=30pF, -1 and -2 versions
Measured at 0.6 to 1.8V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
tr/f1
2.4
1.7
1.7
1.4
175
150
300
ns
ns
ns
ns
ps
ps
ps
CL=15pF, -1 and -2 versions
Measured at 0.6 to 1.8V
tr/f2
-
-
CL=30pF, -1H and -2H versions
Measured at 0.6 to 1.8V
tr/f3
-
-
CL=15pF, -1H and -2H versions
Measured at 0.6 to 1.8V
tr/f4
-
-
Output-to-Output Skew
on Same Bank
-1 and -2, measured at VDD/2
and outputs are equally loaded
SKW1
SKW2
SKW3
-
80
70
125
Output-to-Output Skew
on Same Bank
-1H and -2H, measured at VDD/2
and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1 and -2, measured at VDD/2
and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1H and -2H, measured at VDD/2
and outputs are equally loaded
SKW4
SKW5
-
-
110
175
250
450
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Dt
-250
+/-90
250
ps
Fout=66.6 MHz and CL=15pF
Fout=133.3 MHz and CL=15pF
-
-
70
60
140
120
ps
ps
Cycle-to-Cycle Jitter
(-1 and -2 Versions)
CCJ1
Switching Electrical Characteristics (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Fout=66.6 MHz and CL=15pF
Fout=166.6 MHz and CL=15pF
-
-
60
50
120
100
ps
ps
Cycle-to-Cycle Jitter
CCJ2
(-1H and -2H Versions)
From 0.95VDD and valid clock
presented at CLKIN
PLL Lock Time
tLOCK
-
-
1.0
ms
Rev 1.1, May 25, 2007
Page 9 of 14
SL23EP04
Operating Conditions (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Operating Voltage
Symbol
VDD
TA
Condition
VDD+/-10%
Min
2.25
-40
-
Typ
2.5
-
Max
2.75
85
Unit
V
Operating Temperature
Input Capacitance
Ambient Temperature
Pins 1 and 8
°C
pF
VIH
5
8
DC Electrical Characteristics (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°
Description
Input LOW Voltage
Input HIGH Voltage
Symbol
VINL
Condition
CLKIN and FBK
Min
–
Typ
–
Max
0.7
Unit
V
VINH
CLKIN and FBK
1.7
–
VDD+0.3
V
0 < VIN < 0.8V
CLKIN and FBK
Input LOW Current
Input HIGH Current
IINL
IINH
–
–
30
30
60
60
µA
µA
2.4V < VIN < VDD
CLKIN and FBK
IOL = 6 mA, -1 and -2 versions
IOL = 8 mA, -1H and -2H versions
IOH = –6 mA, -1 and -2 versions
IOH = –8 mA, -1H and -2H versions
–
–
–
–
–
0.3
0.3
–
V
V
V
V
Output LOW Voltage
Output HIGH Voltage
VOL
VOH
–
2.0
2.0
–
Power Down Supply
Current
Measured when CLKIN= GND to VDD
or floating
IDDPD
IDD1
IDD2
IDD3
–
–
–
–
15
10
12
14
25
14
17
20
µA
mA
mA
mA
All Outputs CL=0, 33.3 MHz CLKIN
All versions
Power Supply Current
Power Supply Current
Power Supply Current
All Outputs CL=0, 66.6 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLKIN
All versions
Power Supply Current
Pull-down Resistors
IDD4
–
16
24
mA
RPUD
Pin-1, 2, 3, 5 and 6
125
250
375
kȍ
Rev 1.1, May 25, 2007
Page 10 of 14
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Symbol
FOUT1
FOUT2
FOU3
Condition
Min
10
10
10
10
10
10
40
Typ
Max
175
135
100
135
100
75
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
CL=30pF, -1H and -2H versions
CL=15pf, -1 and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
Measured at VDD/2, all versions
-
-
-
Output Frequency Range
FOUT4
FOUT5
FOUT6
DC1
-
-
-
Input Duty Cycle
50
60
CL=30pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Duty Cycle
DC2
DC3
DC4
DC5
tr/f1
40
45
45
40
-
50
50
50
50
-
60
55
%
%
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Duty Cycle
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
Output Duty Cycle
55
%
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
Output Duty Cycle
60
%
CL=30pF, -1 and -2 versions
Measured at 0.6 to 1.8V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
2.5
1.8
1.8
1.5
220
220
220
ns
ns
ns
ns
ps
ps
ps
CL=15pF, -1 and -2 versions
Measured at 0.6 to 1.8V
tr/f2
-
-
CL=30pF, -1H and -2H versions
Measured at 0.6 to 1.8V
tr/f3
-
-
CL=15pF, -1H and -2H version
Measured at 0.6 to 1.8V
tr/f4
-
-
Output-to-Output Skew
on Same Bank
-1 and -2, measured at VDD/2, and
outputs are equally loaded
SKW1
SKW2
SKW3
-
100
100
100
Output-to-Output Skew
on Same Bank
-1H and -2H, measured at VDD/2 and
outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1 and -2, measured at VDD/2, and
outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1H and -2H, measured at VDD/2 and
outputs are equally loaded
SKW4
SKW5
-
-
180
225
375
550
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Dt
-300
+/-125
300
ps
Rev 1.1, May 25, 2007
Page 11 of 14
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=2.5V – Cont.)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Fout=66.6 MHz and CL=15pF
Fout=133.3 MHz and CL=15pF
Fout=66.6 MHz and CL=15pF
Fout=166.6 MHz and CL=15pF
From 0.95VDD and valid CLKIN
-
-
-
-
-
80
70
70
60
-
160
140
140
120
1.0
ps
ps
ps
ps
ms
Cycle-to-Cycle Jitter
(-1 and -2 Versions)
CCJ1
Cycle-to-Cycle Jitter
CCJ2
(-1H and -2H Versions)
PLL Lock Time
tLOCK
External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1ȝF must be used between VDD and VSS pins. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and
to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output
clocks and the load is over 1 ½ inch. Place the series termination resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero
Delay” between the CLKIN and the outputs. The FBK pin is connected to PLL internally on-chip for feedback and
should be connected to one of to output clocks externally. For applications requiring zero input/output delay, the load
at the all output pins including the FBK pin must be the same. If any delay adjustment is required, the capacitance at
the FBK pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks
relative to CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
In addition, the rise and fall time of the reference clock at CLKIN pin should be similar to rise and fall times at the
CLKA and CLK B bank outputs.
Rev 1.1, May 25, 2007
Page 12 of 14
SL23EP04
Package Outline and Package Dimensions
8-Pin SOIC (150 Mil)
Thermal Characteristics
Parameter
Symbol
ș JA
Condition
Min
Typ
150
140
120
40
Max
Unit
°C/W
°C/W
°C/W
°C/W
Still air
-
-
-
-
-
-
-
-
Thermal Resistance
Junction to Ambient
ș JA
1m/s air flow
3m/s air flow
ș JA
Thermal Resistance
Junction to Case
ș JC
Independent of air flow
Rev 1.1, May 25, 2007
Page 13 of 14
SL23EP04
Ordering Information [3]
Ordering Number
Marking
Shipping Package
Package
Temperature
SL23EP04SC-1
SL23EP04SC-1T
SL23EP04SI-1
SL23EP04SC-1
SL23EP04SC-1
SL23EP04SI-1
SL23EP04SI-1
SL23EP04SC-1H
SL23EP04SC-1H
SL23EP04SI-1H
SL23EP04SI-1H
SL23EP04SC-2
SL23EP04SC-2
SL23EP04SI-2
SL23EP04SI-2
SL23EP04SC-2H
SL23EP04SC-2H
SL23EP04SI-2H
SL23EP04SI-2H
Tube
Tape and Reel
Tube
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to 70°C
0 to 70°C
-40 to 85°C
-40 to 85°C
0 to 70°C
SL23EP04SI-1T
SL23EP04SC-1H
SL23EP04SC-1HT
SL23EP04SI-1H
SL23EP04SI-1HT
SL23EP04SC-2
SL23EP04SC-2T
SL23EP04SI-2
Tape and Reel
Tube
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
0 to 70°C
Tape and Reel
Tube
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
0 to 70°C
SL23EP04SI-2T
SL23EP04SC-2H
SL23EP04SC-2HT
SL23EP04SI-2H
SL23EP04SI-2HT
Tape and Reel
Tube
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
Tape and Reel
Notes:
3. The SL23EP04 products are RoHS compliant.
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use
of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product
is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical
instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental
requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra
Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.1, May 25, 2007
Page 14 of 14
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