W164 [SPECTRALINEAR]
Spread Spectrum Desktop/Notebook System Frequency Generator; 扩频台式机/笔记本电脑系统频率发生器
| 型号： | W164 |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Spread Spectrum Desktop/Notebook System Frequency Generator |
| 文件： | 总11页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W164
Spread Spectrum Desktop/Notebook System Frequency Generator
Features
Key Specifications
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Supply Voltages:....................................... VDDQ3 = 3.3V±±5
...............................................................................................
VDDQ2 = 2.±V±±5
• Reduces measured EMI by as much as 10 dB
• I2C programmable to 153 MHz (16 selectable
frequencies)
CPU Cycle to Cycle Jitter: .......................................... 200 ps
CPU, PCI Output Edge Rate:ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀt1 V/ns
CPU0:1 Output Skew: ................................................ 17± ps
PCI_F, PCI1:6 Output Skew: ...................................... ±00 ps
CPU to PCI Skew: ..............................1 to 4 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA ................2±0-k: pull-up
• Two skew-controlled copies of CPU output
• SEL100/66# selects CPU frequency (100 or 66.8 MHz)
• Seven copies of PCI output (synchronous w/CPU
output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
Note: Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.
• Selectable 24-/48-MHz output is determined by resistor
straps on power-up
Table 1. Pin Selectable Frequency
SEL100/66#
CPU(0:1)
100 MHz
66.8 MHz
PCI
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
1
0
33.3 MHz
33.4 MHz
• Isolated core VDD pin for noise reduction
Rev 1.0, November 28, 2006
Page 1 of 11
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
W164
Block Diagram
Pin Configuration
VDDQ3
X1
X2
GND
PCI_F
PCI1
PCI2
1
2
3
4
±
6
7
8
28
27
26
2±
24
23
22
21
20
19
18
17
16
1±
GND
REF2X/SEL48#
GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
X1
X2
XTAL
OSC
VDDQ3
IOAPIC
PLL Ref Freq
PCI3
PCI4
VDDQ3
PCI±
9
10
11
12
13
14
PCI6
SDATA
VDDQ3
48MHz
24/48MHz
SCLOCK
SEL100/66#
GND
VDDQ2
CPU0
CPU1
GND
100/66#_SEL
PLL 1
÷2/÷3/÷4
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
PCI±
PCI6
GND
2
SDATA
I C
LOGIC
SCLOCK
VDDQ3
48MHz
PLL2
24/48MHz
GND
Rev 1.0,November 28, 2006
Page 2 of 11
W164
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU0:1
22, 21
O
O
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI1:6
PCI_F
±, 6, 7, 8, 10,
11, 4
PCI Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection to
VDDQ3.
IOAPIC
48MHz
24
13
O
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24/48MHz
14
27
O
24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up.
REF2X/SEL48#
I/O
I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin
14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
SEL100/66#
SDATA
SCLOCK
X1
16
I
I/O
I
Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on
page 1.
18
I2C Data Pin: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 2±0-k: pull-up resistor.
I2C Clock Pin: The I2C data clock should be presented to this input as described in
the I2C section of this data sheet.
17
1
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
X2
2
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
VDDQ2
GND
9, 12, 20, 26
23, 2±
P
P
G
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.±V supply.
3, 1±, 19, 28
Ground Connections: Connect all ground pins to the common system ground
plane.
of the 2-ms period, the established logic “0” or “1” condition of
the l/O pin is then latched. Next the output buffer is enabled
which converts the l/O pin into an operating clock output. The
2-ms timer is started when VDD reaches 2.0V. The input bit can
Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with
input select pins.
only be reset by turning VDD off and then back on again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 2±: (nominal) which is minimally affected by
the 10-k: strap to ground or VDD. As with the series termi-
nation resistor, the output strapping resistor should be placed
as close to the l/O pin as possible in order to keep the inter-
connecting trace short. The trace from the resistor to ground
or VDD should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
An external 10-k: “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
When the clock output is enabled following the 2-ms input
period, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
Upon W164 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
output buffer is three-stated, allowing the output strapping
resistor on the l/O pin to pull the pin and its associated capac-
itive clock load to either a logic HIGH or LOW state. At the end
Rev 1.0,November 28, 2006
Page 3 of 11
W164
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
VDD
Output Strapping Resistor
Series Termination Resistor
10 k:
(Load Option 1)
Clock Load
W164
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 k:
(Load Option 0)
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
VDD
Series Termination Resistor
10 k:
Clock Load
W164
R
Output
Buffer
Power-on
Reset
Timer
Resistor Value R
Hold
Output
Low
Output Three-state
Q
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if required. The
interface can also be used during system operation for power
management functions. Table 2 summarizes the control
functions of the serial data interface.
Serial Data Interface
The W164 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W164
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
Operation
Data is written to the W164 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond
the 100- and 66.6-MHz selections that are provided management options. Smooth frequency
by the SEL100/66# pin. Frequency is changed in a transition allows CPU frequency change
For alternate microprocessors and power
smooth and controlled fashion.
under normal system operation.
Output Three-state
Test Mode
Puts all clock outputs into a high-impedance state. Production PCB testing.
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be
written as 0.
Rev 1.0,November 28, 2006
Page 4 of 11
W164
Table 3. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W164 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W164 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
3
Command
Code
Don’t Care
Don’t Care
Don’t Care
Unused by the W164, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Byte Count
Unused by the W164, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
4
±
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte ±
Data Byte 6
Refer to Cypress SDRAM drivers.
6
7
Refer to Table 4 The data bits in these bytes set internal W164 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.
8
9
10
Rev 1.0,November 28, 2006
Page ± of 11
W164
Writing Data Bytes
Table 5 details additional frequency selections that are
available through the serial data interface.
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 3–6.
Table 6 details the select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3–6 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 3
7
6
±
4
3
--
--
--
--
--
--
--
--
--
--
SEL_3
--
--
0
0
0
0
0
SEL_2
SEL_1
SEL_0
Refer to Table 5
Refer to Table 5
Refer to Table 5
Frequency Table
Selection
Frequency Controlled Frequency Controlled
by BYT3 SEL_(3:0)
Table 5
by external SEL100/
66# pin Table 1
2
--
--
--
--
(Reserved)
Bit 1 Bit 0
--
--
0
1–0
Function (See Table 6 for function details)
Normal Operation
Test Mode
Spread Spectrum on
All Outputs Three-stated
00
0
0
1
1
0
1
0
1
Data Byte 4
7
--
14
--
--
(Reserved)
--
--
Active
--
0
1
0
0
0
1
0
1
6
24/48MHz Clock output Disable
Low
--
±
--
--
(Reserved)
4
--
(Reserved)
--
--
3
--
--
(Reserved)
--
--
2
21
--
CPU1
--
Clock Output Disable
(Reserved)
Low
--
Active
--
1
0
22
CPU0
Clock Output Disable
Low
Active
Data Byte 5
7
4
11
10
-
PCI_F
PCI6
PCI±
--
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
Low
Low
Low
--
Active
Active
Active
--
1
1
1
0
1
1
1
1
6
±
4
3
8
PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
2
7
1
6
0
±
Data Byte 6
7
6
±
4
3
2
1
0
--
--
--
(Reserved)
--
--
--
--
0
0
--
IOAPIC
--
(Reserved)
24
--
Clock Output Disable
(Reserved)
Low
--
Active
--
1
0
--
--
(Reserved)
--
--
0
--
--
(Reserved)
--
--
0
27
27
REF2X
REF2X
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
1[1]
1[1]
Note:
1. Both Bits 0 and 1 of Byte 6 in Table 4 must be programmed as the same value.
Rev 1.0,November 28, 2006
Page 6 of 11
W164
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
If Spread Is On
Data Byte 3, Bit 3 = 1
Bit 7
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM
PCI Clocks
(MHz)
Clocks (MHz)
68.±
7±
Spread Percentage
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
±0.±5 Center
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
34.2±
37.±
83.3
66.8
103
41.6
33.4
34.2±
37.3
112
133.3
100
33.3
33.3
117
39.0
117
29.2±
31.0
124
129
32.2±
34.±
138
143
3±.7±
37.0
148
1±3
38.2±
Table 6. Select Function for Data Byte 3, Bits 0:1
Input Conditions
Output Conditions
REF2X,
Data Byte 3
Function
Normal Operation
Test Mode
Bit 1
Bit 0
CPU0:1
Note 2
X1/2
PCI_F, PCI1:6
IOAPIC
14.318 MHz
X1
48MHZ
24MHZ
24 MHz
X1/4
0
0
1
1
0
1
0
1
Note 2
48 MHz
X1/2
CPU/2, 3, or 4
Spread Spectrum
±0.±5
Hi-Z
±0.±5
Hi-Z
14.318 MHz
Hi-Z
48 MHz
Hi-Z
24 MHz
Hi-Z
Three-state
Note:
2. CPU and PCI frequency selections are listed in Table 1 and Table 5.
Rev 1.0,November 28, 2006
Page 7 of 11
W164
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Parameter
DD, VIN
TSTG
TA
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.± to +7.0
–6± to +1±0
0 to +70
Unit
V
V
°C
°C
°C
kV
Operating Temperature
TB
Ambient Temperature under Bias
Input ESD Protection
–±± to +12±
2 (min.)
ESDPROT
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±±5, VDDQ2 = 2.±V±±5
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDDQ3
Combined 3.3V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[4]
8±
30
mA
mA
IDDQ3
Combined 2.±V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[4]
Logic Inputs
VIL
Input Low Voltage
Input High Voltage
GND –
0.3
0.8
V
V
VIH
2.0
VDD
0.3
+
IIL
IIH
IIL
IIH
Input Low Current[±]
–2±
10
–±
±
µA
µA
µA
µA
Input High Current[±]
Input Low Current (SEL100/66#)
Input High Current (SEL100/66#)
Clock Outputs
VOL Output Low Voltage
Output High Voltage
IOL = 1 mA
±0
mV
V
VOH
VOH
IOL
IOH = –1 mA
3.1
2.2
±0
Output High Voltage CPU0:1/IOAPIC IOH = –1 mA
V
Output Low Current CPU0:1
PCI_F, PCI1:6
VOL = 1.2±V
VOL = 1.±V
VOL = 1.2±V
VOL = 1.±V
70
80
100
120
140
1±2
76
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
60
IOAPIC
REF2X
40
8±
100
40
130
±0
48MHz, 24MHz VOL = 1.±V
IOH
Output High Current CPU0:1
VOH = 1.2±V
VOH = 1.±V
VOH = 1.2±V
VOH = 1.±V
±0
70
100
120
1±±
1±0
94
PCI_F, PCI1:6
IOAPIC
60
70
40
87
REF2X
100
40
130
±0
48MHz, 24MHz VOH = 1.±V
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
±. W164 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
Rev 1.0,November 28, 2006
Page 8 of 11
W164
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±±5, VDDQ2 = 2.±V±±5 (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[6]
VDDQ3 = 3.3V
1.6±
13
V
CLOAD
Load Capacitance, as seen by
External Crystal[7]
pF
CIN,X1
X1 Input Capacitance[8]
Pin X2 unconnected
Except X1 and X2
26
pF
Pin Capacitance/Inductance
CIN Input Pin Capacitance
COUT
LIN
pF
pF
nH
Output Pin Capacitance
Input Pin Inductance
7
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V 5ꢀ,VDDQ2 = 2.5V± 5ꢀ, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.2±V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
tP
tH
tL
1±
±.2
±.0
1
1±.±
10
3.0
2.8
1
10.±
ns
ns
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
5
1
1
Duty Cycle
Measured on rising and falling edge at
1.2±V
4±
±±
4±
±±
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.2±V.
Maximum difference of cycle time
between two adjacent cycles.
200
2±0
ps
tSK
fST
Output Skew
Measured on rising edge at 1.2±V
Assumes full supply voltage reached
17±
3
17±
3
ps
Frequency Stabili-
ms
zation from Power-up within 1 ms from power-up. Short cycles
(cold start) exist prior to frequency stabilization.
Zo
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
20
20
:
Notes:
6. X1 input threshold voltage (typical) is V /2.
DD
7. The W164 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Rev 1.0,November 28, 2006
Page 9 of 11
W164
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF
CPU = 66.8/100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.±V
Min.
30
12
12
1
Typ.
Max.
Unit
ns
tP
tH
tL
High Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
ns
Low Time
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
5
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on rising and falling edge at 1.±V
4±
±±
2±0
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.±V. Maximum
difference of cycle time between two adjacent cycles.
ps
tSK
tO
Output Skew
Measured on rising edge at 1.±V
±00
4
ps
ns
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.±V. CPU leads PCI output.
1
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
20
:
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
5
f
14.31818
tR
tF
tD
fST
1
1
4
4
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.2±V
4±
±±
1.±
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Averagevalueduringswitchingtransition.Used
for determining series termination value.
1±
:
REF2X Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.318
MHz
tR
0.±
0.±
4±
2
2
V/ns
V/ns
5
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.±V
±±
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
ms
Power-up (cold start)
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
1±
:
Rev 1.0,November 28, 2006
Page 10 of 11
W164
48-MHz and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max. Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
24.004
MHz
fD
Deviation from 48 MHz
PLL Ratio
(48.008 – 48)/48
+167
ppm
m/n
tR
(14.31818 MHz x ±7/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
±7/17, ±7/34
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.±
0.±
4±
2
2
V/ns
V/ns
5
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.±V
±±
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
2±
:
Ordering Information
Ordering Code
Package Name
Package Type
W164
G
28-pin SOIC (300 mils)
Package Diagram
28-Lead Molded
SOIC S28
DIMENSIONS IN INCHES[MM]
MIN.
MAX.
PART #
DETAIL
A
S28.4 STANDARD PKG.
SZ28.4 LEAD FREE PKG.
EXTERNAL LEAD DESIGN
PIN 1 ID
14
1
.395[10.033]
.405[10.287]
.530[13.462]
.545[13.843]
.026[0.660]
.032[0.812]
.013[0.330]
.019[0.482]
.015[0.381]
.020[0.508]
15
28
OPTION 1
OPTION 2
SEATING PLANE
.720[18.288]
.730[18.542]
.090[2.286]
.109[2.768]
A
0.004[0.102]
.050[1.270]
TYP.
.007[0.177]
.013[0.330]
.015[0.381]
.050[1.270]
.002[0.050]
.014[0.355]
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 28, 2006
Page 11 of 11
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