W191 [SPECTRALINEAR]
Skew Controlled SDRAM Buffer; 偏斜受控SDRAM缓冲区
| 型号： | W191 |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Skew Controlled SDRAM Buffer |
| 文件： | 总9页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W191
Skew Controlled SDRAM Buffer
Key Specifications
Features
• Six skew controlled CMOS outputs
• Output skew between any two outputs is less than 150 ps
• SMBus Serial configuration interface
• 2.5 ns to 5 ns propagation delay
Supply Voltages:...................................... VDDQ3 = 3.3V 5ꢀ
Operating Temperature: (Commercial) ............. 0°C to +70°C
Operating Temperature: (Industrial).............. –40°C to +85°C
Input Threshold:...................................................1.5V typical
Maximum Input Voltage: .................................. VDDQ3 + 0.5V
Input Frequency: (Commercial) ........................0 to 133 MHz
Input Frequency: (Industrial).............................0 to 100 MHz
BUF_IN to SDRAM0:5 Propagation Delay:.......2.5 ns to 5 ns
Min. Output Edge Rate: .............................................1.0V/ns
Max. Output Skew: ..................................................... 150 ps
Output Duty Cycle:...................................45/55ꢀ worst case
Output Impedance: ...................................................15:typ.
• DC to 133 MHz operation (Commercial)
• DC to 100 MHz operation (Industrial)
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 16-pin SSOP
(Small Shrink Outline Package)
Pin Configuration[1]
Block Diagram
SDATA
SDRAM0
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDQ3
SDRAM5
GND
SMBus
Device Control
SCLOCK
SDRAM1
BUF_IN
GND
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM4
VDDQ3
SDRAM3
GND
BUF_IN
SDRAM2
VDDQ3
SDATA
SCLK
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLK.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 9
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
W191
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
SDRAM0:5
1, 3, 6,
11, 13, 15
O
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 2.5 to 5 ns. All outputs are skew controlled
to within 150 ps of each other.
BUF_IN
SDATA
4
8
I
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
I/O
SMBus Data input: Data should be presented to this input as described in the SMBus
section of this data sheet. Internal 250-k: pull-up resistor.
SCLOCK
VDDQ3
GND
9
I
SMBus clock input: The SMBus Data clock should be presented to this input as
described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor.
7, 12, 16
P
G
Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.
2, 5, 10,
14
Ground Connection: Connect all ground pins to the common system ground plane.
Serial Control
Overview
Serial control data is written to the W191 in ten bytes of eight
bits each. Bytes are written in the order shown in Table 1
The W191 is a skew controlled fanout buffer optimized for
interface with registered DIMMs.
Writing Data Bytes
Functional Description
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.
Table 1 gives the bit formats for registers located in Data
Bytes 0-2.
Output Drivers
The W191 output buffers are CMOS type which deliver a
rail-to-rail (GND to VDD) output voltage swing into a nominal
capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15:.
Table 1. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W191 to accept the bits in Data Bytes 0-6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W191 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
3
Command Code
Byte Count
Don’t Care
Don’t Care
Unused by the W191, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W191, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to
Table 2
The data bits in these bytes set internal W191 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 2.
6
7
Don’t Care
8
9
10
Rev 1.0,November 20, 2006
Page 2 of 9
W191
Table 2. Data Bytes 0–2 Serial Configuration Map[2]
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7
6
5
4
3
2
1
0
6
--
--
--
--
3
SDRAM2
Clock Output Disable
(Reserved)
Low
--
Active
--
--
--
(Reserved)
--
--
--
--
(Reserved)
--
--
--
(Reserved)
--
SDRAM1
--
Clock Output Disable
(Reserved)
Low
--
Active
--
--
1
SDRAM0
Clock Output Disable
--
--
Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7
6
5
4
3
2
1
0
--
15
--
--
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
--
Low
--
--
SDRAM5
Active
--
--
--
--
--
--
Active
--
13
--
SDRAM4
Clock Output Disable
(Reserved)
Low
--
--
--
--
--
(Reserved)
--
--
--
(Reserved)
--
--
Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7
6
5
4
3
2
1
0
11
--
--
--
--
--
--
--
SDRAM3
Clock Output Disable
(Reserved)
Low
--
Active
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
Note:
2. At power up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
Rev 1.0,November 20, 2006
Page 3 of 9
W191
Absolute Maximum Ratings[3]
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
Parameter
VDDQ3, VIN
TSTG
TB
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
Unit
V
–0.5 to + 7.0
–65 to + 150
–55 to + 125
0 to + 70
°C
°C
°C
°C
Ambient Temperature under Bias
Operating Temperature (Commercial)
Operating Temperature (Industrial)
TA
TA
–40 to + 85
DC Electrical Characteristics: TA = 0°C to +70°C (Commercial), VDDQ3 = 3.3V 5%,TA = –40°C to +85°C (Industrial),
V
DDQ3 = 3.3V 5% [4]
Parame-
ter
Description
Test Condition
BUF_IN = 100 MHz
BUF_IN = 100 MHz
Min.
Typ.
173
5
Max.
Unit
mA
mA
IDD
IDD
3.3V Supply Current
3.3V Supply Current in three-state
Logic Inputs (BUF_IN, OE, SCLOCK, SDATA)
VIL
Input Low Voltage
GND–0.3
2.0
0.8
VDDQ3+0.5
+5
V
V
VIH
Input High Voltage
IILEAK
IILEAK
Input Leakage Current, BUF_IN
Input Leakage Current[5]
–5
µA
µA
–20
+5
Logic Outputs (SDRAM0:5)
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOL = 1 mA
IOH = –1 mA
VOL = 1.5V
VOH = 1.5V
50
mV
V
3.1
65
70
100
110
160
185
mA
mA
IOH
Pin Capacitance/Inductance
CIN Input Pin Capacitance (Except BUF_IN)
5
6
7
pF
pF
nH
COUT
Output Pin Capacitance
Input Pin Inductance
LIN
Notes:
3. Multiple supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Outputs loaded by 6” 60 transmission lines with 20 pF capacitors.
5. OE, SCLOCK, and SDATA logic pins have a 250-k: internal pull-up resistor (not CMOS level).
:
Rev 1.0,November 20, 2006
Page 4 of 9
W191
AC Electrical Characteristics: TA = 0°C to +70°C (Commercial), VDDQ3 = 3.3V 5%,TA = -40°C to +85°C (Industrial),
VDDQ3 = 3.3V 5% (Lump Capacitance Test Load = 30pF)
Parameter
Description
Test Condition
Min.
0
Typ.
Max.
133
100
4.0
Unit
MHz
MHz
V/ns
fIN
fIN
tR
Input Frequency (Commercial)
Input Frequency (Industrial)
Output Rise Edge Rate
0
Measured from 0.4V
to 2.4V
1.0
tF
Output Fall Edge Rate
Measured from 2.4V
to 0.4V
1.0
4.0
V/ns
tSR
tSF
tEN
tDIS
tPR
tPF
tD
Output Skew, Rising Edges
Output Skew, Falling Edges
Output Enable Time
150
150
8.0
8.0
5.0
5.0
55
ps
ps
ns
ns
ns
ns
ꢀ
1.0
1.0
2.5
2.5
45
Output Disable Time
Rising Edge Propagation Delay
Falling Edge Propagation Delay
Duty Cycle
Measured at 1.5V
Zo
AC Output Impedance
15
:
Rev 1.0,November 20, 2006
Page 5 of 9
W191
pulse. A transitioning data line during a clock high pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
How To Use the Serial Data Interface
Electrical Requirements
Figure 1 illustrates electrical characteristics for the serial
interface bus used with the W191. Devices send data over the
bus with an open drain logic output that can (a) pull the bus
line low, or (b) let the bus default to logic 1. The pull-up resistor
on the bus (both clock and data lines) establish a default logic
1. All bus devices generally have logic inputs to receive data.
A write sequence is initiated by a “Start Bit” as shown in
Figure 3. A “Stop Bit” signifies that a transmission has ended.
As stated previously, the W191 sends an “acknowledge” pulse
after receiving eight data bits in each byte as shown in
Figure 4.
Although the W191 is a receive-only device (no data
write-back capability), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
Sending Data to the W191
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double
buffered). Partial transmission is allowed meaning that a trans-
mission can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Trans-
mission is truncated with either a stop bit or new start bit
(restart condition).
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration
total bus line capacitance.
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
VDD
VDD
~ 2k
:
~ 2k:
SERIAL BUS DATA LINE
SERIAL BUS CLOCK LINE
SDCLK
SDATA
SCLOCK
SDATA
CLOCK IN
DATA IN
DATA OUT
CLOCK IN
DATA IN
DATA OUT
N
N
N
CLOCK OUT
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
Figure 1. Serial Interface Bus Electrical Characteristics
.
Rev 1.0,November 20, 2006
Page 6 of 9
W191
TA
CK
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
A
K
Start
Bit
Stop
Bit
Figure 3. Serial Data Bus Start and Stop Bit
Rev 1.0,November 20, 2006
Page 7 of 9
W191
Signaling from System Core Logic
Start Condition
Stop Condition
Slave Address
(First Byte)
Command Code
(Second Byte)
Byte Count
(Third Byte)
Last Data Byte
(Last Byte)
LSB
0
MSB
1
SDATA
SCLOCK
SDATA
1
2
0
1
0
0
6
1
7
MSB
LSB
MSB
MSB
LSB
1
3
4
5
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
Acknowledgment Bit
from Clock Device
Signaling by Clock Device
Figure 4. Serial Data Bus Write Sequence
SDATA
t
SPF
t
t
t
LOW
DSU
DHD
t
SP
t
t
t
t
STHD
STHD
HIGH
SPSU
SCLOCK
t
SPSU
t
t
R
F
Figure 5. Serial Data Bus Timing Diagrams
Ordering Information
Ordering Code
W191HI
Package Type
Temperature Range
I = Industrial
16 pin = SSOP (150 mil)
16 pin = SSOP (150 mil)
W191H
Commercial
Rev 1.0,November 20, 2006
Page 8 of 9
W191
Package Diagrams
Shrink Small Outline Package (SSOP 150 inch)
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 9 of 9
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