MN5925 [SPECTRUM]
ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, PDIP32, PLASTIC, DIP-32;
| 型号： | MN5925 |
| 厂家： | 
SPECTRUM MICROWAVE, INC. |
| 描述： | ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, PDIP32, PLASTIC, DIP-32 光电二极管 转换器 |
| 文件： | 总8页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MN5925
12-Bit, 20MHz
Sampling A/D Converter
FEATURES
DESCRIPTION
The MN5925 is a monolithic 12-bit, 20MHz
sampling A/D converter with an on-board input
buffer and T/H amplifier. This device is packaged
in a small 32-pin plastic DIP and consumes 1.1
Watts of power from +/- 5V supplies.
·
·
·
12-Bit Resolution
20MHz Sampling Rate
120MHz Small Signal
Input Bandwidth
The MN5925 is TTL-compatible and provides an
over-range output bit. The device is clocked from
a single sampling clock.
·
·
+/-2.0V Input Range
TTL-Compatible Digital
Inputs/Outputs
The device is available for commercial and
industrial applications and is specified for 0°C to
+70°C applications.
·
·
Small 32-Pin Plastic DIP
APPLICATIONS
1.1 Watt Power
Consumption
Video Digitizer
RADAR
Pulse Measurement
Systems
Infrared Imaging
IF Digitizer
Imaging
·
Dynamic Performance
@ fin = 1MHz
Communications
SNR = 66dB min
THD = 65dB min
SINAD = 62dB
SFDR = 74dB
m ic ro ne tworks
324 Clark Street Worcester MA 01606-1293
Phone: (508) 852-5400 FAX (508) 853-8296
MN5925 12-Bit 20MHz Sampling A/D Converter
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
PART NUMBER
Operating Temperature Range
Specified Temperature Range
Storage Temperature Range
Power Supplies
0°C to +70°C
MN5925
0°C to +70°C
-65°C to +150°C
+/-6 Volts
Standard model is specified for
0°C to +70°C operation.
Digital Inputs
+VCC
Analog Input
VFT, VFB
VFB<VIN>VFT
+3.0V, -3.0V
SPECIFICATIONS Typical at +25°C,
SPECIFICATIONS
ANALOG INPUT
MIN.
TYP.
MAX
UNITS
Input Voltage Range
Input Capacitance
+/-2
5
Volts
pF
Input Resistance
Input Bias Current
100
300
30
k Ohms
uA
60
Input Bandwidth (3dB Small Signal)
120
MHz
DIGITAL INPUTS
Logic Levels:
TTL
TTL
DIGITAL OUTPUTS
Logic Levels
TRANSFER CHARACTERISTICS
+ Full Scale Error
- Full Scale Error
+/-5
+/-5
LSB
LSB
No Missing Codes - Guaranteed
DYNAMIC CHARACTERISTICS
Conversion Rate
20
MHz
Overvoltage Recovery Time
Aperture Delay
20
1
nsec
hsec
Aperture Jitter
5
psec-rms
Output Propagation Delay
Pipeline Delay
14
18
1
hsec
Clock
Cycle
Signal-to-Noise Ratio (SNR)
fIN = 500KHz
64
62
67
64
dB
dB
fIN =3.58MHz
Total Harmonic Distortion (THD)
fIN = 500kHz
63
59
66
61
dB
dB
fIN =3.58MHz
Signal-to-(Noise + Distortion) (SINAD)
fIN = 500kHz
60
57
63
59
dB
dB
fIN =3.58MHz
Spurious Free Dynamic Range (SFDR)
fIN =1MHz
74
dB
POWER SUPPLY REQUIREMENTS
Power Supplies
Power Consumption
+/-5.00
1.1
Volts
Watts
m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
PIN DESIGNATIONS
1. Digital Ground
2. Bit 12 (LSB)
3. Bit 11
4. Bit 10
5. Bit 9
32. +5.0V Supply (Digital)
31. -5.2V Supply
30. Analog Ground
29. +5.0V Supply (Analog)
28. VFB
1
32
6. Bit 8
27. VSB
7. Bit 7
26. VRT1
8. Bit 6
25. VRT2
9. Bit 5
10. Bit 4
24. Analog Input
23. VRT3
11. Bit 3
22. VST
12. Bit 2
21. VFT
13. Bit 1 (MSB)
14. Overrange
15. Digital Ground
16. +5.0V Supply (Digital)
20. +5.0V Supply
19. Analog Ground
18. -5.2V Supply (Analog)
17. Clock Input
16
17
BLOCK DIAGRAM
APPLICATIONS INFORMATION
TYPICAL INTERFACE CIRCUIT - The
criteria to consider for achieving
optimum performance.
MN5925
requires
few
external
components to achieve the stated
operation and performance. The figure
below shows the typical interface
requirements when using the MN5925.
POWER
SUPPLIES
AND
GROUNDING - The MN5925 requires
-5.2V and +5.0V power supplies. The
+5V supply is common to both analog
and digital circuitry. A ferrite bead in
series with each supply line is intended
to reduce the transient noise injected
The
following
section
provides
additional information regarding the pin
functions and critical performance
mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
into the analog VCC. These beads
should be connected as close to the
device as possible. The connection
between the beads and the MN5925
should not be shared with any other
device. Each power supply pin should
be bypassed as close to the device as
possible. Use 0.1uF for the -5.2V and
+5.0V analog supplies. Use 0.01uF for
the +5.0V digital supply. The use of
the mid-point of the reference ladder
(nominally 0.0V) while VSB is the sense
line for the bottom of the reference
resistor ladder (nominally -2.0V when -
2.5V is applied to VFB). VRT1 and VRT3
are quarter point ladder taps nominally
at +1.0V and -1.0V respectively.
The voltages seen at VST and VSB are
the true full scale input voltages of the
device when VFT and VFB are
connected to +2.5V and -2.5V,
respectively. VST and VSB should be
used to monitor the actual full scale
voltage points. VRT1, VRT2 and VRT3
should not be driven to expected ideal
values as is commonly done with
standard flash converter devices. To
minimize high-frequency noise injection
into these points, it is recommended
that each tap be decoupled to analog
ground with a 0.01uF capacitor.
chip
capacitors
is
strongly
recommended.
Analog and digital ground are the two
ground returns available on the
MN5925. These two returns are
isolated on the device. The use of
separate digital and analog ground
planes are recommended. Analog
ground and Digital ground should
connect together only at the MN5925
through a ferrite bead.
The analog input range will scale
proportionally with respect to the
reference voltage if a different input
range is required. The maximum
scaling factor for device operation is +/-
20% of the recommended reference
voltages of VFT and VFB. However,
because the device is laser trimmed to
optimize performance with +/-2.5V
references, the accuracy of the device
will degrade if operated outside of a 2%
range.
A Schottky or hot carrier diode
between Analog Ground and -5.2V
supply is required. The use of separate
power supplies for +5V analog and
+5V digital is not recommended due to
the possibility of power supply
sequencing latch-up conditions.
VOLTAGE REFERENCES - The
MN5925 requires the use of two
voltage references: VFT and VFB
(reference top and reference bottom).
VFT is the force line for the top of the
reference ladder (+2.5V), while VFB is
the force line for the bottom of the
reference ladder (-2.5V). Both voltages
are applied across an internal
reference ladder resistance of 800W.
The +2.5V voltage source must be
limited to 20mA maximum. In addition,
there are five reference ladder taps.
VST is the sense line for the top of the
reference ladder (nominally at 2.0V
when +2.5V is applied to VFT. VRT2 is
An example of a recommended drive
circuit is shown in figure 2. IC1 is the
reference with a tolerance of 0.6% or
+/-0.015V. The potentiometer R1 is
10kW and supports
a
minimum
adjustment range of up to 150mV. IC2
is recommended to be an OP-07 or
equivalent device. R2 and R3 must be
matched to within 0.1% with good TC
tracking to maintain a 0.3LSB matching
between VFT and VFB. If 0.1% matching
is not met, then potentiometer R4 can
mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
be used to adjust the VFB voltage to the
desired level. R1 and R4 should be
adjusted such that VST and VSB are
exactly +2.0V and -2.0V respectively.
output current required for the driving
circuit is only 628uA.
CLOCK INPUT - The MN5925 is
driven from a single-ended TTL clock
input. For optimal noise performance,
the clock input rise time should be a
minimum of 6nsec. Because of this
requirement, the use of fast logic is
recommended. The clock input duty
cycle should be 50% where possible,
but performance will not be degraded if
kept within the range of 40%-60%.
However, in any case, the clock pulse
width high (TpwH) must be 300nsec
maximum to ensure proper operation
of the internal T/H amplifier (please
refer to the timing diagrams). The
analog input signal is latched on the
rising edge of the clock.
The following errors are defined:
+FS Error = top of the ladder offset
voltage = D(+FS-VST)
-FS Error = bottom of ladder offset
voltage = D(-FS-VSB)
Where the +FS (full scale) input
voltage is defined as the output 1LSB
above the transition 1111 1111 1110 to
1111 1111 1111 and the -FS (full
scale) input voltage is defined as the
output 1LSB below the transition of
0000 0000 0001 to 0000 0000
0000.
ANALOG INPUT - The full scale input
The clock input must be driven from
fast TTL logic (VIH<4.5V, rise time
<6nsec). In the event the clock is
driven from a high current source, use
a 100W resistor in series to current limit
to approximately 45mA.
range will be 80% of the reference
DIGITAL OUTPUTS - The format of
the digital output data is straight binary
(see coding table). The outputs are
latched on the rising edge of the clock
with a propagation delay of 14nsec
typical. There is a one clock cycle
latency between clock and output data
(please see timing diagrams).
voltage or +/-2V for VFB = -2.5V and VFT
= +2.5V.
The rise and fall times of digital output
data bits are not symmetrical. The
propagation delay for a logic “0” to a
logic “1” transition is typically 14nsec
while the transition from a logic “1” to a
logic “0” is typically 6nsec. The non-
symmetrical rise and fall times of data
output bits creates approximately
8nsec of invalid data.
The drive requirements for the analog
inputs are minimal when compared to
conventional flash A/D converters due
to the MN5925’s extremely low input
capacitance of only 5pF and high input
impedance of 300kW. For example, for
an input signal of +/-2Vp-p with an
input frequency of 10MHz, the peak
mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
When this condition occurs, the
outputs will switch to all logic “1’s”. All
other data outputs are unaffected by
this operation.
OVERRANGE
OUTPUT
-
The
overrange output bit is an indication
that the analog input has exceeded the
full scale voltage by at least 1LSB.
TIMING DIAGRAMS
DIGITAL OUTPUT CHARACTERISTICS
mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
TIMING PARAMETERS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
18
UNITS
nsec
td
Clock to Data Valid
Clock Pulse Width High
Clock Pulse Width Low
14
tpwH
tpwL
20
20
300
nsec
nsec
SINGLE EVENT TIMING
APPLICATIONS DIAGRAM
PACKAGE OUTLINE
Symbol
Inches
Millimeters
Min
Max
0.099
0.20
Min
Max
2.51
0.51
2.67
A
B
C
D
E
F
G
H
I
0.081
0.016
0.095
2.06
0.41
2.41
0.105
0.050 typ
1.27 typ
0.040
0.175
1.580
0.585
0.009
0.600
1.02
4.45
0.225
1.620
0.605
0.012
0.620
5.72
41.15
15.37
0.30
40.13
14.86
0.23
J
15.24
15.75
mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
相关型号：
MN5930
ADC, Flash Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, PDIP32, PLASTIC, DIP-32
SPECTRUM
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