SS6383ACSTR [SSC]
2A DDR Termination Regulator; 2A DDR终端稳压器型号: | SS6383ACSTR |
厂家: | SILICON STANDARD CORP. |
描述: | 2A DDR Termination Regulator |
文件: | 总7页 (文件大小:751K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SS6383A(G)
2A DDR Termination Regulator
FEATURES
DESCRIPTION
Source and sink current capability of 2A
The SS6383A linear regulator is designed to
provide 2A source and sink current while
regulating an output voltage to within 20mV.
Low output voltage offset, ±20mV
High accuracy output voltage at full-load
VOUT adjustable by external resistors
Low external component count
Current limit protection
The SS6383A converts voltage supplies ranging
from 1.6V to 6V into an output voltage that
is set by two external voltage-divider resistors.
It provides an excellent voltage source for
active termination schemes for high-speed
transmission lines such as those seen in high-
speed memory buses.
Thermal protection
SO-8 and TO-252-5 packages
APPLICATIONS
Mother Boards
The built-in current-limiting in source and sink
mode, together with thermal shutdown, provides
maximum protection to the SS6383A against
fault conditions.
Graphic Cards
DDR Termination Voltage Supply - supports
DDR1 (1.25VTT), DDR2 (0.9VTT), and meets
JEDEC SSTL-2 and SSTL-3 term. specifications
TYPICAL APPLICATION CIRCUIT
1
VIN=2.5V
VIN
5
4
VOUT
VREF
VOUT
+
CIN
470µF
2
3
COUT
220µF
+
R1
100K
GND
VCNTL
R2
100K
C1
100pF
VCNTL=3.3V
+
EN
SSM7002EN
SS6383ACE5
CCNTL
47µF
This device is available with Pb-free lead finish (second-level interconnect) as SS6383AGxx
11/07/2004 Rev.2.01
www.SiliconStandard.com
1 of 7
SS6383A(G)
ORDERING INFORMATION
PIN CONFIGURATION
SS6383AXXX XX
TO-252-5
TOP VIEW
1: VIN
Packing
TR: Tape and reel
2: GND
1 2 3 4 5
3. VCNTL
Package type
4. VREF
CE5: TO-252-5, commercial
GE5: TO-252-5, Pb-free, commercial
CS: SO-8, commercial
5: VOUT
SO-8
GS: SO-8, Pb-free, commercial
TOP VIEW
1
VCNTL
8
VIN
Example:
SS6383AGE5TR
VCNTL
VCNTL
VCNTL
2
3
7
6
5
GND
VREF
VOUT
ꢀ in TO-252-5 package, Pb-free lead finish,
shipped on tape and reel
4
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.4V to 7V
-40°C~85°C
-65°C ~150°C
260°C
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Solder, 10sec)
Thermal Resistance θJC
TO-252
12.5°C /W
40°C /W
SO-8
100°C /W
160°C /W
Thermal Resistance θJA
TO-252
SO-8
(Assumes no ambient airflow, no heatsink)
Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
11/07/2004 Rev.2.01
www.SiliconStandard.com
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SS6383A(G)
TEST CIRCUIT
1
2
3
2.5V
3.3V
VIN
5
4
VOUT
VREF
V
OUT
+
GND
C
OUT
10µF
1.25V
VCNTL
SS6383ACE5
ELECTRICAL CHARACTERISTICS
(VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, COUT=10µF, TA=25°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
SYMBOL
VIN
MIN.
1.6
TYP.
2.5/1.8
3.3
MAX.
UNIT
Keep VCNTL≥VIN during
Input Voltage (DDR1/2)
V
power on and off sequences
VCNTL
VOUT
VOS
3.0
6
Output Voltage
IOUT = 0mA
VREF
V
Output Voltage Offset
IOUT = 0mA
-20
20
20
20
30
10
1
mV
IOUT =0.1mA ~ +2A
IOUT =0.1mA ~ -2A
VREF<0.2V, VOUT = OFF
10
10
8
Load Regulation (DDR1/2)
∆VLOR
mV
Quiescent Current
IQ
µA
mA
µA
A
Operating Current of VCNTL No load
ICNTL
3
VREF Bias Current
Current Limit
VREF=1.25V
0
IIL
2.2
3
4.5
THERMAL PROTECTION
Thermal Shutdown
Temperature
3.3V≤VCNTL≤5V
TSD
125
0.8
150
30
°C
°C
Thermal Shutdown
Hysteresis
Guaranteed by design
SHUTDOWN SPECIFICATIONS
Output ON (VREF=0Vꢀ1.25V)
Output OFF (VREF=1.25Vꢀ0V)
Shutdown Threshold
V
0.2
Note 2: VOS is the voltage measurement, which is defined as the difference between VOUT and VREF.
Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low ON time.
Note 4: Current limit is measured by pulsing a short time.
Note 5: To operate the system safely; VCNTL must be always greater than VIN.
Note 6: Specifications are guaranteed by Statistical Quality Controls (SQC), and not production tested,
within the operating temperature range of -40°C to 85°C.
11/07/2004 Rev.2.01
www.SiliconStandard.com
3 of 7
SS6383A(G)
TYPICAL PERFORMANCE CHARACTERISTICS
0.52
0.48
0.44
0.40
0.36
0.32
0.52
0.48
0.44
0.40
0.36
0.32
V
=3.3V
CNTL
V
=5V
CNTL
V =2.5V
IN
V =2.5V
IN
40
20
0
20
40
60
80
100
120
-20
0
20
40
80
100
120
Temperatur6e0(°C)
Temperature (°C)
Fig. 1 Turn-On Threshold vs. Temp.
Fig. 2 Turn On Threshold vs. Temp.
5
4
3
2
1
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VCNTL=3.3V, VIN=2.5V
VOUT=1.25V
V
V
V
=3.3V
=2.5V
=1.25V
CNTL
IN
REF
No Load
0
-40
-20
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Fig. 4 Current-Limit (Sourcing) vs. Temp.
Fig. 3 Output Voltage Offset vs. Temp.
5
4
3
2
VCNTL=3.3V, VIN=2.5V
VOUT=1.25V
1
0
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Fig. 5 Current Limit (Sinking) vs. Temp.
11/07/2004 Rev.2.01
www.SiliconStandard.com
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SS6383A(G)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
VCNTL=3.3V
VIN=2.5V
VCNTL=3.3V,
VIN=2.5V
VREF=1.25V
V
REF=1.25V
Fig.7 Output Short-Circuit (Sourcing)
Fig. 6
Output Short-Circuit (Sinking)
VCNTL=3.3V
VCNTL=3.3V,
VIN=2.5V
VIN=1.8V
VREF=0.9V
VREF=1.25V
Fig.8 Transient Response at 1.25VTT/2A
Fig. 9 Transient Response at 0.9VTT/2A
BLOCK DIAGRAM
VCNTL
VIN
+
Control
-
VOUT
VREF
Thermal
Current
Limit
Shutdown
VOUT
Shutdown
GND
11/07/2004 Rev.2.01
www.SiliconStandard.com
5 of 7
SS6383A(G)
PIN DESCRIPTIONS (TO-252-5)
PIN 4: VREF - Reference voltage input. Pull
this pin low to shutdown device.
PIN 1: VIN
- Input supply pin. It provides
main power to create the
external reference voltage by
divider resistors for regulating
PIN 5: VOUT - Output pin.
VREF and VOUT
.
PIN 2: GND - Ground pin.
PIN 3: VCNTL - Input supply pin. It is used to
supply all the internal control
circuitry.
APPLICATION INFORMATION
The large copper area shown at VCNTL pins is
able to relieve the thermal dissipation. Using the
via to direct heat into the large copper area shown
on the bottom layer also helps significantly.
All capacitors should be placed as close as
possible to the relevant pins.
Layout Consideration
As the SS6383A is in SO-8 and TO-252-5
packages, it is unable to dissipate heat easily when
it operates at high current. To avoid exceeding
the maximum junction temperature, a suitable
copper area must be used.
Figure 10. Top layer
Figure 11. Bottom layer
Figure 12. Placement
11/07/2004 Rev.2.01
www.SiliconStandard.com
6 of 7
SS6383A(G)
PHYSICAL DIMENSIONS
SO-8
D
SYMBOL
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
A
A1
B
H
E
C
D
E
e
e
1.27(TYP)
A
H
L
5.80
0.40
6.20
1.27
C
B
L
TO-252-5
SYMBOL
MIN
2.19
0
MAX
2.38
0.13
5.46
0.58
5.59
6.73
E
A
A
A1
b3
c2
D
b3
c2
5.21
0.46
5.33
6.35
L3
D
H
E
e
1.27 BSC
H
9.40
1.4
10.41
1.78
L
A
e
A
L1
L2
L3
θ
2.67 REF
0.51 BSC
1.52
2.03
L
A1
0°
8°
L2
L1
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
11/07/2004 Rev.2.01
www.SiliconStandard.com
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