SS8000G [SSC]
GSM Power-Management System; GSM电源管理系统
| 型号： | SS8000G |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | GSM Power-Management System |
| 文件： | 总14页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SS8000G
GSM Power-Management System
FEATURES
DESCRIPTION
Handles all GSM baseband power management
Input range 2.8V to 5.5V
Charger input up to 15V
The SS8000 is a power-management system chip
optimized for GSM handsets. It contains seven LDOs,
one to power each of the critical GSM sub-blocks.
Seven LDOs optimized for specific GSM
subsystems
High operating efficiency and low stand-by
current
Li-Ion and NiMH battery charge function
SIM card interface
Sophisticated controls are available for power-up
during battery charging, keypad interface, and RTC alarm.
The SS8000 is optimized for maximum battery life
featuring a ground current of only 107µA in standby and
187µA when the phone is in operation.
Three open-drain output switches to control
the LED, alerter and vibrator
Thermal overload protection
Under-voltage lock-out protection
Over-voltage protection
The SS8000 battery charger can be used with lithium
ion (Li-Ion) and nickel metal hydride (NiMH) batteries.
The SS8000 contains three open-drain output
switches for LED, alerter and vibrator control. The SIM
interface provides the level shift between SIM card and
microprocessor.
Power-on reset and start-up timer
QFN-48 package
The SS8000 is available in a 48-pin QFN package. The
operating temperature range is from -25°C to +85°C.
APPLICATIONS
GSM/GPRS Mobile Handsets
Basic and High-end Phones
This device is supplied with a Pb-free lead finish (second-level interconnect).
12/06/2004 Rev.2.10
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SS8000G
ORDERING INFORMATION
SS8000GQXX
Packing:
TR: Tape and reel
TY: Tray
Package type
GQ: QFN-48L, Pb-free lead finish
PIN CONFIGURATION
LEDEN
CHRIN
GATEDRV
36
35
34
33
32
1
2
ALERTEREN
VIBRATOREN
PWRBB
NC
3
4
ISENSE
CHRCNTL
CHRDET
PWRKEY
5
31 SRCLKEN
6
7
SS8000
VREF
30
BATSNS
VSIM
NC
29
28
27
8
AGND
VA
SIMIO
9
SIMRST
10
26 AVBAT
25 VTCXO
SIMCLK 11
SIMVCC 12
ABSOLUTE MAXIMUM RATINGS
CHRIN and GATEDRV relative to GND……………………………………………….-0.3V to 15V
All other pins relative to GND………………………………………………….….……-0.3V to 7V
Operating Temperature Ranges…………………………..………….……..………...-25°C to +85°C
Maximum Junction Temperature……………………………………………………….+165°C
Storage Temperature Range……………………………………………………….……-65°C to +165°C
Thermal Impedance, qJA ……………………………………………………………………………………………………….23°C/W
Lead Temperature (soldering, 10sec).……………………………………………......+260°C
12/06/2004 Rev.2.10
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SS8000G
ELECTRICAL CHARACTERISTICS
(Vbat = 3V-5.5V, CVa=10µF, CVcore =CVm=4.7mF, CVrtc=0.22µF, CVref=CVtcxo=CVsim=CVio=1µF, minimum loads applied on all
outputs, unless otherwise noted. Typical values are at TA=+25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Main Controller
Battery Input Voltage Range
Charger Input Voltage Range
Shutdown Supply Current
3
5.5
15
V
V
Vbat<2.5V
5
20
2.5V<Vbat<3.2V
3.2V<Vbat
30
55
µA
µA
45
80
Operation Ground Current
All Output on
187
148
108
3.18
200
2.6
100
165
25
500
200
150
3.2
Vtcxo off, all others on
Va, Vtcxo off, all others on
UVLO on Threshold
Vbat
Vbat
3.15
V
mV
V
UVLO Hysteresis
Deep Discharging Lockout on Threshold
Deep Discharging Lockout Hysteresis
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
LDO Enable Response Time
Power Key Input High Voltage
Power Key Input Low Voltage
PWRBB Input High Voltage
PWRBB Input Low Voltage
Control Input High Voltage
Control Input Low Voltage
Digital Core Voltage LDO (Vcore)
Output Voltage
mV
°C
°C
µs
V
250
PWRKEY
0.7xVbat
PWRKEY
0.3xVbat
0.2
V
PWRBB
1
2
PWRBB
VMSEL,SIMSEL,SIMVCC,SRCLKEN,VASEL,
BATUSE,LEDEN,VIBRATOREN,ALERTEREN
V
V
0.5
1.7
2.7
2.7
1.8
430
1.3
3.3
1.9
V
Output Short Current Limit
Load Regulation
mA
mV
mV
0.05mA < I_load< 200mA
3.2V < Vbat < 5.5V
10
5
Line Regulation
Digital IO Voltage LDO (Vio)
Output Voltage
2.8
275
3
2.9
V
Output Short Current Limit
Load Regulation
mA
mV
mV
0.05mA<I_load<100mA at Vbat=3.6V
3.2V<Vbat<5.5V
10
5
Line Regulation
4.6
Analog Voltage LDO (Va)
Output Voltage
2.8
400
3.3
0.4
50
2.9
V
mA
Output Short Current Limit
Load Regulation
0.05mA<I_load<150mA at Vbat=3.6V
3.2V<Vbat<5.5V
10
5
mV
Line Regulation
mV
Output Noise Voltage
Frequency from 10Hz to 100kHz
Frequency from 10Hz to 3kHz
Frequency from 3kHz to 1MHz
µVrms
Ripple Rejection
65
dB
40
VTCXO Voltage LDO (Vtcxo)
Output Voltage
2.7
2.8
45
2.9
V
mA
Output Short Current Limit
Load Regulation
0.05mA<I_load<20mA at Vbat=3.6V
3.2V<Vbat<5.5V
0.1
0.4
50
2
3
mV
Line Regulation
mV
Output Noise Voltage
Ripple Rejection
Frequency from 10Hz to 100kHz
Frequency from 10Hz to 3kHz
Frequency from 3kHz to 1MHz
µVrms
65
dB
40
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SS8000G
ELECTRICAL CHARACTERISTICS (cont.)
PARAMETER
RTC Voltage LDO (Vrtc)
Output Voltage
CONDITIONS
MIN
TYP
MAX UNITS
1.3
1.5
1.65
1
V
Output Short Current Limit
Off Reverse Input Current
Memory Voltage LDO (Vm)
1.8V Output Voltage
1.35
0.02
mA
µA
1.7
2.7
1.8
2.8
315
2.7
4.4
2.6
2.8
1.9
2.9
V
V
2.8V Output Voltage
Output Short Current Limit
Load Regulation(1.8V)
Load Regulation(2.8V)
Line Regulation(1.8V)
Line Regulation(2.8V)
SIM Voltage LDO (Vsim)
1.8V Output Voltage
mA
0.05mA<I_load<150mA at Vbat=3.6V
3.2V<Vbat<5.5V
10
10
5
mV
mV
5
1.65
2.75
1.8
3.0
38
1
1.95
3.1
V
V
3.0V Output Voltage
Output Short Current Limit
Load Regulation(1.8V)
Load Regulation(3.0V)
Line Regulation(1.8V)
Line Regulation(3.0V)
Reference Voltage Output
Reference Voltage
mA
0.05mA<I_load<20mA at Vbat=3.6V
3.2V<Vbat<5.5V
2
2
3
3
mV
mV
1.7
1.2
1.235
0.3
40
V
mV
Line Regulation
2.7V<Vbat<5.5V without load
Frequency from 10Hz to 100kHz
Frequency at 217Hz
2
Output Noise Voltage
µVrms
dB
Ripple Rejection
65
75
Reset Generator
Reset Output High Voltage
Reset Output Low Voltage
Reset Output Current
Vio-0.5
V
V
0.2
1
2
mA
Reset on Delay Time per unit Cap.
LED/Alerter/Vibrator Driver
Sink Current of LED Driver
Sink Current of Alerter Driver
Sink Current of Vibrator Driver
Battery Charger
ms/nF
Von<0.3V
Von<0.3V
Von<0.5V
150
300
250
mA
mA
mA
Charge Output Voltage (Li-ion Battery)
BATUSE=0
4.2
5.1
3.75
2.5
50
V
V
Charge Output Voltage (NiMH Battery) BATUSE=1
Chr_Det On Threshold
Chr_Det Off Threshold
Pre-charging Current
GSM Interface
(Chrin-Vbat)/Vbat , Chrin>4V
%
(Chrin-Vbat)/Vbat , Chrin>4V
%
I_charge@Vbat=3V(UVLO Active), R1=0.2W
mV
Vih(SIMCLK,SIMRST)
Vil (SIMCLK,SIMRST)
Vilsimio
Vio-0.6
V
V
0.6
0.23
0.335
Vol? 0.4V, Iol=1mA
Vol? 0.4V, Iol=0mA
Iih,Ioh=± 20µA
Vil=0V
V
V
Vihsimio , Vohsimio
Iilsimio
Vio-0.6
16
V
-0.9
0.42
24
mA
V
Volsimio
Vil=0.4V
SIMIO Pull-up Resistance to Vio
20
KW
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SS8000G
ELECTRICAL CHARACTERISTICS (cont.)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Interface to 3V SIM card
Volrst
I=20µA
0.4
0.4
0.4
V
V
Vohrst
I=-200µA
I=20µA
0.9Vsim
0.9Vsim
Vsim-0.4
Volclk
V
Vohclk
I=-200µA
V
Vil
V
Vihsio , Vohsio
I=± 20µA
V
Iil
Vil=0V
-1
mA
V
Vol
Iol=1mA , SIMIO? 0.23V
0.4
Interface to 1.8V SIM card
Volrst
I=20µA
0.2Vsim
0.2Vsim
0.4
V
V
Vohrst
I=-200µA
I=20µA
0.9Vsim
0.9Vsim
Vsim-0.4
Volclk
V
Vohclk
I=-200µA
V
Vil
V
Vihsio , Vohsio
I=± 20µA
V
Iil
Vil=0V
-1
mA
V
Vol
Iol=1mA , SIMIO? 0.23V
0.4
SIM Card Interface Timing
SIO Pull-up Resistance to Vsim
SRST , SIO rise/fall time
SCLK rise/fall time
8
10
30
12
1
KW
µS
nS
Vsim=3/1.8V, load with 30pF
Vsim=3V, CLK load with 30pF
Vsim=1.8V, CLK load with 30pF
CLK load with 30pF
18
50
nS
SCLK frequency
SCLK duty cycle
SCLK Prop. Delay
5
Mhz
%
SIMCLK Duty=50%, fsimclk=5Mhz
47
53
50
nS
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SS8000G
PIN DESCRIPTIONS
PIN
1
NAME
CHRIN
GATEDRV
NC
FUNCTION
Charger Input Voltage
Gate Drive Output
2
3,29
4
ISENSE
CHRCNTL
CHRDET
BATSNS
VSIM
Charger Current Sense Input
5
Microprocessor Control Input Signal for Gate Drive
Charger Detect Output
6
7
Battery Input Voltage Sense
SIM Supply
8
9
SIMIO
Non-Level-Shifted Bidirectional Data I/O
Non-Level-Shifted SIM Reset Input
Non-Level-Shifted SIM Clock Input
SIM Enable
10
11
12
13
14
15
16
17,21,46
18
19
20
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37,40
38
39
41
42
43
44
45
47
48
SIMRST
SIMCLK
SIMVCC
SIMSEL
SIO
High for Vsim=3.0V, Low for Vsim=1.8V
Level-Shifted SIM Bidirectional Data Input/Output
Level-Shifted SIM Reset Output
Level-Shifted SIM Clock Output
Digital Ground
SRST
SCLK
DGND
VM
Memory Supply
VBAT
Battery Input Voltage
VIO
Digital IO Supply
VRTC
Real Time Clock Supply
RSTCAP
/RESET
VTCXO
AVBAT
VA
Reset Delay Time Capacitance
System Reset, Low Active
TCXO Supply
Battery Input Voltage for Analog Block Circuits
Analog Supply
AGND
Analog Ground
VREF
Reference Voltage Output
VTCXO and VA Enable
SRCLKEN
PWRKEY
PWRBB
VIBRATOREN
ALERTEREN
LEDEN
PGND
Power on/off Key
Power on/off Signal from Microprocessor
Vibrator Driver Enable
Alerter Driver Enable
LED Driver Enable
Power Ground
VIBRATOR
ALERTER
LED
Vibrator Driver Input
Alerter Driver Input
LED Driver Input
BATUSE
BATDET
VASEL
VMSEL
VBAT
Battery Type Selection, High for NiMH, Low for Li-ion
Battery Detect Output
High for VA enabled with VTCXO, Low for VA enabled with VD
High for Vm=2.8 V, Low for Vm=1.8V
Battery Input Voltage
VCORE
Digital Core Supply
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SS8000G
APPLICATION INFORMATION
The SS8000 is a power management chip optimized for use with GSM baseband chipsets in handset applications.
Figure 1 shows the block diagram of the SS8000.
Seven low-dropout regulators (core, digital I/O,
analog, crystal oscillator, real-time clock,
memory, SIM)
SIM card interface
Vibrator, alerter, and LED drivers
Power sequence and protection logic
Reset generator
Under-voltage lockout
Deep discharge lockout
Battery charger
DIGITAL CORE LDO
VBAT
48
OUT
VREF
EN
VCORE
DGND
UVLO
DDLO
DIGITAL IO LDO
VBAT
OVER
TEMP
20
18
8
32
33
OUT
VIO
VREF
EN
PWRKEY
PWRBB
DGND
MOMORY LDO
VBAT
VREF
OUT
EN
VM
45
VSEL
VMSEN
DGND
CHARGER
DETECT
SIM LDO
VBAT
VREF
OUT
VSIM
EN
12
SIMVCC
VSEL
DGND
6
CHRDET
BATDET
RTC LDO
VBAT
43
22
26
27
OUT
VREF
EN
VRTC
DGND
31
SRCLKEN
AVBAT
VA
ANALOG LDO
VBAT
1
2
4
CHRIN
GATEDRV
ISENSE
OUT
VREF
EN
AGND
BATTERY
5
7
CHARGER
CHRCNTL
BATSNS
BATUSE
VASEL
TCXO LDO
VBAT
42
44
25
30
OUT
VREF
EN
VTCXO
VREF
AGND
13
SIMSEL
REFERENCE
VBAT
OUT
EN
14
15
16
AGND
SIO
SRST
SCLK
SIM
28
LOGIC
LEVEL
SHIFTER
AGND
DGND
RESET
GENERATOR
17,21,46
Figure 1. Functional Block Diagram
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SS8000G
APPLICATION INFORMATION (cont.)
Low Dropout Regulator ( LDOs ) and Reference
The SS8000 integrates seven LDOs that are optimized
for their given functions by balancing quiescent current,
dropout voltage, line/load regulation, ripple rejection,
and output noise.
SIM LDO (Vsim)
The SIM LDO is a regulator that can source 20mA (max)
with 1.8V or 3.0V output voltage, selected according to
the supply specs of the subscriber identity modules (SIM)
card. It supplies the SIMs in the handset. The LDO is
controlled independently of the others LDO.
Digital Core LDO (Vcore)
The digital core LDO is a regulator that can source
200mA (max) with 1.8V output voltage. It supplies the
baseband circuitry in the handset. The LDO is optimized
for very low quiescent current.
Reference Voltage Output (Vref)
The reference voltage output is a low noise, high PSRR
and high precision reference with a guaranteed accuracy
of 1.5% over temperature. It is used as an internal system
reference within the SS8000. However, to maintain ac-
curate specs on every LDO output voltage, it is important
to avoid loading the reference voltage and it should be
bypassed to GND with 100 nF minimum.
Digital IO LDO (Vio)
The digital I/O LDO is a regulator that can source
100mA (max) with 2.8V output voltage. It supplies the
baseband circuitry in the handset. The LDO is optimized
for very low quiescent current and will power up at the
same time as the digital core LDO.
SIM Card Interface
The SIM card interface circuitry of the SS8000 meets
all ETSI and IMT-2000 SIM interface requirements. It
provides level shifting needs for the low-voltage GSM
controller to communicate with either 1.8V or 3V SIM
cards. All SIM cards contain a clock input, a reset input,
and a bi-directional data input/output. The clock and
reset inputs to SIM cards are level shifted from the sup-
ply of the digital IO (Vio) of the baseband chipset to the
SIM supply (Vsim). The bi-directional data bus is inter-
nally pulled high with a 20kohm resistor on the controller
side and with a 10kohm resistor on the SIM side.
Analog LDO (Va)
The analog LDO is a regulator that can source 150mA
(max) with 2.8V output voltage. It supplies the analog
sections of the baseband chipsets. The LDO is opti-
mized for low frequency ripple rejection in order to reject
the ripple coming from the RF power amplifier burst fre-
quency at 217kHz.
TCXO LDO (Vtcxo)
The TCXO LDO is a regulator that can source 20mA (max)
with 2.8V output voltage. It supplies the temperature com-
pensated crystal oscillator, which needs its own ultra low
noise supply and very good ripple rejection ratio.
All pins that connect to the SIM card (Vsim, SRST,
SCLK, SIO) withstand over 5kV of human-body-mode
ESD. In order to ensure proper ESD protection, careful
board layout is required.
RTC LDO (Vrtc)
The RTC LDO is a regulator that can source 200µA
(max) with 1.5V output voltage. It charges up a capaci-
tor-type backup coin cell to run the real-time clock mod-
ule. The LDO features the reverse current protection
and is optimized for ultra low quiescent current since it is
always on except when the battery voltage is below
2.5V.
Vibrator, Alerter, LED Switches
Three built-in open-drain output switches drive the vi-
brator motor, alerter beeper and LEDs in the handset.
Each switch is controlled by the baseband chipset with
enable pins. The LED switch can sink 150mA to drive up
to 10 LEDs simultaneously for backlight. The vibrator
switch can sink 250mA for a vibrator motor. The alerter
switch can sink 300mA to drive the beeper. All the
open-drain output switches are high impedance when
disabled.
Memory LDO (Vm)
The memory LDO is a regulator that can source 150mA
(max) with 1.8V or 2.8V output voltage, selected ac-
cording to the supply specs of the memory chips. It sup-
plies the memory circuitry in the handset. The LDO is
optimized for very low quiescent current and will power
up at the same time as the digital core LDO.
12/06/2004 Rev.2.10
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SS8000G
APPLICATION INFORMATION (cont.)
Power Sequence and Protection Logic
The SS8000 handles the power-ON and -OFF of the
handset. It is possible to start the power-on sequence in
three different ways:
are turned on when SRCLKEN is high. The microproc-
essor then starts and pulls PWRBB high after which the
PWRKEY can be released. Pulling PWRBB high will
also turn on the handset. This is the case when the
alarm in the RTC expires.
n
n
Pulling PWRKEY low
Pulling PWRBB high
Applying an external supply on CHRIN will also turn the
handset on. If the SS8000 is in the UVLO state, ap-
plying the adapter will not start up the LDOs.
n
CHRIN exceeds Chr_Det threshold
Pulling PWRKEY low is the normal way of turning on the
handset. This will turn on Vcore, Vio, Vm LDOs as long
as the PWRKEY is held low. The Vtcxo and Va LDOs
Table 1 shows states of the handset and the LDOs
Table 1. States of Mobile Handset and LDO
Phone State
No Battery or Vbat < 2.5V
2.5V < Vbat < 3.2V
Pre-Charging
Charger-on
Chr_on -UV
PWRBB (–PWRKEY) SRCLKEN Vrtc
Vd,Vio,Vm Va, Vtcxo
X
L
L
L
X
X
X
X
L
X
X
X
X
X
L
Off
On
On
On
On
On
On
Off
Off
Off
On
Off
Off
On
Off
Off
Off
On
Off
On
On
H
H
L
L
H
H
H
H
Switched off
Stand-by
L
H
H
Active
L
H
Undervoltage Lockout (UVLO)
RSTCAP:
tRESET = 2
The UVLO function in the SS8000 prevents startup
when initial voltage of the main battery is below the 3.2V
threshold. When the battery voltage is greater than 3.2V,
the UVLO comparator trips and the threshold is reduced
to 3.0V. This allows the handset to start normally until
the battery decays to below 3.0V.
ms
nF
´ CRSTCAP
(1)
At power-off, RESET will be kept low.
Over-temperature Protection
If the die temperature of the SS8000 exceeds 165°C,
the SS8000 will disable all the LDOs except the RTC
LDO. Once the over-temperature state is resolved, a
new power-on sequence is required to enable the LDOs.
Once the SS8000 enters a UVLO state, it draws very
low quiescent current, typically 30µA. The RTC LDO is
still running until the DDLO disables it. In this mode the
SS8000 draws 5µA of quiescent current.
Battery Charger
Deep Discharge Lockout (DDLO)
The SS8000 battery charger can be used with Li-ion
and NiMH batteries. The BATUSE pin can set SS8000
to fit the battery type. BATUSE is set low when a Li-ion
battery is used, and set high when a NiMH battery is
used. The SS8000 charges the battery in three phases:
pre-charging, constant current mode charging, and con-
stant voltage mode charging. Figure 2 shows the flow
chart of charger behavior. The circuitry of the SS8000
combines a PMOS transistor, diode, current-sense re-
sistor externally to form a simple and low cost linear
charger shown in Figure 3. The SS8000 provides a
pulsed top-off charging algorithm through the CHRCNTL
pin from the baseband chipset.
The DDLO in the SS8000 has two functions:
l To turn off the Vrtc LDO.
l To shut down the handset when the software fails to
turn off the phone when the battery drops below 3.0V.
The DDLO will shut down the handset when the bat-
tery falls below 2.5 V to prevent further discharge and
damage to the cells.
Reset
The SS8000 contains a reset circuit that is active at
both power-up and power-down. The RESET pin is held
low at initial power-up, and the reset delay timer is
started. The delay is set by an external capacitor on
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SS8000G
APPLICATION INFORMATION (cont.)
NO-CHARGING
CHARGER
DETECTOR
NO
CHRIN > BATSNS
YES
YES
VBAT > UVLO
NO
NiMH
BATTERY
TYPE
PRE-CHARGING
Li+
BATUSE=LOW
BATUSE=HIGH
CONSTANT
CURRENT MODE
PULSE CHARGE
MODE
NO
NO
VBAT > 4.2V
YES
VBAT > 5.1V
YES
CONSTANT
VOLTAGE MODE
CHARGER OFF
GATEDRV=HIGH
NO
NO
VBAT < 4.3V
YES
VBAT < 5.1V
YES
CHARGER
OFF
NO
VBAT < 4.3V
YES
Figure 2. Batter Charger Flow Chart
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SS8000G
APPLICATION INFORMATION (cont.)
Battery Used
LED SW
Battery Detect
Va Selection
Vm Selection
Vcore
Alerter SW
Vibrator SW
C17
4.7µF
R4
PGND
100K
DGND
1
36
35
34
33
32
LEDEN
Charger In
LED SW Enable
CHRIN
GATEDRV
NC
2
ALERTEREN
VIBRATOREN
Q1
Alerter SW Enable
1µF
DGND
3
4
Power On
CLK ON
PWRBB
PWRKEY
SRCLKEN
ISENSE
CHRCNTL
D1
5
6
31
Charge Control
Charger Detect
CHRDET
7
8
30
29
28
BATSNS
VSIM
VREF
NC
SWI
SW-PB
C16
1µF
R1
0.2W
9
SIMIO
AGND
10
27
26
25
SIMRST
SIMCLK
SIMVCC
VA
AVBAT
VTCXO
LI or NiMH
BATTERY
11
12
DGND
C15
10µF
AGND
Vsim
DGND PGND
C2
1µF
C13
1µF
SIM Pin of
GSM Processor
10µF
AGND
DGND
Vsim Enable
Vsim Slectioin
AGND
C12
C4
I/O To SIM Card
RST To SIM Card
CLK To SIM Card
0.1µF
1µF
C3
C11
0.22µF
4.7µF
DGND
Figure 3. Typical Application Circuit
12/06/2004 Rev.2.10
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11 of 14
SS8000G
APPLICATION INFORMATION (cont.)
Charge Detection
If the battery voltage is below 4.2V when charging a
Li-ion battery (5.1V for a NiMH battery), the constant
current charging mode is used.
The SS8000 charger block has a detection circuit that
determines via the CHRIN pin if an adapter has been
connected. If the adapter voltage exceeds the battery
voltage by 3.75%, the CHRDET output will go high. If
the adapter is then removed and the voltage at the
CHRIN pin drops to only 2.5% above the VBAT pin,
CHRDET goes low.
Constant Voltage Charging Mode
This mode only applies to Li-ion battery charging. If the
battery has reached the final charge voltage, a constant
voltage is applied to the battery and keeps it at 4.2V.
This termination of charging is determined by the base-
band chip internally, which will pull the CHRCNTL low to
stop the charger.
Pre-Charging mode
When the battery voltage is below the UVLO threshold,
the charge current is in the pre-charging mode. There
are two steps in this mode. While the battery voltage is
deeply discharged below 2V, a 10mA trickle current from
the SS8000 charges the battery. When the battery
voltage exceeds 2V, the pre-charge current is enabled,
which allows 10mV (typically) across the external cur-
rent sense resistor. This pre-charge current can be cal-
culated:
Once the battery voltage exceeds 4.3V for a Li-ion bat-
tery (5.1V for a NiMH battery), a hardware over-voltage
protection (OV) should be activated to turn off the
charger block of the SS8000.
Pulsed Charging Algorithm
The SS8000 provide a pulsed top-off charging algo-
rithm via the CHRCNTL pin. The control signal from the
baseband chipset limits the charging duty cycle. This
charging algorithm combines the efficiency of
switch-mode chargers with the simplicity and low cost of
linear chargers.
VSENSE 10mV
IPRE _ CHARGING
=
=
(2)
R1
R1
Constant Current Charging Mode
Once the battery voltage has exceeded the UVLO
threshold, the charger will switch to the constant current
charging mode. The SS8000 allows 160mV (typically)
across the external current sense resistor. This constant
current can be calculated.
Battery Voltage Monitor
As Table 2 shows, the relationship between battery
voltage and charger control with the corresponding sig-
nals is listed. When Vbat <3.2V, an UVB signal is active
low. When Vbat >/= 4.3V, an OV signal is active and
charging is halted.
VSENSE 160mV
ICONSTANT
=
=
(3)
R1
R1
Table 2. Charger and Voltage Detection
Chr_Det
Output
Charger
Condition
Vbat
Charger_on
Chr_cntl
-UV
Batuse
Any Vbat
L
X
H
H
H
H
X
L
L
X
H
H
H
H
X
X
L
X
X
X
L
No-Charging
No-Charging
Pre-Charging
CC mode
Vbat > 3.2V
Vbat < UV
X
H
H
H
3.2V<Vbat<4.2V
Vbat = 4.2V
3.2V<Vbat
H
H
H
L
CV mode
H
CC mode
Notes: OV terminates charging at 4.3V for Li-ion battery or 5.1V for NiMH battery.
12/06/2004 Rev.2.10
www.SiliconStandard.com
12 of 14
SS8000G
APPLICATION INFORMATION (cont.)
External Components Selection
Charger FET Selection
Input Capacitor Selection
In selecting the P-channel MOSFET for the charger,
consider the minimum drain-source breakdown voltage
(BVDS), the minimum turn-on threshold voltage (VGS),
and current-handling and power-dissipation capabilities.
For each of the input pins (VBAT) of the SS8000, a
10µF, low ESR capacitor is recommended for local by-
pass. MLCC capacitors provide the best combination of
low ESR and small size. Using a 10µF tantalum capaci-
tor with a small (1µF or 2.2µF) ceramic in parallel is an
alternative low cost solution.
Charger Diode Selection
The diode shown in Figure 3 is used to prevent the bat-
tery from discharging through the P-channel MOSFETs
body-diode into the charger’s internal circuits. Choose a
diode with a current rating high enough to handle the
battery charging current and a voltage rating greater
than Vbat.
For the charger input pin (CHRIN), a 1µF ceramic ca-
pacitor is recommended for bypass.
LDO Capacitor Selection
The digital core, analog, and memory LDOs require a
4.7µF capacitor, the digital IO and SIM TCXO LDOs
require a 1µF capacitor and the RTC LDO requires a
0.22µF capacitor. Larger value capacitors may be used
for improved noise or PSRR performance, but do not
forget to consider the settling time that is acceptable for
the application. For these, MLCC is recommended.
Layout Guidelines
Use the following general guidelines when designing the
printed circuit boards:
1. Split the battery connection to the VBAT, AVBAT pins
of the SS8000. Locate the input capacitor as close
to the pins as possible.
2. Va and Vtcxo capacitors should be returned to AGND.
3. Split the ground connection. Use separate traces or
planes for the analog, digital, and power grounds (i.e.
AGND, DGND, PGND pins of the SS8000, respec-
tively) and tie them together at a single point, prefera-
bly close to the battery return.
RESET Capacitor Selection
RESET is held low during power-up for a delay until the
LDOs are up. The delay is set by an external capacitor
on the RESCAP pin. It can be determined by Eq.(1). A
100nF capacitor will produce a 200ms delay.
4. Run a separate trace from the BATSNS pin to the
battery to prevent any voltage drop error in the meas-
urement.
5. Kelvin-connect the charge-current sense-resistor by
running separate traces to the BATSNS and ISENSE
pins. Make sure that the traces are terminated as
close to the resistor’s body as possible.
Setting the Charge Current
The SS8000 is capable of charging the battery with a
charging current programmed by an external sense re-
sistor, Rsen. It is calculated using Eq.(3). If the charge
current is defined, Rsen can be found.
Appropriate sense resistors are available from the fol-
lowing vendors: Vishay Dale, IRC, Panasonic.
6. Careful use of copper area, weight, and multi-layer
construction will help to improve thermal performance.
12/06/2004 Rev.2.10
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13 of 14
SS8000G
PHYSICAL DIMENSIONS
C
C
0.1
0.08
C
B
A
D
M
PIN 1 CORNER
E
M
A2
A1
C
0.1
A
J
0.1
C
A B
PIN 1 CORNER
48
37
Taping Specification
36
1
P
K
e
0.1
C A B
e/2
Feed Direction
Typical QFN Package Orientation
12
25
EXPOSED DIE
ATTACH PAD
24
13
48X L
M
0.1
C
A B
48X b
VIEW M-M
Note:
Coplanarity applies to leads, corner leads and die attach pad.
DIMENSION IN MM
DIMENSION IN INCH
SYMBOL
MIN.
0.80
0
0.75
0.20
NOM.
-----
-----
-----
0.25
MAX.
1.00
0.05
1.00
0.30
MIN.
0.031
0
0.030
0.008
NOM.
-----
-----
-----
0.010
MAX.
0.039
0.002
0.039
0.012
A
A1
A2
b
D
E
e
J
K
7 BSC
7 BSC
0.5 BSC
4.60
4.60
0.40
0.276 BSC
0.276 BSC
0.020 BSC
0.181
4.50
4.50
0.35
4.70
4.70
0.45
0.177
0.177
0.014
0.185
0.185
0.018
0.181
0.016
L
P
45° REF
45° REF
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
12/06/2004 Rev.2.10
www.SiliconStandard.com
14 of 14
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