SSM4880AGM [SSC]

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET; N沟道增强模式功率MOSFET


型号：	SSM4880AGM
厂家：	SILICON STANDARD CORP.
描述：	N-CHANNEL ENHANCEMENT-MODE POWER MOSFET N沟道增强模式功率MOSFET
文件：	总5页 (文件大小：227K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SSM4880AGM

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET

Low on-resistance

BV_DSS

R_DS(ON)

I_D

30V

Fast switching, planar construction

Simple drive requirement

9mΩ

13A

SO-8

Description

Power MOSFETs from Silicon Standard provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and cost-effectiveness.

The SO-8 package is widely preferred for commercial and

industrial surface mount applications and the SSM4880AGM is well suited for

for low-voltage applications such as DC/DC converters.

Pb-free lead finish (second-level interconnect)

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

V_DS

V_GS

Drain-Source Voltage

Gate-Source Voltage

±20

I_D@ T_A=25°C

I_D@ T_A=70°C

I_DM

Continuous Drain Current³

Pulsed Drain Current¹

P_D@ T_A=25°C

Total Power Dissipation

2.5

Linear Derating Factor

Single Pulse Avalanche Energy⁴

0.02

266

W/°C

E_AS

I_AR

Avalanche Current

7.3

T_STG

T_J

Storage Temperature Range

Operating Junction Temperature Range

-55 to 150

°C

Thermal Data

Symbol

Parameter

Value

Unit

Rthj-a

Thermal Resistance Junction-ambient³

Max.

°C/W

3/08/2005 Rev.2.2

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SSM4880AGM

Electrical Characteristics @ T_j=25^oC (unless otherwise specified)

Symbol

BV_DSS

Parameter

Test Conditions

V_GS=0V, I_D=250uA

Min. Typ. Max. Units

Drain-Source Breakdown Voltage

0.037

∆BV_DSS/∆Tj

Breakdown Voltage Temperature Coefficient Reference to 25°C, I_D=1mA

Static Drain-Source On-Resistance V_GS=10V, I_D=13A

V_GS=4.5V, I_D=10A

V/°C

mΩ

R_DS(ON)

mΩ

V_GS(th)

g_fs

Gate Threshold Voltage

V_DS=V_GS, I_D=250uA

V_DS=15V, I_D=10A

V_DS=30V, V_GS=0V

V_DS=24V, V_GS=0V

Forward Transconductance

Drain-Source Leakage Current (Tj=25°C)

Drain-Source Leakage Current (T_j=55°C)

I_DSS

I_GSS

Q_g

Gate-Source Leakage

Total Gate Charge²

Gate-Source Charge

Gate-Drain ("Miller") Charge

Turn-on Delay Time²

Rise Time

V =

± 20V

±100

I_D=13A

22.5

3.3

15.4

Q_gs

Q_gd

t_d(on)

t_r

V_DS=15V

V_GS=5V

V_DS=15V

I_D=1A

813

516

224

t_d(off)

t_f

Turn-off Delay Time

Fall Time

R_G=6.2Ω ,VGS=10V

R_D=15Ω

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

V_GS=0V

V_DS=25V

f=1.0MHz

Source-Drain Diode

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

I_S

Continuous Source Current ( Body Diode )

Pulsed Source Current ( Body Diode )¹

Forward On Voltage²

V_D=V_G=0V , V_S=1.3V

2.3

I_SM

V_SD

T_j=25°C, I_S=2.3A, V_GS=0V

1.3

Notes:

1.Pulse width limited by safe operating area.

2.Pulse width <300us , duty cycle <2%.

3.Surface mounted on 1 in²copper pad of FR4 board ; 125°C/W when mounted on min. copper pad.

4.Starting T_j=25^oC , V_DD=25V , L=10mH , R_G=25Ω

3/08/2005 Rev.2.2

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SSM4880AGM

10V

8.0V

6.0V

5.0V

10V

8.0V

6.0V

5.0V

T _A=150 ^oC

T _A=25 ^oC

V _G= 4 .0 V

V _DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1.8

1.6

1.4

1.2

I _D=10A

I _D=13A

V _G=10V

_A=25°C

0.8

0.6

-50

100

150

T _j, Junction Temperature ( ^oC)

V _GS, Gate-to-Source Voltage (V)

Fig 3. On-Resistance vs. Gate Voltage

Fig 4. Normalized On-Resistance

vs. Junction Temperature

100

T _j=150 ^oC

T _j=25 ^oC

0.1

0.3

0.5

0.7

0.9

1.1

1.3

-50

100

150

V _SD, Source-to-Drain Voltage (V)

T _j, Junction Temperature( ^oC)

Fig 5. Forward Characteristic of

Reverse Diode

Fig 6. Gate Threshold Voltage vs.

Junction Temperature

3/08/2005 Rev.2.2

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SSM4880AGM

f=1.0MHz

10000

1000

100

I _D=13A

_DS=15V

C _iss

C _oss

C _rss

Q _G, Total Gate Charge (nC)

V _DS, Drain-to-Source Voltage (V)

Fig 7. Gate Charge Characteristics

Fig 8. Typical Capacitance Characteristics

100

Duty factor = 0.5

0.2

0.1

1ms

0.1

0.05

0.02

10ms

100ms

0.01

P_DM

0.01

Single Pulse

10s

0.1

T _A=25 ^oC

Duty Factor = t/T

Single Pulse

Peak T_j= P_DMx R_thja+ T_a

R_thja=125^oC/W

0.01

0.001

0.1

100

0.0001

0.001

0.01

0.1

100

1000

V _DS, Drain-to-Source Voltage (V)

t , Pulse Width (s)

Fig 9. Maximum Safe Operating Area

Fig 10. Effective Transient Thermal Impedance

V_G

V_DS

90%

Q_G

Q_GS

Q_GD

10%

V_GS

t_r

Charge

t_d(on)

_d(off)t_f

Fig 11. Switching Time Waveform

Fig 12. Gate Charge Waveform

3/08/2005 Rev.2.2

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SSM4880AGM

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no

guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no

responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its

use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including

without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to

the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of

Silicon Standard Corporation or any third parties.

3/08/2005 Rev.2.2

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