SST29EE010-70-4C-NH 概述
1 Mbit (128K x8) Page-Mode EEPROM 1兆位( 128K ×8 )页面模式的EEPROM
SST29EE010-70-4C-NH 数据手册
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PDF下载1 Mbit (128K x8) Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
SST29EE010 / SST29LE010 / SST29VE0101Mb Page-Mode flash memories
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
•
Latched Address and Data
– 5.0V-only for SST29EE010
– 3.0-3.6V for SST29LE010
– 2.7-3.6V for SST29VE010
Automatic Write Timing
– Internal VPP Generation
End of Write Detection
•
•
•
Superior Reliability
– Toggle Bit
– Data# Polling
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Hardware and Software Data Protection
Low Power Consumption
Product Identification can be accessed via
Software Operation
– Active Current: 20 mA (typical) for 5V and 10 mA
(typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
•
•
TTL I/O Compatibility
JEDEC Standard
•
•
Fast Page-Write Operation
– Flash EEPROM Pinouts and command sets
Packages Available
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs (typical)
•
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm, 8mm x 20mm)
– 32-pin PDIP
Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
PRODUCT DESCRIPTION
The SST29EE/LE/VE010 are 128K x8 CMOS Page-Write
EEPROMs manufactured with SST’s proprietary, high per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST29EE/LE/VE010 write with a single
power supply. Internal Erase/Program is transparent to the
user. The SST29EE/LE/VE010 conform to JEDEC stan-
dard pinouts for byte-wide memories.
The SST29EE/LE/VE010 are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
the SST29EE/LE/VE010 significantly improve performance
and reliability, while lowering power consumption. The
SST29EE/LE/VE010 improve flexibility while lowering the
cost for program, data, and configuration storage applica-
tions.
To meet high density, surface mount requirements, the
SST29EE/LE/VE010 are offered in 32-lead PLCC and 32-
lead TSOP packages. A 600-mil, 32-pin PDIP package is
also available. See Figures 1, 2, and 3 for pinouts.
Featuring high performance Page-Write, the SST29EE/LE/
VE010 provide a typical Byte-Write time of 39 µsec. The
entire memory, i.e., 128 KBytes, can be written page-by-
page in as little as 5 seconds, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of a Write cycle. To protect against inadvertent write,
the SST29EE/LE/VE010 have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, the
SST29EE/LE/VE010 are offered with a guaranteed Page-
Write endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electrical
write capability. The SST29EE/LE/VE010 does not require
separate Erase and Program operations. The internally
timed write cycle executes both erase and program trans-
parently to the user. The SST29EE/LE/VE010 have indus-
try standard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE/LE/
VE010 are compatible with industry standard EEPROM
pinouts and functionality.
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SSF is a trademark of Silicon Storage Technology, Inc.
S71061-07-000 6/01
1
304
These specifications are subject to change without notice.
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
consists of a specific three-byte load sequence that allows
writing to the selected page and will leave the SST29EE/
LE/VE010 protected at the end of the Page-Write. The
page load cycle consists of loading 1 to 128 bytes of data
into the page buffer. The internal write cycle consists of the
TBLCO time-out and the write timer operation. During the
Write operation, the only valid reads are Data# Polling and
Toggle Bit.
Read
The Read operations of the SST29EE/LE/VE010 are con-
trolled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the read cycle timing diagram for further details
(Figure 4).
The Page-Write operation allows the loading of up to 128
bytes of data into the page buffer of the SST29EE/LE/
VE010 before the initiation of the internal write cycle. Dur-
ing the internal write cycle, all the data in the page buffer is
written simultaneously into the memory array. Hence, the
Page-Write feature of SST29EE/LE/VE010 allow the entire
memory to be written in as little as 5 seconds. During the
internal write cycle, the host is free to perform additional
tasks, such as to fetch data from other locations in the sys-
tem to set up the write to the next page. In each Page-Write
operation, all the bytes that are loaded into the page buffer
must have the same page address, i.e. A7 through A16. Any
byte not loaded with user data will be written to FFH.
Write
The Page-Write to the SST29EE/LE/VE010 should always
use the JEDEC Standard Software Data Protection (SDP)
three-byte command sequence. The SST29EE/LE/VE010
contain the optional JEDEC approved Software Data Pro-
tection scheme. SST recommends that SDP always be
enabled, thus, the description of the Write operations will
be given using the SDP enabled format. The three-byte
SDP Enable and SDP Write commands are identical;
therefore, any time a SDP Write command is issued, Soft-
ware Data Protection is automatically assured. The first
time the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the same
command bypasses the data protection for the page being
written. At the end of the desired Page-Write, the entire
device remains protected. For additional descriptions,
please see the application notes, The Proper Use of
JEDEC Standard Software Data Protection and Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories.
See Figures 5 and 6 for the Page-Write cycle timing dia-
grams. If after the completion of the three-byte SDP load
sequence or the initial byte-load cycle, the host loads a sec-
ond byte into the page buffer within a byte-load cycle time
(TBLC) of 100 µs, the SST29EE/LE/VE010 will stay in the
page load cycle. Additional bytes are then loaded consecu-
tively. The page load cycle will be terminated if no addi-
tional byte is loaded into the page buffer within 200 µs
(TBLCO) from the last byte-load cycle, i.e., no subsequent
WE# or CE# high-to-low transition after the last rising edge
of WE# or CE#. Data in the page buffer can be changed by
a subsequent byte-load cycle. The page load period can
continue indefinitely, as long as the host continues to load
the device within the byte-load cycle time of 100 µs. The
page to be loaded is determined by the page address of
the last byte loaded.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE/LE/VE010. Steps 1 and 2 use the same timing
for both operations. Step 3 is an internally controlled write
cycle for writing the data loaded in the page buffer into the
memory array for nonvolatile storage. During both the SDP
three-byte load sequence and the byte-load cycle, the
addresses are latched by the falling edge of either CE# or
WE#, whichever occurs last. The data is latched by the ris-
ing edge of either CE# or WE#, whichever occurs first. The
internal write cycle is initiated by the TBLCO timer after the
rising edge of WE# or CE#, whichever occurs first. The
Write cycle, once initiated, will continue to completion, typi-
cally within 5 ms. See Figures 5 and 6 for WE# and CE#
controlled Page-Write cycle timing diagrams and Figures
15 and 17 for flowcharts.
Software Chip-Erase
The SST29EE/LE/VE010 provide a Chip-Erase operation,
which allows the user to simultaneously clear the entire
memory array to the “1” state. This is useful when the entire
device must be quickly erased.
The Software Chip-Erase operation is initiated by using a
specific six-byte load sequence. After the load sequence,
the device enters into an internally timed cycle similar to the
Write cycle. During the Erase operation, the only valid read
is Toggle Bit. See Table 4 for the load sequence, Figure 10
for timing diagram, and Figure 19 for the flowchart.
The Write operation has three functional cycles: the Soft-
ware Data Protection load sequence, the page load cycle,
and the internal write cycle. The Software Data Protection
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
2
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Write Operation Status Detection
The SST29EE/LE/VE010 provide two software means to
detect the completion of a Write cycle, in order to optimize
the system write cycle time. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle Bit
(DQ6). The end of write detection mode is enabled after the
rising WE# or CE# whichever occurs first, which initiates
the internal write cycle.
Software Data Protection (SDP)
The SST29EE/LE/VE010 provide the JEDEC approved
optional Software Data Protection scheme for all data alter-
ation operations, i.e., Write and Chip-Erase. With this
scheme, any Write operation requires the inclusion of a
series of three byte-load operations to precede the data
loading operation. The three byte-load sequence is used to
initiate the Write cycle, providing optimal protection from
inadvertent write operations, e.g., during the system power-
up or power-down. The SST29EE/LE/VE010 are shipped
with the Software Data Protection disabled.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
The software protection scheme can be enabled by apply-
ing a three-byte sequence to the device, during a page-
load cycle (Figures 5 and 6). The device will then be auto-
matically set into the data protect mode. Any subsequent
Write operation will require the preceding three-byte
sequence. See Table 4 for the specific software command
codes and Figures 5 and 6 for the timing diagrams. To set
the device into the unprotected mode, a six-byte sequence
is required. See Table 4 for the specific codes and Figure 9
for the timing diagram. If a write is attempted while SDP is
enabled the device will be in a non-accessible state for
~300 µs. SST recommends Software Data Protection
always be enabled. See Figure 17 for flowcharts.
Data# Polling (DQ7)
When the SST29EE/LE/VE010 are in the internal write
cycle, any attempt to read DQ7 of the last byte loaded dur-
ing the byte-load cycle will receive the complement of the
true data. Once the Write cycle is completed, DQ7 will
show true data. The device is then ready for the next opera-
tion. See Figure 7 for Data# Polling timing diagram and Fig-
ure 16 for a flowchart.
The SST29EE/LE/VE010 Software Data Protection is a
global command, protecting (or unprotecting) all pages in
the entire memory array once enabled (or disabled). There-
fore using SDP for a single Page-Write will enable SDP for
the entire array. Single pages by themselves cannot be
SDP enabled or disabled.
Toggle Bit (DQ6)
During the internal write cycle, any consecutive attempts to
read DQ6 will produce alternating 0s and 1s, i.e. toggling
between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 8 for Toggle Bit timing diagram and
Figure 16 for a flowchart. The initial read of the Toggle Bit
will typically be a “1”.
Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE/LE/VE010 should be programmed
using the SDP command sequence. SST recommends the
SDP Disable Command Sequence not be issued to the
device prior to writing.
Data Protection
The SST29EE/LE/VE010 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Please refer to the following Application Notes for more
information on using SDP:
•
•
Protecting Against Unintentional Writes When
Using Single Power Supply Flash Memories
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
The Proper Use of JEDEC Standard Software
Data Protection
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
3
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Product Identification
Product Identification Mode Exit
The product identification mode identifies the device as the
SST29EE/LE/VE010 and manufacturer as SST. This mode
is accessed via software. For details, see Table 4, Figure
11 for the software ID entry and read timing diagram and
Figure 18, for the ID entry command sequence flowchart.
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Software ID Exit (reset) opera-
tion, which returns the device to the Read operation. The
Reset operation may also be used to reset the device to the
Read mode after an inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. See Table 4 for software command
codes, Figure 12 for timing waveform, and Figure 18 for a
flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST29EE010
SST29LE010
SST29VE010
0001H
0001H
0001H
07H
08H
08H
T1.3 304
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
A
- A
0
16
Address Buffer & Latches
Control Logic
Y-Decoder and Page Latches
I/O Buffers and Data Latches
CE#
OE#
WE#
DQ - DQ
7
0
304 ILL B1.1
4
3
2
1
32 31 30
29
5
A7
A6
A14
A13
A8
6
28
27
26
25
24
23
22
21
7
A5
8
A4
A9
32-lead PLCC
Top View
9
A3
A11
OE#
A10
CE#
DQ7
10
11
12
13
A2
A1
A0
DQ0
14 15 16 17 18 19 20
304 ILL F02.3
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
4
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
2
A8
3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
NC
4
5
Standard Pinout
Top View
6
WE#
7
V
8
DD
NC
A16
A15
A12
A7
9
V
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
A6
A1
A5
A2
A4
A3
304 ILL F01.2
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
NC
A16
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
WE#
NC
2
3
4
A14
A13
A8
5
32-pin
PDIP
A6
6
A5
7
A9
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
A3
9
A2
10
11
12
13
14
15
16
A1
A0
DQ0
DQ1
DQ2
V
SS
304 ILL F19.0
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
A16-A7
A6-A0
Pin Name
Functions
Row Address Inputs
Column Address Inputs
To provide memory addresses. Row addresses define a page for a Write cycle.
Column Addresses are toggled to load page data
DQ7-DQ0 Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide: 5.0V supply (±10%) for SST29EE010
3.0V supply (3.0-3.6V) for SST29LE010
2.7V supply (2.7-3.6V) for SST29VE010
VSS
NC
Ground
No Connection
Unconnected pins.
T2.1 304
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
5
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
CE# OE# WE# DQ
Address
Read
VIL
VIL
VIH
X
VIL
VIH
X1
VIH
VIL
X
DOUT
DIN
AIN
AIN
X
Page-Write
Standby
Write Inhibit
High Z
VIL
X
X
High Z/ DOUT
High Z/ DOUT
DIN
X
X
VIH
VIL
X
Software Chip-Erase
Product Identification
Software Mode
VIL
VIH
AIN, See Table 4
VIL
VIH
VIL
Manufacturer’s ID (BFH)
Device ID2
See Table 4
SDP Enable Mode
SDP Disable Mode
VIL
VIL
VIH
VIH
VIL
VIL
See Table 4
See Table 4
T3.3 304
1. X can be VIL or VIH, but no other value.
2. Device ID = 07H for SST29EE010 and 08H for SST29LE/VE010
TABLE 4: SOFTWARE COMMAND SEQUENCE
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Command
Sequence
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
5555H AAH 2AAAH 55H 5555H A0H
Addr2 Data
Software
Data Protect Enable
& Page-Write
Software
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H
Data Protect Disable
Software Chip-Erase3 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry4,5
5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit
5555H AAH 2AAAH 55H 5555H F0H
Alternate
Software ID Entry6
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H
T4.3 304
1. Address format A14-A0 (Hex), Addresses A15 and A16 can be VIL or VIH, but no other value.”
2. Page-Write consists of loading up to 128 Bytes (A6-A0)
3. The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST if you require this function for an industrial temperature part.
4. The device does not remain in Software Product ID Mode if powered down.
5. With A14-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,
SST29EE010 Device ID = 07H, is read with A0 = 1
SST29LE/VE010 Device ID = 08H, is read with A0 = 1
6. Alternate six-byte Software Product ID Command Code
Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code
sequence. For new designs, SST recommends that the three-byte command code sequence be used.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
6
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD + 1.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST29EE010
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
5.0V±10%
5.0V±10%
-40°C to +85°C
OPERATING RANGE FOR SST29LE010
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
3.0-3.6V
3.0-3.6V
-40°C to +85°C
OPERATING RANGE FOR SST29VE010
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
See Figures 13 and 14
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
7
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10% FOR SST29EE010
Limits
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
Symbol Parameter
Min
IDD
Power Supply Current
VDD=VDD Max
Read
Write
30
50
3
mA
mA
mA
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max
CE#=OE#=WE#=VIH, VDD=VDD Max
ISB1
ISB2
Standby VDD Current
(TTL input)
Standby VDD Current
(CMOS input)
50
µA
CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN =GND to VDD, VDD=VDD Max
VOUT =GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
VIH
VOL
VOH
10
0.8
Input High Voltage
2.0
2.4
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
0.4
V
IOL=2.1 mA, VDD=VDD Min
IOH=-400 µA, VDD=VDD Min
V
T5.3 304
TABLE 6: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST29LE010 AND 2.7-3.0V FOR SST29VE010
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
IDD
Power Supply Current
VDD=VDD Max
Read
Write
12
15
1
mA
mA
mA
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max
CE#=OE#=WE#=VIH, VDD=VDD Max
ISB1
ISB2
Standby VDD Current
(TTL input)
Standby VDD Current
(CMOS input)
15
µA
CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
VIH
VOL
VOH
10
0.8
Input High Voltage
2.0
2.4
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
T6.3 304
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
8
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
5
1
TPU-WRITE
ms
T7.1 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T8.0 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100
T9.5 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
9
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
AC CHARACTERISTICS
TABLE 10: READ CYCLE TIMING PARAMETERS FOR SST29EE010
SST29EE010-70
SST29EE010-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TCE
Chip Enable Access Time
Address Access Time
70
70
30
90
90
40
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
30
30
ns
1
TOHZ
ns
1
TOH
0
0
ns
T10.2 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST29LE010
SST29LE010-150
SST29LE010-200
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
150
200
TCE
Chip Enable Access Time
Address Access Time
150
150
60
200
200
100
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
30
30
50
50
ns
1
TOHZ
ns
1
TOH
0
0
ns
T11.1 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST29VE010
SST29VE010-200
SST29VE010-250
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
200
250
TCE
Chip Enable Access Time
Address Access Time
200
200
100
250
250
120
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
50
50
50
50
ns
1
TOHZ
ns
1
TOH
0
0
ns
T12.1 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
10
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
SST29EE010
SST29LE/VE010
Symbol
TWC
TAS
Parameter
Min
Max
Min
Max
Units
ms
ns
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
10
10
0
50
0
0
70
0
TAH
ns
TCS
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
ns
TCH
0
0
ns
TOES
TOEH
TCP
0
0
ns
0
0
ns
70
70
35
0
120
120
50
0
ns
TWP
TDS
WE# Pulse Width
ns
Data Setup Time
ns
1
TDH
Data Hold Time
ns
1
TBLC
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
Software Chip-Erase
0.05
200
100
0.05
200
100
µs
1
TBLCO
µs
1
TIDA
10
20
10
20
µs
TSCE
ms
T13.5 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
11
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
T
T
RC
AA
ADDRESS A
16-0
T
CE
CE#
T
OE
OE#
T
T
OHZ
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DATA VALID
DATA VALID
DQ
7-0
304 ILL F03.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
Three-Byte Sequence for
Enabling SDP
T
AH
T
AS
ADDRESS A
5555 2AAA 5555
16-0
T
T
CS
CH
CE#
T
T
OEH
OES
OE#
WE#
T
WP
T
BLCO
T
BLC
T
DH
DQ
AA
55
A0
DATA VALID
7-0
T
WC
T
DS
SW0
SW1
SW2
BYTE 0
BYTE 1
BYTE 127
304 ILL F04.1
FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
12
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Three-Byte Sequence for
T
AH
Enabling SDP
T
AS
ADDRESS A
5555 2AAA 5555
16-0
T
CP
T
T
BLCO
BLC
CE#
T
T
OEH
OES
OE#
WE#
T
T
CS
CH
T
DH
DQ
AA
55
A0
DATA VALID
7-0
T
WC
T
DS
SW0
SW1
SW2
BYTE 0
BYTE 1
BYTE 127
304 ILL F05.1
FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
ADDRESS A
16-0
T
CE
CE#
T
OES
T
OEH
OE#
T
OE
WE#
DQ
7
D
D
D#
D#
T
+ T
BLCO
WC
304 ILL F06.0
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
13
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
ADDRESS A
16-0
CE#
OE#
T
T
CE
T
OEH
T
OES
OE
WE#
DQ
6
T
+ T
BLCO
WC
TWO READ CYCLES
WITH SAME OUTPUTS
304 ILL F07.0
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
Six-Byte Sequence for Disabling
Software Data Protection
T
WC
ADDRESS A
14-0
5555
2AAA
5555
5555
2AAA
5555
DQ
AA
55
80
AA
55
20
7-0
CE#
OE#
WE#
T
BLCO
T
WP
T
BLC
SW0
SW1
SW2
SW3
SW4
SW5
304 ILL F08.1
FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
14
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Six-Byte Code for Software Chip-Erase
T
SCE
ADDRESS A
14-0
5555
2AAA
5555
5555
2AAA
5555
DQ
AA
55
80
AA
55
10
7-0
CE#
OE#
WE#
T
BLCO
T
WP
T
BLC
SW0
SW1
SW2
SW3
SW4
SW5
304 ILL F09.1
FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence
for Software ID Entry
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
T
AA
DQ
AA
55
90
BF
DEVICE ID
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
BLC
DEVICE ID = 07H for SST29EE010
= 08H for SST29LE010/29VE010
SW0
SW1
SW2
304 ILL F10.2
FIGURE 11: SOFTWARE ID ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
15
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Three-Byte Sequence
for Software ID Exit and Reset
ADDRESS A
14-0
5555
2AAA
5555
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
BLC
SW0
SW1
SW2
304 ILL F11.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
16
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
304 ILL F12.1
AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE
TO TESTER
V
DD
R
L HIGH
TO DUT
C
L
R
L LOW
304 ILL F13.1
FIGURE 14: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
17
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Start
Software Data
Protect Write
Command
See Figure 17
Set Page
Address
Set Byte
Address = 0
Load Byte
Data
Increment
Byte Address
By 1
Byte
Address =
128?
No
Yes
Wait T
BLCO
Wait for end of
Write (T
,
WC
Data# Polling bit
or Toggle bit
operation)
Write
Completed
304 ILL F14.1
FIGURE 15: WRITE ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
18
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Page-Write
Initiated
Page-Write
Initiated
Page-Write
Initiated
Read DQ
(Data for last
byte loaded)
7
Read a byte
from page
Wait T
WC
Write
Completed
No
Read same
byte
Is DQ =
7
true data?
Yes
Write
Completed
No
Does DQ
match?
6
Yes
Write
Completed
304 ILL F15.1
FIGURE 16: WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
19
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Software Data Protect Enable
Command Sequence
Software Data Protect
Disable Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: A0H
Address: 5555H
Write data: 80H
Address: 5555H
Optional Page Load
Operation
Load 0 to
128 Bytes of
page data
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Wait T
BLCO
Write data: 20H
Address: 5555H
Wait T
WC
Wait T
BLCO
SDP Enabled
Wait T
WC
SDP Disabled
304 ILL F16.1
FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
20
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 90H
Address: 5555H
Write data: F0H
Address: 5555H
Pause 10 µs
Pause 10 µs
Return to normal
operation
Read Software ID
304 ILL F17.1
FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
21
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Software Chip-Erase
Command Sequence
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 80H
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 10H
Address: 5555H
Wait T
SCE
Chip-Erase
to FFH
304 ILL F18.2
FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
22
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST29xE010
-
XXX
-
XX
-
XX
Package Modifier
H = 32 leads or pins
Numeric = Die modifier
Package Type
N = PLCC
W = TSOP (die up) (8mm x 14mm)
E = TSOP (die up) (8mm x 20mm)
P = PDIP
U = Unencapsulated die
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
250 = 250 ns
200 = 200 ns
150 = 150 ns
90 = 90 ns
70 = 70 ns
Voltage
E = 5.0V-only
L = 3.0-3.6V
V = 2.7-3.6V
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
23
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
Valid combinations for SST29EE010
SST29EE010-70-4C-NH
SST29EE010-90-4C-NH
SST29EE010-70-4C-WH
SST29EE010-90-4C-WH
SST29EE010-70-4C-EH
SST29EE010-90-4C-EH
SST29EE010-70-4C-PH
SST29EE010-90-4C-PH
SST29EE010-70-4I-NH
SST29EE010-90-4C-U2
SST29EE010-70-4I-WH
SST29EE010-70-4I-EH
Valid combinations for SST29LE010
SST29LE010-150-4C-NH SST29LE010-150-4C-WH SST29LE010-150-4C-EH
SST29LE010-150-4I-NH
SST29LE010-150-4I-WH
SST29LE010-150-4I-EH
SST29LE010-200-4C-U2
Valid combinations for SST29VE010
SST29VE010-200-4C-NH SST29VE010-200-4C-WH SST29VE010-200-4C-EH
SST29VE010-200-4I-NH
SST29VE010-200-4I-WH
SST29VE010-200-4I-EH
SST29VE010-250-4C-U2
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Note: The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
24
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.485
.495
.447
.106
.112
Optional
.453
Pin #1 Identifier
.042
.048
.023
.029
.030
.040
.020 R.
MAX.
x 30˚
R.
2
1
32
.042
.048
.013
.021
.400 .490
BSC .530
.585
.595
.547
.553
.026
.032
.050
BSC.
.015 Min.
.075
.095
.050
BSC.
.026
.032
.125
.140
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32.PLCC.NH-ILL.2
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
1.05
0.95
Pin # 1 Identifier
.50
BSC
.270
.170
8.10
7.90
0.15
0.05
12.50
12.30
0.70
0.50
14.20
13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
25
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
1.05
0.95
Pin # 1 Identifier
.50
BSC
.27
.17
8.10
7.90
0.15
0.05
18.50
18.30
0.70
0.50
20.20
19.80
32.TSOP-EH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM
SST PACKAGE CODE: EH
32
C
L
.600
.625
1
Pin #1 Identifier
.530
.550
1.645
1.655
.065
.075
7˚
4 PLCS.
.170
.200
Base Plane
Seating Plane
.015
.050
0˚
15˚
.008
.012
.120
.150
.070
.080
.045
.065
.016
.022
.100 BSC
.600 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
32.pdipPH-ILL.2
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01 304
26
SST29EE010-70-4C-NH 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
SST29EE010-70-4C-NHE | SST | 1 Mbit (128K x8) Page-Write EEPROM | 获取价格 | |
SST29EE010-70-4C-NHE | MICROCHIP | 128K X 8 FLASH 5V PROM, 70 ns, PQCC32, ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 | 获取价格 | |
SST29EE010-70-4C-PH | SST | 1 Mbit (128K x8) Page-Mode EEPROM | 获取价格 | |
SST29EE010-70-4C-PHE | SST | 1 Mbit (128K x8) Page-Write EEPROM | 获取价格 | |
SST29EE010-70-4C-PHE | MICROCHIP | 128K X 8 FLASH 5V PROM, 70 ns, PDIP32, 0.600 INCH, ROHS COMPLIANT, PLASTIC, MO-015AP, DIP-32 | 获取价格 | |
SST29EE010-70-4C-UH | SST | 1 Mbit (128K x8) Page-Mode EEPROM | 获取价格 | |
SST29EE010-70-4C-WH | SST | 1 Mbit (128K x8) Page-Mode EEPROM | 获取价格 | |
SST29EE010-70-4C-WHE | SST | 1 Mbit (128K x8) Page-Write EEPROM | 获取价格 | |
SST29EE010-70-4C-WHE | MICROCHIP | 128K X 8 FLASH 5V PROM, 70 ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, MO-142BA, TSOP1-32 | 获取价格 | |
SST29EE010-70-4I-EH | SST | 1 Mbit (128K x8) Page-Mode EEPROM | 获取价格 |
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