SST29LE010-120-4I-W [SST]
1 Megabit (128K x 8) Page Mode EEPROM; 1兆位（ 128K ×8 ）页面模式的EEPROM
| 型号： | SST29LE010-120-4I-W |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 1 Megabit (128K x 8) Page Mode EEPROM |
| 文件： | 总27页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 Megabit (128K x 8) Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
Fast Read Access Time
1
– 5.0V-only for the 29EE010
– 3.0V-only for the 29LE010
– 2.7V-only for the 29VE010
– 5.0V-only operation: 90 and 120 ns
– 3.0V-only operation: 150 and 200 ns
– 2.7V-only operation: 200 and 250 ns
•
•
Superior Reliability
•
•
Latched Address and Data
2
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Automatic Write Timing
– Internal Vpp Generation
End of Write Detection
3
Low Power Consumption
•
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
– Toggle Bit
– Data# Polling
4
•
•
•
•
Hardware and Software Data Protection
•
Fast Page-Write Operation
TTL I/O Compatibility
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-write Cycle Time: 39 µs
(typical)
5
JEDEC Standard Byte-wide EEPROM Pinouts
Packages Available
6
– 32-Pin TSOP (8x20 & 8x14 mm)
– 32-Lead PLCC
– 32 Pin Plastic DIP
7
applications, the 29EE010/29LE010/29VE010 signifi-
cantly improve performance and reliability, while lower-
ingpowerconsumption,whencomparedwithfloppydisk
or EPROM approaches. The 29EE010/29LE010/
29VE010 improve flexibility while lowering the cost for
program, data, and configuration storage applications.
PRODUCT DESCRIPTION
8
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS
pagemodeEEPROMsmanufacturedwithSST’spropri-
etary, highperformanceCMOSSuperFlashtechnology.
The split gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches. The 29EE010/
29LE010/29VE010 write with a single power supply.
Internal Erase/Program is transparent to the user. The
29EE010/29LE010/29VE010 conform to JEDEC stan-
dard pinouts for byte-wide memories.
9
To meet high density, surface mount requirements, the
29EE010/29LE010/29VE010 are offered in 32-pin
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
PDIP package is also available. See Figures 1 and 2 for
pinouts.
10
11
12
13
14
15
16
Device Operation
Featuring high performance page write, the 29EE010/
29LE010/29VE010 provide a typical byte-write time of
39 µsec. The entire memory, i.e., 128K bytes, can be
writtenpagebypageinaslittleas5seconds,whenusing
interface features such as Toggle Bit or Data# Polling to
indicate the completion of a write cycle. To protect
against inadvertent write, the 29EE010/29LE010/
29VE010 have on-chip hardware and software data
protection schemes. Designed, manufactured, and
testedforawidespectrumofapplications,the29EE010/
29LE010/29VE010 are offered with a guaranteed page-
write endurance of 104 or 103 cycles. Data retention is
rated at greater than 100 years.
TheSSTpagemodeEEPROMoffersin-circuitelectrical
write capability. The 29EE010/29LE010/29VE010 does
notrequireseparateeraseandprogramoperations.The
internally timed write cycle executes both erase and
program transparently to the user. The 29EE010/
29LE010/29VE010 have industry standard optional
Software Data Protection, which SST recommends al-
ways to be enabled. The 29EE010/29LE010/29VE010
arecompatiblewithindustrystandardEEPROMpinouts
and functionality.
Read
The Read operations of the 29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
The29EE010/29LE010/29VE010aresuitedforapplica-
tionsthatrequireconvenientandeconomicalupdatingof
program, configuration, or data memory. For all system
3©0149-0948 S1i2li/c9o7n Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
chipisdeselectedandonlystandbypowerisconsumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
leave the 29EE010/29LE010/29VE010 protected at the
end of the page write. The page load cycle consists of
loading 1 to 128 bytes of data into the page buffer. The
internalwritecycleconsistsoftheTBLCO time-outandthe
writetimeroperation.DuringtheWriteoperation,theonly
valid reads are Data# Polling and Toggle Bit.
Write
ThePage-Writeoperationallowstheloadingofupto128
bytes of data into the page buffer of the 29EE010/
29LE010/29VE010 before the initiation of the internal
write cycle. During the internal write cycle, all the data in
thepagebufferiswrittensimultaneouslyintothememory
array. Hence, the page-write feature of 29EE010/
29LE010/29VE010allowtheentirememorytobewritten
in as little as 5 seconds. During the internal write cycle,
the host is free to perform additional tasks, such as to
fetchdatafromotherlocationsinthesystemtosetupthe
write to the next page. In each Page-Write operation, all
the bytes that are loaded into the page buffer must have
thesamepageaddress,i.e.A7 throughA16.Anybytenot
loaded with user data will be written to FF.
ThePageWritetotheSST29EE010/29LE010/29VE010
should always use the JEDEC Standard Software Data
Protection (SDP) 3-byte command sequence. The
29EE010/29LE010/29VE010 contain the optional
JEDEC approved Software Data Protection scheme.
SSTrecommendsthatSDPalwaysbeenabled,thus,the
descriptionoftheWriteoperationswillbegivenusingthe
SDP enabled format. The 3-byte SDP Enable and SDP
Write commands are identical; therefore, any time a
SDPWritecommandisissued,softwaredataprotec-
tion is automatically assured. The first time the 3-byte
SDP command is given, the device becomes SDP en-
abled. Subsequent issuance of the same command
bypasses the data protection for the page being written.
At the end of the desired page write, the entire device
remains protected. For additional descriptions, please
see the application notes on “The Proper Use of JEDEC
Standard Software Data Protection” and “Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories” in this data book.
See Figures 4 and 5 for the page-write cycle timing
diagrams. If after the completion of the 3-byte SDP load
sequence or the initial byte-load cycle, the host loads a
second byte into the page buffer within a byte-load cycle
time (TBLC) of 100 µs, the 29EE010/29LE010/29VE010
will stay in the page load cycle. Additional bytes are then
loaded consecutively. The page load cycle will be termi-
nated if no additional byte is loaded into the page buffer
within 200 µs (TBLCO) from the last byte-load cycle, i.e.,
no subsequent WE# or CE# high-to-low transition after
the last rising edge of WE# or CE#. Data in the page
buffer can be changed by a subsequent byte-load cycle.
The page load period can continue indefinitely, as long
as the host continues to load the device within the byte-
load cycle time of 100 µs. The page to be loaded is
determined by the page address of the last byte loaded.
TheWriteoperationconsistsofthreesteps. Step1isthe
three byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
29EE010/29LE010/29VE010. Steps 1 and 2 use the
same timing for both operations. Step 3 is an internally
controlled write cycle for writing the data loaded in the
page buffer into the memory array for nonvolatile stor-
age. During both the SDP 3-byte load sequence and the
byte-load cycle, the addresses are latched by the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched by the rising edge of either CE# or WE#,
whicheveroccursfirst.Theinternalwritecycleisinitiated
by the TBLCO timer after the rising edge of WE# or CE#,
whicheveroccursfirst.Thewritecycle,onceinitiated,will
continue to completion, typically within 5 ms. See Fig-
ures4and5forWE#andCE#controlledpagewritecycle
timing diagrams and Figures 14 and 16 for flowcharts.
Software Chip-Erase
The 29EE010/29LE010/29VE010 provide a Chip-Erase
operation, which allows the user to simultaneously clear
the entire memory array to the “1” state. This is useful
when the entire device must be quickly erased.
The Software Chip-Erase operation is initiated by using
a specific six byte-load sequence. After the load se-
quence, the device enters into an internally timed cycle
similar to the write cycle. During the erase operation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure9fortimingdiagram, andFigure18for
the flowchart.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three byte load se-
quence that allows writing to the selected page and will
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
2
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Write Operation Status Detection
Hardware Data Protection
The 29EE010/29LE010/29VE010 provide two software
means to detect the completion of a write cycle, in order
to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7)
andToggleBit(DQ6). Theendofwritedetectionmodeis
enabled after the rising WE# or CE# whichever occurs
first, which initiates the internal write cycle.
Noise/GlitchProtection:AWE#orCE#pulseoflessthan
5 ns will not initiate a write cycle.
1
VCC Power Up/Down Detection: The write operation is
inhibited when VCC is less than 2.5V.
2
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation. This prevents inad-
vertent writes during power-up or power-down.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
maypossiblygetanerroneousresult,i.e.,validdatamay
appear to conflict with either DQ7 or DQ6. In order to
preventspuriousrejection,ifanerroneousresultoccurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
3
Software Data Protection (SDP)
The 29EE010/29LE010/29VE010 provide the JEDEC
approved optional software data protection scheme for
all data alteration operations, i.e., Write and Chip erase.
With this scheme, any write operation requires the inclu-
sion of a series of three byte-load operations to precede
the data loading operation. The three byte-load se-
quence is used to initiate the write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down. The
29EE010/29LE010/29VE010 are shipped with the soft-
ware data protection disabled.
4
5
6
Data# Polling (DQ7)
7
When the 29EE010/29LE010/29VE010 are in the inter-
nal write cycle, any attempt to read DQ7 of the last byte
loaded during the byte-load cycle will receive the com-
plement of the true data. Once the write cycle is com-
pleted, DQ7 willshowtruedata. Thedeviceisthenready
for the next operation. See Figure 6 for Data# Polling
timing diagram and Figure 15 for a flowchart.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 4 and 5). The device will then
be automatically set into the data protect mode. Any
subsequent write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
ware command codes and Figures 4 and 5 for the timing
diagrams. To set the device into the unprotected mode,
a six-byte sequence is required. See Table 4 for the
specific codes and Figure 8 for the timing diagram. If a
writeisattemptedwhileSDPisenabledthedevicewillbe
inanon-accessiblestatefor~300µs.SSTrecommends
SoftwareDataProtectionalwaysbeenabled.SeeFigure
16 for flowcharts.
8
9
Toggle Bit (DQ6)
10
11
12
13
14
15
16
Duringtheinternalwritecycle,anyconsecutiveattempts
to read DQ6 will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is
completed, the toggling will stop. The device is then
ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 15 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
The 29EE010/29LE010/29VE010 Software Data Pro-
tectionisaglobalcommand,protecting(orunprotecting)
all pages in the entire memory array once enabled (or
disabled). Therefore using SDP for a single page write
will enable SDP for the entire array. Single pages by
themselves cannot be SDP enabled or disabled.
Data Protection
The 29EE010/29LE010/29VE010 provide both hard-
ware and software features to protect nonvolatile data
from inadvertent writes.
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
3
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Single power supply reprogrammable nonvolatile
memories may be unintentionally altered. SST strongly
recommends that Software Data Protection (SDP) al-
ways be enabled. The 29EE010/29LE010/29VE010
should be programmed using the SDP command se-
quence. SST recommends the SDP Disable Command
Sequence not be issued to the device prior to writing.
multiple manufacturers in the same socket. For details,
see Table 3 for hardware operation or Table 4 for
software operation, Figure 10 for the software ID entry
and read timing diagram and Figure 17 for the ID entry
command sequence flowchart. The manufacturer and
device codes are the same for both operations.
TABLE 1: PRODUCT IDENTIFICATION TABLE
PleaserefertothefollowingApplicationNoteslocatedat
the back of this databook for more information on using
SDP:
Byte
Data
BF H
07 H
08 H
Manufacturer’s Code
29EE010 Device Code
29LE010 Device Code
29VE010 Device Code
0000 H
0001 H
0001 H
0001 H
•
ProtectingAgainstUnintentionalWritesWhenUsing
Single Power Supply Flash Memories
08 H
304 PGM T1.1
•
The Proper Use of JEDEC Standard Software Data
Protection
Product Identification Mode Exit
Product Identification
In order to return to the standard read mode, the Soft-
wareProductIdentificationmodemustbeexited.Exiting
is accomplished by issuing the Software ID Exit (reset)
operation,whichreturnsthedevicetothereadoperation.
The Reset operation may also be used to reset the
device to the read mode after an inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g. not read correctly. See Table 4 for
software command codes, Figure 11 for timing wave-
form and Figure 17 for a flowchart.
The product identification mode identifies the device as
the 29EE010/29LE010/29VE010 and manufacturer as
SST. This mode may be accessed by hardware or
softwareoperations. Thehardwareoperationistypically
used by a programmer to identify the correct algorithm
for the 29EE010/29LE010/29VE010. Users may wish to
usethesoftwareproductidentificationoperationtoiden-
tify the part (i.e. using the device code) when using
FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010/29LE010/29VE010
1,048,576 Bit
EEPROM
Cell Array
X-Decoder
A
16 - A0
Address buffer & Latches
Control Logic
Y-Decoder and Page Latches
CE#
OE#
WE#
I/O Buffers and Data Latches
DQ7 - DQ0
304 MSW B1.0
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
4
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
A11
A9
A8
1
2
3
4
5
6
7
8
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A13
A14
NC
WE#
Vcc
NC
A16
A15
A12
A7
Standard Pinout
Top View
2
9
10
11
12
13
14
15
16
Die up
3
A6
A5
A4
A1
A2
A3
304 MSW F01.1
4
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
5
NC
A15
3
NC
1
WE#
Vcc
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
WE#
NC
6
A12
4
A16
2
NC
A16
A15
A12
A7
2
3
4
A14
A13
A8
32 31 30
A14
A13
A8
29
28
27
26
25
24
23
22
21
A7
A6
5
6
7
8
9
5
7
A6
6
A5
7
A9
A5
32-Pin PDIP
Top View
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A9
A4
A3
9
A11
OE#
A10
CE#
DQ7
32-Lead PLCC
Top View
A3
8
A2
10
11
12
13
14
15
16
A2
10
11
12
13
A1
A1
A0
DQ0
DQ1
DQ2
Vss
A0
9
DQ0
14 15 16 17 18 19 20
DQ1
Vss
DQ3
DQ4
DQ6
10
11
12
13
14
15
16
DQ2
DQ5
304 MSW F02.1
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A16-A7
Row Address Inputs
To provide memory addresses. Row addresses define a page for a
write cycle.
A6-A0
Column Address
Inputs
Column Addresses are toggled to load page data.
DQ7-DQ0
Data Input/output
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE#
OE#
WE#
Vcc
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations
To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010
Vss
NC
Ground
No Connection
Unconnected pins.
304 PGM T2.0
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
5
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
VIL
VIL
VIH
X
OE#
VIL
VIH
X
WE#
VIH
VIL
X
DQ
Address
Read
DOUT
AIN
Page Write
DIN
AIN
Standby
High Z
X
Write Inhibit
Write Inhibit
Software Chip Erase
Product Identification
Hardware Mode
VIL
X
X
High Z/ DOUT
High Z/ DOUT
DIN
X
X
VIH
VIL
X
VIL
VIH
AIN, See Table 4
VIL
VIL
VIH
Manufacturer Code (BF)
A16 - A1 = VIL, A9 = VH, A0 = VIL
Device Code (see notes) A16 - A1 = VIL, A9 = VH, A0= VIH
Software Mode
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIL
See Table 4
See Table 4
See Table 4
304 PGM T3.0
SDP Enable Mode
SDP Disable Mode
TABLE 4: SOFTWARE COMMAND CODES
Command
Sequence
1st Bus
Write Cycle
Addr(1) Data Addr(1) Data
2nd Bus
Write Cycle
3rd Bus
Write Cycle
Addr(1) Data Addr(1) Data
4th Bus
Write Cycle
5th Bus
Write Cycle
Addr(1) Data Addr(1) Data
6th Bus
Write Cycle
Software Data
Protect Enable
& Page Write
5555H AAH
2AAAH 55H
5555H A0H
Addr(2) Data
Software Data
Protect Disable
5555H AAH
5555H AAH
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
5555H 80H
5555H 80H
5555H 90H
5555H F0H
5555H 80H
5555H AAH
5555H AAH
2AAAH 55H 5555H 20H
2AAAH 55H 5555H 10H
Software Chip
Erase
Software ID Entry 5555H AAH
Software ID Exit 5555H AAH
Alternate Software 5555H AAH
ID Entry(3)
5555H AAH
2AAAH 55H 5555H 60H
304 PGM T4.1
(1)
Notes:
Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”.
Page Write consists of loading up to 128 bytes (A6 - A0).
Alternate 6 byte software Product-ID Command Code
The software chip erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
(2)
(3)
(4)
Notes for Software Product ID Command Code:
1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0,
29EE010 Device Code = 07H, is read with A0 = 1.
29LE010/29VE010 Device Code = 08H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
6
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
1
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
2
3
4
Output Short Circuit Current(1) ....................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
5
6
29EE010 OPERATING RANGE
AC CONDITIONS OF TEST
Range
Ambient Temp
VCC
Input Rise/Fall Time......... 10 ns
Output Load..................... 1 TTL Gate and CL = 100 pF
See Figures 12 and 13
Commercial
Industrial
0°C to +70°C
5V±10%
5V±10%
7
-40°C to +85°C
29LE010 OPERATING RANGE
8
Range
Ambient Temp
VCC
Commercial
Industrial
0°C to +70°C
3.0V to 3.6V
3.0V to 3.6V
9
-40°C to +85°C
29VE010 OPERATING RANGE
10
11
12
13
14
15
16
Range
Ambient Temp
VCC
Commercial
Industrial
0°C to +70°C
2.7V to 3.6V
2.7V to 3.6V
-40°C to +85°C
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
7
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 5: 29EE010 DC OPERATING CHARACTERISTICS VCC = 5V±10%
Limits
Max
Symbol Parameter
Min
Units
Test Conditions
ICC
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read
30
mA
Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write
50
3
mA
mA
CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
CE#=OE#=WE#=VIH, VCC =VCC Max.
ISB1
ISB2
Standby VCC Current
(TTL input)
Standby VCC Current
(CMOS input)
50
µA
CE#=OE#=WE#=VCC -0.3V.
VCC = VCC Max.
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN =GND to VCC, VCC = VCC Max.
VOUT =GND to VCC, VCC = VCC Max.
VCC = VCC Max.
ILO
VIL
VIH
VOL
VOH
VH
IH
10
0.8
Input High Voltage
2.0
V
VCC = VCC Max.
Output Low Voltage
Output High Voltage
Supervoltage for A9
0.4
V
IOL = 2.1 mA, VCC = VCC Min.
IOH = -400µA, VCC = VCC Min.
CE# = OE# =VIL, WE# = VIH
2.4
V
11.6
12.4
100
V
Supervoltage Current
for A9
µA
CE# = OE# = VIL, WE# = VIH,
A9 = VH Max.
304 PGM T5.0
T
ABLE 6: 29LE010/29VE010 DC OPERATING
C
HARACTERISTICS VCC = 3.0-3.6 FOR 29LE010, VCC = 2.7-3.6 FOR 29VE010
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
ICC
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read
12
mA
Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write
15
1
mA
mA
CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
CE#=OE#=WE#=VIH, VCC =VCC Max.
ISB1
ISB2
Standby VCC Current
(TTL input)
Standby VCC Current
(CMOS input)
15
µA
CE#=OE#=WE#=VCC -0.3V.
VCC = VCC Max.
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN =GND to VCC, VCC = VCC Max.
VOUT =GND to VCC, VCC = VCC Max.
VCC = VCC Max.
ILO
VIL
VIH
VOL
VOH
VH
IH
10
0.8
Input High Voltage
2.0
V
VCC = VCC Max.
Output Low Voltage
Output High Voltage
Supervoltage for A9
0.4
V
IOL = 100 µA, VCC = VCC Min.
IOH = -100 µA, VCC = VCC Min.
CE# = OE# =VIL, WE# = VIH
2.4
V
11.6
12.4
100
V
Supervoltage Current
for A9
µA
CE# = OE# = VIL, WE# = VIH,
A9 = VH Max.
304 PGM T6.0
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
8
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 7: POWER-UP TIMINGS
Symbol
Parameter
Maximum
Units
µs
(1)
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
5
1
(1)
TPU-WRITE
ms
304 PGM T7.0
2
TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
3
(1)
CI/O
I/O Pin Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6 pF
304 PGM T8.0
4
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
5
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Cycles
Years
Volts
Test Method
6
NEND
Endurance
10,000(2)
MIL-STD-883, Method 1033
JEDEC Standard A103
JEDEC Standard A114
(1)
TDR
Data Retention
100
7
(1)
VZAP_HBM
ESD Susceptibility
Human Body Model
1000
(1)
VZAP_MM
ESD Susceptibility
Machine Model
200
100
Volts
mA
JEDEC Standard A115
8
(1)
ILTH
Latch Up
JEDEC Standard 78
304 PGM T9.1
9
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(2)See Ordering Information for desired type.
10
11
12
13
14
15
16
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
9
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
AC CHARACTERISTICS
TABLE 10: 29EE010 READ CYCLE TIMING PARAMETERS
29EE010-90
29EE010-120
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle time
90
120
TCE
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
90
90
40
120
120
50
ns
TAA
ns
TOE
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
(1)
TCHZ
30
30
30
30
ns
(1)
TOHZ
ns
(1)
TOH
Output Hold from Address
Change
0
0
ns
304 PGM T10.1
TABLE 11: 29LE010 READ CYCLE TIMING PARAMETERS
29LE010-150
29LE010-200
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
Read Cycle time
150
200
ns
TCE
Chip Enable Access Time
Address Access Time
150
150
60
200
200
100
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
(1)
TCHZ
30
30
50
50
ns
ns
(1)
TOHZ
(1)
TOH
0
0
ns
304 PGM T11.0
TABLE 12: 29VE010 READ CYCLE TIMING PARAMETERS
29VE010-200
29VE010-250
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
Read Cycle time
200
250
ns
TCE
Chip Enable Access Time
Address Access Time
200
200
100
250
250
120
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
(1)
TCHZ
50
50
50
50
ns
ns
(1)
TOHZ
(1)
TOH
0
0
ns
304 PGM T12.0
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
10
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
29EE010
Max
29LE/VE010
Symbol
TWC
TAS
Parameter
Min
Min
Max
Units
ms
ns
1
Write Cycle (erase and program)
Address Setup Time
Address Hold Time
10
10
0
50
0
0
70
0
2
TAH
ns
TCS
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
ns
TCH
0
0
ns
3
TOES
TOEH
TCP
0
0
ns
0
0
ns
4
70
70
35
0
120
120
50
0
ns
TWP
TDS
WE# Pulse Width
ns
Data Setup Time
ns
5
TDH
Data Hold Time
ns
(1)
TBLC
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
Software Chip Erase
0.05
200
100
0.05
200
100
µs
(1)
6
TBLCO
µs
TIDA
10
20
10
20
µs
TSCE
ms
7
304 PGM T13.1
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
8
9
10
11
12
13
14
15
16
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
11
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
304 AC F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
304 AC F04.0
FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
12
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
1
2
3
4
5
6
304 AC F05.0
7
FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
8
9
10
11
12
13
14
15
16
304 AC F06.0
FIGURE 6: DATA# POLLING TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
13
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
304 AC F07.0
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
304 AC F08.0
FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
14
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
1
2
3
4
5
6
7
304 AC F09.0
FIGURE 9: SOFTWARE CHIP ERASE TIMING DIAGRAM
8
9
10
11
12
13
14
15
16
DEVICE CODE
DEVICE CODE = 07 for 29EE010
= 08 for 29LE010/29VE010
304 AC F10.0
FIGURE 10: SOFTWARE ID ENTRY AND READ
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
15
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
304 AC F11.0
FIGURE 11: SOFTWARE ID EXIT AND RESET
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
16
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
1
2.4
2.0
2.0
0.8
OUTPUT
INPUT
REFERENCE POINTS
0.8
2
0.4
304 MSW F12.0
3
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.4 VTTL) for a logic “0”. Measurement reference
points for inputs and outputs are VIH (2.0 VTTL) and VIL (0.8 VTTL). Inputs rise and fall times (10% ↔ 90%) are <10
ns.
4
FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS
5
6
7
TEST LOAD EXAMPLE
8
VCC
TO TESTER
9
RL
HIGH
10
11
12
13
14
15
16
TO DUT
CL
RL
LOW
304 MSW F13.0
FIGURE 13: TEST LOAD EXAMPLE
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
17
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Start
Software Data
See Figure 16
Protect Write
Command
Set Page
Address
Set Byte
Address = 0
Load Byte
Data
Increment
Byte Address
By 1
Byte
Address =
128 ?
No
Yes
Wait T
Wait T
BLCO
Wait for end of
Write (TWC, Data
# Polling bit or
Toggle bit
operation)
Write
Completed
304 MSW F14.0
FIGURE 14: WRITE ALGORITHM
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
18
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Data# Polling
Internal Timer
Toggle Bit
1
2
Page Write
Initiated
Page Write
Initiated
Page Write
Initiated
3
Read DQ7
4
Read a byte
from page
Wait TWC
(Data for last
byte loaded)
5
6
Write
Completed
Read same
byte
No
Is DQ7 =
7
true data?
Yes
8
No
Does DQ6
match?
Write
Completed
9
Yes
10
11
12
13
14
15
16
Write
Completed
304 MSW F15.0
FIGURE 15: WAIT OPTIONS
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
19
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Software Data Protect Enable
Command Sequence
Software Data Protect
Disable Command Sequence
Write data: AA
Address: 5555
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 55
Address: 2AAA
Write data: 80
Address: 5555
Write data: A0
Address: 5555
Write data: AA
Address: 5555
Load 0 to
128 Bytes of
page data
Optional Page Load
Operation
Write data: 55
Address: 2AAA
Wait TBLCO
Write data: 20
Address: 5555
Wait TWC
Wait TBLCO
SDP Enabled
Wait TWC
SDP Disabled
304 MSW F16.0
FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
20
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
1
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
2
Write data: AA
Address: 5555
Write data: AA
Address: 5555
3
4
Write data: 55
Address: 2AAA
Write data: 55
Address: 2AAA
5
6
Write data: 90
Address: 5555
Write data: F0
Address: 5555
7
8
Pause 10 µs
Pause 10 µs
9
Return to normal
operation
Read Software ID
10
11
12
13
14
15
16
304 MSW F17.0
FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
21
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Software Chip-Erase
Command Sequence
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 80
Address: 5555
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 10
Address: 5555
Wait TSCE
Chip Erase
to FFH
304 MSW F18.0
FIGURE 18: SOFTWARE CHIP ERASE COMMAND CODES
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
22
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
PRODUCT ORDERING INFORMATION
1
Device
Speed
Suffix1 Suffix2
XX XX
SST29XE010
-
XXX
-
-
2
Package Modifier
H = 32 leads
3
Numeric = Die modifier
Package Type
4
P = PDIP
N = PLCC
E = TSOP (die up) 8x20 mm
W = TSOP (die up) 8x14 mm
U = Unencapsulated die
5
6
Operating Temperature
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
7
Minimum Endurance
3 = 1000 cycles
8
4 = 10,000 cycles
Read Access Speed
250 = 250 ns
200 = 200 ns
150 = 150 ns
120 = 120 ns
90 = 90 ns
9
10
11
12
13
14
15
16
Voltage
E = 5V-only
L = 3V-only
V = 2.7V-only
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
23
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
29EE010 Valid combinations
SST29EE010- 90-4C- EH
SST29EE010-120-4C- EH
SST29EE010- 90-4C- NH
SST29EE010-120-4C- NH
SST29EE010- 90-4C- PH
SST29EE010-120-4C- PH
SST29EE010- 90-4C- WH
SST29EE010-120-4C- WH
SST29EE010- 90-4I-EH
SST29EE010-120-4I-EH
SST29EE010- 90-4I-NH
SST29EE010-120-4I-NH
SST29EE010-120-4C-U2
29LE010 Valid combinations
SST29LE010-150-4C- EH
SST29LE010-200-4C- EH
SST29LE010-150-4C- NH
SST29LE010-200-4C- NH
SST29LE010-150-4C- PH
SST29LE010-200-4C- PH
SST29LE010-150-4C- WH
SST29LE010-200-4C- WH
SST29LE010-150-4I-EH
SST29LE010-200-4C-U2
SST29LE010-150-4I-NH
29VE010 Valid combinations
SST29VE010-200-4C- EH
SST29VE010-250-4C- EH
SST29VE010-200-4C- NH
SST29VE010-250-4C- NH
SST29VE010-200-4C- PH
SST29VE010-250-4C- PH
SST29VE010-200-4C-WH
SST29VE010-250-4C-WH
SST29VE010-200-4I-EH
SST29VE010-250-4C-U2
SST29VE010-200-4I-NH
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Note:
The software chip erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
24
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
PACKAGING DIAGRAMS
1
2
3
4
5
6
32pn PDIP PH AC.2
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
7
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
8
9
10
11
12
13
14
15
16
32pn PLCC NH AC.2
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
25
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
32pn TSOP WH AC.3
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: WH
Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
32pn TSOP EH AC.4
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: EH
© 1998 Silicon Storage Technology, Inc.
304-04 12/97
26
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
SST Area Offices
Canada - Toronto
Kaltron Components Inc.
Canada - Ottawa
Kaltron Components Inc.
Canada - Montreal
U.S.A. - California
U.S.A. - Florida
U.S.A. - Florida
U.S.A. - Massachusetts
Japan - Yokohama
Europe - UK
(408) 523-7722
(813) 771-8819
(941) 505-8893
(978) 356-3845
(81)45-471-1851
(44)1784-490455
(905) 405-6276
(819) 457-1225
(514) 696-6589
(604) 294-3999
(787) 746-9897
1
Kaltron Components Inc.
Canada - B.C.
Thorson Pacific, Inc.
Puerto Rico
North American Sales Representatives
2
MEC/Caribe
Alabama
Elcom, Inc.
Arizona
QuadRep, Inc.
California
(205) 830-4001
International Sales Representatives & Distributors
3
(602) 839-2102
(408) 736-2260
Australia
ACD
Belgium
(61) 3-762 7644
(32) 2778-9850
(86)21-6482-8021
(45) 39-57-71-10
(353) 61 411842
(358) 9-5842 600
Northern
Premier Technical Sales
Southern
QuadRep, Inc., San Diego
QuadRep, Inc., Irvine
Memec Brussels
China
Actron Technology Co., Ltd.
Denmark
Berendsen Components A/S
Ireland
Memec Ireland LTD
Finland
OXXO OY AB
France
RepDesign
4
(619) 775-1188
(714) 727-4222
Colorado
QuadRep, Inc.
Florida
5
(303) 771-6886
MEC Corporation - Central/East Coast
MEC Corporation - South/East Coast
MEC Corporation - West Coast
(904) 427-7236
(954) 426-8944
(813) 393-5011
6
Georgia
Elcom, Inc.
Iowa
Oasis Sales Corporation
Idaho
QuadRep, Inc.
Illinois
(33) 1 46 23 7990
(33) 1 46 23 7900
(770) 447-8200
(319) 377-8738
(208) 939-9626
A2M
Germany
7
Endrich Bauelemente
Vertriebs GMBH
Metronik GmbH
(49) 7452-60070
(49) 89-61108-0
Hong Kong
Oasis Sales Corporation - Northern
Rush & West Associates - Southern
(847) 640-1850
(314) 965-3322
8
Actron Technology Co., Ltd.
Serial System (HK) Ltd.
(852) 2727-3978
(852) 2950-0820
Kansas
Rush & West Associates
Massachusetts
S-J Associates
Minnesota
Cahill, Schmitz & Cahill
Missouri
Rush & West Associates
North Carolina
Israel
(913) 764-2700
(978) 670-8899
(612) 646-7217
(314) 965-3322
Elina Electronics
(972) 3-649 8543
(39)2-4801.2355
9
Italy
Carla Gavazzi Cefra SpA
Japan
Asahi Electronics Co., Ltd.
(81)3-3350-5418
(81)93-511-6471
(81)3-3355-7615
(81)3-5300-5525
(81)3-5396-6206
(81)3-3795-6461
Asahi Electronics Co., Ltd.
Hakuto Co., Ltd.
MICROTEK Inc.
Ryoden Trading Co., Ltd.
Silicon Technology Co., Ltd.
10
11
12
13
14
15
16
Elcom, Inc. - Charlotte
Elcom, Inc. - Raleigh
(704) 543-1229
(919) 743-5200
New Jersey
S-J Associates
New Mexico
QuadRep, Inc.
New York
S-J Associates - NYC
S-J Associates - Upstate
Ohio
Great Lakes - Columbus
Great Lakes - Cleveland
Oregon
Thorson Pacific, Inc.
Texas
Korea
Bigshine Korea Co., Ltd.
Netherlands
Memec Benelux
Singapore
Serial System Ltd.
South Africa
KH Distributors
Spain
Tekelec Espana S.A.
Sweden
Pelcon Electronics AB
Switzerland
Leading Technology
Taiwan, R.O.C.
(609) 866-1234
(505) 332-2417
(82) 2-832-8881
(31)40-265-9399
(65) 286-1812
(516) 536-4242
(716) 924-1720
(27) 11 845-5011
(34) 13 20 41 60
(46) 8.795 98 70
(41) 277-21 7-446
(614) 885-6700
(216) 349-2700
(503) 293-9001
Tech. Mktg, Inc. - Carrollton
Tech. Mktg, Inc. - Houston
Tech. Mktg, Inc. - Austin
(972) 387-3601
(713) 783-4497
(512) 343-6976
Award Software
PCT Limited
Tonsam Corporation
(886)22-555-0880
(886)22-698-0098
(886)22-651-0011
Utah
QuadRep, Inc.
Virginia
S-J Associates
Washington
Thorson Pacific, Inc.
Wisconsin
Oasis Sales Corporation
(801) 521-4717
(703) 533-2233
(425) 603-9393
(414) 782-6660
United Kingdom
Ambar Components, Ltd.
(44)1844-261144
Revised 3-12-98
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
304-04 12/97
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