SST29VE010A-150-4I-EH [SST]
1 Megabit (128K x 8) Page Mode EEPROM; 1兆位（ 128K ×8 ）页面模式的EEPROM
| 型号： | SST29VE010A-150-4I-EH |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 1 Megabit (128K x 8) Page Mode EEPROM |
| 文件： | 总26页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 Megabit (128K x 8) Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
Fast Read Access Time
– 5.0V-only for the SST29EE010A
– 3.0-3.6V for the SST29LE010A
– 2.7-3.6V for the SST29VE010A
– 5.0V-only operation: 90 and 120 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
1
•
•
Superior Reliability
•
•
Latched Address and Data
2
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Automatic Write Timing
– Internal VPP Generation
End of Write Detection
Low Power Consumption
3
•
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
– Toggle Bit
– Data# Polling
4
•
•
•
Hardware and Software Data Protection
•
Fast Page Write Operation
TTL I/O Compatibility
– 128 Bytes per Page, 1024 Pages
– Page Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte Write Cycle Time: 39 µs
(typical)
5
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
•
6
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 20mm & 8mm x 14mm)
7
updatingofprogram, configuration, ordatamemory. For
all system applications, the SST29EE010A/29LE010A/
29VE010A significantly improve performance and reli-
ability, while lowering power consumption. The
SST29EE010A/29LE010A/29VE010A improve flexibil-
itywhileloweringthecostforprogram,data,andconfigu-
ration storage applications.
PRODUCT DESCRIPTION
8
TheSST29EE010A/29LE010A/29VE010Aare128Kx8
CMOSPageWriteEEPROMsmanufacturedwithSST’s
proprietary, high performance CMOS SuperFlash tech-
nology. The split-gate cell design and thick oxide tunnel-
ing injector attain better reliability and manufacturability
compared with alternate approaches. The
SST29EE010A/29LE010A/29VE010A write with a
singlepowersupply.InternalErase/Programistranspar-
ent to the user. The SST29EE010A/29LE010A/
29VE010AconformtoJEDECstandardpinoutsforbyte-
wide memories.
9
10
11
12
13
14
15
16
To meet high density, surface mount requirements, the
SST29EE010A/29LE010A/29VE010Aareofferedin32-
pin TSOP and 32-lead PLCC packages. A 600-mil, 32-
pin PDIP package is also available. See Figures 1 and 2
for pinouts.
Device Operation
Featuring high performance page write, the
SST29EE010A/29LE010A/29VE010A provide a typical
byte-write time of 39 µsec. The entire memory, i.e., 128
KBytes, can be written page-by-page in as little as 5
seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of a write
cycle. To protect against inadvertent write, the
SST29EE010A/29LE010A/29VE010A have on-chip
hardware and software data protection schemes. De-
signed, manufactured, andtestedforawidespectrumof
applications, the SST29EE010A/29LE010A/29VE010A
are offered with a guaranteed page write endurance of
104 cycles. Data retention is rated at greater than 100
years.
TheSSTpagemodeEEPROMoffersin-circuitelectrical
write capability. The SST29EE010A/29LE010A/
29VE010A does not require separate Erase and
Program operations. The internally timed write cycle
executes both erase and program transparently to the
user. The SST29EE010A/29LE010A/29VE010A have
industry standard Software Data Protection. The
SST29EE010A/29LE010A/29VE010A are compatible
with industry standard EEPROM pinouts and
functionality.
Read
The Read operations of the SST29EE010A/29LE010A/
29VE010A are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
The SST29EE010A/29LE010A/29VE010A are suited
for applications that require convenient and economical
3©0139-0919 S2i/l9ic9on Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
CE# is used for device selection. When CE# is high, the
array. Hence, the page write feature of SST29EE010A/
29LE010A/29VE010A allow the entire memory to be
written in as little as 5 seconds. During the internal write
cycle,thehostisfreetoperformadditionaltasks,suchas
to fetch data from other locations in the system to set up
the write to the next page. In each Page Write operation,
all the bytes that are loaded into the page buffer must
have the same page address, i.e. A7 through A16. Any
byte not loaded with user data will be written to FF.
chipisdeselectedandonlystandbypowerisconsumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
Write
The Page Write to the SST29EE010A/29LE010A/
29VE010A uses the JEDEC Standard Software Data
Protection (SDP) three-byte command sequence.
See Figures 4 and 5 for the page write cycle timing
diagrams. If after the completion of the three-byte SDP
load sequence the host loads a byte into the page buffer
within a byte-load cycle time (TBLC) of 100 µs, the
SST29EE010A/29LE010A/29VE010A will stay in the
page load cycle. Additional bytes are then loaded con-
secutively. The page load cycle will be terminated if no
additional byte is loaded into the page buffer within 200
µs (TBLCO) from the last byte-load cycle, i.e., no sub-
sequent WE# or CE# high-to-low transition after the last
rising edge of WE# or CE#. Data in the page buffer can
be changed by a subsequent byte-load cycle. The page
load period can continue indefinitely, as long as the host
continues to load the device within the byte-load cycle
time of 100 µs. The page to be loaded is determined by
the page address of the last byte loaded.
TheWriteoperationconsistsofthreesteps. Step1isthe
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE010A/29LE010A/29VE010A. Steps 1 and 2
use the same timing for both operations. Step 3 is an
internallycontrolledwritecycleforwritingthedataloaded
in the page buffer into the memory array for nonvolatile
storage. During both the SDP three-byte load sequence
andthebyte-loadcycle,theaddressesarelatchedbythe
fallingedgeofeitherCE#orWE#,whicheveroccurslast.
The data is latched by the rising edge of either CE# or
WE#, whichever occurs first. The internal write cycle is
initiated by the TBLCO timer after the rising edge of WE#
or CE#, whichever occurs first. The write cycle, once
initiated,willcontinuetocompletion,typicallywithin5ms.
See Figures 4 and 5 for WE# and CE# controlled page
write cycle timing diagrams and Figures 13 and 15 for
flowcharts.
Software Chip Erase
The SST29EE010A/29LE010A/29VE010A provide a
Chip Erase operation, which allows the user to simulta-
neously clear the entire memory array to the “1” state.
This is useful when the entire device must be quickly
erased.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three-byte load se-
quence that allows writing to the selected page and will
leave the SST29EE010A/29LE010A/29VE010A pro-
tected at the end of the Page Write. The page load cycle
consists of loading 1 to 128 bytes of data into the page
buffer. The internal write cycle consists of the TBLCO
time-out and the write timer operation. During the Write
operation, the only valid reads are Data# Polling and
Toggle Bit.
The Software Chip Erase operation is initiated by using
a specific six-byte load sequence. After the load se-
quence, the device enters into an internally timed cycle
similartothewritecycle. DuringtheEraseoperation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure8fortimingdiagram, andFigure17for
the flowchart.
ThePageWriteoperationallowstheloadingofupto128
bytes of data into the page buffer of the SST29EE010A/
29LE010A/29VE010Abeforetheinitiationoftheinternal
write cycle. During the internal write cycle, all the data in
thepagebufferiswrittensimultaneouslyintothememory
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
2
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Write Operation Status Detection
Data Protection
The SST29EE010A/29LE010A/29VE010A provide two
softwaremeanstodetectthecompletionofawritecycle,
in order to optimize the system write cycle time. The
softwaredetectionincludestwostatusbits:Data#Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising WE# or CE# whichever
occurs first, which initiates the internal write cycle.
TheSST29EE010A/29LE010A/29VE010Aprovideboth
hardware and software features to protect nonvolatile
data from inadvertent writes.
1
Hardware Data Protection
Noise/GlitchProtection:AWE#orCE#pulseoflessthan
5 ns will not initiate a write cycle.
2
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
maypossiblygetanerroneousresult,i.e.,validdatamay
appear to conflict with either DQ7 or DQ6. In order to
preventspuriousrejection,ifanerroneousresultoccurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
VCC Power Up/Down Detection: The write operation is
inhibited when VCC is less than 2.5V.
3
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation. This prevents inad-
vertent writes during power-up or power-down.
4
5
Software Data Protection (SDP)
The SST29EE010A/29LE010A/29VE010A provide the
JEDEC approved software data protection scheme for
all data alteration operations, i.e., Write and Chip Erase.
With this scheme, any Write operation requires the
inclusion of a series of three byte-load operations to
precede the data loading operation. The three byte-load
sequence is used to initiate the write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down.
6
Data# Polling (DQ7)
7
When the SST29EE010A/29LE010A/29VE010A are in
the internal write cycle, any attempt to read DQ7 of the
last byte loaded during the byte-load cycle will receive
the complement of the true data. Once the write cycle is
completed, DQ7 will show true data. The device is then
ready for the next operation. See Figure 6 for Data#
Polling timing diagram and Figure 14 for a flowchart.
8
9
Toggle Bit (DQ6)
10
11
12
13
14
15
16
Duringtheinternalwritecycle,anyconsecutiveattempts
to read DQ6 will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is
completed, the toggling will stop. The device is then
ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 14 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
3
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Product Identification Mode Exit
Product Identification
In order to return to the standard read mode, the Soft-
wareProductIdentificationmodemustbeexited.Exiting
is accomplished by issuing the Software ID Exit (reset)
operation,whichreturnsthedevicetothereadoperation.
The Reset operation may also be used to reset the
device to the read mode after an inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g. not read correctly. See Table 4 for
software command codes, Figure 10 for timing wave-
form and Figure 16 for a flowchart.
The product identification mode identifies the device as
the SST29EE010A/29LE010A/29VE010A and manu-
facturer as SST. This mode may be accessed by hard-
ware or software operations. The hardware operation is
typically used by a programmer to identify the correct
algorithmfortheSST29EE010A/29LE010A/29VE010A.
Usersmaywishtousethesoftwareproductidentification
operation to identify the part (i.e. using the device code)
when using multiple manufacturers in the same socket.
For details, see Table 3 for hardware operation or Table
4forsoftwareoperation,Figure9forthesoftwareIDentry
and read timing diagram and Figure 16 for the ID entry
command sequence flowchart. The manufacturer and
device codes are the same for both operations.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Byte
Data
BF H
22 H
23 H
Manufacturer’s Code
0000 H
SST29EE010A Device Code 0001 H
SST29LE010A Device Code 0001 H
SST29VE010A Device Code 0001 H
23 H
303 PGM T1.1
FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010A/29LE010A/29VE010A
1,048,576 Bit
EEPROM
Cell Array
X-Decoder
A
- A
0
16
Address Buffer & Latches
Control Logic
Y-Decoder and Page Latches
I/O Buffers and Data Latches
CE#
OE#
WE#
DQ - DQ
7
0
303 ILL B1.0
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
4
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
2
A8
3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1
A13
A14
NC
4
5
Standard Pinout
Top View
6
WE#
7
V
8
CC
2
NC
A16
A15
A12
A7
9
V
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
3
A6
A1
A5
A2
A4
A3
4
303 ILL F01.0
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
5
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A15
A12
A7
V
CC
WE#
NC
6
2
3
4
3
2
1
32 31 30
5
29
A7
A6
A14
A13
A8
4
A14
A13
A8
6
28
27
26
25
24
23
22
21
5
7
32-Pin
PDIP
7
6
A5
A6
7
A5
A9
8
A4
A9
32-Lead PLCC
Top View
8
A4
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
9
A3
A11
OE#
A10
CE#
DQ7
8
9
A3
10
11
12
13
A2
10
11
12
13
14
15
16
A2
A1
A1
A0
A0
9
DQ0
DQ0
DQ1
DQ2
14 15 16 17 18 19 20
V
SS
10
11
12
13
14
15
16
303 ILL F02.0
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A16-A7
Row Address Inputs
To provide memory addresses. Row addresses define a page for a
write cycle.
A6-A0
Column Address
Inputs
Column Addresses are toggled to load page data.
DQ7-DQ0
Data Input/output
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE#
OE#
WE#
Vcc
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations
To provide 5-volt supply (± 10%) for the SST29EE010A, 3-volt supply
(3.0-3.6V) for the SST29LE010A and 2.7-volt supply (2.7-3.6V) for the
SST29VE010A
Vss
NC
Ground
No Connection
Unconnected pins.
303 PGM T2.0
303-01 2/99
© 1999 Silicon Storage Technology, Inc.
5
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
VIL
VIL
VIH
X
OE#
VIL
VIH
X
WE#
VIH
VIL
X
DQ
Address
Read
DOUT
AIN
Page Write
DIN
AIN, See Table 4
Standby
High Z
High Z/ DOUT
High Z/ DOUT
DIN
X
Write Inhibit
Write Inhibit
Software Chip Erase
Product Identification
Hardware Mode
VIL
X
X
X
X
VIH
VIL
X
VIL
VIH
AIN, See Table 4
VIL
VIL
VIH
Manufacturer Code (BF)
A16 - A1 = VIL, A9 = VH, A0 = VIL
Device Code (see notes) A16 - A1 = VIL, A9 = VH, A0= VIH
Software Mode
VIL
VIL
VIH
VIH
VIL
VIL
See Table 4
See Table 4
SDP Enable Mode
303 PGM T3.0
TABLE 4: SOFTWARE COMMAND CODES
Command
Sequence
1st Bus
Write Cycle
Addr(1) Data Addr(1) Data
2nd Bus
Write Cycle
3rd Bus
Write Cycle
Addr(1) Data Addr(1) Data
4th Bus
Write Cycle
5th Bus
Write Cycle
Addr(1) Data Addr(1) Data
6th Bus
Write Cycle
Page Write
5555H AAH
5555H AAH
2AAAH 55H
2AAAH 55H
5555H A0H
5555H 80H
Addr(2) Data
Software Chip
Erase
5555H AAH
2AAAH 55H 5555H 10H
Software ID Entry 5555H AAH
2AAAH 55H
2AAAH 55H
2AAAH 55H
5555H 90H
5555H F0H
5555H 80H
Software ID Exit 5555H AAH
Alternate Software 5555H AAH
ID Entry(3)
5555H AAH
2AAAH 55H 5555H 60H
303 PGM T4.0
(1)
Notes:
Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”.
Page Write consists of loading up to 128 bytes (A6 - A0).
Alternate six-byte software Product-ID Command Code
The software Chip Erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
(2)
(3)
(4)
Notes for Software Product ID Command Code:
1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0,
SST29EE010A Device Code = 22H, is read with A0 = 1.
SST29LE010A/29VE010A Device Code = 23H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
3. This device supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code
sequence. For new designs, SST recommends the three-byte command code sequence be used.
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
6
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
1
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
2
3
4
Output Short Circuit Current(1) ....................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
5
6
SST29EE010A OPERATING RANGE
AC CONDITIONS OF TEST
Range
Ambient Temp
0°C to +70°C
VCC
Input Rise/Fall Time......... 10 ns
Output Load..................... 1 TTL Gate and CL = 100 pF
See Figures 12 and 13
Commercial
Industrial
5V±10%
5V±10%
7
-40°C to +85°C
SST29LE010A OPERATING RANGE
8
Range
Ambient Temp
0°C to +70°C
VCC
Commercial
Industrial
3.0V to 3.6V
3.0V to 3.6V
9
-40°C to +85°C
SST29VE010A OPERATING RANGE
10
11
12
13
14
15
16
Range
Ambient Temp
0°C to +70°C
VCC
Commercial
Industrial
2.7V to 3.6V
2.7V to 3.6V
-40°C to +85°C
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
7
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
TABLE 5: SST29EE010A DC OPERATING CHARACTERISTICS VCC = 5V±10%
Limits
Max
Symbol Parameter
Min
Units
Test Conditions
ICC
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read
30
mA
Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write
50
3
mA
mA
CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
CE#=OE#=WE#=VIH, VCC =VCC Max.
ISB1
ISB2
Standby VCC Current
(TTL input)
Standby VCC Current
(CMOS input)
50
µA
CE#=OE#=WE#=VCC -0.3V.
VCC = VCC Max.
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN =GND to VCC, VCC = VCC Max.
VOUT =GND to VCC, VCC = VCC Max.
VCC = VCC Min.
ILO
VIL
VIH
VOL
VOH
VH
IH
10
0.8
Input High Voltage
2.0
V
VCC = VCC Max.
Output Low Voltage
Output High Voltage
Supervoltage for A9
0.4
V
IOL = 2.1 mA, VCC = VCC Min.
IOH = -400µA, VCC = VCC Min.
CE# = OE# =VIL, WE# = VIH
2.4
V
11.6
12.4
100
V
Supervoltage Current
for A9
µA
CE# = OE# = VIL, WE# = VIH,
A9 = VH Max.
303 PGM T5.1
TABLE 6: SST29LE010A/29VE010A DC OPERATING CHARACTERISTICS VCC = 3.0-3.6 FOR SST29LE010A,
VCC = 2.7-3.6 FOR SST29VE010A
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
ICC
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read
12
mA
Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write
15
1
mA
mA
CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
CE#=OE#=WE#=VIH, VCC =VCC Max.
ISB1
ISB2
Standby VCC Current
(TTL input)
Standby VCC Current
(CMOS input)
15
µA
CE#=OE#=WE#=VCC -0.3V.
VCC = VCC Max.
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN =GND to VCC, VCC = VCC Max.
VOUT =GND to VCC, VCC = VCC Max.
VCC = VCC Min.
ILO
VIL
VIH
VOL
VOH
VH
IH
10
0.8
Input High Voltage
2.0
V
VCC = VCC Max.
Output Low Voltage
Output High Voltage
Supervoltage for A9
0.4
V
IOL = 100 µA, VCC = VCC Min.
IOH = -100 µA, VCC = VCC Min.
CE# = OE# =VIL, WE# = VIH
2.4
V
11.6
12.4
100
V
Supervoltage Current
for A9
µA
CE# = OE# = VIL, WE# = VIH,
A9 = VH Max.
303 PGM T6.1
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
8
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
TABLE 7: POWER-UP TIMINGS
Symbol
Parameter
Maximum
Units
µs
(1)
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
5
1
(1)
TPU-WRITE
ms
303 PGM T7.0
2
TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
3
(1)
CI/O
I/O Pin Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6 pF
303 PGM T8.0
4
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
5
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Cycles
Years
Volts
Test Method
6
NEND
Endurance
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
(1)
TDR
Data Retention
7
(1)
VZAP_HBM
ESD Susceptibility
Human Body Model
2000
(1)
VZAP_MM
ESD Susceptibility
Machine Model
200
100
Volts
mA
JEDEC Standard A115
JEDEC Standard 78
8
(1)
ILTH
Latch Up
303 PGM T9.2
9
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
10
11
12
13
14
15
16
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
9
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
AC CHARACTERISTICS
TABLE 10: SST29EE010A READ CYCLE TIMING PARAMETERS
SST29EE010A-90 SST29EE010A-120
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle time
90
120
TCE
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
90
90
40
120
120
50
ns
TAA
ns
TOE
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
(1)
TCHZ
30
30
30
30
ns
(1)
TOHZ
ns
(1)
TOH
Output Hold from Address
Change
0
0
ns
303 PGM T10.0
TABLE 11: SST29LE010A READ CYCLE TIMING PARAMETERS
SST29LE010A-150 SST29LE010A-200
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
Read Cycle time
150
200
ns
TCE
Chip Enable Access Time
Address Access Time
150
150
60
200
200
100
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
(1)
TCHZ
30
30
50
50
ns
ns
(1)
TOHZ
(1)
TOH
0
0
ns
303 PGM T11.0
TABLE 12: SST29VE010A READ CYCLE TIMING PARAMETERS
SST29VE010A-200 SST29VE010A-250
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
Read Cycle time
200
250
ns
TCE
Chip Enable Access Time
Address Access Time
200
200
100
250
250
120
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
(1)
TCHZ
50
50
50
50
ns
ns
(1)
TOHZ
(1)
TOH
0
0
ns
303 PGM T12.0
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
10
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
TABLE 13: PAGE WRITE CYCLE TIMING PARAMETERS
SST29EE010A
SST29LE/VE010A
Symbol
TWC
TAS
Parameter
Min
Max
Min
Max
Units
ms
ns
1
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
10
10
0
50
0
0
70
0
2
TAH
ns
TCS
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
ns
TCH
0
0
ns
3
TOES
TOEH
TCP
0
0
ns
0
0
ns
4
70
70
35
0
120
120
50
0
ns
TWP
TDS
WE# Pulse Width
ns
Data Setup Time
ns
5
TDH
Data Hold Time
ns
(1)
TBLC
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
Software Chip Erase
0.05
200
100
0.05
200
100
µs
(1)
6
TBLCO
µs
TIDA
10
20
10
20
µs
TSCE
ms
7
303 PGM T13.1
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
8
9
10
11
12
13
14
15
16
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
11
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
T
T
RC
AA
ADDRESS A
16-0
CE#
T
CE
T
OE
OE#
T
T
OHZ
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DATA VALID
DATA VALID
DQ
7-0
303 ILL F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
T
AH
Page Write
T
AS
ADDRESS A
5555 2AAA 5555
16-0
CE#
T
T
CS
CH
T
T
OEH
OES
OE#
WE#
T
WP
T
BLCO
T
BLC
T
DH
DQ
AA
55
A0
DATA VALID
7-0
T
WC
T
DS
SW0
SW1
SW2
BYTE 0
BYTE 1
BYTE 127
303 ILL F04.0
FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
12
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
T
AH
Page Write
1
T
AS
ADDRESS A
5555 2AAA 5555
16-0
CE#
2
T
CP
T
T
BLCO
BLC
3
T
T
OEH
OES
OE#
WE#
4
T
T
CS
CH
5
T
DH
DQ
AA
55
A0
DATA VALID
7-0
T
6
WC
T
DS
SW0
SW1
SW2
BYTE 0
BYTE 1
BYTE 127
303 ILL F05.0
7
FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
8
9
10
11
12
13
14
15
16
ADDRESS A
16-0
T
CE
CE#
T
OES
T
OEH
OE#
T
OE
WE#
DQ
7
D
D
D#
D#
T
+ T
BLCO
WC
303 ILL F06.0
FIGURE 6: DATA# POLLING TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
13
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
ADDRESS A
16-0
CE#
OE#
T
T
CE
T
OEH
T
OES
OE
WE#
DQ
6
T
+ T
BLCO
WC
TWO READ CYCLES
WITH SAME OUTPUTS
303 ILL F07.0
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
Six-Byte Code for Software Chip Erase
T
SCE
ADDRESS A
5555
2AAA
5555
5555
2AAA
5555
14-0
DQ
AA
55
80
AA
55
10
7-0
CE#
OE#
WE#
T
BLCO
T
WP
T
BLC
SW0
SW1
SW2
SW3
SW4
SW5
303 ILL F09.0
FIGURE 8: SOFTWARE CHIP ERASE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
14
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Three-Byte Sequence
for Software ID Entry
1
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
2
T
AA
DQ
AA
55
90
BF
DEVICE CODE
7-0
3
T
IDA
CE#
4
OE#
WE#
5
T
WP
6
T
BLC
DEVICE CODE = 22 for SST29EE010A
= 23 for SST29LE010A/29VE010A
SW0
SW1
SW2
7
303 ILL F10.1
FIGURE 9: SOFTWARE ID ENTRY AND READ
8
9
Three-Byte Sequence
for Software ID Exit and Reset
10
11
12
13
14
15
16
ADDRESS A
5555
2AAA
5555
14-0
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
BLC
SW0
SW1
SW2
303 ILL F11.0
FIGURE 10: SOFTWARE ID EXIT AND RESET
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
15
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
303 ILL F12.1
AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT–VHIGH Test
V
LT–VLOW Test
VIHT–VINPUT HIGH Test
ILT–VINPUT LOW Test
V
FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE
V
CC
TO TESTER
R
L HIGH
TO DUT
C
L
R
L LOW
303 ILL F13.0
FIGURE 12: A TEST LOAD EXAMPLE
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
16
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Start
1
Page Write
See Figure 15
2
Command
3
Set Page
Address
4
5
Set Byte
Address = 0
6
Load Byte
Data
7
8
Increment
Byte Address
By 1
9
Byte
No
10
11
12
13
14
15
16
Address =
128?
Yes
Wait T
BLCO
Wait for end of
Write (T
,
WC
Data# Polling bit
or Toggle bit
operation)
Write
Completed
303 ILL F14.0
FIGURE 13: WRITE ALGORITHM
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
17
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Internal Timer
Toggle Bit
Data# Polling
Page Write
Initiated
Page Write
Initiated
Page Write
Initiated
Read DQ
(Data for last
byte loaded)
7
Read a byte
from page
Wait T
WC
Write
Completed
No
Read same
byte
Is DQ =
7
true data?
Yes
Write
Completed
No
Does DQ
match?
6
Yes
Write
Completed
303 ILL F15.0
FIGURE 14: WAIT OPTIONS
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
18
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Command Sequence
1
Write data: AA
Address: 5555
2
3
Write data: 55
Address: 2AAA
4
Write data: A0
Address: 5555
5
6
Load 0 to
128 Bytes of
page data
Page Load Operation
7
8
Wait T
BLCO
9
Wait T
WC
10
11
12
13
14
15
16
Device Written
303 ILL F16.1
FIGURE 15: PAGE WRITE FLOWCHART
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
19
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: AA
Address: 5555
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 55
Address: 2AAA
Write data: 90
Address: 5555
Write data: F0
Address: 5555
Pause 10 µs
Pause 10 µs
Return to normal
operation
Read Software ID
303 ILL F17.0
FIGURE 16: SOFTWARE PRODUCT COMMAND FLOWCHARTS
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
20
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Software Chip Erase
Command Sequence
1
Write data: AA
Address: 5555
2
3
Write data: 55
Address: 2AAA
4
Write data: 80
Address: 5555
5
6
Write data: AA
Address: 5555
7
8
Write data: 55
Address: 2AAA
9
Write data: 10
Address: 5555
10
11
12
13
14
15
16
Wait T
SCE
Chip Erase
to FFH
303 ILL F18.0
FIGURE 17: SOFTWARE CHIP ERASE COMMAND CODES
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
21
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1 Suffix2
XX XX
SST29XE010A - XXX
-
-
Package Modifier
H = 32 leads
Numeric = Die modifier
Package Type
P = PDIP
N = PLCC
E = TSOP (die up) 8mm x 20mm
W = TSOP (die up) 8mm x 14mm
U = Unencapsulated die
Operating Temperature
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
250 = 250 ns
200 = 200 ns
150 = 150 ns
120 = 120 ns
90 = 90 ns
Version Code
Voltage
E = 5.0V-only
L = 3.0 - 3.6V
V = 2.7 - 3.6V
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
22
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
SST29EE010A Valid combinations
SST29EE010A- 90-4C- EH
SST29EE010A-120-4C- EH
SST29EE010A- 90-4C- NH
SST29EE010A-120-4C- NH
SST29EE010A- 90-4C- PH
SST29EE010A-120-4C- PH
1
SST29EE010A- 90-4C- WH
SST29EE010A-120-4C- WH
2
SST29EE010A- 90-4I-EH
SST29EE010A-120-4I-EH
SST29EE010A- 90-4I-NH
SST29EE010A-120-4I-NH
3
SST29EE010A-120-4C-U2
4
SST29LE010A Valid combinations
SST29LE010A-150-4C- EH
SST29LE010A-200-4C- EH
SST29LE010A-150-4C- NH
SST29LE010A-200-4C- NH
SST29LE010A-150-4C- WH
SST29LE010A-200-4C- WH
5
SST29LE010A-150-4I-EH
SST29LE010A-200-4C-U2
SST29LE010A-150-4I-NH
6
SST29VE010A Valid combinations
7
SST29VE010A-200-4C- EH
SST29VE010A-250-4C- EH
SST29VE010A-200-4C- NH
SST29VE010A-250-4C- NH
SST29VE010A-200-4C-WH
SST29VE010A-250-4C-WH
8
SST29VE010A-200-4I-EH
SST29VE010A-250-4C-U2
SST29VE010A-200-4I-NH
9
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
10
11
12
13
14
15
16
Note:
The software chip erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
23
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
PACKAGING DIAGRAMS
pin 1 index
1
C
L
.600
.625
32
.530
.550
1.645
1.655
.065
.075
7˚
4 PLCS.
.170
.200
Base Plane
Seating Plane
.015
.050
0˚
15˚
.008
.012
.120
.150
.070
.080
.045
.065
.016
.022
.100 BSC
.600 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.1
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.485
.495
.447
.106
.112
Optional Pin #1
.453
Identifier
.042
.023
.029
.030
.040
.020 R.
MAX.
x 30˚
R.
.048
2
1
32
.042
.048
.013
.021
.400 .490
BSC .530
.585
.595
.547
.553
.026
.032
.050
BSC.
.015 Min.
.075
.095
.050
BSC.
.026
.032
.125
.140
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
32.PLCC.NH-ILL.1
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
24
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
1.05
0.95
PIN # 1 IDENTIFIER
.50
BSC
1
2
.270
.170
8.10
7.90
3
4
0.15
0.05
12.50
12.30
5
0.70
0.50
6
14.20
13.80
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
7
32.TSOP-WH-ILL.2
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: WH
8
9
1.05
0.95
PIN # 1 IDENTIFIER
.50
BSC
10
11
12
13
14
15
16
.270
.170
8.10
7.90
0.15
0.05
18.50
18.30
0.70
0.50
20.20
19.80
Note:
1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
32.TSOP-EH-ILL.2
3. Coplanarity: 0.1 (±.05) mm.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: EH
© 1999 Silicon Storage Technology, Inc.
303-01 2/99
25
1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
SST Area Offices
International Sales Representatives & Distributors
Customer Service
(408) 523-7754
(408) 523-7661
(727) 771-8819
(978) 356-3845
(941) 505-8893
(408) 523-7762
(81)45-471-1851
(44)1932-230555
(45) 3833-5000
Australia ACD
(61) 3-762 7644
(32) 1540-0080
Northwest USA, Rocky Mtns. & West Canada
Central & Southwest USA
East USA & East Canada
North America - Distribution
Asia Pacific
East Asia
Europe
Northern Europe
Belgium Memec Benelux
China/Hong Kong
Actron Technology Co., Ltd. (HQ) Hong Kong
Actron Technology Co., Ltd. - Shanghai
Actron Technology Co., Ltd. - Shenzhen
Actron Technology Co., Ltd. - Chengdu
Actron Technology Co., Ltd. - Beijing
Actron Technology Co., Ltd. - Wuhan
Actron Technology Co., Ltd. - Xian
(852) 2727-3978
(86)21-6482-8021
(86)755-376-2763
(86)28-553-2896
(86)10-6261-0042
(86)27-8788-7226
(86)29-831-4585
North American Sales Representatives
MetaTech Limited (HQ) - Hong Kong
MetaTech Limited - Beijing
MetaTech Limited - Shanghai
MetaTech Limited - Chengdu
MetaTech Limited - Fuzhou
MetaTech Limited - Shenzhen
(852) 2421-2379
(86)10-6858-2188
(86)21-6485-7530
(86)28-5577-415
(86)591-378-1033
(86)755-321-9726
Alabama M-Squared, Inc. - Huntsville
Arizona QuadRep, Inc.
(205) 830-0498
(602) 839-2102
California
Costar - Northern
Falcon Sales & Technology - San Marcos
Westar Rep Company, Inc. - Calabasas
Westar Rep Company, Inc. - Irvine
(408) 946-9339
(760) 591-0504
(818) 880-0594
(949) 453-7900
Serial System Ltd. - Hong Kong
Serial System Ltd. - Chengdu
Serial System Ltd. - Shanghai
Serial System Ltd. - Shenzhen
(852) 2950-0820
(86)28-524-0208
(86)21-6473-2080
(86)755-212-9076
Colorado Lange Sales, Inc.
(303) 795-3600
Florida
Denmark C-88 AS
France
(45) 7010-4888
M-Squared, Inc. - Clearwater
M-Squared, Inc. - Coral Springs
M-Squared, Inc. - Longwood
(727) 669-2408
(954) 753-5314
(407) 682-6662
A2M - Bron
(33) 4 72 37 0414
(33) 1 46 23 7900
A2M - Sevres
Georgia M-Squared, Inc. - Atlanta
(770) 447-6124
Germany
Illinois
Endrich Bauelemente
Vertriebs GMBH - Bramstedt
Oasis Sales Corporation - Northern
Rush & West Associates - Southern
(847) 640-1850
(314) 965-3322
(49)4192-897910
(49) 7452-60070
Endrich Bauelemente
Vertriebs GMBH - Nagold
Indiana Applied Data Management
Iowa Rush & West Associates
(317) 257-8949
(319) 398-9679
(913) 764-2700
(301) 663-4159
(978) 851-5400
(734) 741-9292
(612) 699-0200
(314) 965-3322
India
Kansas Rush & West Associates
Maryland Nexus Technology Sales
Massachusetts A/D Sales
Team Technology - Bangalore
Team Technology - Hyderabad
Team Technology - New Delhi
(91)80-526-1102
(91) 40-231130
(91)11-220-5624
Michigan Applied Data Management
Minnesota Cahill, Schmitz & Cahill
Missouri Rush & West Associates
Ireland Curragh Technology
Israel Spectec Electronics
Italy Carlo Gavazzi Cefra SpA
(353) 61 316116
(972) 3-6498404
(39) 2-424-1471
North Carolina
Japan
M-Squared, Inc. - Charlotte
M-Squared, Inc. - Raleigh
(704) 522-1150
(919) 848-4300
Asahi Electronics Co., Ltd. - Tokyo
Asahi Electronics Co., Ltd. - Kitakyushu
(81)3-3350-5418
(81)93-511-6471
New Jersey Nexus Technology Sales
New Mexico QuadRep, Inc.
(201) 947-0151
(505) 332-2417
Microtek, Inc. - Osaka
Microtek, Inc. - Tokyo
(81)6-6263-5080
(81)3-5300-5515
Ryoden Trading Co., Ltd. - Osaka
Ryoden Trading Co., Ltd. - Tokyo
(81)6-6399-3443
(81)3-5396-6218
New York
Nexus Technology Sales
Reagan/Compar - Endwell
Reagan/Compar - E. Rochester
(516) 843-0100
(607) 754-2171
(716) 218-4370
Silicon Technology Co., Ltd.
(81)3-3795-6461
(82) 2-832-8881
Korea Bigshine Korea Co., Ltd.
Ohio
Malaysia
MetaTech (M) SDN BHD
Applied Data Management - Cincinnati
Applied Data Management - Cleveland
(513) 579-8108
(440) 946-6812
(60)4-658-4276
Serial System SDN BHD
Serial System - Kuala Lumpur
(60) 4-657-0204
(60) 3-737-1243
Oregon Thorson Pacific, Inc.
(503) 293-9001
(215) 675-9600
Pennsylvania Nexus Technology Sales
Netherlands Memec Benelux
(31)40-265-9399
Texas
Singapore
MetaTech (S) Pte Ltd.
Technical Marketing, Inc. - Carrollton
Technical Marketing, Inc. - Houston
Technical Marketing, Inc. - Austin
(972) 387-3601
(713) 783-4497
(512) 343-6976
(65) 748-4844
Serial System Ltd. (HQ)
(65) 280-0200
South Africa KH Distributors
Spain Tekelec Espana S.A.
Switzerland Leading Technologies
(27) 11 845-5011
(34) 91 371-7768
(41)27-721-7440/43
Utah Lange Sales, Inc.
(801) 487-0843
(425) 603-9393
(414) 782-6660
Washington Thorson Pacific, Inc.
Wisconsin Oasis Sales Corporation
Taiwan, R.O.C.
Canada
GCH-Sun Systems Co., Ltd. (GSS)
PCT Limited
Tonsam Corporation
(886)2-2555-0880
(886)2-2698-0098
(886)2-2651-0011
Electronics Sales Professionals - Ottawa
Electronics Sales Professionals - Toronto
Electronics Sales Professionals - Montreal
(613) 828-6881
(905) 856-8448
(514) 388-6596
United Kingdom Ambar Components, Ltd.
(44)1296-397396
Thorson Pacific, Inc. - B.C.
(604) 294-3999
Revised 4-7-99
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
303-01 2/99
相关型号：
©2020 ICPDF网 联系我们和版权申明