SST32HF402-70-4C-L3KE [SST]
Multi-Purpose Flash (MPF) + SRAM ComboMemory; 多用途闪存（ MPF） + SRAM ComboMemory
| 型号： | SST32HF402-70-4C-L3KE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| 文件： | 总30页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
SST32HF202 / 402 / 8022Mb Flash + 2Mb SRAM, 4Mb Flash + 2Mb SRAM, 8Mb Flash + 2Mb SRAM
(x16) MCP ComboMemory
Data Sheet
FEATURES:
•
MPF + SRAM ComboMemory
•
•
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
– SST32HF202: 128K x16 Flash + 128K x16 SRAM
– SST32HF402: 256K x16 Flash + 128K x16 SRAM
– SST32HF802: 512K x16 Flash + 128K x16 SRAM
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
– Read from or write to SRAM while
Erase/Program Flash
SST32HF202: 2 seconds (typical)
SST32HF402: 4 seconds (typical)
SST32HF802: 8 seconds (typical)
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Flash Automatic Erase and Program Timing
– Internal VPP Generation
Low Power Consumption:
Flash End-of-Write Detection
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 20 µA (typical)
– Toggle Bit
– Data# Polling
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Conforms to Flash pinout
Packages Available
•
•
Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
Fast Read Access Times:
– 48-ball LFBGA (6mm x 8mm)
– 48-ball LBGA (10mm x 12mm)
(SST32HF802 only)
– Flash: 70 ns
– SRAM: 70 ns
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF202/402/802 ComboMemory devices inte-
grate a 128K x16, 256K x16, 512K x16 CMOS flash mem-
ory bank with a 128K x16 CMOS SRAM memory bank in a
Multi-Chip Package (MCP), manufactured with SST’s pro-
prietary, high performance SuperFlash technology.
memory banks share common address lines, data lines,
WE# and OE#. The memory bank selection is done by
memory bank enable signals. The SRAM bank enable sig-
nal, BES# selects the SRAM bank. The flash memory
bank enable signal, BEF# selects the flash memory bank.
The WE# signal has to be used with Software Data Protec-
tion (SDP) command sequence when controlling the Erase
and Program operations in the flash memory bank. The
SDP command sequence protects the data stored in the
flash memory bank from accidental alteration.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 2 seconds for the
SST32HF202, 4 seconds for the SST32HF402, and 8 sec-
onds for the SST32HF802, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. To protect against inadvertent
flash write, the SST32HF202/402/802 devices contain on-
chip hardware and software data protection schemes. The
SST32HF202/402/802 devices offer a guaranteed endur-
ance of 10,000 cycles. Data retention is rated at greater
than 100 years.
The SST32HF202/402/802 provide the added functionality
of being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HF202/402/802 devices consist of two inde-
pendent memory banks with respective bank enable sig-
nals. The Flash and SRAM memory banks are
superimposed in the same memory address space. Both
©2005 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71209-06-000
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5/05
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
The SST32HF202/402/802 devices are suited for applica-
tions that use both flash memory and SRAM memory to
store code or data. For systems requiring low power and
small form factor, the SST32HF202/402/802 devices signif-
icantly improve performance and reliability, while lowering
power consumption, when compared with multiple chip
solutions. The SST32HF202/402/802 inherently use less
energy during erase and program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies.
SRAM Read
The SRAM Read operation of the SST32HF202/402/802 is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high. See
Figure 3 for the Read cycle timing diagram.
SRAM Write
The SRAM Write operation of the SST32HF202/402/802 is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE#, whichever occurs first. The
write time is measured from the last falling edge to the first
rising edge of BES# or WE#. See Figures 4 and 5 for the
Write cycle timing diagrams.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Flash Operation
With BEF# active, the SST32HF202 operates as 128K x16
flash memory, the SST32HF402 operates as 256K x16
flash memory, and the SST32HF802 operates as 512K
x16 flash memory. The flash memory bank is read using
the common address lines, data lines, WE# and OE#.
Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and during the
internally-timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. When
BES# is low, the SRAM Bank is activated for Read and
Write operation. When BEF# is low the flash bank is acti-
vated for Read, Program or Erase operation. BES# and
BEF# cannot be at low level at the same time. If BES# and
BEF# are both asserted to low level bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by SRAM
Bank and flash bank which minimizes power consumption
and loading. The device goes into standby when both bank
enables are high.
Flash Read
The Read operation of the SST32HF202/402/802 devices
is controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The data
bus is in high impedance state when OE# is high. Refer to
Figure 6 for further details.
SRAM Operation
With BES# low and BEF# high, the SST32HF202/402/802
operate as 128K x16 CMOS SRAM, with fully static opera-
tion requiring no external clocks or timing strobes. The
SST32HF202/402/802 SRAM is mapped into the first 128
KWord address space. When BES# and BEF# are high,
both memory banks are deselected and the device enters
standby mode. Read and Write cycle times are equal. The
control signals UBS# and LBS# provide access to the
upper data byte and lower data byte. See Table 3 for SRAM
Read and Write data byte control modes of operation.
©2005 Silicon Storage Technology, Inc.
S71209-06-000
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
SST32HF202, A17-A15, for SST32HF402, and A18-A15, for
SST32HF802, are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 12
and 13 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST32HF202/402/
802. SDP commands are loaded to the flash memory bank
using standard microprocessor Write sequences. A com-
mand is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
Flash Chip-Erase Operation
Flash Word-Program Operation
The SST32HF202/402/802 provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
The flash memory bank of the SST32HF202/402/802
devices is programmed on a word-by-word basis. Before
Program operations, the memory must be erased first. The
Program operation consists of three steps.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 10 for timing diagram,
and Figure 21 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load word address
and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either BEF# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either BEF# or WE#, whichever occurs first. The
third step is the internal Program operation which is initiated
after the rising edge of the fourth WE# or BEF#, whichever
occurs first.
The Program operation, once initiated, will be completed,
within 20 µs. See Figures 7 and 8 for WE# and BEF# con-
trolled Program operation timing diagrams and Figure 18 for
flowcharts. During the Program operation, the only valid
flash Read operations are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any SDP commands loaded dur-
ing the internal Program operation will be ignored.
Write Operation Status Detection
The SST32HF202/402/802 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF202/402/802 offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle.
The address lines A16-A11, for SST32HF202, A17-A11, for
SST32HF402, and A18-A11, for SST32HF802, are used to
determine the sector address. The Block-Erase operation
is initiated by executing a six-byte command sequence with
Block-Erase command (50H) and block address (BA) in
the last bus cycle. The address lines A16-A15, for
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
3
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Flash Data# Polling (DQ7)
Flash Software Data Protection (SDP)
When the SST32HF202/402/802 flash memory banks are
in the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles, after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will pro-
duce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 9 for Data# Polling timing diagram and Figure
19 for a flowchart.
The SST32HF202/402/802 provide the JEDEC approved
software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF202/402/802 devices are shipped with the soft-
ware data protection permanently enabled. See Table 4 for
the specific software command codes. During SDP com-
mand sequence, invalid SDP commands will abort the
device to the Read mode, within Read cycle time (TRC).
Concurrent Read and Write Operations
The SST32HF202/402/802 provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the Flash. This allows
data alteration code to be executed from SRAM, while alter-
ing the data in Flash. The following table lists all valid states.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
Sector- or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 10 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
CONCURRENT READ/WRITE STATE TABLE
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Memory Data Protection
The SST32HF202/402/802 flash memory bank provides
both hardware and software features to protect nonvolatile
data from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
©2005 Silicon Storage Technology, Inc.
S71209-06-000
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4
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Product Identification
Product Identification Mode Exit/Reset
The Product Identification mode identifies the devices as
the SST32HF202/402/802 and manufacturer as SST. This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, applica-
tion of high voltage to pin A9 may damage this device.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 14 for the
software ID entry and Read timing diagram, and Figure 20
for the ID entry command sequence flowchart.
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 15 for timing waveform and
Figure 20 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
00BFH
SST32HF202
SST32HF402
SST32HF802
0001H
0001H
0001H
2789H
2780H
2781H
T1.2 1209
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
UBS#
LBS#
BES#
BEF#
OE#
Control Logic
DQ - DQ
15
A
MS
-A
0
8
I/O Buffers
DQ - DQ
7
0
WE#
Address Buffers
& Latches
SuperFlash
Memory
1209 B1.0
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
5
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TOP VIEW (balls facing down)
SST32HF202
TOP VIEW (balls facing down)
SST32HF402
6
5
4
3
2
1
6
V
A13 A12 A14 A15 A16 UBS# DQ15
V
SS
SS
A13 A12 A14 A15 A16 UBS# DQ15
5
4
3
2
1
DQ6
A9
A8
A10 A11 DQ7 DQ14 DQ13
DQ6
DQ4
DQ3
DQ1
A9
A8
A10 A11 DQ7 DQ14 DQ13
DQ4
DQ3
DQ1
WE# NC LBS# NC DQ5 DQ12
V
WE# NC LBS# NC DQ5 DQ12
V
DD
DD
BES# NC
NC
A6
A2
NC DQ2 DQ10 DQ11
A5 DQ0 DQ8 DQ9
BES# NC
NC
A6
A2
NC DQ2 DQ10 DQ11
A7
A3
NC
A4
A7
A3
A17
A4
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
V
A1
A0 BEF# OE#
V
SS
SS
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
TOP VIEW (balls facing down)
SST32HF802
6
V
A13 A12 A14 A15 A16 UBS# DQ15
SS
5
4
3
2
1
DQ6
DQ4
DQ3
DQ1
A9
WE# NC LBS# NC DQ5 DQ12
BES# NC A18 NC DQ2 DQ10 DQ11
A8
A10 A11 DQ7 DQ14 DQ13
V
DD
A7
A3
A17
A4
A6
A2
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
V
SS
A
B
C
D
E
F
G
H
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
6
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TOP VIEW (balls facing down)
SST32HF802
6
BES#
V
DQ1 A1
A2
A3
A4
A7
NC
NC A14
A15
SS
A9
5
4
3
2
1
A10 DQ5 DQ2 A0
OE# DQ7 DQ4 DQ0
A6 A18
NC
A11 A8
A5 DQ8 DQ3 DQ12 A12 LBS#
A13 A17 UBS# BEF# DQ10
V
DQ6 DQ15
DDF
WE#
V
A16
V
DQ9 DQ11 DQ13 DQ14
DDS
SS
A B C D E F G H
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM)
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide flash addresses, A16-A0 for 2M, A17-A0 for 4M, and A18-A0 for 8M.
To provide SRAM addresses, A16-A0 for 2M.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
OE#
WE#
VDD
SRAM Memory Bank Enable
Flash Memory Bank Enable
Output Enable
To activate the SRAM memory bank when BES# is low.
To activate the Flash memory bank when BEF# is low.
To gate the data output buffers.
Write Enable
To control the Write operations.
Power Supply
2.7-3.3V power supply (for L3K package only)
2.7-3.3V power supply to flash only
2
VDDF
Power Supply (Flash)
Power Supply (SRAM)
Ground
2
VDDS
2.7-3.3V power supply to SRAM only
VSS
UBS#
LBS#
NC
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
No Connection
To enable DQ15-DQ8
To enable DQ7-DQ0
Unconnected Pins
T2.4 1209
1. AMS = Most significant address
2. For SST32HF802 in the LBK package only
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
7
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
BES#1 BEF#1 OE# WE# UBS# LBS# DQ15 to DQ8 DQ7 to DQ0
Address
Not Allowed
Flash
VIL
VIL
X2
X
X
X
X
X
X
Read
VIH
VIH
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
X
X
X
X
X
X
DOUT
DIN
X
DOUT
DIN
X
AIN
AIN
Program
Erase
Sector or Block address,
XXH for Chip-Erase
SRAM
Read
VIL
VIL
VIL
VIL
VIL
VIL
VIHC
X
VIH
VIH
VIH
VIH
VIH
VIH
VIHC
X
VIL
VIL
VIL
X
VIH
VIH
VIH
VIL
VIL
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
VIL
VIH
VIL
VIL
VIH
VIL
X
DOUT
DOUT
High Z
DIN
DOUT
High Z
DOUT
DIN
AIN
AIN
AIN
AIN
AIN
AIN
X
Write
X
DIN
High Z
DIN
X
High Z
High Z
Standby
X
High Z
Flash Write Inhibit
VIL
X
X
X
X
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
X
X
X
VIH
X
X
X
X
X
VIH
VIL
VIH
VIH
X
X
X
X
Output Disable
VIH
VIL
VIL
VIH
X
VIH
X
X
X
High Z
High Z
High Z
High Z
High Z
High Z
X
VIH
X
VIH
X
X
VIH
VIH
X
Product Identification
Software Mode
VIH
VIL
VIL
VIH
X
X
Manufacturer’s ID (00BFH)
Device ID3
AMSF4-A1=VIL, A0=VIH
(See Table 4)
T3.5 1209
1. Do not apply BES#=VIL and BEF#=VIL at the same time
2. X can be VIL or VIH, but no other value.
3. Device ID for: SST32HF202 = 2789H, SST32HF402 = 2780H, and SST32HF802 = 2781H
4. AMS = Most significant flash address
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
8
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data
Addr1
Data Addr1 Data Addr1 Data
Addr1
Data Addr1 Data
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
5555H AAH 2AAAH 55H 5555H A0H Data
WA2
3
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
3
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit
Software ID Exit
XXH
F0H
5555H AAH 2AAAH 55H 5555H F0H
T4.4 1209
1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.
2. WA = Program Word address
3. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A16 for SST32HF202, A17 for SST32HF402, and A18 for SST32HF802
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST32HF202 Device ID = 2789H, is read with A0 = 1,
SST32HF402 Device ID = 2780H, is read with A0 = 1
SST32HF802 Device ID = 2781H, is read with A0 = 1.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 16 and 17
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
9
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
IDD Power Supply Current
Min
Max Units Test Conditions
Address input=VILT/VIHT, at f=5 MHz,
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
BEF#=VIL, BES#=VIH
30
30
55
mA
mA
mA
SRAM
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
Concurrent Operation
Write
Flash
WE#=VIL
BEF#=VIL, BES#=VIH, OE#=VIH
30
30
mA
mA
SRAM
BEF#=VIH, BES#=VIL
ISB
Standby VDD Current
SST32HF202/402
30
40
1
µA
µA
µA
µA
V
VDD=VDD Max, BEF#=BES#=VIHC
SST32HF802
VDD=VDD Max, BEF#=BES#=VIHC
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
ILO
10
0.8
VIL
VIH
Input High Voltage
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
Output Low Voltage
Output High Voltage
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL=1 mA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
T5.7 1209
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
µs
µs
1
TPU-WRITE
100
T6.0 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
24 pF
12 pF
1
CIN
VIN = 0V
T7.0 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T8.0 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
10
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
AC CHARACTERISTICS
TABLE 9: SRAM READ CYCLE TIMING PARAMETERS
Symbol
TRCS
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TAAS
Address Access Time
70
70
35
70
ns
TBES
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
TOES
ns
TBYES
ns
1
TBLZS
0
0
0
ns
1
TOLZS
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
ns
1
TOHZS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
0
ns
1
TBYHZS
ns
TOHS
10
ns
T9.3 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
70
60
60
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
ns
30
ns
0
30
0
ns
ns
TDHS
Data Hold from Write Time
ns
T10.3 1209
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
11
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
ns
TRC
TBE
TAA
Read Cycle Time
70
Bank Enable Access Time
Address Access Time
70
70
35
ns
ns
TOE
TBLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
ns
TOLZ
TBHZ
ns
1
1
20
20
ns
TOHZ
ns
1
TOH
0
ns
T11.2 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
20
TAS
0
30
0
ns
TAH
ns
TBS
ns
TBH
0
ns
TOES
TOEH
TBPW
TWP
TWPH
TBPH
TDS
0
ns
10
40
40
30
30
30
0
ns
ns
ns
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
ns
ns
TDH
Data Hold Time
ns
TIDA
TSE
Software ID Access and Exit Time
Sector-Erase
150
25
ns
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
100
ms
T12.0 1209
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
12
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
T
RCS
ADDRESSES A
MSS-0
BES#
T
T
OHS
AAS
T
BES
T
T
BLZS
BHZS
T
OE#
OES
T
T
OLZS
OHZS
T
BYES
UBS#, LBS#
T
T
BYLZS
BYHZS
DQ
DATA VALID
15-0
1209 F02.0
Note: WE# remains High (V ) for the Read cycle
IH
A
= Most Significant SRAM Address
MSS
FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESSES A
MSS-0
WE#
T
ASTS
T
T
WPS
WRS
T
AWS
T
T
BWS
BES#
BYWS
UBS#, LBS#
T
OEWS
T
DHS
T
ODWS
T
DSS
NOTE 2
VALID DATA IN
NOTE 2
DQ
DQ
7-0
15-8,
1209 F03.1
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because D signals may be in the output state at this time, input signals of reverse polarity must not be applied.
IN
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
13
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
T
WCS
ADDRESSES A
MSS-0
WE#
T
T
WRS
WPS
T
BWS
BES#
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
DQ
DQ
7-0
15-8,
NOTE 2
NOTE 2
VALID DATA IN
1209 F04.0
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because D signals may be in the output state at this time, input signals of reverse polarity must not be applied.
IN
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
T
T
AA
RC
ADDRESSES A
MSF-0
BEF#
OE#
T
BE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
BHZ
T
OH
T
HIGH-Z
BLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1209 F05.0
A
= Most Significant Flash Address
MSF
FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
14
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
WE#
T
AH
T
DH
T
WP
T
T
AS
DS
T
WPH
OE#
T
CH
BEF#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1209 F06.0
A
= Most Significant Flash Address
MSF
Note: X can be V or V , but no other value
IL IH
FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
BEF#
T
AH
T
DH
T
CP
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1209 F07.0
A
= Most Significant Flash Address
MSF
Note: X can be V or V , but no other value
IL IH
FIGURE 8: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
15
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
ADDRESSES A
MSF-0
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
Data
Data#
Data#
Data
1209 F08.0
A
= Most Significant Flash Address
MSF
FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESSES A
MSF-0
T
BE
BEF#
OE#
T
OES
T
T
OE
OEH
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
A
= Most Significant Flash Address
MSF
1209 F09.0
FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
16
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
MSF-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
1209 F10.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 12)
X can be V or V , but no other value
IL
IH
A
= Most Significant Flash Address
MSF
FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
T
SE
SIX-WORD CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESSES A
MSF-0
BEF#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
1209 F11.0
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
X can be V or V , but no other value
IL
IH
SA = Sector Address
X
A
= Most Significant Flash Address
MSF
FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
17
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
T
BE
SIX-WORD CODE FOR BLOCK-ERASE
5555 5555 2AAA
5555
2AAA
BA
X
ADDRESSES A
MSF-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
1209 F12.1
Note: The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
X can be V or V , but no other value
IL
IH
BA = Block Address
X
A
= Most Significant Flash Address
MSF
FIGURE 13: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
DEVICE ID
MFG ID
1209 F13.4
Note: X can be V or V , but no other value
Device ID = 2789H for SST32HF202,
2780H for SST32HF402,
IL
IH
2781H for SST32HF802
FIGURE 14: SOFTWARE ID ENTRY AND READ
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
18
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
THREE-WORD SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
1209 F14.0
Note: X can be V or V , but no other value
IL IH
FIGURE 15: SOFTWARE ID EXIT AND RESET
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
19
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1209 F15.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 16: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1209 F16.0
FIGURE 17: A TEST LOAD EXAMPLE
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
20
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Start
Write data: XXAAH
Address: 5555H
Write data: XX55H
Address: 2AAAH
Write data: XXA0H
Address: 5555H
Write Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1209 F17.0
X can be V or V , but no other value.
IL
IH
FIGURE 18: WORD-PROGRAM ALGORITHM
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
21
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, or BE
No
Read same
word
Is DQ =
7
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1209 F18.0
FIGURE 19: WAIT OPTIONS
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
22
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: XXAAH
Address: 5555H
Write data: XXAAH
Address: 5555H
Write data: XXF0H
Address: XXXXH
Write data: XX55H
Address: 2AAAH
Write data: XX55H
Address: 2AAAH
Wait T
IDA
Write data: XX90H
Address: 5555H
Write data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
1209 F19.0
X can be V or V but no other value.
IH,
IL
FIGURE 20: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
23
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1209 F20.0
X can be V or V but no other value.
IH,
IL
FIGURE 21: ERASE COMMAND SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
24
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
1209 F21.0
FIGURE 22: CONCURRENT OPERATION FLOWCHART
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
25
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST32HFxxx
-
XXX
-
XX
-
XXXX
Package Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Package Type
L3 = LFBGA (6mm x 8mm x 1.4mm)
LB = LBGA (10mm x 12mm x 1.4mm)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
SRAM
2 = 2 Mbit SRAM
Density
20 = 2 Mbit Flash
40 = 4 Mbit Flash
80 = 8 Mbit Flash
Voltage
H = 2.7-3.3V
Product Series
32 = MPF + SRAM ComboMemory
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
26
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Valid combinations for SST32HF202
SST32HF202-70-4C-L3K
SST32HF202-70-4C-L3KE
SST32HF202-70-4E-L3K
SST32HF202-70-4E-L3KE
Valid combinations for SST32HF402
SST32HF402-70-4C-L3K
SST32HF402-70-4C-L3KE
SST32HF402-70-4E-L3K
SST32HF402-70-4E-L3KE
Valid combinations for SST32HF802
SST32HF802-70-4C-L3K SST32HF802-70-4C-LBK
SST32HF802-70-4C-L3KE SST32HF802-70-4C-LBKE
SST32HF802-70-4E-L3K SST32HF802-70-4E-LBK
SST32HF802-70-4E-L3KE SST32HF802-70-4E-LBKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
27
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
8.00 ± 0.20
BOTTOM VIEW
5.60
0.45 ± 0.05
(48X)
0.80
6
5
6
5
4
3
2
1
4.00
4
6.00 ± 0.20
3
2
1
0.80
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.30 ± 0.10
SIDE VIEW
0.12
1mm
SEATING PLANE
0.35 ± 0.05
Note:
1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1',
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-lfbga-L3K-6x8-450mic-5
48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM
SST PACKAGE CODE: L3K
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
28
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TOP VIEW
12.00 ± 0.20
BOTTOM VIEW
7.0
1.0
6
5
6
5
4
3
2
1
5.0
4
10.00 ± 0.20
3
2
1
1.0
0.50 ± 0.05
(48X)
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
A1 CORNER
A1 CORNER
1.4 Max
SIDE VIEW
0.12
SEATING PLANE
1mm
0.40 ± 0.05
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
48-lbga-LBK-10x12-500mic-2
4. Ball opening size is 0.4 mm (± 0.05 mm)
48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM
SST PACKAGE CODE: LBK
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
29
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TABLE 13: REVISION HISTORY
Number
Description
Date
00
01
02
03
Feb 2002
Apr 2002
Apr 2002
Mar 2003
•
•
•
•
•
•
•
2002 Data Book
Document Control Release (SST Internal): No technical changes
Removed the 1 Mbit SRAM devices
Added the 0 Mbit SRAM parts
Migrated the 8 Mbit parts from S71171 to S71209
Added L3K package for 8 Mb parts
Changes to Table 5 on page 10
– IDD active Read and Write current increased to 30 mA for SRAM and Flash
– Test Conditions for Power Supply Current corrected
– IDD active Concurrent Operation increased to 55 mA
– ISB Standby current decreased to 40 µA on SST32HF802
– Output leakage current increased to 10 µA
04
05
Sep 2003
Nov 2003
•
•
•
•
Removed all MPNs for 0 Mbit SRAM parts and 90 ns parts (See page 27)
2004 Data Book
Updated L3K and LBK package diagrams
06
May 2005
Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz
See Table 5 on page 10
•
•
Added RoHS compliance information on page 1 and in the “Product Ordering Infor-
mation” on page 26
Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on
page 9.
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
30
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