SST34HF1621C-70-4E-L1PE [SST]
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory; 16兆位并行的SuperFlash + 2/4兆位的SRAM ComboMemory
| 型号： | SST34HF1621C-70-4E-L1PE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory |
| 文件： | 总38页 (文件大小：649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
SST34HF168116Mb CSF (x8/x16) + 2/4/8 Mb SRAM (x16) MCP ComboMemory
Data Sheet
FEATURES:
•
•
Flash Organization: 1M x16 or 2M x8
Dual-Bank Architecture for Concurrent
Read/Write Operation
•
•
Block-Erase Capability
– Uniform 32 KWord blocks
Read Access Time
– Bottom Sector Protection
– 16 Mbit: 12 Mbit + 4 Mbit
– Flash: 70 ns
– SRAM: 70 ns
•
SRAM Organization:
– 2 Mbit: 128K x16
– 4 Mbit: 256K x16
Single 2.7-3.3V Read and Write Operations
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Erase-Suspend / Erase-Resume Capabilities
Security ID Feature
– SST: 128 bits
– User: 128 bits
•
•
•
•
Latched Address and Data
Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
•
•
Low Power Consumption:
– Active Current: 25 mA (typical)
– SRAM Standby Current: 20 µA (typical)
Hardware Sector Protection (WP#)
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
Byte Selection for Flash (CIOF pin)
– Selects 8-bit or 16-bit mode (56-ball package
only)
•
•
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
– 56-ball LFBGA (8mm x 10mm)
– 62-ball LFBGA (8mm x 10mm)
Sector-Erase Capability
– Uniform 2 KWord sectors
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST34HF16x1C ComboMemory devices integrate
either a 1M x16 or 2M x8 CMOS flash memory bank with
either a 128K x16 or 256K x16 CMOS SRAM memory
bank in a multi-chip package (MCP). These devices are
fabricated using SST’s proprietary, high-performance
CMOS SuperFlash technology incorporating the split-gate
cell design and thick-oxide tunneling injector to attain better
reliability and manufacturability compared with alternate
approaches. The SST34HF16x1C devices are ideal for
applications such as cellular phones, GPS devices, PDAs,
and other portable electronic devices in a low power and
small form factor system.
memory banks are partitioned into 12 Mbit and 4 Mbit with
bottom sector protection options for storing boot code, pro-
gram code, configuration/parameter data and user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF16x1C devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
operations, the flash memory banks provide a typical Pro-
gram time of 7 µsec. The entire flash memory bank can be
erased and programmed word-by-word in typically 4 sec-
onds for the SST34HF16x1C, when using interface fea-
tures such as Toggle Bit, Data# Polling, or RY/BY# to
indicate the completion of Program operation. To protect
The SST34HF16x1C feature dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
©2006 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71252-03-000
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8/06
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
against inadvertent flash write, the SST34HF16x1C
devices contain on-chip hardware and software data pro-
tection schemes.
Concurrent Read/Write Operation
Dual bank architecture of SST34HF16x1C devices allows
the Concurrent Read/Write operation whereby the user
can read from one bank while programming or erasing in
the other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank. See Figures 2 and 3 for dual-bank
memory organization.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signals, BES1# and BES2, select the
SRAM bank. The flash memory bank enable signal, BEF#,
has to be used with Software Data Protection (SDP) com-
mand sequence when controlling the Erase and Program
operations in the flash memory bank. The memory banks
are superimposed in the same memory address space
where they share common address lines, data lines, WE#
and OE# which minimize power consumption and area.
Concurrent Read/Write States
Flash
Bank 1
Read
Bank 2
Write
SRAM
No Operation
No Operation
Read
Write
Read
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF16x1C
are offered in extended temperatures and a small footprint
package to meet board space constraint requirements. See
Figures 4 and 5 for pin assignments.
Write
No Operation
Write
No Operation
Write
Read
No Operation
Write
Write
No Operation
Write
Note: For the purposes of this table, Write means to perform
Block-/Sector-Erase or Program operations
as applicable to the appropriate bank.
Device Operation
The SST34HF16x1C uses BES1#, BES2 and BEF# to
control operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
Flash Read Operation
The Read operation of the SST34HF16x1C is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram for further
details (Figure 9).
©2006 Silicon Storage Technology, Inc.
S71252-03-000
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2
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Flash Program Operation
Flash Chip-Erase Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the CIOF pin.
Before programming, one must ensure that the sector
which is being programmed is fully erased.
The SST34HF16x1C provide a Chip-Erase operation,
which allows the user to erase all sectors/blocks to the “1”
state. This is useful when the device must be quickly
erased.
The Program operation is accomplished in three steps:
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 5 for the command sequence, Figure 14 for timing
diagram, and Figure 28 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored.
1. Software Data Protection is initiated using the
three-byte load sequence.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or BEF#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
Flash Erase-Suspend/-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (TES
maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ2 toggling and
DQ6 at “1”. While in Erase-Suspend mode, a Program
operation is allowed except for the sector or block selected
for Erase-Suspend. To resume Sector-Erase or Block-
Erase operation which has been suspended, the system
must issue an Erase-Resume command. The operation is
executed by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the one-
byte sequence.
See Figures 10 and 11 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 24 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector-Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase
command (50H) and block address (BA) in the last bus
cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse.
The internal Erase operation begins after the sixth WE#
pulse. Any commands issued during the Block- or Sector-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 15 and 16 for timing wave-
forms.
Flash Write Operation Status Detection
The SST34HF16x1C provide one hardware and two soft-
ware means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write
cycle time. The hardware detection uses the Ready/
Busy# (RY/BY#) pin. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE#, which initiates the internal Program or
Erase operation.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
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16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result,
i.e., valid data may appear to conflict with either DQ7 or
DQ6. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cycle, otherwise the rejection is valid.
Flash Data# Polling (DQ7)
When the devices are in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 12 for Data# Poll-
ing (DQ7) timing diagram and Figure 25 for a flowchart.
Ready/Busy# (RY/BY#)
The SST34HF16x1C include a Ready/Busy# (RY/BY#)
output signal. RY/BY# is an open drain output pin that indi-
cates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to VDD via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (CIOF)
This function, found only on the 56-ball package, includes a
CIOF pin to control whether the device data I/O pins oper-
ate x8 or x16. If the CIOF pin is at logic “1” (VIH) the device
is in x16 data configuration: all data I/0 pins DQ0-DQ15 are
active and controlled by BEF# and OE#.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 13 for Toggle Bit tim-
ing diagram and Figure 25 for a flowchart.
If the CIOF pin is at logic “0”, the device is in x8 data config-
uration: only data I/O pins DQ0-DQ7 are active and con-
trolled by BEF# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
TABLE 1: Write Operation Status
Status
DQ7
DQ7#
0
DQ6
Toggle
Toggle
1
DQ2
No Toggle
Toggle
RY/BY#
Normal Operation
Standard Program
0
0
1
1
Standard Erase
Erase-Suspend Mode
Read From Erase Suspended Sector/Block
Read From Non-Erase Suspended Sector/Block
Program
1
Toggle
Data
DQ7#
Data
Toggle
Data
No Toggle
0
T1.2 1252
Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. The address must be in the bank where the operation is in
progress in order to read the operation status. If the address is pointing to a different bank (not busy), the device will output array data.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
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4
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Data Protection
Software Data Protection (SDP)
The SST34HF16x1C provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
The SST34HF16x1C provide the JEDEC standard Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST34HF16x1C are shipped with
the Software Data Protection permanently enabled. See
Table 5 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within TRC. The contents of DQ15-
DQ8 are “Don’t Care” during any SDP command
sequence.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF16x1C provide a hardware block protection
which protects the outermost 8 KWord in Bank 1. The block
is protected when WP# is held low. See Figures 2 and 3 for
Block-Protection location.
Common Flash Memory Interface (CFI)
These devices also contain the CFI information to describe
the characteristics of the devices. In order to enter the CFI
Query mode, the system must write the three-byte
sequence same as the Software ID Entry command with
98H (CFI Query command) to address 555H in the last
byte sequence. For CFI Entry and Bead timing diagram,
See Figure 18. Once the device enters the CFI Query
mode, the system can read CFI data a t the addresses
given in Tables 7 and 9. The system must write the CFI Exit
command to return to Bead mode from the CFI Query
mode.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
Hardware Reset (RST#)
Security ID
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode, see Figure 21. When no internal Pro-
gram/Erase operation is in progress, a minimum period of
TRHR is required after RST# is driven high before a valid
Read can take place, see Figure 20.
The SST34HF16x1C devices offer a 256-bit Security ID
space. The Secure ID space is divided into two 128-bit seg-
ments—one factory programmed segment and one user
programmed segment. The first segment is programmed
and locked at SST with a unique, 128-bit number. The user
segment is left un-programmed for the customer to pro-
gram as desired. To program the user segment of the
Security ID, the user must use the Security ID Program
command. End-of-Write status is checked by reading the
toggle bits. Data# Polling is not used for Security ID End-of-
Write detection. Once programming is complete, the Sec
ID should be locked using the User-Sec-ID-Program-Lock-
Out. This disables any future corruption of this space. Note
that regardless of whether or not the Sec ID is locked, nei-
ther Sec ID segment can be erased. The Secure ID space
can be queried by executing a three-byte command
sequence with Query-Sec-ID command (88H) at address
555H in the last byte sequence. To exit this mode, the Exit-
Sec-ID command should be executed. Refer to Table 5 for
more details.
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 20 and 21 for timing
diagrams.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
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5
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Product Identification
SRAM Operation
The Product Identification mode identifies the device as the
SST34HF16x1C and manufacturer as SST. This mode
may be accessed by software operations only. The hard-
ware device ID Read operation, which is typically used by
programmers cannot be used on this device because of
the shared lines between flash and SRAM in the multi-chip
package. Therefore, application of high voltage to pin A9
may damage this device. Users may use the software
Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Tables 4 and 5 for soft-
ware operation, Figure 17 for the Software ID Entry and
Read timing diagram and Figure 26 for the ID Entry com-
mand sequence flowchart.
With BES1# low, BES2 and BEF# high, the
SST34HF16x1C operate as either 128K x16, 256K x16, or
512K x16 CMOS SRAM, with fully static operation requir-
ing no external clocks or timing strobes. The
SST34HF16x1C SRAM is mapped into the first 512
KWord address space. When BES1#, BEF# are high and
BES2 is low, all memory banks are deselected and the
device enters standby. Read and Write cycle times are
equal. The control signals UBS# and LBS# provide access
to the upper data byte and lower data byte. For SRAM
Read and Write data byte control modes of operation, see
Table 4.
SRAM Read
The SRAM Read operation of the SST34HF16x1C is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. BES1# and BES2 are used for SRAM bank selection.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
OE# is high. Refer to the Read cycle timing diagram, Fig-
ure 6, for further details.
TABLE 2: Product Identification
ADDRESS DATA
Manufacturer’s ID
Device ID
BK0000H
00BFH
SST34HF16x1C
BK0001H
734BH
T2.1 1252
Note: BK = Bank Address (A19-A18
)
SRAM Write
Product Identification Mode Exit
The SRAM Write operation of the SST34HF16x1C is con-
trolled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 7 and 8, for further details.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Note that the Software ID Exit/CFI Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for software command codes, Fig-
ure 19 for timing waveform and Figure 26 for a flowchart.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
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6
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Address
Buffers
A
MS
1- A
0
SuperFlash Memory
(Bank 1)
CIOF
RST#
BEF#
WP#
SuperFlash Memory
(Bank 2)
LBS#
Control
Logic
UBS#
WE#2
OE#2
I/O Buffers
DQ /A- - DQ
15
1
0
BES1#
BES2
RY/BY#
2 / 4 Mbit
SRAM
Address
Buffers
Notes: 1. A
= Most significant address
MS
2. For LSE package only: WE# = WEF# and/or WES#
OE# = OEF# and/or OES#
1252 B1.5
FIGURE 1: Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
7
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
FFFFFH
Block 31
F8000H
F7FFFH
Block 30
F0000H
EFFFFH
Block 29
E8000H
E7FFFH
Block 28
E0000H
DFFFFH
Block 27
D8000H
D7FFFH
D0000H
Block 26
CFFFFH
C8000H
Block 25
C7FFFH
Block 24
C0000H
BFFFFH
B8000H
Block 23
B7FFFH
Block 22
B0000H
AFFFFH
A8000H
Block 21
A7FFFH
Block 20
A0000H
9FFFFH
Block 19
98000H
97FFFH
Block 18
90000H
8FFFFH
Block 17
88000H
87FFFH
Block 16
80000H
7FFFFH
Block 15
78000H
77FFFH
Block 14
70000H
6FFFFH
Block 13
68000H
67FFFH
Block 12
60000H
5FFFFH
Block 11
58000H
57FFFH
Block 10
50000H
4FFFFH
Block 9
48000H
47FFFH
Block 8
40000H
3FFFFH
Block 7
38000H
37FFFH
Block 6
30000H
2FFFFH
Block 5
28000H
27FFFH
Block 4
20000H
1FFFFH
Block 3
18000H
17FFFH
Block 2
10000H
0FFFFH
Block 1
08000H
07FFFH
02000H
01FFFH
00000H
Block 0
8 KWord Sector Protection
(4-2 KWord Sectors)
1252 F01.0
Note: The address input range in x16 mode (COIF=VIH) is A19-A0
FIGURE 2: 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
8
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
1FFFFFH
Block 31
1F0000H
1EFFFFH
Block 30
1E0000H
1DFFFFH
Block 29
1D0000H
1CFFFFH
Block 28
1C0000H
1BFFFFH
Block 27
1B0000H
1AFFFFH
1A0000H
Block 26
19FFFFH
190000H
Block 25
18FFFFH
Block 24
180000H
17FFFFH
170000H
Block 23
16FFFFH
Block 22
160000H
15FFFFH
150000H
Block 21
14FFFFH
Block 20
140000H
13FFFFH
Block 19
130000H
12FFFFH
Block 18
120000H
11FFFFH
Block 17
110000H
10FFFFH
Block 16
100000H
0FFFFFH
Block 15
0F0000H
0EFFFFH
Block 14
0E0000H
0DFFFFH
Block 13
0D0000H
0CFFFFH
Block 12
0C0000H
0BFFFFH
Block 11
0B0000H
0AFFFFH
Block 10
0A0000H
09FFFFH
090000H
Block 9
08FFFFH
080000H
Block 8
07FFFFH
070000H
Block 7
06FFFFH
060000H
Block 6
05FFFFH
050000H
Block 5
04FFFFH
040000H
Block 4
03FFFFH
030000H
Block 3
02FFFFH
020000H
Block 2
01FFFFH
010000H
Block 1
00FFFFH
004000H
003FFFH
000000H
Block 0
16 KByte Sector Protection
(4-4 KByte Sectors)
1252 F01b.0
Note: The address input range in x8 mode (CIOF=VIL) is A19-A-1
FIGURE 3: 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
9
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TOP VIEW (balls facing down)
8
A15 NC
NC
A16 CIOF
V
SS
7
6
5
4
3
2
1
A11 A12 A13 A14
NC
DQ7 DQ14
DQ12 DQ5
NOTE*
DQ13
DQ4
DQ3
DQ9
OE#
A8 A19 A9
WE# BES2 NC
WP# RST# RY/BY#
A10 DQ6
V
V
NC
DDS
DQ11
DDF
LBS# UBS# A18 A17 DQ1
DQ10 DQ2
DQ0 DQ8
BES1#
A7
A6
A5
A4
V
SS
A3
A2
A1
A0
BEF#
A
B
C
D
E
F
G
H
Note* = DQ /A
15 -1
FIGURE 4: Pin Assignments for 56-ball LFBGA (8mm x 10mm)
TOP VIEW (balls facing down)
8
NC
NC
A11
A8
A15
A10
A14
A13
A12
V
NC
NC
SSF
7
6
5
4
3
2
1
A16
A9 DQ15 WES# DQ14 DQ7
DQ13 DQ6 DQ4 DQ5
WEF# RY/BY#
V
SSS
RST#
NC
DQ12 BES2
V
V
DDS DDF
WP#
A19 DQ11
DQ10 DQ2 DQ3
LBS# UBS# OES#
DQ9 DQ8 DQ0 DQ1
A18
A17
A7
A6
A3
A2
A1 BES1#
OEF# NC
NC
NC
A5
A4
A0
BEF#
V
SSF
NC
A
B
C
D
E
F
G
H
J
K
FIGURE 5: Pin Assignments for 62-ball LFBGA (8mm x 10mm)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
10
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 3: Pin Description
Symbol
Pin Name
Functions
AMS1 to A0 Address Inputs
To provide flash address, A19-A0.
To provide SRAM address, AMS-A0
DQ14-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
DQ15/A-1
Data Input/Output
and LBS Address
DQ15 is used as data I/O pin when in x16 mode (CIOF = “1”)
A-1 is used as the LBS address pin when in x8 mode (CIOF = “0”)
BEF#
BES1#
BES2
OEF#2
OES#2
WEF#2
WES#2
OE#
Flash Memory Bank Enable
SRAM Memory Bank Enable
SRAM Memory Bank Enable
Output Enable
To activate the Flash memory bank when BEF# is low
To activate the SRAM memory bank when BES1# is low
To activate the SRAM memory bank when BES2 is high
To gate the data output buffers for Flash2 only
To gate the data output buffers for SRAM2 only
To control the Write operations for Flash2 only
To control the Write operations for SRAM2 only
To gate the data output buffers
Output Enable
Write Enable
Write Enable
Output Enable
WE#
Write Enable
To control the Write operations
CIOF3
UBS#
LBS#
WP#
Byte Selection for Flash
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Write Protect
When low, select Byte mode. When high, select Word mode.
To enable DQ15-DQ8
To enable DQ7-DQ0
To protect and unprotect the bottom 8 KWord (4 sectors) from Erase or Program
operation
RST#
Reset
To Reset and return the device to Read mode
RY/BY#
Ready/Busy#
To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to
allow RY/BY# to transition high indicating the device is ready to read.
2
VSSF
Ground
Flash2 only
SRAM2 only
2
VSSS
Ground
VSS
Ground
VDDF
Power Supply (Flash)
Power Supply (SRAM)
No Connection
2.7-3.3V Power Supply to Flash only
2.7-3.3V Power Supply to SRAM only
VDD
S
NC
Unconnected pins
T3.1 1252
1. AMS = Most Significant Address
AMS = A16 for SST34HF1621C, A17 for SST34HF1641C
2. LSE package only
3. L1PE package only
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
11
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 4: Operational Modes Selection
DQ15-8
CIOF = VIL
Mode
BEF#1 BES1#1,2
BES21,2 OE#2,3
WE#2,3 LBS#2 UBS#2
DQ7-0
CIOF = VIH
Full Standby
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIH
X
X
VIL
VIH
VIH
X
X
X
X
X
X
X
X
X
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
Output Disable
VIL
VIL
VIH
X
VIH
X
VIH
X
X
X
HIGH-Z
HIGH-Z
DOUT
DIN
HIGH-Z
HIGH-Z
DOUT
DIN
VIH
X
VIH
X
VIH
VIH
VIL
X
Flash Read
Flash Write
Flash Erase
SRAM Read
VIH
X
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
X
X
X
X
X
DQ14-8 = HIGH-Z
DQ15 = A-1
VIL
X
VIH
X
DQ14-8 = HIGH-Z
DQ15 = A-1
VIL
X
VIH
X
X
X
X
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
DOUT
HIGH-Z
DOUT
DIN
DOUT
DOUT
HIGH-Z
DIN
DOUT
DOUT
HIGH-Z
DIN
SRAM Write
VIH
VIL
VIH
X
VIL
HIGH-Z
DIN
DIN
DIN
HIGH-Z
HIGH-Z
Product
VIL
VIH
VIL
VIL
VIH
Manufacturer’s ID5
Device ID5
Identification4
T4.1 1252
1. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time
2. X can be VIL or VIH, but no other value.
3. OE# = OEF# and OES#
WE# = WEF# and WES# for LSE package only
4. Software mode only
5. With A19-A18 = VIL;SST Manufacturer’s ID = BFH, is read with A0=0,
SST34HF16x1C Device ID = 734BH, is read with A0=1
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
12
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 5: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
555H
555H
AAH
AAH
AAH
AAH
B0H
30H
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Program
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
30H
50H
10H
Sector-Erase
Block-Erase
Chip-Erase
555H
555H
555H
XXXXH
XXXXH
555H
Erase-Suspend
Erase-Resume
Query Sec ID5
2AAH
2AAH
55H
55H
555H
555H
88H
A5H
555H
SIWA6
XXH
Data
User Security ID
Program
555H
AAH
2AAH
55H
555H
85H
0000H
User Security ID
Program Lock-out7
9
Software ID Entry8
CFI Query Entry
555H
555H
555H
AAH
AAH
AAH
2AAH
2AAH
2AAH
55H
55H
55H
BKX
90H
98H
F0H
555H
9
BKX
555H
555H
Software ID Exit/
CFI Exit
Sec ID Exit10,11
XXH
F0H
Software ID Exit/
CFI Exit
Sec ID Exit10,11
T5.4 1252
1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.
When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word/byte address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. For SST34HF16x1C,
SST ID is read with A4 = 0 (Address range = 00000H to 00007H),
User ID is read with A4 = 1 (Address range = 00010H to 00017H).
Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. SIWA = User Security ID Program word/byte address
For SST34HF16x1C, valid Word-Addresses for User Sec ID are from 00010H-00017H.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The User Security ID Program Lock-out command must be executed in x16 mode (CIOF=VIH).
8. The device does not remain in Software Product Identification mode if powered down.
9. A19 and A18 = VIL
10. Both Software ID Exit operations are equivalent
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the
User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
For SST34HF16x1C, valid Word-Addresses for User Sec ID are from 00010H-00017H.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
13
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
1
TABLE 6: CFI QUERY IDENTIFICATION STRING
Address
x16 Mode
Address
x8 Mode
Data2
Description
10H
11H
12H
20H
22H
24H
0051H
0052H
0059H
Query Unique ASCII string “QRY”
13H
14H
26H
28H
001H
007H
Primary OEM command set
15H
16H
2AH
2CH
0000H
0000H
Address for Primary Extended Table
17H
18H
2EH
30H
0000H
0000H
Alternate OEM command set (00H = none exits)
Address for Alternate OEM extended Table (00H - none exits)
19H
1AH
32H
34H
0000H
0000H
T6.0 1252
1. Refer to CFI publication 100 for more details.
2. In x8 mode only the lower byte of data is output.
TABLE 7: SYSTEM INTERFACE INFORMATION
Address
x16 Mode
Address
x8 Mode
Data1
Description
1BH
1CH
36H
0027H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 Millivolts
38H
0036H
V
DD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 Millivolts
DD Min (00H = No VDD pin)
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
3AH
3CH
3EHh
40H
42H
44H
46H
48H
4AH
4CH
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
0001H
V
VDD Max (00H = No VDD pin)
Typical time out for Program 2N µs (24 = 16 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector-/Block-Erase 2N ms (2N = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Program 2N time typical (21 x 24 - 32 µs)
Maximum time out for buffer program 2N time typical
Maximum time out for individual Sector-Block-Erase 2N time typical (21 x 24 - 32 ms)
Maximum time out for individual Chip-Erase 2N time typical (21 x 26 - 128 ms)
T7.0 1252
1. In x8 mode, only the lower byte of data is output.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
14
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 8: SYSTEM INTERFACE INFORMATION
Address
x16 Mode
Address
x8 Mode
Data1
Description
27H
4EH
0015H
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
28H
29H
50H
52H
0002H
0000H
Flash Device Interface description; 0002H = x8/x16 asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
2AH
2BH
54H
56H
00000H
0000H
2CH
58H
0002H
2DH
2EH
2FH
30H
5AH
5CH
5EH
60H
00FFH
0001H
0010H
0000H
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FFH = 512)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H
32H
33H
34H
62H
64H
66H
68H
001FH
0000H
0000H
0001H
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T8.0 1252
1. In x8 mode, only the lower byte of data is output.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
15
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Ambient Temp
VDD
Extended
-20°C to +85°C
2.7-3.3V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 22 and 23
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
16
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
DC Characteristics
TABLE 9: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V)
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input = VILT/VIHT, at f=5 MHz,
1
IDD
Active VDD Current
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
35
30
60
mA
mA
mA
BEF#=VIL, BES1#=VIH, or BES2=VIL
BEF#=VIH, BES1#=VIL , BES2=VIH
BEF#=VIH, BES1#=VIL , BES2=VIH
WE#=VIL
SRAM
Concurrent Operation
Write2
Flash
40
30
30
30
1
mA
mA
µA
µA
µA
µA
BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH
BEF#=VIH, BES1#=VIL , BES2=VIH
VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC
RST#=GND
SRAM
ISB
IRT
ILI
Standby VDD Current
Reset VDD Current
Input Leakage Current
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST# pin
10
WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
V
V
V
V
V
V
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
VDD=VDD Max
0.7 VDD
VDD-0.3
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
VDD=VDD Max
0.2
0.4
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL =1 mA, VDD=VDD Min
VDD-0.2
2.2
IOH =-500 µA, VDD=VDD Min
T9.1 1252
1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 22)
2. IDD active while Erase or Program is in progress.
TABLE 10: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T10.0 1252
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
20 pF
16 pF
1
CIN
VIN = 0V
T11.0 1252
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
17
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 12: Flash Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T12.0 1252
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
AC CHARACTERISTICS
TABLE 13: SRAM Read Cycle Timing Parameters
Min
Max
Units
ns
TRCS
TAAS
TBES
TOES
TBYES
Read Cycle Time
70
Address Access Time
70
70
35
70
ns
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
ns
ns
1
TBLZS
TOLZS
0
0
0
ns
1
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
1
TBHZS
25
25
35
ns
TOHZS
TBYHZS
TOHS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
ns
1
ns
10
ns
T13.0 1252
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: SRAM Write Cycle Timing Parameters
Symbol Parameter
Min
70
60
60
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
50
ns
30
ns
0
30
0
ns
ns
TDHS
Data Hold from Write Time
ns
T14.0 1252
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
18
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 15: Flash Read Cycle Timing Parameters VDD = 2.7-3.3V
Symbol Parameter
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
70
Chip Enable Access Time
Address Access Time
70
70
35
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
1
0
0
ns
ns
1
1
TCHZ
20
20
ns
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High Before Read
RST# Pin Low to Read
ns
1,2
TRY
20
µs
T15.0 1252
1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
TABLE 16: Flash Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ms
ms
TBP
Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
0
40
0
TAH
TCS
TCH
TOES
TOEH
TCP
0
0
10
40
40
30
30
30
0
TWP
TWPH
1
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
1
TCPH
TDS
1
TDH
Data Hold Time
1
TIDA
Software ID Access and Exit Time
Erase-Suspend Latency
RY/BY# Delay Time
Bus# Recovery Time
Sector-Erase
150
10
TES
1,2
TBY
TBR
TSE
TBE
90
1
1
25
25
50
Block-Erase
TSCE
Chip-Erase
ms
T16.1 1252
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
19
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
T
RCS
ADDRESSES
A
MSS-0
T
T
OHS
AAS
T
T
BES
BES
BES1#
BES2
T
T
BLZS
BHZS
T
OES
OE#
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
1252 F04.0
Note: AMSS = Most Significant Address
MSS = A16 for SST34HF1621C, A17 for SST34HF1641C
A
FIGURE 6: SRAM Read Cycle Timing Diagram
T
WCS
3
ADDRESSES A
MSS -0
T
T
WPS
ASTS
T
WRS
WE#
T
AWS
T
BWS
BES1#
BES2
T
T
BWS
BYWS
UBS#, LBS#
T
OEWS
T
DHS
T
ODWS
T
DSS
NOTE 2
NOTE 2
VALID DATA IN
DQ
DQ
7-0
15-8,
1252 F05.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.
If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
A
MSS = A16 for SST34HF1621C and A17 for SST34HF1641C
FIGURE 7: SRAM Write Cycle Timing Diagram (WE# Controlled)1
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
20
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
T
WCS
3
ADDRESSES A
MSS -0
T
T
WRS
WPS
WE#
T
BWS
BWS
BES1#
BES2
T
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
VALID DATA IN
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
NOTE 2
NOTE 2
DQ
DQ
7-0
15-8,
1252 F06.0
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
A
MSS = A16 for SST34HF1621C and A17 for SST34HF1641C
FIGURE 8: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)1 x16 SRAM ONLY
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
21
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
T
T
AA
RC
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OE
T
OHZ
T
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1252 F07.0
FIGURE 9: Flash Read Cycle Timing Diagram for Word Mode
(For Byte Mode A-1 = Address Input)
T
BP
555
2AA
555
ADDR
ADDRESS A
19-0
T
AH
T
WP
WE#
T
WPH
T
AS
OE#
BEF#
T
CH
T
CS
?
T
BY
T
BR
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
Note: X can be V or V , but no other value.
IL
IH
1252 F08.1
FIGURE 10: Flash WE# Controlled Program Cycle Timing Diagram for Word Mode
(For Byte Mode A-1 = Address Input)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
22
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESS A
19-0
T
AH
T
CP
BEF#
OE#
T
CPH
T
AS
T
CH
WE#
T
CS
?
T
T
BY
BR
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
WORD
VALID
(ADDR/DATA)
Note: X can be V or V , but no other value.
IL
IH
1252 F09.1
FIGURE 11: Flash BEF# Controlled Program Cycle Timing Diagram for Word Mode
(For Byte Mode A-1 = Address Input)
ADDRESS A
19-0
T
CE
BEF#
OE#
T
T
OES
OEH
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
1252 F10.0
FIGURE 12: Flash Data# Polling Timing Diagram for Word Mode
(For Byte Mode A-1 = Address Input)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
23
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OEH
T
OE
WE#
T
BR
VALID DATA
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1252 F11.0
FIGURE 13: Flash Toggle Bit Timing Diagram for Word Mode
(For Byte Mode A-1 = Don’t Care)
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS A
19-0
555
2AA
555
555
2AA
555
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1252 F12.1
Note: This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 16.)
X can be VIL or VIH, but no other value.
FIGURE 14: Flash WE# Controlled Chip-Erase Timing Diagram for Word Mode
(For Byte Mode A-1 = Don’t Care)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
24
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
555 555 2AA
BE
ADDRESS
555
2AA
BA
X
A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
XXAA
XX55
XX80
XXAA
XX55
XX50
DQ
VALID
15-0
1252 F13.1
Note: This device also supports BEF# controlled Block-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 16.)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 15: Flash WE# Controlled Block-Erase Timing Diagram for Word Mode
(For Byte Mode A-1 = Don’t Care)
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS
T
SE
555
2AA
555
555
2AA
SA
X
A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1252 F14.1
Note: This device also supports BEF# controlled Sector-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 16.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 16: Flash WE# Controlled Sector-Erase Timing Diagram for Word Mode
(For Byte Mode A-1 = Don’t Care)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
25
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Three-Byte Sequence For Software ID Entry
ADDRESS A
555
2AA
555
0000
0001
14-0
BEF#
OE#
T
WP
T
IDA
WE#
T
WPH
T
AA
DQ
15-0
Device ID
XXAA
XX55
XX90
00BF
1252 F15.1
Note: X can be VIL or VIH, but no other value.
Device ID - 734BH for SST34HF16x1C
FIGURE 17: Flash Software ID Entry and Read for Word Mode
(For Byte Mode A-1 = 0)
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES
555
2AA
555
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
XXAA
XX55
XX98
15-0
Note: X can be V or V but no other value.
IL
IH,
1252 F26.0
Note: X can be VIL or VIH, but no other value.
FIGURE 18: CEI Entry and Read
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
26
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Three-Byte Sequence for Software ID Exit and Reset
555
2AA
555
ADDRESS A
DQ
14-0
15-0
XXAA
XX55
XXF0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
1252 F16.1
Note: X can be V or V , but no other value
IL
IH
FIGURE 19: Flash Software ID Exit/CEI Exit for Word Mode
(For Byte Mode A-1 = 0)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
27
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
RY/BY#
0V
T
RP
RST#
BEF#/OE#
T
RHR
1252 F17.0
FIGURE 20: RST Timing (when no internal operations in progress)
T
RY
RY/BY#
RST#
BEF#
OE#
T
RP
T
BR
1252 F18.0
FIGURE 21: RST# Timing (during Sector- or Block-Erase operation)
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
28
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
V
V
IHT
V
V
OT
IT
INPUT?
REFERENCE POINTS
OUTPUT
ILT
1252 F19.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 22: AC Input/Output Reference Waveforms
TO TESTER
TO DUT
C
L
1252 F20.0
FIGURE 23: A Test Load Example
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
29
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load
Address/Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1252 F21.2
Note: X can be VIL or V but no other value.
IH,
FIGURE 24: Program Algorithm
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
30
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read
byte/word
Read DQ
7
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
byte/word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1252 F22.1
FIGURE 25: Wait Options
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
31
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555H
Load data: XX98H
Address: 555H
Load data: XX88H
Address: 555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read Software ID
Read CFI data
Read Sec ID
X can be V or V , but no other value
IL IH
1252 F23.2
FIGURE 26: Software Product ID/CFI/Sec ID Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
32
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
1252 F24.2
Wait T
IDA
Return to normal
operation
X can be V or V but no other value
IL
IH,
FIGURE 27: Software Sec ID/CFI/ Exit/Sec ID Exit Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
33
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1252 F25.1
Note: X can be V or V but no other value.
IL
IH,
FIGURE 28: Erase Command Sequence
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
34
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST34HF16x1X- XXX
-
XX
-
XXXX
Package Attribute
E1 = non-Pb
Package Modifier
P = 56 balls
S = 62 balls
Package Type
L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size)
L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)
Temperature Range
E = Extended = -20°C to +85°C
Minimum Endurance
4 =10,000 cycles
Read Access Speed
70 = 70 ns
Version
C = x16 Mbit SRAM
Boot Block Protection
1 = Bottom Boot Block
SRAM Density
2 = 2 Mbit
4 = 4 Mbit
Flash Density
16 = 16 Mbit
Voltage
H = 2.7-3.3V
Product Series
34 = Concurrent SuperFlash +
SRAM ComboMemory
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST34HF1621C
SST34HF1621C-70-4E-L1PE SST34HF1621C-70-4E-LSE
Valid combinations for SST34HF1641C
SST34HF1641C-70-4E-L1PE
SST34HF1641C-70-4E-LSE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
35
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
10.00 0.20
BOTTOM VIEW
5.60
0.80
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
5.60
0.80
8.00 0.20
0.45 0.05
(56X)
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
1mm
0.12
SEATING PLANE
0.35 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
56-lfbga-L1P-8x10-450mic-4
FIGURE 29: 56-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm
SST Package Code: L1PE
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
36
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TOP VIEW
10.00 0.20
BOTTOM VIEW
7.20
0.80
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
8.00 0.20
5.60
1
0.40 0.05
(62X)
0.80
A
B
C
D
E
F
G
H
J
K
K
J
H
G
F
E
D
C
B
A
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
1mm
0.12
SEATING PLANE
0.32 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
62-lfbga-LS-8x10-400mic-4
4. Ball opening size is 0.32 mm ( 0.05 mm)
FIGURE 30: 62-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm
SST Package Code: LSE
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
37
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
TABLE 17: Revision History
Number
Description
Date
00
01
Mar 2004
Nov 2005
•
•
•
•
•
•
Initial Release
Renamed all devices previously released with version “D” to “J”
Removed 8 Mbit x8 PSRAM organization for SST34HF1681J
Changed references to Word-Program and Byte-Program to Program
Updated “Flash Erase-Suspend/-Resume Operations” on page 3
Added RoHS compliance information on page 1 and in the “Product Ordering Infor-
mation” on page 37
•
•
•
•
Removed all references to, and MPNs for, SST34HF1601C to EOL Data Sheet
Removed all references to, and MPNs for, SST34HF1601S
Moved all references to, and MPNs for, SST34HF1601S to S71301
Updated software command sequence addresses in Table 5 on page 13, timing
diagrams, and flowcharts
•
Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on
page 17
•
•
•
•
•
Corrected footnote 5 in Table 6 “Software Command Sequence” on page 14
Added Table 7, “CFI Query Identification String” on page 15
Added Table 8, “System Interface Information” on page 15
Added Table 9, “Device Geometry Information” on page 16
Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz
See Table 9 on page 17
•
•
•
•
•
•
•
•
Updated TES parameter from 20 µs to 10 µs in Table 17 on page 21
Removed all occurrences of 256K x8
02
03
Feb 2006
Aug 2006
Removed x8 SRAM Read and Write cross reference on page 6
Removed x8 SRAM from Figure 1 Functional Block Diagram page 7
Removed SRAM x8 Address from Table 3 on page 11
Removed Table 5 Operational Modes Selection for x8 SRAM
Applied new style formats throughout
Removed PSRAM references, and moved to S71336
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2006 Silicon Storage Technology, Inc.
S71252-03-000
8/06
38
相关型号：
SST34HF1621C-70-4E-LS
Memory Circuit, 1MX16, CMOS, PBGA62, 8 X 10 MM, 1.40 MM HEIGHT, MO-210, LFBGA-62
SILICON
SST34HF1621S-70-4E-L1P
Memory Circuit, 1MX16, CMOS, PBGA56, 8 X 10 MM, 1.40 MM HEIGHT, MO-210, LFBGA-56
SILICON
SST34HF1622C-70-4C-L1P
Memory Circuit, 1MX16, CMOS, PBGA56, 8 X 10 MM, 1.40 MM HEIGHT, MO-210, LFBGA-56
SILICON
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