SST34HF1681-70-4E-L1P [SST]
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory; 16兆位并行的SuperFlash + 8兆位的SRAM ComboMemory
| 型号： | SST34HF1681-70-4E-L1P |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory |
| 文件： | 总30页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
SST34HF16818 Mb Flash (x16) Concurrent SuperFlash ComboMemory
Advance Specifications
FEATURES:
•
•
Flash Organization: 1M x16
Dual-Bank Architecture for Concurrent
Read/Write Operation
•
•
Block-Erase Capability
– Uniform 32 KWord blocks
Read Access Time
– 16 Mbit: 12 Mbit + 4 Mbit
SRAM Organization:
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
•
– 8 Mbit: 512K x16
•
•
Latched Address and Data
Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
•
•
Single 2.7-3.3V Read and Write Operations
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
•
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Conforms to Common Flash Memory Interface
(CFI)
Packages Available
Sector-Erase Capability
– Uniform 1 KWord sectors
•
– 56-ball LFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST34HF1681 ComboMemory devices integrate a
1M x16 CMOS flash memory bank with a 512K x16 CMOS
SRAM memory bank in a Multi-Chip Package (MCP).
These devices are fabricated using SST’s proprietary, high-
performance CMOS SuperFlash technology incorporating
the split-gate cell design and thick oxide tunneling injector
to attain better reliability and manufacturability compared
with alternate approaches. The SST34HF1681 devices are
ideal for applications such as cellular phones, GPSs, PDAs
and other portable electronic devices in a low power and
small form factor system.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF1681 devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high performance Word-Pro-
gram, the flash memory banks provide a typical Word-Pro-
gram time of 14 µsec. The entire flash memory bank can
be erased and programmed word-by-word in typically 8
seconds for the SST34HF1681, when using interface fea-
tures such as Toggle Bit or Data# Polling to indicate the
completion of Program operation. To protect against inad-
vertent flash write, the SST34HF1681 devices contain on-
chip hardware and software data protection schemes.
The SST34HF1681 features dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 4 Mbit and 12 Mbit with
top or bottom sector protection options for storing boot
code, program code, configuration/parameter data and
user data.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
©2001 Silicon Storage Technology, Inc.
SST, the SST logo, and SuperFlash are Trademarks registered by Silicon Storage Technology, Inc. in the U.S. Patent and Trademark Office.
Concurrent SuperFlash, CSF, and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71214-00-000 12/01
1
561
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
SRAM bank enable signal, BES1# and BES2, selects the
CONCURRENT READ/WRITE STATE TABLE
Flash
SRAM bank. The flash memory bank enable signal, BEF#,
has to be used with Software Data Protection (SDP) com-
mand sequence when controlling the Erase and Program
operations in the flash memory bank. The memory banks
are superimposed in the same memory address space
where they share common address lines, data lines, WE#
and OE# which minimize power consumption and area.
Bank 1
Read
Bank 2
Write
SRAM
No Operation
No Operation
Read
Write
Read
Write
No Operation
Write
No Operation
Write
Read
No Operation
Write
Write
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF1681 are
offered in both commercial and extended temperatures
and a small footprint package to meet board space con-
straint requirements.
No Operation
Write
Note: For the purposes of this table, write means to Block-, Sector,
or Chip-Erase, or Word-Program as applicable to the
appropriate bank.
Device Operation
Flash Read Operation
The SST34HF1681 uses BES1#, BES2 and BEF# to con-
trol operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
The Read operation of the SST34HF1681 is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram for further
details (Figure 6).
Flash Word-Program Operation
The SST34HF1681 are programmed on a word-by-word
basis. Before Program operations, the memory must be
erased first. The Program operation consists of three steps.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load word address
and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either BEF# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either BEF# or WE#, whichever occurs first.
The third step is the internal Program operation which is ini-
tiated after the rising edge of the fourth WE# or BEF#,
whichever occurs first. The Program operation, once initi-
ated, will be completed typically within 10 µs. See Figures 7
and 8 for WE# and BEF# controlled Program operation tim-
ing diagrams and Figure 21 for flowcharts. During the Pro-
gram operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Concurrent Read/Write Operation
Dual bank architecture of SST34HF1681 devices allows
the Concurrent Read/Write operation whereby the user
can read from one bank while program or erase in the
other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank. See Figure 1 for Dual-Bank Memory
Organization.
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
i.e., valid data may appear to conflict with either DQ7 or
Flash Sector/Block-Erase Operation
DQ6. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cycle, otherwise the rejection is valid.
The Sector/Block-Erase operation allows the system to
erase the device on a sector-by-sector or block-by-block
basis. The SST34HF1681 offer both Sector-Erase and
Block-Erase mode. The sector architecture is based on
uniform sector size of 1 KWord. The Block-Erase mode is
based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. See Figures 12
and 13 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Ready/Busy# (RY/BY#)
The SST34HF1681 includes a Ready/Busy# (RY/BY#)
output signal. During any SDP initiated operation, e.g.,
Erase, Program, CFI or ID Read operation, RY/BY# is
actively pulled low, indicating a SDP controlled operation is
in Progress. The status of RY/BY# is valid after the rising
edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-, Block- or Bank-Erase, the RY/BY# is valid after
the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an
open drain output that allows several devices to be tied in
parallel to VDD via an external pull up resistor. Ready/
Busy# is in high impedance whenever OE# or CE# is high
or RST# is low. There is a 1 µs bus recovery time (TBR)
required before valid data can be read on the data bus.
New commands can be entered immediately after RY/BY#
goes high.
Flash Chip-Erase Operation
The SST34HF1681 provide a Chip-Erase operation, which
allows the user to erase all unprotected sectors/blocks to
the “1” state. This is useful when the device must be quickly
erased.
Flash Data# Polling (DQ7)
When the SST34HF1681 are in the internal Program oper-
ation, any attempt to read DQ7 will produce the comple-
ment of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles. During internal Erase operation, any attempt to
read DQ7 will produce a ‘0’. Once the internal Erase opera-
tion is completed, DQ7 will produce a ‘1’. The Data# Polling
(DQ7) is valid after the rising edge of fourth WE# (or BEF#)
pulse for Program operation. For Sector-, Block- or Chip-
Erase, the Data# Polling (DQ7) is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Poll-
ing (DQ7) timing diagram and Figure 22 for a flowchart.
There is a 1 µs bus recovery time (TBR) required before
valid data can be read on the data bus. New commands
can be entered immediately after DQ7 becomes true data.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 4 for the command sequence, Figure 11 for timing
diagram, and Figure 24 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
Flash Write Operation Status Detection
The SST34HF1681 provide one hardware and two soft-
ware means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write
cycle time. The hardware detection uses the Ready/
Busy# (RY/BY#) pin. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE#, which initiates the internal Program or
Erase operation.
Flash Toggle Bits (DQ6)
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result,
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next oper-
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
ation. The Toggle Bit (DQ6) is valid after the rising edge
Software Data Protection (SDP)
of fourth WE# (or BEF#) pulse for Program operation.
For Sector-, Block- or Chip-Erase, the Toggle Bit (DQ6) is
valid after the rising edge of sixth WE# (or BEF#) pulse.
See Figure 10 for Toggle Bit timing diagram and Figure
The SST34HF1681 provide the JEDEC standard Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. The SST34HF1681 are shipped with the Soft-
ware Data Protection permanently enabled. See Table 4 for
the specific software command codes. During SDP com-
mand sequence, invalid commands will abort the device to
Read mode within TRC. The contents of DQ15-DQ8 are
“Don’t Care” during any SDP command sequence.
22 for a flowchart. There is a 1 µs bus recovery time (TBR
)
required before valid data can be read on the data bus.
New commands can be entered immediately after DQ6 no
longer toggles.
Data Protection
The SST34HF1681 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
Common Flash Memory Interface (CFI)
The SST34HF1681 also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as Software ID Entry command with 98H
(CFI Query command) to address 555H in the last byte
sequence. Once the device enters the CFI Query mode, the
system can read CFI data at the addresses given in Tables
5 through 7. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF1681 provide a hardware block protection
which protects the outermost 4 KWord in Bank 1. The block
is protected when WP# is held low. See Figure 1 for Block-
Protection location.
Product Identification
The Product Identification mode identifies the device as the
SST34HF1681 and manufacturer as SST. This mode may
be accessed by software operations only. The hardware
device ID Read operation, which is typically used by pro-
grammers cannot be used on this device because of the
shared lines between flash and SRAM in the multi-chip
package. Therefore, application of high voltage to pin A9
may damage this device. Users may use the software
Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Tables 3 and 4 for soft-
ware operation, Figure 14 for the Software ID Entry and
Read timing diagram and Figure 23 for the ID Entry com-
mand sequence flowchart.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 18). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 17).
TABLE 1: PRODUCT IDENTIFICATION
ADDRESS
DATA
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 17 and 18 for timing
diagrams.
Manufacturer’s ID
Device ID
0000H
00BFH
SST34HF1681
0001H
2761H
T1.0 561
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
and LBS# provide access to the upper data byte and
lower data byte. See Table 3 for SRAM Read and Write
data byte control modes of operation.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 16 for timing waveform and Figure 23 for a
flowchart.
SRAM Read
The SRAM Read operation of the SST34HF1681 is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. BES1# and BES2 are used for SRAM bank selection.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
OE# is high. Refer to the Read cycle timing diagram, Fig-
ure 3, for further details.
SRAM Write
SRAM Operation
The SRAM Write operation of the SST34HF1681 is con-
trolled by WE# and BES1#, both have to be low, BES2
have to be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagram, Figures 4 and 5, for further details.
With BES1# low, BES2 and BEF# high, the
SST34HF1681 operates as 512K x16 CMOS SRAM,
with fully static operation requiring no external clocks or
timing strobes. The SST34HF1681 SRAM is mapped
into the first 512 KWord address space. When BES1#,
BEF# are high and BES2 is low, all memory banks are
deselected and the device enters standby. Read and
Write cycle times are equal. The control signals UBS#
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
A
MS
- A
0
SuperFlash Memory
(Bank 1)
RST#
BEF#
WP#
SuperFlash Memory
(Bank 2)
LBS#
UBS#
WE#
Control
Logic
I/O Buffers
DQ - DQ
15
0
OE#
BES1#
BES2
RY/BY#
8 Mbit
SRAM
Address
Buffers
561 ILL B1.2
A
= Most significant address
MS
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors
FFFFFH
Block 31
F8000H
F7FFFH
Block 30
F0000H
EFFFFH
Block 29
E8000H
E7FFFH
Block 28
E0000H
DFFFFH
Block 27
D8000H
D7FFFH
D0000H
Block 26
CFFFFH
C8000H
Block 25
C7FFFH
Block 24
C0000H
BFFFFH
B8000H
Block 23
B7FFFH
Block 22
B0000H
AFFFFH
A8000H
Block 21
A7FFFH
Block 20
A0000H
9FFFFH
Block 19
98000H
97FFFH
Block 18
90000H
8FFFFH
Block 17
88000H
87FFFH
Block 16
80000H
7FFFFH
Block 15
78000H
77FFFH
Block 14
70000H
6FFFFH
Block 13
68000H
67FFFH
Block 12
60000H
5FFFFH
Block 11
58000H
57FFFH
Block 10
50000H
4FFFFH
Block 9
48000H
47FFFH
Block 8
40000H
3FFFFH
Block 7
38000H
37FFFH
Block 6
30000H
2FFFFH
Block 5
28000H
27FFFH
Block 4
20000H
1FFFFH
Block 3
18000H
17FFFH
Block 2
10000H
00FFFFH
008000H
Block 1
007FFFH
001000H
000FFFH
000000H
Block 0
4 KWord Sector Protection
(Four 1 KWord Sectors)
561 ILL F02.0
FIGURE 1: SST34HF1681, 1 MBIT X 16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
TOP VIEW (balls facing down)
8
A15 NC
NC
A16 NC
NC DQ15 DQ7 DQ14
A10 DQ6 DQ13 DQ12 DQ5
V
SS
7
6
5
4
3
2
1
A11 A12 A13 A14
A8 A19 A9
WE# BES2 NC
WP# RST# RY/BY#
DQ4
DQ3
V
V
NC
DDS
DQ11
DDF
LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2
A7
A6
A3
A5
A2
A4
A1
V
OE# DQ0 DQ8
SS
A0 BEF# BES1#
A B C D E F G H
561 ILL F03.0
SST34HF1681
FIGURE 2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM) COMBOMEMORY PINOUT
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1 to A0 Address Inputs
To provide flash address, A19-A0.
To provide SRAM address, A18-A0
DQ15-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
BEF#
BES1#
BES2
OE#
Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low
SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low
SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high
Output Enable
Write Enable
To gate the data output buffers
To control the Write operations
WE#
UBS#
LBS#
WP#
Upper Byte Control (SRAM) To enable DQ15-DQ8
Lower Byte Control (SRAM) To enable DQ7-DQ0
Write Protect
Reset
To protect and unprotect sectors from Erase or Program operation
RST#
RY/BY#
To Reset and return the device to Read mode
Ready/Busy#
To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to
allow RY/BY# to transition high indicating the device is ready to read.
VSS
Ground
VDD
Power Supply (Flash)
Power Supply (SRAM)
No Connection
2.7-3.3V Power Supply to Flash only
2.7-3.3V Power Supply to SRAM only
Unconnected pins
F
VDDS
NC
T2.1 561
1. AMS = Most Significant Address
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
1
TABLE 3: OPERATIONAL MODES SELECTION
Mode
BEF#
BES1#
VIH
X
BES22
OE#
X
WE#
X
LBS#
X
UBS#
DQ0-7
DQ8-15
Full Standby
VIH
X
X
X
HIGH-Z
HIGH-Z
VIL
VIH
VIH
X
X
X
X
Output Disable
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
X
VIH
X
X
X
HIGH-Z
HIGH-Z
DOUT
DIN
HIGH-Z
HIGH-Z
DOUT
DIN
VIH
X
VIH
X
VIH
VIH
VIL
X
Flash Read
Flash Write
Flash Erase
SRAM Read
VIH
X
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
X
X
X
X
X
VIL
X
VIH
X
VIL
X
VIH
X
X
X
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
DOUT
HIGH-Z
DOUT
DIN
DOUT
DOUT
HIGH-Z
DIN
SRAM Write
VIH
VIL
VIH
X
VIL
HIGH-Z
DIN
DIN
HIGH-Z
Product
VIL
VIH
X
X
VIL
VIH
Manufacturer’s ID4
Identification3
Device ID4
VIL
T3.2 561
1. X can be VIL or VIH, but no other value.
2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time
3. Software mode only
4. With A19-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0,
SST34HF1681 Device ID = 2761H, is read with A0=1
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
8
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
Word-Program
Sector-Erase
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
4
Block-Erase
Chip-Erase
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
5555H AAH 2AAAH 55H 5555H 90H
Software ID Entry5
CFI Query Entry5
5555H AAH 2AAAH 55H 5555H 98H
Software ID Exit/
CFI Exit6
5555H AAH 2AAAH 55H 5555H F0H
T4.1 561
1. Address format A14-A0 (Hex),Address A19-A15 can be VIL or VIH, but no other value, for the Command sequence.
2. Data format DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence.
3. WA = Program Word address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX, for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product Identification Mode if powered down.
6. With A20-A1 = 0;
SST Manufacturer’s ID = 00BFH, is read with A0=0
SST34HF1681 Device ID = 2761H, is read with A0=1.
1
TABLE 5: CFI QUERY IDENTIFICATION STRING
Address
10H
Data
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Query Unique ASCII string “QRY”
11H
12H
13H
Primary OEM command set
14H
15H
Address for Primary Extended Table
16H
17H
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T5.0 561
1. Refer to CFI publication 100 for more details.
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
9
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
TABLE 6: SYSTEM INTERFACE INFORMATION
Address
Data
Data
1BH
0027H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
VPP Min (00H = no VPP pin)
VPP Max (00H = no VPP pin)
Typical time out for Word-Program 2N µs (24 = 16 µs)
Typical time out for Min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical
(21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.0 561
TABLE 7: DEVICE GEOMETRY INFORMATION
Address
27H
Data
Data
0015H
0001H
0000H
0000H
0000H
0002H
00FFH
0003H
0008H
0000H
001FH
0000H
0000H
0001H
Device size = 2N Byte (15H = 21; 221 = 2M Bytes)
28H
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 1023 + 1 = 1024 sectors (03FF = 1023)
z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001F = 31)
31H
32H
33H
34H
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.0 561
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
10
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 19 and 20
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
11
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
TABLE 8: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
IDD Active VDD Current
Min
Max Units Test Conditions
Address input = VIL/VIH, at f=1/TRC Min,
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
35
30
60
mA
mA
mA
BEF#=VIL, BES1#=VIH, or BES2=VIL
BEF#=VIH, BES1#=VIL , BES2=VIH
BEF#=VIH, BES1#=VIL , BES2=VIH
WE#=VIL
SRAM
Concurrent Operation
Write1
Flash
40
30
mA
mA
BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH
BEF#=VIH, BES1#=VIL , BES2=VIH
VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC
SRAM
ISB
Standby VDD Current 3.0V
3.3V
40
75
µA
µA
IRT
Reset VDD Current
30
1
µA
µA
µA
V
Reset=VSS 0.3V
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
1
VIL
0.8
0.3
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL =1 mA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
IOH =-500 µA, VDD=VDD Min
T8.1 561
1. IDD active while Erase or Program is in progress.
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
12
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T9.0 561
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
20 pF
16 pF
1
CIN
VIN = 0V
T10.1 561
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T11.0 561
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
13
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
AC CHARACTERISTICS
TABLE 12: SRAM READ CYCLE TIMING PARAMETERS
SST34HF1681-70
SST34HF1681-90
Symbol
TRCS
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TAAS
Address Access Time
70
70
35
70
90
90
45
90
ns
TBES
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
TOES
ns
TBYES
ns
1
TBLZS
0
0
0
0
0
0
ns
1
TOLZS
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
35
35
45
ns
1
TOHZS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
ns
1
TBYHZS
ns
TOHS
10
10
ns
T12.0 561
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: SRAM WRITE CYCLE TIMING PARAMETERS
SST34HF1681-70
SST34HF1681-90
Symbol
TWCS
TBWS
Parameter
Min
70
60
60
0
Max
Min
90
80
80
0
Max
Units
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
TAWS
TASTS
TWPS
Write Pulse Width
60
0
80
0
TWRS
TBYWS
TODWS
TOEWS
TDSS
Write Recovery Time
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
80
30
40
0
30
0
0
40
0
TDHS
Data Hold from Write Time
ns
T13.0 561
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
14
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
TABLE 14: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V
SST34HF1681-70
SST34HF1681-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TCE
Chip Enable Access Time
Address Access Time
70
70
35
90
90
45
ns
TAA
ns
TOE
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
30
30
ns
1
TOHZ
ns
1
TOH
0
0
ns
1
TRP
500
50
500
50
ns
1
TRHR
RST# High Before Read
RST# Pin Low to Read
ns
1,2
TRY
100
100
µs
T14.0 561
1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
TABLE 15: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
20
TAS
0
40
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
ns
1
TWPH
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
RY/BY# Delay Time
Bus# Recovery Time
Sector-Erase
150
ns
1
TBY
90
ns
1
TBR
1
µs
TSE
25
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
100
ms
T15.2 561
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
15
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
T
RCS
ADDRESSES A
MSS-0
T
T
OHS
AAS
T
BES1#
BES2
BES
T
BES
T
T
BLZS
BHZS
T
OES
OE#
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
561 ILL F04.0
A
= Most Significant SRAM Address
MSS
FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESSES A
MSS-0
WE#
T
ASTS
T
T
WPS
WRS
T
AWS
T
BWS
BES1#
BES2
T
BWS
T
BYWS
UBS#, LBS#
T
OEWS
T
ODWS
T
DHS
T
DSS
NOTE 2
VALID DATA IN
NOTE 2
DQ
DQ
7-0
15-8,
561 ILL F05.0
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will
remain at high impedance.
If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will
remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity
must not be applied.
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
16
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
T
WCS
ADDRESSES A
MSS-0
WE#
T
T
WRS
WPS
T
BWS
BES1#
BES2
T
BWS
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
DQ
DQ
7-0
15-8,
NOTE 2
NOTE 2
VALID DATA IN
561 ILL F06.0
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
17
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
T
T
AA
RC
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OE
T
OHZ
T
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
561 ILL F07.0
FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
T
AH
T
WP
WE#
T
WPH
T
AS
OE#
BEF#
T
CH
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
561 ILL F08.2
Note: X can be V or V , but no other value.
IL
IH
FIGURE 7: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
18
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
T
AH
T
CP
BEF#
OE#
T
CPH
T
AS
T
CH
WE#
T
CS
T
T
BY
BR
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
WORD
VALID
(ADDR/DATA)
561 ILL F09.2
Note: X can be V or V , but no other value.
IL
IH
FIGURE 8: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
T
BR
DQ
7
DATA#
DATA#
VALID DATA
561 ILL F10.1
FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
19
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OEH
T
OE
WE#
T
BR
VALID DATA
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
561 ILL F11.2
FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
561 ILL F12.2
Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
X can be V or V , but no other value.
IL IH
FIGURE 11: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
20
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS A
19-0
5555
2AAA
5555
5555
2AAA
BA
X
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
561 ILL F13.2
Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
BA = Block Address
X
X can be V or V , but no other value.
IL IH
FIGURE 12: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESS A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
561 ILL F14.2
Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
SA = Sector Address
X
X can be V or V , but no other value.
IL IH
FIGURE 13: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
21
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
Device ID
XXAA
XX55
XX90
00BF
561 ILL F15.2
Device ID = 2761H for SST34HF1681
Note: X can be V or V , but no other value
IL
IH
FIGURE 14: FLASH SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
14-0
5555
2AAA
5555
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
XXAA
XX55
XX98
15-0
561 ILL F16.1
Note: X can be V or V , but no other value.
IL IH
FIGURE 15: FLASH CFI ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
22
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
15-0
XXAA
XX55
XXF0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
561 ILL F17.1
Note: X can be V or V , but no other value
IL IH
FIGURE 16: FLASH SOFTWARE ID EXIT/CFI EXIT
RY/BY#
0V
T
RP
RST#
BEF#/OE#
T
RHR
561 ILL F26.0
FIGURE 17: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
23
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
T
RY
RY/BY#
RST#
T
RP
BEF#
OE#
T
BR
561 ILL F19.1
FIGURE 18: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE OPERATION)
V
V
IHT
ILT
V
V
OT
IT
INPUT
REFERENCE POINTS
OUTPUT
561 ILL F20.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
561 ILL F21.0
FIGURE 20: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
24
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
561 ILL F22.0
Note: X can be V or V but no other value.
IL
IH
,
FIGURE 21: WORD-PROGRAM ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
25
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
561 ILL F23.0
FIGURE 22: WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
26
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
CFI Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read CFI data
Read Software ID
561 ILL F24.1
Note: X can be V or V but no other value.
IL
IH,
FIGURE 23: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
27
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
561 ILL F25.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 24: ERASE COMMAND SEQUENCE
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
28
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST34HF16xx - XXX
-
XX
-
XX
Package Modifier
P = 56 balls
Package Type
L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 =10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Bank Split
1 = 12M + 4M
SRAM Density
0 = No SRAM
8 = 8 Mbit
Flash Density
16 = 16 Mbit
Voltage
H = 2.7-3.3V
Device Family
Valid combinations for SST34HF1681
SST34HF1681-70-4C-L1P
SST34HF1681-90-4C-L1P
SST34HF1681-70-4E-L1P
SST34HF1681-90-4E-L1P
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
29
16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
PACKAGING DIAGRAMS
BOTTOM VIEW
10.00 0.20
5.60
TOP VIEW
0.80
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
5.60
8.00 0.20
0.80
0.45 0.05
(56X)
H G F E D C B A
A B C D E F G H
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
56ba-LFBGA-L1P-8x10-450mic-ILL.1
1mm
0.15
SEATING PLANE
0.35 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 ( .05) mm.
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM
SST PACKAGE CODE: L1P
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71214-00-000 12/01 561
30
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