SST34HF324G-70-4E-L3KE [SST]
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory; 32百万位元双组闪存+ 4兆位的SRAM ComboMemory
| 型号： | SST34HF324G-70-4E-L3KE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory |
| 文件： | 总30页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory
Data Sheet
FEATURES:
•
Flash Organization: 2M x16
– 32 Mbit: 24Mbit + 8Mbit
Concurrent Operation
•
•
Block-Erase Capability
– Uniform 32 KWord blocks
Read Access Time
•
– Read from or Write to SRAM while
Erase/Program Flash
– Flash: 70 ns
– SRAM: 70 ns
•
SRAM Organization:
– 4 Mbit: 256K x16
Single 2.7-3.3V Read and Write Operations
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption: (typical values @ 5 MHz)
– Active Current: Flash 10 mA (typical)
SRAM 6 mA (typical)
•
•
•
Erase-Suspend / Erase-Resume Capabilities
Latched Address and Data
Fast Erase and Word-Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
•
•
•
•
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
– 48-ball LFBGA (6mm x 8mm)
All non-Pb (lead-free) devices are RoHS compliant
– Standby Current: 10 µA (typical)
Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (8 KWord) in the
smaller bank by holding WP# low and unprotects
by holding WP# high
Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
•
•
•
•
•
•
Sector-Erase Capability
– Uniform 2 KWord sectors
PRODUCT DESCRIPTION
The SST34HF324G ComboMemory devices integrate a
2M x16 CMOS flash memory bank with 256K x16 CMOS
SRAM memory bank in a multi-chip package (MCP).
These devices are fabricated using SST’s proprietary, high-
performance CMOS SuperFlash technology incorporating
the split-gate cell design and thick-oxide tunneling injector
to attain better reliability and manufacturability compared
with alternate approaches. The SST34HF324G devices
are ideal for applications such as cellular phones, GPS
devices, PDAs, and other portable electronic devices in a
low power and small form factor system.
gram time of 7 µsec. The entire flash memory bank can be
erased and programmed word-by-word in 4 seconds (typi-
cally) for the SST34HF324G, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. To protect against inadvertent
flash write, the SST34HF324G devices contain on-chip
hardware and software data protection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signal, BES#, selects the SRAM bank.
The flash memory bank enable signal, BEF#, has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The memory banks are
superimposed in the same memory address space where
they share common address lines, data lines, WE# and
OE# which minimize power consumption and area. See
Table 3 for memory organization.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF324G devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
operations, the flash memory banks provide a typical Pro-
©2006 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF324G
are offered in both commercial and extended temperatures
and a small footprint package to meet board space con-
straint requirements. See Figure 2 for pin assignments.
Flash Program Operation
These devices are programmed on a word-by-word basis.
Before programming, one must ensure that the sector
which is being programmed is fully erased.
The Program operation is accomplished in three steps:
Device Operation
1. Software Data Protection is initiated using the
three-byte load sequence.
The SST34HF324G use BES# and BEF# to control opera-
tion of either the flash or the SRAM memory bank. When
BEF# is low, the flash bank is activated for Read, Program
or Erase operation. When BES# is low the SRAM is acti-
vated for Read and Write operation. BEF# and BES# can-
not be at low level at the same time. If all bank enable
signals are asserted, bus contention will result and the
device may suffer permanent damage. All address,
data, and control lines are shared by flash and SRAM
memory banks which minimizes power consumption and
loading. The device goes into standby when BEF# and
BES# bank enables are raised to VIHC (Logic High) or
when BEF# is high.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or BEF#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Figures 7 and 8 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 20 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
Concurrent Read/Write Operation
The SST34HF324G provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. The following table lists all valid states.
Flash Sector- /Block-Erase Operation
Concurrent Read/Write State Table
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector-Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector-Erase command (50H) and sector address (SA) in
the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase
command (30H) and block address (BA) in the last bus
cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse.
The internal Erase operation begins after the sixth WE#
pulse. Any commands issued during the Block- or Sector-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 12 and 13 for timing wave-
forms.
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST34HF324G is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram for further
details (Figure 6).
©2006 Silicon Storage Technology, Inc.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling
(DQ7) or Toggle Bit (DQ6) read may be simultaneous with
the completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Flash Chip-Erase Operation
The SST34HF324G provide a Chip-Erase operation,
which allows the user to erase all sectors/blocks to the “1”
state. This is useful when the device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 6 for the command sequence, Figure 11 for timing
diagram, and Figure 23 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
Flash Data# Polling (DQ7)
When the device is in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Poll-
ing (DQ7) timing diagram and Figure 21 for a flowchart.
Flash Erase-Suspend/-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within erase-suspended sectors/blocks will output DQ2 tog-
gling and DQ6 at “1”. While in Erase-Suspend mode, a Pro-
gram operation is allowed except for the sector or block
selected for Erase-Suspend. To resume Sector-Erase or
Block-Erase operation which has been suspended, the
system must issue an Erase-Resume command. The
operation is executed by issuing a one-byte command
sequence with Erase Resume command (30H) at any
address in the one-byte sequence.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
Flash Write Operation Status Detection
The SST34HF324G provides two software means to
detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system Write cycle time.
The software detection includes two status bits: Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 10 for Toggle Bit tim-
ing diagram and Figure 21 for a flowchart.
©2006 Silicon Storage Technology, Inc.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 1: Write Operation Status
Hardware Reset (RST#)
Status
DQ7
DQ6
DQ2
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 17). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 16).
Normal
Operation
Standard
Program
DQ7#
Toggle
No Toggle
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 16 and 17 for timing
diagrams.
Block
Read From
Non-Erase
Suspended
Sector/
Data
Data
Data
Block
Software Data Protection (SDP)
Program
DQ7#
Toggle
No Toggle
T1.0 1310
The SST34HF324G provide the JEDEC standard Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST34HF324G are shipped with
the Software Data Protection permanently enabled. See
Table 6 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within TRC. The contents of DQ15-
DQ8 are “Don’t Care” during any SDP command
sequence.
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information.
Data Protection
The SST34HF324G provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF324G provide a hardware block protection
which protects the outermost 8 KWord in Bank 1. The block
is protected when WP# is held low. See Figure 3 for Block-
Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
©2006 Silicon Storage Technology, Inc.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Product Identification
SRAM Operation
The Product Identification mode identifies the device as
SST34HF324G and the manufacturer as SST. This mode
may be accessed by software operations only. The hard-
ware device ID Read operation, which is typically used by
programmers cannot be used on this device because of
the shared lines between flash and SRAM in the multi-chip
package. Therefore, application of high voltage to pin A9
may damage this device. Users may use the software
Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Tables 5 and 6 for soft-
ware operation, Figure 14 for the Software ID Entry and
Read timing diagram and Figure 22 for the ID Entry com-
mand sequence flowchart.
With BES# low and BEF# high, the SST34HF324G oper-
ates as either 256K x16 CMOS SRAM, with fully static
operation requiring no external clocks or timing strobes.
When BES# and BEF# are high, all memory banks are
deselected and the device enters standby. Read and Write
cycle times are equal. The control signals UBS# and LBS#
provide access to the upper data byte and lower data byte.
See Table 5 for SRAM Read and Write data byte control
modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF324G is con-
trolled by OE# and BES#, both have to be low with WE#
high for the system to obtain data from the outputs. BES#
is used for SRAM bank selection. OE# is the output control
and is used to gate data from the output pins. The data
bus is in high impedance state when OE# is high. Refer to
the Read cycle timing diagram, Figure 3, for further details.
TABLE 2: Product Identification
ADDRESS DATA
Manufacturer’s ID
Device ID
BK0000H
00BFH
SST34HF324G
BK0001H
7353H
T2.0 1310
SRAM Write
The SRAM Write operation of the SST34HF324G is con-
trolled by WE# and BES#, both have to be low for the sys-
tem to write to the SRAM. During the Word-Write
operation, the addresses and data are referenced to the
rising edge of either BES# or WE# whichever occurs first.
The write time is measured from the last falling edge of
BES# or WE# to the first rising edge of BES# or WE#.
Refer to the Write cycle timing diagrams, Figures 4 and 5,
for further details.
Note: BK = Bank Address (A20-A18
)
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 6 for software command codes, Fig-
ure 15 for timing waveform and Figure 22 for a flowchart.
©2006 Silicon Storage Technology, Inc.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Address
Buffers
SuperFlash Memory
(Bank 1)
A
20
- A
0
SuperFlash Memory
(Bank 2)
WP#
RST#
BEF#
LBS#
UBS#
WE#
Control
Logic
I/O Buffers
DQ - DQ
15
0
OE#
BES#
Address
Buffers
4 Mbit SRAM
1310 B1.0
FIGURE 1: Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 3: Dual-Bank Memory Organization (1 of 2)
SST34HF324G
Block
Block Size
Address Range x8
3FC000H–3FFFFFH
3F0000H–3FBFFFH
3E0000H–3EFFFFH
3D0000H–3DFFFFH
3C0000H–3CFFFFH
3B0000H–3BFFFFH
3A0000H–3AFFFFH
390000H–39FFFFH
380000H–38FFFFH
370000H–37FFFFH
360000H–36FFFFH
350000H–35FFFFH
340000H–34FFFFH
330000H–33FFFFH
320000H–32FFFFH
310000H–31FFFFH
300000H–30FFFFH
2F0000H–2FFFFFH
2E0000H–2EFFFFH
2D0000H–2DFFFFH
2C0000H–2CFFFFH
2B0000H–2BFFFFH
2A0000H—2AFFFFH
290000H—29FFFFH
280000H—28FFFFH
270000H—27FFFFH
260000H—26FFFFH
250000H—25FFFFH
240000H—24FFFFH
230000H—23FFFFH
220000H—22FFFFH
210000H—21FFFFH
200000H—20FFFFH
1F0000H—1FFFFFH
1E0000H—1EFFFFH
1D0000H—1DFFFFH
1C0000H—1CFFFFH
1B0000H—1BFFFFH
1A0000H—1AFFFFH
190000H—19FFFFH
180000H—18FFFFH
170000H—17FFFFH
160000H—16FFFFH
Address Range x16
8 KW / 16 KB
24 KW / 48 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
1FE000H–1FFFFFH
1F8000H–1FDFFFH
1F0000H–1F7FFFH
1E8000H–1EFFFFH
1E0000H–1E7FFFH
1D8000H–1DFFFFH
1D0000H–1D7FFFH
1C8000H–1CFFFFH
1C0000H–1C7FFFH
1B8000H–1BFFFFH
1B0000H–1B7FFFH
1A8000H–1AFFFFH
1A0000H–1A7FFFH
198000H–19FFFFH
190000H–197FFFH
188000H–18FFFFH
180000H–187FFFH
178000H–17FFFFH
170000H–177FFFH
168000H–16FFFFH
160000H–167FFFH
158000H–15FFFFH
150000H–157FFFH
148000H–14FFFFH
140000H–147FFFH
138000H–13FFFFH
130000H–137FFFH
128000H–12FFFFH
120000H–127FFFH
118000H–11FFFFH
110000H–117FFFH
108000H–10FFFFH
100000H–107FFFH
0F8000H–0FFFFFH
0F0000H–0F7FFFH
0E8000H–0EFFFFH
0E0000H–0E7FFFH
0D8000H–0DFFFFH
0D0000H–0D7FFFH
0C8000H–0CFFFFH
0C0000H–0C7FFFH
0B8000H–0BFFFFH
0B0000H–0B7FFFH
BA63
BA62
BA61
BA60
BA59
BA58
BA57
BA56
BA55
BA54
BA53
BA52
BA51
BA50
BA49
BA48
BA47
BA46
BA45
BA44
BA43
BA42
BA41
BA40
BA39
BA38
BA37
BA36
BA35
BA34
BA33
BA32
BA31
BA30
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
Bank 1
Bank 2
©2006 Silicon Storage Technology, Inc.
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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 3: Dual-Bank Memory Organization (Continued) (2 of 2)
SST34HF324G
Block
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
Block Size
Address Range x8
150000H—15FFFFH
140000H—14FFFFH
130000H—13FFFFH
120000H—12FFFFH
110000H—11FFFFH
100000H—10FFFFH
0F0000H—0FFFFFH
0E0000H—0EFFFFH
0D0000H—0DFFFFH
0C0000H—0CFFFFH
0B0000H—0BFFFFH
0A0000H—0AFFFFH
090000H—09FFFFH
080000H—08FFFFH
070000H—07FFFFH
060000H—06FFFFH
050000H–05FFFFH
040000H–04FFFFH
030000H–03FFFFH
020000H–02FFFFH
010000H–01FFFFH
000000H–00FFFFH
Address Range x16
0A8000H–0AFFFFH
0A0000H–0A7FFFH
098000H–09FFFFH
090000H–097FFFH
088000H–08FFFFH
080000H–087FFFH
078000H–07FFFFH
070000H–077FFFH
068000H–06FFFFH
060000H–067FFFH
058000H–05FFFFH
050000H–057FFFH
048000H–04FFFFH
040000H–047FFFH
038000H–03FFFFH
030000H–037FFFH
028000H–02FFFFH
020000H–027FFFH
018000H–01FFFFH
010000H–017FFFH
008000H–00FFFFH
000000H–007FFFH
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
Bank 2
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
T3.0 1310
TOP VIEW (balls facing down)
SST34HF324G
6
5
4
3
2
1
V
A13 A12 A14 A15 A16 UBS# DQ15
SS
DQ6
DQ4
DQ3
DQ1
A9
WE# RST# LBS# A19 DQ5 DQ12
BES# WP# A18 A20 DQ2 DQ10 DQ11
A8
A10 A11 DQ7 DQ14 DQ13
V
DD
A7
A3
A17
A4
A6
A2
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
V
SS
A B C D E F G H
FIGURE 2: Pin Assignments for 48-ball LFBGA (6mm x 8mm)
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
8
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 4: Pin Description
Symbol
Pin Name
Functions
AMS1 to A0 Address Inputs
To provide Flash address, A20-A0.
To provide SRAM address, A17-A0
DQ15-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE#, BES#, and BEF# are high.
BEF#
BES#
OE#
Flash Memory Bank Enable
To activate the Flash memory bank when BEF# is low
To activate the SRAM memory bank when BES# is low
To gate the data output buffers
SRAM Memory Bank Enable
Output Enable
WE#
UBS#
LBS#
WP#
Write Enable
To control the Write operations
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Write Protect
To enable DQ15-DQ8
To enable DQ7-DQ0
To protect and unprotect the bottom 8 KWord (4 sectors)
from Erase or Program operation
RST#
VSS
Reset
To Reset and return the device to Read mode
Ground
VDD
Power Supply
2.7-3.3V Power Supply
T4.0 1310
1. AMS = Most Significant Address
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
9
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 5: Operational Modes Selection for SRAM
Mode
BEF#1
BES#1,2
VIH
X
OE#2
X
WE#2
X
LBS#2 UBS#2
DQ15-0
DQ15-8
Full Standby
VIH
X
X
X
X
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
DOUT
DIN
HIGH-Z
HIGH-Z
HIGH-Z
X
X
Output Disable
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
X
VIH
X
X
X
HIGH-Z
HIGH-Z
DOUT
DIN
VIH
X
VIH
X
VIH
VIH
Flash Read
Flash Write
Flash Erase
SRAM Read
VIH
X
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
X
X
X
X
X
DQ15-8=HIGH-Z
DQ15-8=HIGH-Z
X
VIH
X
VIH
X
X
X
VIL
VIL
VIH
VIL
VIL
VIH
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
DOUT
HIGH-Z
DOUT
DIN
DOUT
DOUT
HIGH-Z
DIN
DOUT
DOUT
HIGH-Z
DIN
SRAM Write
VIH
VIL
X
VIL
HIGH-Z
DIN
DIN
DIN
HIGH-Z
HIGH-Z
Product
VIL
VIH
VIL
VIH
Manufacturer’s ID4
Identification3
Device ID4
T5.0 1310
1. Do not apply BEF# = VIL and BES# = VIL at the same time
2. X can be VIL or VIH, but no other value.
3. Software mode only
4. With A20-A18 = VIL;SST Manufacturer’s ID = BFH, is read with A0=0,
SST34HF324G Device ID = 7353H, is read with A0=1
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
10
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
555H
555H
AAH
AAH
AAH
AAH
B0H
30H
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Program
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
50H
30H
10H
Sector-Erase
Block-Erase
555H
555H
555H
Chip-Erase
XXXXH
XXXXH
555H
Erase-Suspend
Erase-Resume
Software ID Entry5
6
2AAH
2AAH
55H
55H
BKX
90H
F0H
555H
555H
XXH
AAH
F0H
555H
Software ID Exit
Software ID Exit
T6.0 1310
1. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses A20-A11 address lines
BAX for Block-Erase; uses A20-A15 address lines
BKx for Bank address; uses A20-A15 address lines
5. The device does not remain in Software Product Identification mode if powered down.
6. A20-A18 = VIL
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 18 and 19
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
11
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 7: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V)
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input = VILT/VIHT, at f=5 MHz,
1
IDD
Active VDD Current
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
15
10
45
mA
mA
mA
BEF#=VIL, BES#=VIH
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
WE#=VIL
SRAM
Concurrent Operation
Write2
Flash
40
30
30
30
1
mA
mA
µA
µA
µA
µA
BEF#=VIL, BES#=VIH, OE#=VIH
BEF#=VIH, BES#=VIL
VDD = VDD Max, BEF#=BES#=VIHC
RST#=GND
SRAM
ISB
IRT
ILI
Standby VDD Current
Reset VDD Current
Input Leakage Current
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current on
WP# pin and RST# pin
10
WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Flash and SRAM Output Low Voltage
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Flash and SRAM Output High Voltage VDD-0.2
V
T7.0 1310
1. See Figure 18
2. IDD active while Erase or Program is in progress.
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
12
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 8: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
µs
1
TPU-WRITE
100
µs
T8.0 1310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
20 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
16 pF
T9.0 1310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Flash Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T10.0 1310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
13
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
AC CHARACTERISTICS
TABLE 11: SRAM Read Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
ns
TRCS
TAAS
TBES
TOES
TBYES
Read Cycle Time
70
Address Access Time
70
70
35
70
ns
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
ns
ns
1
TBLZS
TOLZS
0
0
0
ns
1
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
ns
1
TOHZS
TBYHZS
TOHS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
ns
1
ns
10
ns
T11.0 1310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: SRAM Write Cycle Timing Parameters
Symbol Parameter
Min
70
60
60
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
ns
30
ns
0
30
0
ns
ns
TDHS
Data Hold from Write Time
ns
T12.0 1310
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
14
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
TABLE 13: Flash Read Cycle Timing Parameters VDD = 2.7-3.3V
Symbol Parameter
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
70
Chip Enable Access Time
Address Access Time
70
70
35
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
1
0
0
ns
ns
1
1
TCHZ
16
16
ns
TOHZ
ns
1
TOH
0
ns
1,2
TRP
500
50
ns
1,2
TRHR
RST# High Before Read
RST# Pin Low to Read
ns
1,2,3
TRY
20
µs
T13.0 1310
1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
2. L3K package only
3. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
TABLE 14: Flash Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
µs
TBP
Program Time
12
TAS
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
0
40
0
ns
ns
ns
TAH
TCS
TCH
TOES
TOEH
TCP
0
ns
0
ns
ns
ns
10
40
40
30
30
30
0
TWP
TWPH
ns
ns
ns
1
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
1
TCPH
TDS
ns
ns
ns
1
TDH
Data Hold Time
1
TIDA
Software ID Access and Exit Time
Erase-Suspend Latency
Bus# Recovery Time
Sector-Erase
150
10
1
TES
µs
1
TBR
µs
TSE
25
25
50
ms
ms
TBE
Block-Erase
TSCE
Chip-Erase
ms
T14.1 1310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
15
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
T
RCS
ADDRESSES
A
MSS-0
T
T
T
OHS
AAS
T
BES
BES#
T
BLZS
BHZS
T
OES
OE#
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
1310 F02.0
Note: AMSS = Most Significant Address
MSS = A17 for SST34HF324G
A
FIGURE 3: SRAM Read Cycle Timing Diagram
T
WCS
ADDRESSES
3
A
MSS -0
T
ASTS
T
WPS
T
WRS
WE#
T
AWS
T
T
BWS
BES#
BYWS
UBS#, LBS#
T
OEWS
T
DHS
T
ODWS
T
DSS
NOTE 2
NOTE 2
VALID DATA IN
DQ
15-8,
DQ
7-0
1310 F03.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes low coincident with or after WE# goes low, the output will remain at high impedance.
If BES# goes high coincident with or before WE# goes high, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
A
MSS = A17 for SST34HF324G
FIGURE 4: SRAM Write Cycle Timing Diagram (WE# Controlled)
©2006 Silicon Storage Technology, Inc.
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6/06
16
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
T
WCS
ADDRESSES
3-0
A
MSS
T
T
WRS
WPS
WE#
T
BWS
BES#
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
NOTE 2
NOTE 2
VALID DATA IN
DQ
DQ
7-0
15-8,
1310 F04.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A17 for SST34HF324G
FIGURE 5: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)
T
T
AA
RC
ADDRESS A20
-0
T
CE
BEF#
OE#
T
OE
T
OHZ
T
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1310 F05.0
FIGURE 6: Flash Read Cycle Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
17
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESS A
-0
20
T
AH
T
WP
WE#
OE#
T
WPH
T
AS
T
CH
BEF#
T
CS
?
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
Note: X can be V or V , but no other value.
IL
IH
1310 F06.0
FIGURE 7: Flash WE# Controlled Program Cycle Timing Diagram
T
BP
555
2AA
555
ADDR
ADDRESS A
20-0
T
AH
T
CP
BEF#
OE#
T
CPH
T
AS
T
CH
WE#
T
DS
T
CS
?
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
Note: X can be V or V , but no other value.
IL
IH
1310 F07.0
FIGURE 8: Flash BEF# Controlled Program Cycle Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
18
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
ADDRESS A
20-0
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
DATA
DATA#
DATA#
DATA
1310 F08.0
FIGURE 9: Flash Data# Polling Timing Diagram
ADDRESS A
20
-0
T
CE
BEF#
OE#
T
OEH
T
OE
WE#
T
BR
VALID DATA
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1310 F09.0
FIGURE 10: Flash Toggle Bit Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
19
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
SCE
555
2AA
555
ADDRESS A
20-0
BEF#
OE#
T
WP
WE#
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
DQ
15-0
1310 F10.0
Note: This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.)
X can be VIL or VIH, but no other value.
FIGURE 11: Flash WE# Controlled Chip-Erase Timing Diagram
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS
555
2AA
555
555
2AA
BA
X
A
20-0
BEF#
OE#
T
WP
WE#
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
DQ
15-0
1310 F11.0
Note: This device also supports BEF# controlled Block-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 12: Flash WE# Controlled Block-Erase Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
20
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS
T
SE
555
2AA
555
555
2AA
SA
X
A
20-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1310 F12.0
Note: This device also supports BEF# controlled Sector-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 13: Flash WE# Controlled Sector-Erase Timing Diagram
Three-Byte Sequence For Software ID Entry
555
2AA
555
0000
0001
ADDRESSES
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
Device ID
XXAA
XX55
XX90
00BF
DQ
15-0
1310 F13.0
Note: X can be VIL or VIH, but no other value.
Device ID - 7353H for SST34HF324G
FIGURE 14: Flash Software ID Entry and Read
©2006 Silicon Storage Technology, Inc.
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21
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESSES
DQ
15-0
XXAA
XX55
XXF0
T
IDA
CE#
OE#
T
WP
WE#
T
WPH
1310 F14.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 15: Flash Software ID Exit
©2006 Silicon Storage Technology, Inc.
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6/06
22
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
RY/BY#
0V
T
RP
RST#
BEF#/OE#
T
RHR
1310 F15.0
FIGURE 16: RST# Timing (when no internal operation is in progress)
T
RY
RY/BY#
RST#
BEF#
OE#
T
RP
T
BR
1310 F16.0
FIGURE 17: RST# Timing (during Sector- or Block-Erase operation)
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
23
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
V
V
IHT
ILT
V
V
OT
IT
INPUT?
REFERENCE POINTS
OUTPUT
1310 F17.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 18: AC Input/Output Reference Waveforms
TO TESTER
TO DUT
C
L
1310 F18.0
FIGURE 19: A Test Load Example
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
24
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load
Address/Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1310 F19.0
Note: X can be VIL or V but no other value.
IH,
FIGURE 20: Program Algorithm
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
25
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read
byte/word
Read DQ
7
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
byte/word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1310 F20.0
FIGURE 21: Wait Options
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
26
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Software Product ID Entry
Command Sequence
Software ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555
Load data: XXF0H
Address: 555H
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
1310 F21.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 22: Software Product ID Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
27
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1310 F22.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 23: Erase Command Sequence
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
28
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST34HF324G - XXX
-
XX
-
XXXX
Package Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Package Type
L3 = LFBGA (6mm x 8mm x 1.4mm, 0.45mm ball size)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 =10,000 cycles
Read Access Speed
70 = 70 ns
Version
G = Flash WP# and RST# + SRAM
SRAM Density
4 = 4 Mbit
Flash Density
32 = 32Mbit
Voltage
H = 2.7-3.3V
Product Series
34 = Dual-Bank Flash + SRAM ComboMemory
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST34HF324G
SST34HF324G-70-4C-L3KE
SST34HF324G-70-4E-L3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
29
32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60
0.45 0.05
(48X)
0.80
6
5
6
5
4
3
2
1
4.00
4
3
6.00 0.20
2
1
0.80
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
0.12
1mm
SEATING PLANE
0.35 0.05
Note:
1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1',
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-lfbga-L3K-6x8-450mic-5
48-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 6mm x 8mm
SST Package Code: L3K
TABLE 15: Revision History
Number
Description
Date
Jun 2006
00
•
Initial Release
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
30
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