SST36VF1602-90-4C-EK [SST]
16 Megabit Concurrent SuperFlash; 16兆位并行的SuperFlash
| 型号： | SST36VF1602-90-4C-EK |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 16 Megabit Concurrent SuperFlash |
| 文件： | 总26页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
FEATURES:
1
•
Organized as 1M x16
•
ReadAccessTime
– 70 and 90 ns
•
Dual-BankArchitectureforConcurrent
Read/Write Operation
•
•
Latched Address and Data
2
– 16 Mbit Bottom Sector Protection
- SST36VF1601: 12 Mbit + 4 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602: 4 Mbit + 12 Mbit
Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
3
•
•
Single 2.7-3.6V Read and Write Operations
Superior Reliability
4
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-WriteDetection
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
•
Low Power Consumption:
5
– Active Current: 25 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
– Toggle Bit
– Data#Polling
– Ready/Busy#pin
6
Hardware Sector Protection/WP# Input Pin
•
•
CMOS I/O Compatibility
– Protects 4 outer most sectors (4 KWord) in the
larger bank by driving WP# low and unprotects
by driving WP# high
Conforms to Common Flash Memory
Interface (CFI)
7
•
•
JEDEC Standards
HardwareResetPin(RESET#)
– Flash EEPROM Pinouts and command sets
Packages Available
8
– Resets the internal state machine to reading
dataarray
– 48-Pin TSOP (12mm x 20mm)
– 48-Ball TFBGA (8mm x 10mm)
•
•
Sector-EraseCapability
– Uniform 1 KWord sectors
Block-EraseCapability
– Uniform 32 KWord blocks
9
10
11
12
13
14
15
16
PRODUCTDESCRIPTION
The SST36VF1601/1602 are suited for applications that
requireconvenientandeconomicalupdatingofprogram,
configuration, or data memory. For all system applica-
tions,theSST36VF1601/1602significantlyimproveper-
formanceandreliability,whileloweringpowerconsump-
tion.TheSST36VF1601/1602inherentlyuselessenergy
duringEraseandProgramthanalternativeflashtechnolo-
gies. The total energy consumed is a function of the
appliedvoltage,current,andtimeofapplication.Sincefor
anygivenvoltagerange,theSuperFlashtechnologyuses
lesscurrenttoprogramandhasashortererasetime, the
total energy consumed during any Erase or Program
operationislessthanalternativeflashtechnologies.The
SST36VF1601/1602alsoimproveflexibilitywhilelower-
ingthecostforprogram, data, andconfigurationstorage
applications.
The SST36VF1601/1602 are 1M x16 CMOS Concurrent
Read/Write Flash Memory manufactured with SST’s pro-
prietary, high performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability com-
pared with alternate approaches.The SST36VF1601/
1602 write (Program or Erase) with a 2.7-3.6V power
supply. The SST36VF1601/1602 devices conform to
JEDEC standard pinouts for x16 memories.
Featuring high performance Word-Program, the
SST36VF1601/1602 devices provide a typical Word-Pro-
gramtimeof14µsec.ThedevicesuseToggleBitorData#
Polling to detect the completion of the Program or Erase
operation. To protect against inadvertent write, the
SST36VF1601/1602 devices have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, the
SST36VF1601/1602 devices are offered with a guaran-
teed endurance of 10,000 cycles. Data retention is rated
at greater than 100 years.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
temsoftwareorhardwaredoesnothavetobemodifiedor
de-rated as is necessary with alternative flash technolo-
©2000 SiliconStorageTechnology,Inc.TheSSTlogoandSuperFlashareregisteredtrademarksofSiliconStorageTechnology,Inc.ConcurrentSuperFlashisatrademarkofSiliconStorageTechnology,Inc.
373-3 11/00
S71142
Thesespecificationsaresubjecttochangewithoutnotice.
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
gies, whose Erase and Program times increase with
accumulated Erase/Program cycles.
in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure5).
To meet high density, surface mount requirements, the
SST36VF1601/1602areofferedin48-pinTSOPand48-
ball TFBGA packages. See Figures 3 and 4 for pinouts.
Word-ProgramOperation
The SST36VF1601/1602 are programmed on a word-by-
wordbasis.TheProgramoperationconsistsofthreesteps.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load word address
and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever occurs first.
The third step is the internal Program operation which is
initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated,willbecompletedwithin10µs.SeeFigures6and7for
WE# and CE# controlled Program operation timing dia-
grams and Figure 19 for flowcharts. During the Program
operation,theonlyvalidreadsareData#PollingandToggle
Bit. During the internal Program operation, the host is free
to perform additional tasks. Any commands issued during
theinternalProgramoperationareignored.
DeviceOperation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
deviceusingstandardmicroprocessorwritesequences.
AcommandiswrittenbyassertingWE#lowwhilekeeping
CE# low. The address bus is latched on the falling edge
of WE# or CE#, whichever occurs last. The data bus is
latched on the rising edge of WE# or CE#, whichever
occurs first.
TheSST36VF1601/1602alsohavetheAutoLowPower
modewhichputsthedeviceinanearstandbymodeafter
datahasbeenaccessedwithavalidReadoperation.This
reduces the IDD active read current to typically 4 µA. The
deviceexitstheAutoLowPowermodewithanyaddress
transition or control signal transition used to initiate
another read cycle, with no access time penalty.
Sector-(Block-)EraseOperation
ConcurrentRead/WriteOperation
The Sector- (Block-) Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST36VF1601/1602 offer both Sector-Erase
andBlock-Erasemode.Thesectorarchitectureisbasedon
uniform sector size of 1 KWord. The Block-Erase mode is
basedonuniformblocksizeof32KWord.TheSector-Erase
operation is initiated by executing a six-byte command
sequence with Sector-Erase command (30H) and sector
address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operationbeginsafterthesixthWE#pulse.SeeFigures11
and12fortimingwaveforms.Anycommandsissuedduring
the Sector- or Block-Erase operation are ignored.
Dual bank architecture of SST36VF1601/1602 devices
allowstheConcurrentRead/Writeoperationwherebythe
usercanreadfromonebankwhileprogramoreraseinthe
other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank.
CONCURRENT READ/WRITE STATE TABLE
Bank1
Read
Bank2
No Operation
Write
Read
Write
Read
Write
NoOperation
Read
NoOperation
NoOperation
Write
Note: For the purposes of this table, write means to Block-,
Sector-, or Chip-Erase, or Word-Program as applicable to
the appropriate bank.
Chip-EraseOperation
TheSST36VF1601/1602provideaChip-Eraseoperation,
which allows the user to erase all unprotected sectors/
blocks to the “1” state. This is useful when the device must
be quickly erased.
Read
The Read operation of the SST36VF1601/1602 is con-
trolledbyCE#andOE#,bothhavetobelowforthesystem
to obtain data from the outputs. CE# is used for device
selection.WhenCE#ishigh,thechipisdeselectedandonly
standbypowerisconsumed.OE#istheoutputcontroland
is used to gate data from the output pins. The data bus is
The Chip-Erase operation is initiated by executing a six-
bytecommandsequencewithChip-Erasecommand(10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
© 2000 Silicon Storage Technology, Inc.
S71142
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2
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Data# Polling (DQ7)timing diagram and Figure 20 for a
flowchart.
CE#,whicheveroccursfirst.DuringtheEraseoperation,the
onlyvalidreadisToggleBitsorData#Polling. SeeTable4
for the command sequence, Figure 10 for timing diagram,
and Figure 22 for the flowchart. Any commands issued
duringtheChip-Eraseoperationareignored.
1
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1’s
and 0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next
operation.TheToggleBit(DQ6) isvalidaftertherisingedge
of fourth WE# (or CE#) pulse for Program operation. For
Sector-,Block-orChip-Erase,theToggleBit(DQ6)isvalid
aftertherisingedgeofsixthWE#(orCE#)pulse.SeeFigure
9forToggleBittimingdiagramandFigure21foraflowchart.
2
WriteOperationStatusDetection
The SST36VF1601/1602 provide one hardware and two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system write
cycle time. The hadware detection uses the Ready/Busy#
(RY/BY#) output pin. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
End-of-Writedetectionmodeisenabledaftertherisingedge
of WE#, which initiates the internal Program or Erase
operation.
3
4
5
DataProtection
The actual completion of the nonvolatile write is asynchro-
nouswiththesystem;therefore,eitheraReady/Busy#(RY/
BY#), a Data# Polling (DQ7) or Toggle Bit (DQ6) read may
be simultaneous with the completion of the Write cycle. If
this occurs, the system may possibly get an erroneous
result,i.e.,validdatamayappeartoconflictwitheitherDQ7
or DQ6. In order to prevent spurious rejection, if an errone-
ousresultoccurs,thesoftwareroutineshouldincludealoop
toreadtheaccessedlocationanadditionaltwo(2)times. If
bothreadsarevalid,thenthedevicehascompletedthewrite
cycle, otherwise the rejection is valid.
TheSST36VF1601/1602providebothhardwareandsoft-
ware features to protect nonvolatile data from inadvertent
writes.
6
HardwareDataProtection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
7
8
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
WriteInhibitMode:ForcingOE#low,CE#high,orWE#high
will inhibit the Write operation. This prevents inadvertent
writesduringpower-uporpower-down.
9
Ready/Busy#(RY/BY#)
The SST36VF1601/1602 includes a Ready/Busy# (RY/
BY#)outputsignal.DuringanySDPinitiatedoperation,e.g.,
Erase, Program, CFI or ID Read operation, RY/BY# is
activelypulledlow,indicatingaSDPcontrolledoperationis
in Progress. The status of RY/BY# is valid after the rising
edge of fourth WE# (or CE#) pulse for Program operation.
ForSector-,Block-orBank-Erase,theRY/BY#isvalidafter
the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an
open drain output that allows several devices to be tied in
paralleltoVDDviaanexternalpullupresistor.Ready/Busy#
isinhighimpedancewheneverOE#orCE#ishighorRST#
is low.
10
11
12
13
14
15
16
HardwareBlockProtection
TheSST36VF1601/1602provideahardwareblockprotec-
tion which protects the outermost 4 KWords in the larger
bank.The block is protected when WP# is held low. See
Figures 1 and 2 for Block-Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire write
operationhascompleted.
Data# Polling (DQ7)
HardwareReset(RESET#)
WhentheSST36VF1601/1602areintheinternalProgram
operation,anyattempttoreadDQ7willproducethecomple-
ment of the true data. Once the Program operation is
completed, DQ7 will produce true data. The device is then
readyforthenextoperation.DuringinternalEraseoperation,
anyattempttoreadDQ7willproducea‘0’.Oncetheinternal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling (DQ7) is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling (DQ7) is valid after
WhentheRESET#inputpinisheldlowforatleastTRP,any
in progress operation will terminate and return to Read
mode. If the part is not busy, a minimum period of TRHR is
requiredafterRESET#isdrivenhighbeforeavalidreadcan
take place. If the part is busy, poll RY/BY#, Data# Polling,
or Toggle Bit to determine when the device is ready.
Initiating a reset during a Write operation (Program or
Erase) is not recommended. Data may be in an undeter-
mined state.
© 2000 Silicon Storage Technology, Inc.
S71142
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3
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
SoftwareDataProtection(SDP)
ProductIdentification
The SST36VF1601/1602 provide the JEDEC standard
Software Data Protection scheme for all data alteration
operations,i.e.,ProgramandErase.AnyProgramopera-
tion requires the inclusion of the three-byte sequence.
The three-byte load sequence is used to initiate the
Program operation, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-uporpower-down.AnyEraseoperationrequires
the inclusion of six-byte sequence. The SST36VF1601/
1602 are shipped with the Software Data Protection
permanently enabled. See Table 4 for the specific soft-
warecommandcodes.DuringSDPcommandsequence,
invalid commands will abort the device to Read mode
within TRC. The contents of DQ15-DQ8 are “Don’t Care”
during any SDP command sequence.
The Product Identification mode identifies the devices
and manufacturer. For details, see Table 4 for software
operation, Figure 13 for the Software ID Entry and Read
timing diagram and Figure 21 for the Software ID Entry
commandsequenceflowchart.
TABLE 1:PRODUCT IDENTIFICATION
WORD
DATA
00BF H
2761H
ManufacturersID
0000H
Device ID SST36VF1601
Device ID SST36VF1602
0001H
0001H
2762H
373 PGM T1.0
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the
Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit
command sequence, which returns the device to the
Readmode.Thiscommandmayalsobeusedtoresetthe
device to the Read mode after any inadvertent transient
condition that apparently causes the device to behave
abnormally,e.g.,notreadcorrectly.Pleasenotethatthe
SoftwareIDExit/CFIExitcommandisignoredduringan
internal Program or Erase operation. See Table 4 for
softwarecommandcodes,Figure15fortimingwaveform
and Figure 21 for a flowchart.
Common Flash Memory Interface (CFI)
The SST36VF1601/1602 also contain the CFI informa-
tiontodescribethecharacteristicsofthedevice.Inorder
to enter the CFI Query mode, the system must write
three-byte sequence, same as Software ID Entry com-
mand with 98H (CFI Query command) to address 555H
inthelastbytesequence.OncethedeviceenterstheCFI
Query mode, the system can read CFI data at the
addressesgiveninTables5through7.Thesystemmust
writetheCFIExitcommandtoreturntoReadmodefrom
the CFI Query mode.
FUNCTIONAL BLOCK DIAGRAM
(4 KWord Sector Protection)
Address
Buffers
Memory
Address
SuperFlash Memory
12 Mbit Bank
RESET#
CE#
SuperFlash Memory
4 Mbit Bank
WP#
WE#
Control
Logic
DQ - DQ
15
I/O Buffers
0
OE#
RY/BY#
373 ILL B37.4
© 2000 Silicon Storage Technology, Inc.
S71142
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4
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors
FFFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
1
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
2
3
4
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
00FFFFH
008000H
5
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
6
7
8
9
10
11
12
13
14
15
16
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
007FFFH
001000H
000FFFH
000000H
Block 0
4 KWord Sector Protection
(4- 1 KWord Sectors)
373 ILL F38.2
FIGURE 1: SST36VF1601,1MEGABIT X16CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
© 2000 Silicon Storage Technology, Inc.
S71142
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5
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
Top Sector Protection; 32 KWord Blocks; 1 KWord Sectors
4 KWord Sector Protection
(4- 1 KWord Sectors)
FFFFFH
FF000H
FEFFFH
F8000H
F7FFFH
F0000H
Block 31
Block 30
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
00FFFFH
008000H
00FFFFH
000000H
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
373 ILL F39.2
FIGURE 2: SST36VF1602,1MEGABIT X16CONCURRENT SUPERFLASHDUAL-BANK MEMORY ORGANIZATION
© 2000 Silicon Storage Technology, Inc.
S71142
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6
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
1
2
3
V
SS
4
DQ15
DQ7
5
6
DQ14
DQ6
2
7
A8
8
DQ13
DQ5
Standard Pinout
Top View
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
3
WE#
RESET#
NC
V
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
WP#
RY/BY#
A18
A17
A7
4
A6
5
A5
A4
A3
V
SS
A2
CE#
A1
A0
6
373 ILL F01b.2
7
FIGURE 3: PIN ASSIGNMENTS FOR 48-PIN TSOP (12MM X 20MM)
8
TOP VIEW (balls facing down)
9
10
11
12
13
14
15
16
6
5
4
3
2
1
A13 A12 A14 A15 A16 NC DQ15
A9
V
SS
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE#RESET# NC
RY/BY# WP# A18
A7 A17 A6
A19 DQ5 DQ12
V
DQ4
DD
NC DQ2 DQ10 DQ11 DQ3
A5
A1
DQ0 DQ8 DQ9 DQ1
A0 CE# OE#
A3
A4
A2
V
SS
A
B
C
D
E
F
G
H
373 ILL F01a.4
SST36VF1601/1602
FIGURE 4: PIN ASSIGNMENTS FOR 48-BALL TFBGA (8MM X 10MM)
© 2000 Silicon Storage Technology, Inc.
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7
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A19-A0
Address Inputs
Toprovidememoryaddresses. DuringSector-EraseandHardware
Sector Protection A19-A11 address lines will select the sector. During
Block-Erase A19-A15 address lines will select the block.
DQ15-DQ0
DataInput/output
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a Write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE#
Chip Enable
Output Enable
WriteEnable
Reset
To activate the device when CE# is low.
To gate the data output buffers.
OE#
WE#
To control the Write operations.
RESET#
RY/BY#
To reset and return the device to Read mode.
Ready/Busy#
To output the status of a Program or Erase operation. RY/BY# is an open
drain output, so a 10KW - 100KW pull-up resistor is required to allow
RY/BY# to transition high indicating the device is ready to read.
WP#
Write Protect
To protect and unprotect top or bottom 4 sectors from Erase
or Program operation.
VDD
Vss
NC
Power Supply
Ground
To provide 2.7-3.6V power supply voltage
No Connection
Unconnected pins.
373PGMT2.3
TABLE 3:OPERATION MODES SELECTION
Mode
Read
CE#
VIL
VIL
VIL
OE#
VIL
WE# DQ
Address
AIN
VIH
VIL
VIL
DOUT
Program
Erase
VIH
VIH
DIN
X
AIN
Sector or block address,
XXHforChip-Erase
X
Standby
VIH
X
X
X
High Z
Write Inhibit
VIL
X
X
High Z/ DOUT
High Z/ DOUT
X
X
X
VIH
Product Identification
A19 - A1 = VIL, A0 = VIL
A19 - A1 = VIL, A0 = VIH
See Table 4
ManufacturerID(00BF)
Device ID1
Software Mode
VIL
VIL
VIH
373PGMT3a.4
Note 1. Device ID = 2761H for SST36VF1601 and 2762H for SST36VF1602
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
8
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
Addr1 Data5 Addr1
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
1
Data5 Addr1 Data5 Addr1
Data5 Addr1 Data5 Addr1 Data5
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
5555H AAH
5555H AAH
5555H AAH
5555H AAH
2AAAH 55H
5555H A0H
5555H 80H
5555H 80H
5555H 80H
5555H 90H
5555H 98H
WA3
Data
2
2
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
5555H AAH
5555H AAH
5555H AAH
2AAAH 55H SAx
2AAAH 55H BAx
30H
50H
2
2AAAH 55H 5555H 10H
3
Software ID Entry6,7 5555H AAH
CFI Query Entry
5555H AAH
XXH F0H
Software ID Exit/
CFI Exit4
4
Software ID Exit/
CFI Exit4
Notes: 1. Address format A14-A0 (Hex),
5555H AAH
2AAAH 55H
5555H F0H
5
373PGMT4.2
Address A15-A19 are “Don’t Care” for Command sequence for SST36VF1601/1602
2. SAx for Sector-Erase; uses A19-A11 address lines
6
BAx, for Block-Erase; uses A19-A15 address lines
3. WA = Program word address
4. Both Software ID Exit/CFI Exit operations are equivalent
5. DQ15 - DQ8 are “Don’t Care” for Command sequence
7
6. With A19 -A1 =0;
SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST36VF1601 Device ID = 2761H, is read with A0 = 1.
SST36VF1602 Device ID = 2762H, is read with A0 = 1.
8
7. The device does not remain in Software Product Identification Mode if powered down.
9
10
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
9
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
1
TABLE 5: CFI QUERY IDENTIFICATION STRING
Address
Data
Data
10H
11H
12H
0051H
0052H
0059H
Query Unique ASCII string “QRY”
13H
14H
0001H
0007H
Primary OEM command set
15H
16H
0000H
0000H
Address for Primary Extended Table
17H
18H
0000H
0000H
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
19H
1AH
0000H
0000H
373 PGM T5.0
Note 1: Refer to CFI publication 100 for more details.
TABLE 6: SYSTEM INTERFACE INFORMATION
Address
Data
Data
1BH
0027H
VDD Min.(Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max. (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
VPP min. (00H = no VPP pin)
VPP max. (00H = no VPP pin)
Typical time out for Word-Program 2N µs (24 = 16 µs)
Typical time out for min. size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical
(21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
373 PGM T6.0
TABLE 7: DEVICE GEOMETRY INFORMATION
Address
Data
Data
27H
0015H
Device size = 2N Byte (15H = 21; 221 = 2M Bytes)
28H
29H
0001H
0000H
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
2AH
2BH
0000H
0000H
2CH
0002H
2DH
2EH
2FH
30H
00FFH
0003H
0008H
0000H
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 1023 + 1 = 1024 sectors (03FFH = 1023)
z = 8 x 256 Bytes = 2 KBytes/sector (0008H = 8)
31H
32H
33H
34H
001FH
0000H
0000H
0001H
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
373PGMT7.3
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
10
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute maximum Stress
Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
1
TemperatureUnderBias ................................................................................................................... -55°Cto+125°C
StorageTemperature ........................................................................................................................ -65°Cto+150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to VDD + 1.0V
Package Power Dissipation Capability (Ta = 25°C) ............................................................................................ 1.0W
SurfaceMountLeadSolderingTemperature(3Seconds) .................................................................................. 240°C
Output Short Circuit Current ............................................................................................................................. 50 mA
2
3
4
5
AC CONDITIONS OF TEST
OPERATINGRANGE
Range
AmbientTemp
0 °C to +70 °C
-20 °C to +85 °C
VDD
Input Rise/Fall Time ......... 5 ns
OutputLoad ..................... CL = 30 pF
See Figures 16 and 17
6
Commercial
Extended
2.7-3.6V
2.7-3.6V
7
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
8
Limits
Symbol Parameter
Min
Max
Units
TestConditions
9
IDD
PowerSupplyCurrent
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Address input = VIL/VIH, at f=1/TRC Min.
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max.
Read
35
40
75
mA
mA
mA
ProgramandErase
Concurrent
10
11
12
13
14
15
16
ISB
Standby VDD Current
20
20
µA
µA
CE#=VIHC, VDD = VDD Max.
IALP
AutoLowPowerCurrent
CE#=VILC, VDD = VDD Max., all inputs =
VIHC or VILC, WE# = VIHC
IRT
Reset VDD Current
20
1
µA
µA
µA
V
RESET# = VSS ± 0.3V
VIN =GND to VDD, VDD = VDD Max.
VOUT =GND to VDD, VDD = VDD Max.
VDD = VDD Min.
ILI
InputLeakageCurrent
OutputLeakageCurrent
Input Low Voltage
ILO
1
VIL
0.8
0.3
VILC
VIH
VIHC
VOL
VOH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD = VDD Max.
0.7 VDD
V
VDD = VDD Max.
Input High Voltage (CMOS) VDD-0.3
OutputLowVoltage
V
VDD = VDD Max.
0.2
V
IOL = 100 µA, VDD = VDD Min.
IOH = -100 µA, VDD = VDD Min.
OutputHighVoltage
VDD-0.2
V
373PGMT8.2
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
11
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ
TPU-WRITE
Power-uptoReadOperation
Power-uptoWriteOperation
100
100
µs
µs
373PGMT9.1
TABLE 10: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)
Parameter
Description
TestCondition
Maximum
1
CI/O
I/O Pin Capacitance
InputCapacitance
VI/O = 0V
VIN = 0V
12 pF
6 pF
1
CIN
373 PGM T10.0
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
TestMethod
1
NEND
Endurance - Flash
DataRetention
10,000
100
Cycles
Years
Volts
JEDECStandardA117
JEDECStandardA103
JEDECStandardA114
1
TDR
1
VZAP_HBM
ESD Susceptibility
HumanBodyModel
2000
1
VZAP_MM
ESD Susceptibility
MachineModel
200
Volts
mA
JEDECStandardA115
1
ILTH
Latch Up
100 + IDD
JEDEC Standard 78
373 PGM T11.0
Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
12
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
ACCHARACTERISTICS
TABLE 12:READ CYCLE TIMING PARAMETERS VDD=2.7-3.6V
1
SST36VF1601/1602-70 SST36VF1601/1602-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
2
TCE
Chip Enable Access Time
Address Access Time
70
70
35
90
90
45
ns
TAA
ns
3
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RESET# Pulse Width
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
4
1
TCHZ
20
20
30
30
ns
1
TOHZ
ns
5
1
TOH
0
0
ns
1
TRP
500
50
500
50
ns
1
TRHR
RESET#HighbeforeRead
RESET# Pin Low to Read Mode
ns
6
1,2
TRY
20
20
µs
373PGMT12.3
7
8
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-ProgramTime
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
20
9
TAS
0
40
0
ns
TAH
ns
10
11
12
13
14
15
16
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
ms
ns
TBE
Block-Erase
25
TSCE
Chip-Erase
100
1
TBY
RY/BY# Delay Time
RY/BY# Recovery Time
90
0
1
TRB
ns
373PGMT13.3
Note: 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
13
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
TIMING DIAGRAMS Address and data format are in HEX.
T
T
AA
RC
ADDRESS A
19-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
373 ILL F22.0
FIGURE 5:READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
T
AH
T
DH
T
WP
WE#
OE#
T
T
AS
DS
T
WPH
T
CH
CE#
T
CS
T
T
RB
BY
RY/BY#
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
373 ILL F23.3
FIGURE 6:WE#CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
14
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
INTERNAL PROGRAM OPERATION STARTS
1
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
CE#
T
AH
2
T
DH
T
CP
T
T
AS
DS
3
T
CPH
OE#
4
T
CH
WE#
5
T
CS
T
BY
T
RB
RY/BY#
6
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
7
373 ILL F24.1
FIGURE 7:CE#CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
8
9
ADDRESS A
19-0
10
11
12
13
14
15
16
T
CE
CE#
OE#
T
OES
T
OEH
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
373 ILL F25.1
FIGURE 8:DATA#POLLING TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
15
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
ADDRESS A
19-0
T
CE
CE#
T
OES
T
T
OE
OEH
OE#
WE#
T
BY
RY/BY#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
373 ILL F26.1
FIGURE 9:TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
19-0
CE#
OE#
T
WP
WE#
T
BY
RY/BY#
DQ
7-0
AA
55
80
SW2
AA
SW3
55
SW4
10
SW0
SW1
SW5
373 ILL F27.2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
FIGURE 10:WE#CONTROLLEDCHIP-ERASE TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
16
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
5555 5555 2AAA
5555
2AAA
BA
X
1
ADDRESS A
19-0
CE#
2
OE#
3
T
WP
WE#
4
RY/BY#
5
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
50
SW5
6
SW0
373 ILL F28.2
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
7
BA = Block Address
X
FIGURE 11:WE#CONTROLLED BLOCK-ERASE TIMING DIAGRAM
8
9
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
2AAA 5555 5555 2AAA
5555
SA
X
10
11
12
13
14
15
16
ADDRESS A
19-0
CE#
OE#
T
WP
WE#
RY/BY#
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW5
SW0
373 ILL F29.2
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
SA = Sector Address
X
FIGURE 12:WE#CONTROLLED SECTOR-ERASE TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
17
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
Device ID
373 ILL F30.3
Device ID = 2761H for SST36VF1601 and 2762H for SST36VF1602
FIGURE 13:SOFTWARE IDENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
5555
2AAA
5555
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX98
SW2
373 ILL F31.0
FIGURE 14:CFIENTRY AND READ
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
18
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
1
5555
2AAA
5555
ADDRESS A
14-0
2
DQ
AA
55
F0
7-0
3
T
IDA
CE#
OE#
4
5
T
WP
WE#
6
T
WHP
SW0
SW1
SW2
373 ILL F32.0
7
FIGURE 15: SOFTWARE ID EXIT/CFI EXIT
8
9
10
11
12
13
14
15
16
CE#/OE#
RESET#
T
RHR
T
RB
T
RP
T
RY
RY/BY#
373 ILL F21.0
FIGURE 16:RESET#TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
19
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
373 ILL F14.2
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% « 90%) are < 5 ns.
Note: VIT–VINPUT Test
VOT–VOUTPUT Test
VIHT–VINPUT HIGH Test
VILT–VINPUT LOW Test
FIGURE 17:ACINPUT/OUTPUT REFERENCEWAVEFORMS
TO TESTER
TO DUT
C
L
373 ILL F15.1
FIGURE 18:ATEST LOAD EXAMPLE
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
20
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
1
Start
2
Load data: AAH
Address: 5555H
3
Load data: 55H
Address: 2AAAH
4
5
Load data: A0H
Address: 5555H
6
7
Load Word
Address/Word
Data
8
Wait for end of
9
Program (T
,
BP
Data# Polling
bit, or Toggle bit
operation)
10
11
12
13
14
15
16
Program
Completed
373 ILL F33.1
FIGURE19:WORD-PROGRAMALGORITHM
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
21
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
373 ILL F34.0
FIGURE 20:WAIT OPTIONS
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
22
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
1
CFI Query Entry
Command Sequence
Software Product ID Entry
Software ID Exit/CFI Exit
Command Sequence
Command Sequence
2
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
3
4
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
5
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
6
7
Wait T
Wait T
Wait T
IDA
IDA
IDA
8
9
Return to normal
operation
Read CFI data
Read Software ID
373 ILL F35.1
10
11
12
13
14
15
16
FIGURE 21: SOFTWARE PRODUCT ID/CFICOMMAND FLOWCHARTS
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
23
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
373 ILL F36.1
FIGURE 22:ERASECOMMAND SEQUENCE
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
24
16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
PRODUCT ORDERING INFORMATION
Device
Speed Suffix1
- XXX XX
Suffix2
SST36VF160x
-
-
XX
1
PackageModifier
K = 48 pins
2
Numeric = Die modifier
Package Type
3
E = TSOP (12mm x 20mm)
B = TFBGA (8mm x 10mm)
TemperatureRange
4
C = Commercial = 0° to 70°C
E = Extended = -20° to 85°C
5
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
6
70 = 70 ns, 90 = 90 ns
Bank Split
7
1 = 12M + 4M
2 = 4M + 12M
Voltage
8
V = 2.7-3.6V
9
SST36VF1601Validcombinations
SST36VF1601-70-4C-EK
SST36VF1601-70-4C-BK
10
11
12
13
14
15
16
SST36VF1601-90-4C-EK
SST36VF1601-90-4C-BK
SST36VF1601-70-4E-EK
SST36VF1601-90-4E-EK
SST36VF1601-70-4E-BK
SST36VF1601-90-4E-BK
SST36VF1602Validcombinations
SST36VF1602-70-4C-EK
SST36VF1602-70-4C-BK
SST36VF1602-90-4C-EK
SST36VF1602-90-4C-BK
SST36VF1602-70-4E-EK
SST36VF1602-90-4E-EK
SST36VF1602-70-4E-BK
SST36VF1602-90-4E-BK
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
© 2000 Silicon Storage Technology, Inc.
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16MegabitConcurrentSuperFlash
SST36VF1601/SST36VF1602
Advance Information
PACKAGING DIAGRAMS
1.05
0.95
PIN # 1 IDENTIFIER
.50
BSC
.270
.170
12.20
11.80
0.15
0.05
18.50
18.30
0.70
0.50
20.20
19.80
Note:
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
48.TSOP-EK-ILL.4
48-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SSTPACKAGE CODE:EK
TOP VIEW
BOTTOM VIEW
10.00 ± 0.20
5.60
0.80
6
5
4
6
5
4
3
2
1
4.00
8.00 ± 0.20
3
2
1
0.30 ± 0.05
0.80
(48X)
A
B
C
D
E
F
G
H
H G F E D C B A
A1 CORNER
A1 CORNER
1.10 ± 0.10
SIDE VIEW
0.15
SEATING PLANE
48ba TFBGA.BK8x10-ILL.7
0.21 ± 0.05
Note: 1. Complies with the general requirements of JEDEC publication 95 MO-210, although some dimensions may be more stringent.
(This specific outline variant has not yet been registered)
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
48-BALL THIN PROFILE FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM
SSTPACKAGE CODE:BK
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
© 2000 Silicon Storage Technology, Inc.
S71142
373-3 11/00
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