SST39LF010-75-4C-B3HE [SST]
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash; 512千位/ 1兆位/ 2兆位/ 4兆位（ X8 ）多用途闪存
| 型号： | SST39LF010-75-4C-B3HE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| 文件： | 总24页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
Data Sheet
FEATURES:
•
•
Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8
Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF512/010/020/040
– 2.7-3.6V for SST39VF512/010/020/040
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption
(typical values at 14 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 µA (typical)
Sector-Erase Capability
– Uniform 4 KByte sectors
Fast Read Access Time:
•
Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
•
•
1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
CMOS I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
•
•
•
•
– 45 ns for SST39LF512/010/020/040
– 55 ns for SST39LF020/040
– 70 ns for SST39VF512/010/020/040
•
•
Latched Address and Data
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 48-ball TFBGA (6mm x 8mm)
– 34-ball WFBGA (4mm x 6mm) for 1M and 2M
•
All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39LF512, SST39LF010, SST39LF020, SST39LF040
and SST39VF512, SST39VF010, SST39VF020, SST39VF040
are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Pur-
pose Flash (MPF) manufactured with SST’s proprietary, high per-
formance CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches. The
SST39LF512/010/020/040 devices write (Program or Erase) with
a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices
write with a 2.7-3.6V power supply. The devices conform to
JEDEC standard pinouts for x8 memories.
ration, or data memory. For all system applications, they
significantly improves performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program oper-
ation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
Featuring high performance Byte-Program, the
SST39LF512/010/020/040 and SST39VF512/010/020/
040 devices provide a maximum Byte-Program time of 20
µsec. These devices use Toggle Bit or Data# Polling to indi-
cate the completion of Program operation. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, they
are offered with a guaranteed typical endurance of
100,000 cycles. Data retention is rated at greater than 100
years.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet surface mount requirements, the SST39LF512/
010/020/040 and SST39VF512/010/020/040 devices are
offered in 32-lead PLCC and 32-lead TSOP packages. The
SST39LF/VF010 and SST39LF/VF020 are also offered in
a 48-ball TFBGA package. See Figures 2, 3, 4, and 5 for
pin assignments.
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices are suited for applications that require
convenient and economical updating of program, configu-
©2010 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
S71150-14-000
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These specifications are subject to change without notice.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
edge of the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase can be
determined using either Data# Polling or Toggle Bit meth-
ods. See Figure 11 for timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Chip-Erase Operation
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the ‘1’s
state. This is useful when the entire device must be quickly
erased.
Read
The Read operation of the SST39LF512/010/020/040 and
SST39VF512/010/020/040 device is controlled by CE#
and OE#, both have to be low for the system to obtain data
from the outputs. CE# is used for device selection. When
CE# is high, the chip is deselected and only standby power
is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. Refer to the
Read cycle timing diagram for further details (Figure 6).
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 12 for timing diagram, and Figure 20 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
Byte-Program Operation
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are programmed on a byte-by-byte basis. Before
programming, the sector where the byte exists must be
fully erased. The Program operation is accomplished in
three steps. The first step is the three-byte load sequence
for Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program
operation, the addresses are latched on the falling edge of
either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever
occurs first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE# or
CE#, whichever occurs first. The Program operation, once
initiated, will be completed, within 20 µs. See Figures 7 and
8 for WE# and CE# controlled Program operation timing
diagrams and Figure 17 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands written
during the internal Program operation will be ignored.
Write Operation Status Detection
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide two software means to detect the
completion of a Write (Program or Erase) cycle, in order to
optimize the system write cycle time. The software detec-
tion includes two status bits: Data# Polling (DQ7) and Tog-
gle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Pro-
gram or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H) is latched on the rising
©2010 Silicon Storage Technology, Inc.
S71150-14-000
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Data# Polling (DQ7)
Software Data Protection (SDP)
When the SST39LF512/010/020/040 and SST39VF512/
010/020/040 are in the internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. Note that even though DQ7 may
have valid data immediately following completion of an
internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear
in subsequent successive Read cycles after an interval of 1
µs. During internal Erase operation, any attempt to read
DQ7 will produce a “0”. Once the internal Erase operation is
completed, DQ7 will produce a “1”. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector- or Chip-Erase, the Data#
Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 9 for Data# Polling timing diagram and
Figure 18 for a flowchart.
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide the JEDEC approved Software Data Pro-
tection scheme for all data alteration operation, i.e., Pro-
gram and Erase. Any Program operation requires the
inclusion of a series of three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte load
sequence. These devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to read
mode, within TRC.
Product Identification
The Product Identification mode identifies the devices as
the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020
and SST39LF/VF040 and manufacturer as SST. This
mode may be accessed by software operations. Users
may use the Software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Table 4 for software operation, Figure 13 for the Software
ID Entry and Read timing diagram, and Figure 19 for the
Software ID entry command sequence flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 10 for Toggle Bit timing
diagram and Figure 18 for a flowchart.
TABLE 1: Product Identification
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
Data Protection
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide both hardware and software features to
protect nonvolatile data from inadvertent writes.
SST39LF/VF512
SST39LF/VF010
SST39LF/VF020
SST39LF/VF040
0001H
0001H
0001H
0001H
D4H
D5H
D6H
D7H
T1.1 1150
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
Product Identification Mode Exit/Reset
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 14 for timing wave-
form, and Figure 19 for a flowchart.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2010 Silicon Storage Technology, Inc.
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3
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SuperFlash
X-Decoder
Memory
Memory Address
Address Buffers & Latches
Y-Decoder
CE#
OE#
I/O Buffers and Data Latches
Control Logic
WE#
DQ - DQ
7
0
1150 B1.1
FIGURE 1: Functional Block Diagram
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
4
3
2
1
32 31 30
29
5
A7
A6
A7
A6
A7
A6
A7
A6
A14
A13
A8
A14
A13
A8
A14
A13
A8
A14
A13
A8
6
28
27
26
25
24
23
22
21
7
A5
A5
A5
A5
8
A4
A4
A4
A4
A9
A9
A9
A9
32-lead PLCC
Top View
9
A3
A3
A3
A3
A11
OE#
A10
CE#
DQ7
A11
OE#
A10
CE#
DQ7
A11
OE#
A10
CE#
DQ7
A11
OE#
A10
CE#
DQ7
10
11
12
13
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
DQ0
DQ0
DQ0
DQ0
14 15 16 17 18 19 20
1150 32-plcc NH P4.3
FIGURE 2: Pin Assignments for 32-lead PLCC
©2010 Silicon Storage Technology, Inc.
S71150-14-000
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4
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
A11
A9
A8
A13
A14
A17
WE#
A11
A9
A8
A13
A14
A17
WE#
A11
A9
A8
A13
A14
NC
A11
A9
A8
A13
A14
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
OE#
A10
OE#
A10
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Standard Pinout
Top View
WE#
WE#
V
V
V
V
DD
DD
DD
DD
A18
A16
A15
A12
A7
NC
A16
A15
A12
A7
NC
A16
A15
A12
A7
NC
NC
A15
A12
A7
9
V
V
V
V
SS
SS
SS
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
A6
A5
A4
A6
A5
A4
A6
A5
A4
A6
A5
A4
A1
A2
A3
A1
A2
A3
A1
A2
A3
A1
A2
A3
1150 32-tsop WH P1.0
FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
TOP VIEW (balls facing down)
SST39LF/VF010
TOP VIEW (balls facing down)
SST39LF/VF020
6
6
A14 A13 A15 A16 NC NC NC V
SS
A14 A13 A15 A16 A17 NC NC V
SS
5
4
3
2
1
5
4
3
2
1
A9 A8 A11 A12 NC A10 DQ6 DQ7
A9 A8 A11 A12 NC A10 DQ6 DQ7
WE# NC NC NC DQ5 NC V
NC NC NC NC DQ2 DQ3 V
DQ4
NC
DD
DD
WE# NC NC NC DQ5 NC V
NC NC NC NC DQ2 DQ3 V
DQ4
NC
DD
DD
A7 NC A6 A5 DQ0 NC NC DQ1
A7 NC A6 A5 DQ0 NC NC DQ1
A3 A4 A2 A1 A0 CE# OE# V
SS
A3 A4 A2 A1 A0 CE# OE# V
SS
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
TOP VIEW (balls facing down)
SST39LF/VF040
6
5
4
3
2
1
A14 A13 A15 A16 A17 NC NC V
SS
A9 A8 A11 A12 NC A10 DQ6 DQ7
WE# NC NC NC DQ5 NC V
NC NC NC NC DQ2 DQ3 V
DQ4
NC
DD
DD
A7 A18 A6 A5 DQ0 NC NC DQ1
A3 A4 A2 A1 A0 CE# OE# V
SS
A
B
C
D
E
F
G
H
FIGURE 4: Pin Assignment for 48-ball TFBGA (6mm x 8mm) for 1 Mbit, 2 Mbit, and 4 Mbit
©2010 Silicon Storage Technology, Inc.
S71150-14-000
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5
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW (balls facing down)
6
5
4
3
2
1
A2
A1
A0
A8
A17 A14 A13
WE#
A9
A11 NC1 OE# A10 CE#
DQ7 DQ5 DQ6
DQ3 DQ4
DQ2
A0 DQ0 DQ1
V
DD
CE# A16 A18
V
SS
V
SS
A12 A15
A6
A7
A5
A4 NC2 A3
A2
A1
A B
C
D
E
F
G
H
J
Note: For SST39LF020, ball B3 is "No Connect"
For SST39LF010, balls B3 and A5 are "No Connect"
FIGURE 5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit
TABLE 2: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the
sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
VSS
NC
Ground
No Connection
Unconnected pins.
T2.1 1150
1. AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
TABLE 3: Operation Modes Selection
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.4 1150
1. X can be VIL or VIH, but no other value.
©2010 Silicon Storage Technology, Inc.
S71150-14-000
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6
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TABLE 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
5555H AAH 2AAAH 55H 5555H A0H Data
BA2
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
Byte-Program
3
Sector-Erase
SAX
30H
Chip-Erase
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
5555H AAH 2AAAH 55H 5555H 90H
Software ID Entry4,5
Software ID Exit6
Software ID Exit6
XXH
F0H
5555H AAH 2AAAH 55H 5555H F0H
T4.2 1150
1. Address format A14-A0 (Hex),
Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF512.
Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
A
A
MS = Most significant address
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
2. BA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A12 address lines
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST39LF/VF512 Device ID = D4H, is read with A0 = 1,
SST39LF/VF010 Device ID = D5H, is read with A0 = 1,
SST39LF/VF020 Device ID = D6H, is read with A0 = 1,
SST39LF/VF040 Device ID = D7H, is read with A0 = 1.
6. Both Software ID Exit operations are equivalent
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Expo-
sure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range for SST39LF512/010/020/040
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Range
Ambient Temp
VDD
Output Load
Commercial
0°C to +70°C
3.0-3.6V
CL = 30 pF for SST39LF512/010/020/040
CL = 100 pF for SST39VF512/010/020/040
See Figures 15 and 16
Operating Range for SST39VF512/010/020/040
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
7
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TABLE 5: DC Operating Characteristics -VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for
SST39VF512/010/020/0401
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
IDD
Power Supply Current
Address input=VILT/VIHT, at f=1/TRC Min
VDD=VDD Max
Read2
20
30
15
1
mA
mA
µA
µA
µA
V
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
Program and Erase3
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
ISB
ILI
ILO
10
0.8
VIL
VIH
VIHC
VOL
VOH
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
0.7VDD
V
VDD=VDD Max
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
VDD-0.2
V
T5.7 1150
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 3V for VF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
3. 30 mA max for Erase operations in the industrial temperature range.
TABLE 6: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T6.1 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T7.0 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T8.3 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
8
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
AC CHARACTERISTICS
TABLE 9: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for
SST39VF512/010/020/040
SST39LF512-45
SST39LF010-45
SST39LF020-45
SST39LF040-45
SST39VF512-70
SST39VF010-70
SST39VF020-70
SST39VF040-70
SST39LF020-55
SST39LF040-55
Symbol Parameter
Min
Max
Min
Max
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
45
55
70
Chip Enable Access Time
Address Access Time
45
45
30
55
55
30
70
70
35
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
0
0
0
0
ns
ns
1
TCHZ
15
15
15
15
25
25
ns
1
TOHZ
ns
1
TOH
0
0
0
ns
T9.2 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
µs
TBP
Byte-Program Time
20
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
ns
TAH
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
40
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TSCE
Chip-Erase
100
T10.1 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
9
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
T
CE
CE#
T
OE
OE#
WE#
T
OHZ
T
OLZ
V
IH
T
T
OH
T
CLZ
CHZ
HIGH-Z
HIGH-Z
DQ
DATA VALID
DATA VALID
7-0
1150 F03.0
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
A
for SST39LF/VF020 and A for SST39LF/VF040
18
FIGURE 6: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
OE#
CE#
T
AS
T
DS
T
WPH
T
CH
T
CS
DQ
AA
SW0
55
A0
DATA
7-0
SW1
SW2
BYTE
1150 F04.0
(ADDR/DATA)
Note:
A
MS
A
MS
= Most significant address
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
A
for SST39LF/VF020 and A for SST39LF/VF040
18
FIGURE 7: WE# Controlled Program Cycle Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
10
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
OE#
WE#
T
T
T
AS
DS
CPH
T
CH
T
CS
DQ
AA
SW0
55
A0
DATA
7-0
SW1
SW2
BYTE
(ADDR/DATA)
1150 F05.0
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
A
for SST39LF/VF020 and A for SST39LF/VF040
18
FIGURE 8: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
MS-0
T
CE
CE#
T
OEH
T
OES
OE#
WE#
T
OE
D
D#
D#
D
DQ
7
1150 F06.0
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
A
for SST39LF/VF020 and A for SST39LF/VF040
18
FIGURE 9: Data# Polling Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
11
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
ADDRESS A
MS-0
CE#
OE#
WE#
T
CE
T
OEH
T
OES
T
OE
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
A
A
= Most significant address
MS
MS
1150 F07.0
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
A
for SST39LF/VF020 and A for SST39LF/VF040
18
FIGURE 10: Toggle Bit Timing Diagram
T
SIX-BYTE CODE FOR SECTOR-ERASE
5555 5555 2AAA
SE
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW0
SW5
1150 F08.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
SA = Sector Address
X
A
A
= Most significant address
MS
MS
=
A
for SST39LF/VF512, A for SST39LF/VF010, A for SST39LF/VF020, and A for SST39LF/VF040
15 16 17 18
FIGURE 11: WE# Controlled Sector-Erase Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
12
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
T
SIX-BYTE CODE FOR CHIP-ERASE
SCE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
7-0
SW0
SW5
1150 F17.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
A
A
= Most significant address
MS
MS
=
A
for SST39LF/VF512, A for SST39LF/VF010, A for SST39LF/VF020, and A for SST39LF/VF040
15 16 17 18
FIGURE 12: WE# Controlled Chip-Erase Timing Diagram
Three-byte Sequence for
Software ID Entry
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
T
IDA
WP
T
WPH
T
AA
DQ
AA
55
90
BF
Device ID
7-0
SW0
SW1
SW2
1150 F09.2
Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
FIGURE 13: Software ID Entry and Read
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
13
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
14-0
AA
55
F0
DQ
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
WHP
SW0
SW1
SW2
1150 F10.0
FIGURE 14: Software ID Exit and Reset
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1150 F12.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 15: AC Input/Output Reference Waveforms
TO TESTER
TO DUT
C
L
1150 F11.1
FIGURE 16: A Test Load Example
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1150 F13.1
FIGURE 17: Byte-Program Algorithm
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
15
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Byte-Program/
Erase
Byte-Program/
Erase
Byte-Program/
Erase
Initiated
Initiated
Initiated
Read DQ
7
Read byte
Wait T
SCE, or SE
,
T
BP
T
Read same
byte
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1150 F14.0
FIGURE 18: Wait Options
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
16
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Software ID Entry
Software ID Exit &
Command Sequence
Reset Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: F0H
Address: XXH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Wait T
IDA
Load data: 90H
Address: 5555H
Load data: F0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
1150 F15.2
FIGURE 19: Software ID Command Flowcharts
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
17
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Chip-Erase
Sector-Erase
Command Sequence
Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 80H
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 10H
Address: 5555H
Load data: 30H
Address: SA
X
Wait T
Wait T
SE
SCE
Chip erased
to FFH
Sector erased
to FFH
1150 F16.1
FIGURE 20: Erase Command Sequence
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
18
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
PRODUCT ORDERING INFORMATION
SST 39 LF
040
-
45
-
4C
-
NH
E
XX XX XXXX - XXX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
H = 32 leads
K = 48 balls
M = 34 balls (54 possible positions)
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
N = PLCC
M = WFBGA (0.5mm pitch, 4mm x 6mm)
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
Device Density
040 = 4 Mbit
020 = 2 Mbit
010 = 1 Mbit
512 = 512 Kbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder. SST
non-Pb solder devices are RoHS compliant.
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
19
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Valid combinations for SST39LF512
SST39LF512-45-4C-NHE SST39LF512-45-4C-WHE
Valid combinations for SST39VF512
SST39VF512-70-4C-NHE SST39VF512-70-4C-WHE
SST39VF512-70-4I-NHE
SST39VF512-70-4I-WHE
Valid combinations for SST39LF010
SST39LF010-45-4C-NHE SST39LF010-45-4C-WHE SST39LF010-45-4C-B3KE SST39LF010-45-4C-MME
Valid combinations for SST39VF010
SST39VF010-70-4C-NHE SST39VF010-70-4C-WHE SST39VF010-70-4C-B3KE
SST39VF010-70-4I-NHE
SST39VF010-70-4I-WHE
SST39VF010-70-4I-B3KE
Valid combinations for SST39LF020
SST39LF020-45-4C-NHE SST39LF020-45-4C-WHE SST39LF020-45-4C-B3KE SST39LF020-45-4C-MME
SST39LF020-55-4C-NHE SST39LF020-55-4C-WHE
Valid combinations for SST39VF020
SST39VF020-70-4C-NHE SST39VF020-70-4C-WHE SST39VF020-70-4C-B3KE
SST39VF020-70-4I-NHE
SST39VF020-70-4I-WHE
SST39VF020-70-4I-B3KE
Valid combinations for SST39LF040
SST39LF040-45-4C-NHE SST39LF040-45-4C-WHE SST39LF040-45-4C-B3KE
SST39LF040-55-4C-NHE SST39LF040-55-4C-WHE
Valid combinations for SST39VF040
SST39VF040-70-4C-NHE SST39VF040-70-4C-WHE SST39VF040-70-4C-B3KE
SST39VF040-70-4I-NHE
SST39VF040-70-4I-WHE
SST39VF040-70-4I-B3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
20
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.495
.485
.453
.447
.112
.106
Optional
Pin #1
Identifier
.048
.042
.029
.023
.040
.030
.020 R.
MAX.
x 30˚
R.
2
1
32
.042
.048
.021
.013
.400
BSC
.530
.490
.595 .553
.585 .547
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.032
.026
.140
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-3
FIGURE 21: 32-lead Plastic Lead Chip Carrier (PLCC)
SST Package Code: NH
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60
0.80
0.45 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
FIGURE 22: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
21
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
32-tsop-WH-7
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
FIGURE 23: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm
SST Package Code: WH
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
22
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00 0.08
4.00
0.50
0.32 0.05
(34X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00 0.08
2.50
0.50
A B C D E F G H J
J H G F E D C B A
A1 CORNER
A1 INDICATOR4
0.63 0.10
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. No ball is present in position A1; a gold-colored indicator is present.
5. Ball opening size is 0.29 mm ( 0.05 mm)
34-wfbga-MM-4x6-32mic-1
FIGURE 24: 34-ball Very-very-thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm x .63mm
SST Package Code: MM
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
23
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TABLE 11: Revision History
Number
Description
Date
01
02
03
04
Feb 2000
Aug 2000
Feb 2002
Oct 2002
•
•
•
•
•
2000 Data Book
Changed speed from 45 ns to 55 ns for the SST39LF020 and SST39LF040
2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and SST39LF040
Added the B3K package for the 2 Mbit devices
Added footnote in Table 5 to indicate IDD Write is 30 mA max for Erase operations in
the Industrial temperature range.
05
Mar 2003
•
Changes to Table 5 on page 8
– Added footnote for MPF power usage and Typical conditions
– Clarified the Test Conditions for Power Supply Current and Read parameters
– Clarified IDD Write to be Program and Erase
– Corrected IDD Program and Erase from 20 mA to 30 mA
•
•
•
•
•
•
•
•
•
•
Part number changes - see page 20 for additional information
Added new “MM” Micro-Package MPNs for 1M and 2M LF parts- see page 20
2004 Data Book
Added non-Pb MPNs and removed footnote (See page 20)
Updated B3K and MM package diagrams
06
07
Oct 2003
Nov 2003
08
Dec 2005
Added RoHS Compliant statement.
Added 4 MBit to Figure 4.
Revised Absolute Max Stress Ratings for Surface Mount Solder Reflow Temperature
Removed SST39VFxxx-90 Timing Parameters from Figure 9.
Added Footnote and removed Read Access Speed 90 = 90 to Product Ordering Infor-
mation.
•
•
Removed 90 part numbers Valid Combinations lists
09
Jan 2006
Edited page Valid Combinations on page 21. Changed 39LF040-70-4C-B3KE to
39LF040-45-4C-B3KE
10
11
12
13
14
Nov 2008
Feb 2009
Apr 2009
Sep 2009
Jan 2010
•
•
•
•
•
Removed leaded parts
Added package YME
Revised “Product Ordering Information” on page 19
Changed endurance from 10,000 to 100,000 in Product Description, page 1
EOL of SST39LF010-45-4C-YME. Replacement part is SST39LF010-45-4C-MME in
this document.
•
Removed all references to the YME package.
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
24
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