SST39VF1682-70-4I-B3K [SST]
16 Mbit (x8) Multi-Purpose Flash Plus; 16兆位（ X8 ）多用途闪存+
| 型号： | SST39VF1682-70-4I-B3K |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 16 Mbit (x8) Multi-Purpose Flash Plus |
| 文件： | 总29页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit (x8) Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
SST39VF1681 / 16822.7V 16Mb (x8) MPF+ memories
Preliminary Specifications
FEATURES:
•
•
Organized as 2M x8
•
•
Security-ID Feature
Single Voltage Read and Write Operations
– 2.7-3.6V
– SST: 128 bits; User: 128 bits
Fast Read Access Time:
•
•
Superior Reliability
– 70 ns
– 90 ns
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
•
•
Latched Address and Data
Low Power Consumption (typical values at 5 MHz)
Fast Erase and Byte-Program:
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Byte-Program Time: 7 µs (typical)
•
Hardware Block-Protection/WP# Input Pin
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Top Block-Protection (top 64 KByte)
for SST39VF1682
– Bottom Block-Protection (bottom 64 KByte)
for SST39VF1681
– Toggle Bits
– Data# Polling
•
•
Sector-Erase Capability
– Uniform 4 KByte sectors
Block-Erase Capability
•
•
CMOS I/O Compatibility
JEDEC Standard
– Uniform 64 KByte blocks
Chip-Erase Capability
– Flash EEPROM Pinouts and Command sets
Packages Available
•
•
•
•
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
PRODUCT DESCRIPTION
The SST39VF168x devices are 2M x8 CMOS Multi-Pur-
pose Flash Plus (MPF+) manufactured with SST’s propri-
etary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injec-
tor attain better reliability and manufacturability compared
with alternate approaches. The SST39VF168x write (Pro-
gram or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pinouts for x8 mem-
ories.
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
Featuring high performance Byte-Program, the
SST39VF168x devices provide a typical Byte-Program
time of 7 µsec. These devices use Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To pro-
tect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39VF168x are offered in both 48-ball TFBGA and
48-lead TSOP packages. See Figures 1 and 2 for pin
assignments.
The SST39VF168x devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
©2003 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
S71243-03-000
1
11/03
These specifications are subject to change without notice.
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
commands issued during the internal Program operation
are ignored. During the command sequence, WP# should
be statically held high or low.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF168x offer both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 4 KByte. The Block-Erase mode
is based on uniform block size of 64 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (50H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
The SST39VF168x also have the Auto Low Power mode
which puts the device in a near standby mode after data
has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 9 mA to
typically 3 µA. The Auto Low Power mode reduces the typi-
cal IDD active read current to the range of 2 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF168x is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The
data bus is in high impedance state when either CE# or
OE# is high. Refer to the Read cycle timing diagram for
further details (Figure 3).
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Byte-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
Byte-Program Operation
The SST39VF168x are programmed on a byte-by-byte
basis. Before programming, the sector where the byte
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load byte address and byte data. During the Byte-
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed within 10 µs.
See Figures 4 and 5 for WE# and CE# controlled Program
operation timing diagrams and Figure 19 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
2
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 20 for a flowchart.
Chip-Erase Operation
The SST39VF168x provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address AAAH in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 23 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 7 for Toggle Bit timing
diagram and Figure 20 for a flowchart.
Write Operation Status Detection
The SST39VF168x provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
TABLE 1: WRITE OPERATION STATUS
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Status
DQ7 DQ6
DQ2
Normal
Operation Program
Standard
DQ7# Toggle No Toggle
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
Erase-
Read from
Suspend Erase Suspended
Mode
Sector/Block
Read from
Non- Erase Suspended
Sector/Block
Data
Data
Data
Program
DQ7# Toggle
N/A
T1.0 1243
Note: DQ7 and DQ2 require a valid address when reading
Data# Polling (DQ7)
status information.
When the SST39VF168x are in the internal Program oper-
ation, any attempt to read DQ7 will produce the comple-
ment of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
3
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Data Protection
Hardware Reset (RST#)
The SST39VF168x provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 15).
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF168x provide the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. These devices are shipped with the Software
Data Protection permanently enabled. See Table 6 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within TRC.
Hardware Block Protection
The SST39VF1682 supports top hardware block protec-
tion, which protects the top 64 KByte block of the device.
The SST39VF1681 supports bottom hardware block pro-
tection, which protects the bottom 64 KByte block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 64 KByte when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
TABLE 2: BOOT BLOCK ADDRESS RANGES
Common Flash Memory Interface (CFI)
Product
Address Range
000000H-00FFFFH
1F0000H-1FFFFFH
The SST39VF168x also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as product ID entry command with 98H
(CFI Query command) to address AAAH in the last byte
sequence. Once the device enters the CFI Query mode, the
system can read CFI data at the addresses given in Tables
7 through 9. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
Bottom Boot Block
SST39VF1681
Top Boot Block
SST39VF1682
T2.1 1243
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
4
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the software ID Exit/CFI
Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 13 for timing waveform, and Figures 21 and
22 for flowcharts.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF1681 and SST39VF1682, and manufacturer
as SST. Users may use the software Product Identifica-
tion operation to identify the part (i.e., using the device ID)
when using multiple manufacturers in the same socket.
For details, see Table 6 for software operation, Figure 11
for the software ID Entry and Read timing diagram, and
Figure 21 for the software ID Entry command sequence
flowchart.
Security ID
The SST39VF168x devices offer a 256-bit Security ID
space which is divided into two 128-bit segments. The first
segment is programmed and locked at SST with a random
128-bit number. The user segment is left un-programmed
for the customer to program as desired.
TABLE 3: PRODUCT IDENTIFICATION
Address
Data
To program the user segment of the Security ID, the user
must use the Security ID Byte-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
Manufacturer’s ID
Device ID
0000H
BFH
SST39VF1681
SST39VF1682
0001H
0001H
C8H
C9H
T3.1 1243
Product Identification Mode Exit/
CFI Mode Exit
The Security ID space can be queried by executing a
three-byte command sequence with Enter-Sec-ID com-
mand (88H) at address AAAH in the last byte sequence.
Execute the Exit-Sec-ID command to exit this mode. Refer
to Table 6 for more details.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
WP#
I/O Buffers and Data Latches
Control Logic
DQ - DQ
0
RESET#
7
1243 B1.0
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
5
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TOP VIEW (balls facing down)
6
5
4
3
2
1
A14 A13 A15 A16 A17 NC
A10 A9 A11 A12 DQ7 NC
WE# RST# NC A20 DQ5 NC
NC WP# A19 NC DQ2 NC
A0
NC DQ6
DQ4
V
SS
V
DD
NC DQ3
NC DQ1
A8 A18 A7
A6 DQ0 NC
A4
A5
A3
A2
A1 CE# OE# V
SS
A
B
C
D
E F G H
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TFBGA
A17
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
A15
A14
A13
A12
A11
A10
A9
A20
NC
WE#
RST#
NC
WP#
NC
A19
A18
A8
A7
A6
A5
A4
V
A0
SS
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
NC
DD
Die Up
DQ3
NC
DQ2
NC
DQ1
NC
DQ0
OE#
V
SS
CE#
A1
A3
A2
1243 48-tsop P2.0
FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
6
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TABLE 4: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A12 address lines will select the sector.
During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
RST#
CE#
OE#
WE#
VDD
Write Protect
Reset
To protect the top/bottom boot block from Erase/Program operation when grounded.
To reset and return the device to Read mode.
To activate the device when CE# is low.
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
VSS
NC
No Connection
Unconnected pins.
T4.1 1243
1. AMS = Most significant address
MS = A20 for SST39VF1681/1682
A
TABLE 5: OPERATION MODES SELECTION
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector or block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 6
T5.0 1243
1. X can be VIL or VIH, but no other value.
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
7
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TABLE 6: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
AAAH
AAAH
AAAH
AAAH
Data
Addr1
555H
555H
555H
555H
Data Addr1 Data Addr1
Data
Data
AAH
AAH
AAH
Addr1
Data Addr1 Data
BA2
Byte-Program
Sector-Erase
Block-Erase
AAH
AAH
AAH
AAH
55H
55H
55H
55H
AAAH A0H
3
AAAH
AAAH
AAAH
80H
80H
80H
AAAH
AAAH
AAAH
555H
555H
555H
55H
55H
55H
SAX
BAX
50H
30H
10H
3
Chip-Erase
AAAH
Erase-Suspend
Erase-Resume
Query Sec ID4
XXXXH B0H
XXXXH 30H
AAAH
AAAH
AAH
AAH
555H
555H
55H
55H
AAAH
88H
AAAH A5H
BA5
Data
00H
User Security ID
Byte-Program
User Security ID
Program Lock-Out
AAAH
AAH
555H
55H
AAAH
85H
XXH5
Software ID Entry6,7
AAAH
AAAH
AAAH
AAH
AAH
AAH
555H
555H
555H
55H
55H
55H
AAAH
AAAH
90H
98H
CFI Query Entry
Software ID Exit8,9
/CFI Exit/Sec ID Exit
AAAH F0H
Software ID Exit8,9
/CFI Exit/Sec ID Exit
XXH
F0H
T6.1 1243
1. Address format A11-A0 (Hex).
Addresses A20-A12 can be VIL or VIH, but no other value, for Command sequence for SST39VF1681/1682.
2. BA = Program Byte Address
3. SAX for Sector-Erase; uses AMS-A12 address lines
BAX, for Block-Erase; uses AMS-A16 address lines
AMS = Most significant address
AMS = A20 for SST39VF1681/1682
4. With AMS-A5 = 0; Sec ID is read with A4-A0,
SST ID is read with A4 = 0 (Address range = 00000H to 0000FH),
User ID is read with A4 = 1 (Address range = 00010H to 0001FH).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH.
6. The device does not remain in Software Product ID Mode if powered down.
7. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1681 Device ID = C8H, is read with A0 = 1,
SST39VF1682 Device ID = C9H, is read with A0 = 1,
AMS = Most significant address
AMS = A20 for SST39VF1681/1682
8. Both Software ID Exit operations are equivalent
9. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”).
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
8
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
1
TABLE 7: CFI QUERY IDENTIFICATION STRING
Address
10H
11H
12H
13H
14H
15H
16H
17H
Data
51H
52H
59H
01H
07H
00H
00H
00H
00H
00H
00H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T7.1 1243
1. Refer to CFI publication 100 for more details.
TABLE 8: SYSTEM INTERFACE INFORMATION
Address
Data
Data
1BH
27H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
36H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
00H
00H
03H
00H
04H
05H
01H
00H
01H
01H
VPP min. (00H = no VPP pin)
VPP max. (00H = no VPP pin)
Typical time out for Byte-Program 2N µs (23 = 8 µs)
Typical time out for min. size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
Maximum time out for Byte-Program 2N times typical (21 x 23 = 16 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T8.1 1243
TABLE 9: DEVICE GEOMETRY INFORMATION
Address
27H
28H
Data
15H
00H
00H
00H
00H
02H
FFH
01H
10H
00H
1FH
00H
00H
01H
Data
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 00H = x8-only asynchronous interface
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FF = 511
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (1F = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.1 1243
S71243-03-000 11/03
©2003 Silicon Storage Technology, Inc.
9
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
VDD
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
2.7-3.6V
2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
10
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
IDD
Power Supply Current
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read3
18
35
20
20
mA
mA
µA
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
Program and Erase
Standby VDD Current
Auto Low Power
ISB
CE#=VIHC, VDD=VDD Max
IALP
µA
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
WP#=GND to VDD or RST#=GND to VDD
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7VDD
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
IOH=-100 µA, VDD=VDD Min
T10.8 1243
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 17
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T11.0 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T12.0 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T13.2 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
11
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
AC CHARACTERISTICS
TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST39VF168x-70
SST39VF168x-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TCE
Chip Enable Access Time
Address Access Time
70
70
35
90
90
45
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
30
30
ns
1
TOHZ
ns
1
TOH
0
0
ns
1
TRP
500
50
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
20
µs
T14.1 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
µs
TBP
Byte-Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
ns
TAH
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
50
ms
T15.0 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
12
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
WE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1243 F02.0
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
AAA
555
AAA
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
CE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
1243 F03.0
(ADDR/DATA)
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
13
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
T
BP
AAA
555
AAA
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
1243 F04.0
(ADDR/DATA)
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
1243 F05.0
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
14
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
1243 F06.0
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
FIGURE 7: TOGGLE BITS TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
AAA AAA 555
AAA
555
AAA
ADDRESS A
MS-0
CE#
OE#
T
WP
WE#
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
1243 F07.0
SW0
Note: This device also supports CE# controlled Chip-Erase operation.
SW5
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
A
A
MS = Most Significant Address
MS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
15
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
AAA AAA 555
AAA
555
BA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
55
30
SW5
1243 F08.0
SW0
SW3
SW4
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
BAX = Block Address
A
A
MS = Most Significant Address
MS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
16
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
AAA AAA 555
AAA
555
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
AA
55
SW1
80
SW2
AA
SW3
55
SW4
50
SW5
7-0
1243 F9.0
SW0
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
SAX = Sector Address
A
A
MS = Most Significant Address
MS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
17
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
AAA
555
AAA
0000
0001
MS-0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
T
AA
DQ
7-0
55
90
BF
Device ID
1243 F10.1
SW0
SW1
SW2
Note: Device ID - See Table 3 on page 5
A
A
MS = Most Significant Address
MS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 11: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
AAA
555
AAA
MS-0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
T
AA
DQ
7-0
55
98
SW0
SW1
SW2
1243 F11.1
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 12: CFI QUERY ENTRY AND READ
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
18
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
AAA
555
AAA
ADDRESS A
MS-0
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
T
WP
WE#
T
WHP
1243 F12.1
SW0
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
SW1
SW2
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
AAA
555
AAA
MS-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
7-0
AA
55
88
1243 F13.0
SW0
SW1
SW2
Note: AMS = Most Significant Address
MS = A20 for SST39VF168x
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 14: SEC ID ENTRY
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
19
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
T
RP
RST#
T
RHR
1243 F14.0
CE#/OE#
FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
T
RP
RST#
T
RY
CE#/OE#
1243 F15.0
End-of-Write Detection
(Toggle-Bit)
FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
20
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1243 F16.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
V
IHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1243 F17.0
FIGURE 18: A TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
21
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Start
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: A0H
Address: AAAH
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1243 F18.0
X can be V or V , but no other value
IL IH
FIGURE 19: BYTE-PROGRAM ALGORITHM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
22
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1243 F19.0
FIGURE 20: WAIT OPTIONS
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
23
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 98H
Address: AAAH
Load data: 88H
Address: AAAH
Load data: 90H
Address: 5555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read CFI data
Read Sec ID
Read Software ID
X can be V or V , but no other value
IL IH
1243 F20.0
FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
24
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: AAH
Address: AAAH
Load data: F0H
Address: XXH
Load data: 55H
Address: 555H
Wait T
IDA
Load data: F0H
Address: AAAH
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V but no other value
IL
IH,
1243 F21.0
FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
25
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 80H
Address: AAAH
Load data: 80H
Address: AAAH
Load data: 80H
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 10H
Address: AAAH
Load data: 50H
Load data: 30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1243 F22.0
X can be V or V , but no other value
IL IH
FIGURE 23: ERASE COMMAND SEQUENCE
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
26
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
PRODUCT ORDERING INFORMATION
SST 39 VF 1681
-
70
-
4C
-
B3K
E
XX XX XXXX - XXX
-
XX - XXX
X
Environmental Attribute
E = non-Pb
Package Modifier
K = 48 leads
Package Type
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
E = TSOP (type1, die up, 12mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
168 = 16 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
Valid Combinations for SST39VF1681
SST39VF1681-70-4C-EK
SST39VF1681-70-4C-EKE
SST39VF1681-70-4C-B3K
SST39VF1681-70-4C-B3KE
SST39VF1681-70-4I-EK
SST39VF1681-70-4I-EKE
SST39VF1681-90-4I-EK
SST39VF1681-90-4I-EKE
SST39VF1681-70-4I-B3K
SST39VF1681-70-4I-B3KE
Valid Combinations for SST39VF1682
SST39VF1682-70-4C-EK
SST39VF1682-70-4C-EKE
SST39VF1682-70-4C-B3K
SST39VF1682-70-4C-B3KE
SST39VF1682-70-4I-EK
SST39VF1682-70-4I-EKE
SST39VF1682-90-4I-EK
SST39VF1682-90-4I-EKE
SST39VF1682-70-4I-B3K
SST39VF1682-70-4I-B3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
27
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
28
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60
0.80
0.45 0.05
(48X)
6
5
4
3
2
1
6
5
4
4.00
0.80
6.00 0.20
3
2
1
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
TABLE 16: REVISION HISTORY
Number
00
Description
Date
May 2003
Sep 2003
Oct 2003
•
•
•
•
•
•
Initial release
01
Change product number from 166x to 168x
Added B3K package and associated MPNs (See page 27)
Removed 90 ns Commercial temperature for the EK and EKE packages
2004 Data Book
02
03
Nov 2003
Updated B3K package diagram
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
29
相关型号：
SST39VF1682-70-4I-EKE
2M X 8 FLASH 2.7V PROM, 70 ns, PDSO48, 12 X 20 MM, LEAD FREE, MO-142DD, TSOP1-48
MICROCHIP
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