SST39VF800-70-4C-EK [SST]
8 Megabit (512K x 16-Bit) Multi-Purpose Flash; 8兆位（ 512K ×16位）多用途闪存
| 型号： | SST39VF800-70-4C-EK |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 8 Megabit (512K x 16-Bit) Multi-Purpose Flash |
| 文件： | 总23页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8 Megabit (512K x 16-Bit) Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
FEATURES:
•
•
•
Organized as 512 K X 16
•
•
Latched Address and Data
Fast Sector Erase and Word Program:
1
Single 2.7-3.6V Read and Write Operations
-
-
-
-
-
Sector Erase Time: 18 ms (typical)
Block Erase Time: 18 ms (typical)
Chip Erase Time: 70 ms (typical)
Word Program time: 14 µs (typical)
Chip Rewrite Time: 8 seconds (typical)
V
DDQ Power Supply to Support 5V I/O
for SST39VF800Q
2
-
VDDQ not available on SST39VF800
•
•
Superior Reliability
-
-
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
3
•
•
Automatic Write Timing
Internal VPP Generation
End of Write Detection
-
Low Power Consumption:
4
-
-
-
Active Current: 15 mA (typical)
Standby Current: 3 µA (typical)
Auto Low Power Mode: 3 µA (typical)
-
-
Toggle Bit
Data# Polling
•
•
CMOS I/O Compatibility
•
•
•
Small Sector Erase Capability (256 sectors)
Uniform 2 KWord sectors
Block Erase Capability (16 blocks)
Uniform 32 KWord blocks
Fast Read Access Time:
70 and 90 ns
5
JEDEC Standard
-
-
Flash EEPROM Pinouts and command sets
6
•
Packages Available
-
-
-
48-Pin TSOP (12mm x 20mm)
6 x 8 Ball TFBGA
-
7
PRODUCT DESCRIPTION
herentlyuselessenergyduringEraseandProgramthan
alternative flash technologies. The total energy con-
sumed is a function of the applied voltage, current, and
timeofapplication.Sinceforanygivenvoltagerange,the
SuperFlashtechnologyuseslesscurrenttoprogramand
has a shorter erase time, the total energy consumed
during any Erase or Program operation is less than
alternative flash technologies. The SST39VF800Q/
VF800 also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SST39VF800Q/VF800 devices are 512K x 16
CMOS Multi-Purpose Flash (MPF) manufactured with
SST’sproprietary,highperformanceCMOSSuperFlash
technology. The split-gate cell design and thick oxide
tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST39VF800Q/VF800 write (Program or Erase)
with a 2.7-3.6V power supply. The SST39VF800Q/
VF800 conform to JEDEC standard pinouts for x16
memories.
8
9
10
11
12
13
14
15
16
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose erase and program times increase with
accumulated Erase/Program cycles.
Featuring high performance word program, the
SST39VF800Q/VF800 devices provide a typical word
program time of 14 µsec. The entire memory can typi-
cally be erased and programmed word-by-word in 8
seconds, when using interface features such as Toggle
BitorData#PollingtoindicatethecompletionofProgram
operation. To protect against inadvertent write, the
SST39VF800Q/VF800haveon-chiphardwareandsoft-
ware data protection schemes. Designed, manufac-
tured,andtestedforawidespectrumofapplications,the
SST39VF800Q/VF800 are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
To meet high density, surface mount requirements, the
SST39VF800Q/VF800 are offered in 48-pin TSOP and
48-pin TFBGA packages. See Figures 1 and 2 for
pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
deviceusingstandardmicroprocessorwritesequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first.
The SST39VF800Q/VF800 devices are suited for appli-
cationsthatrequireconvenientandeconomicalupdating
of program, configuration, or data memory. For all sys-
tem applications, the SST39VF800Q/VF800 signifi-
cantly improve performance and reliability, while lower-
ing power consumption. The SST39VF800Q/VF800 in-
© 1999 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
343-04 2/99 These specifications are subject to change without notice.
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
The SST39VF800Q/VF800 also have the Auto Low
Powermodewhichputsthedeviceinanearstandbymode
after data has been accessed with a valid read operation.
This reduces the IDD active read current from typically 15
mA to typically 3 µA. The Auto Low Power mode reduces
thetypicalIDD activereadcurrenttotherangeof1mA/MHz
of read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transi-
tionusedtoinitiateanotherreadcycle,withnoaccesstime
penalty.
byte command sequence with Block Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A15-A18 are used to determine the block
address. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command
(30Hor50H)islatchedontherisingedgeofthesixthWE#
pulse. The internal Erase operation begins after the sixth
WE#pulse.TheendofEraseoperationcanbedetermined
using either Data# Polling or Toggle Bit methods. See
Figures 9 and 10 for timing waveforms. Any commands
issued during the Sector or Block Erase operation are
ignored.
Read
The Read operation of the SST39VF800Q/VF800 is con-
trolledbyCE#andOE#,bothhavetobelowforthesystem
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
onlystandbypowerisconsumed.OE#istheoutputcontrol
andisusedtogatedatafromthe outputpins.Thedatabus
isinhighimpedancestatewheneitherCE#orOE#ishigh.
Refer to the Read cycle timing diagram for further details
(Figure 3).
Chip Erase Operation
The SST39VF800Q/VF800 provide a Chip Erase opera-
tion,whichallowstheusertoerasetheentirememoryarray
to the “1” state. This is useful when the entire device must
be quickly erased.
The Chip Erase operation is initiated by executing a six-
byte command sequence with Chip Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation,theonlyvalidreadisToggleBitorData#Polling.
SeeTable4forthecommandsequence,Figure8fortiming
diagram, and Figure 19 for the flowchart. Any commands
issued during the Chip Erase operation are ignored.
Word Program Operation
The SST39VF800Q/VF800 are programmed on a word-
by-word basis. The Program operation consists of three
steps. The first step is the three-byte load sequence for
SoftwareDataProtection. Thesecondstepistoloadword
address and word data. During the Word Program opera-
tion,theaddressesarelatchedonthefallingedgeofeither
CE#orWE#,whicheveroccurslast.Thedataislatchedon
the rising edge of either CE# or WE#, whichever occurs
first.ThethirdstepistheinternalProgramoperationwhich
is initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed within 20 µs. See Figures 4 and 5
for WE# and CE# controlled Program operation timing
diagrams and Figure 16 for flowcharts. During the Pro-
gramoperation, theonlyvalidreadsareData#Pollingand
ToggleBit.DuringtheinternalProgramoperation,thehost
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Write Operation Status Detection
The SST39VF800Q/VF800 provide two software means
to detect the completion of a write (Program or Erase)
cycle, inordertooptimizethesystemwritecycletime. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising edge of WE#, which
initiates the internal program or erase operation.
Theactualcompletionofthenonvolatilewriteisasynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflictwitheitherDQ7orDQ6.Inordertopreventspurious
rejection, if an erroneous result occurs, the software rou-
tineshouldincludealooptoreadtheaccessedlocationan
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Sector/Block Erase Operation
The Sector/Block Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST39VF800Q/VF800 offer both small Sector
Erase and Block Erase mode. The sector architecture is
basedonuniformsectorsizeof2KWord.TheBlockErase
mode is based on uniform block size of 32 KWord. The
SectorEraseoperationisinitiatedbyexecutingasix-byte-
command sequence with Sector Erase command (30H)
andsectoraddress(SA)inthelastbuscycle. Theaddress
lines A11-A18 are used to determine the sector address.
The Block Erase operation is initiated by executing a six-
Data# Polling (DQ7)
When the SST39VF800Q/VF800 are in the internal Pro-
gram operation, any attempt to read DQ7 will produce the
complementofthetruedata. OncetheProgramoperation
is completed, DQ7 will produce true data. The device is
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
2
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Common Flash Memory Interface (CFI)
then ready for the next operation. During internal Erase
operation,anyattempttoreadDQ7willproducea‘0’.Once
the internal Erase operation is completed, DQ7 will pro-
duce a ‘1’. The Data# Polling is valid after the rising edge
of fourth WE# (or CE#) pulse for Program operation. For
Sector,BlockorChipErase,theData#Pollingisvalidafter
the rising edge of sixth WE# (or CE#) pulse. See Figure 6
for Data# Polling timing diagram and Figure 17 for a
flowchart.
The SST39VF800Q/VF800 also contain the CFI informa-
tion to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write three-
byte sequence, same as product ID entry command with
98H (CFI Query command) to address 5555H in the last
byte sequence. Once the device enters the CFI Query
mode,thesystemcanreadCFIdataattheaddressesgiven
in tables 5 through 7. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
1
2
3
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1’s
and 0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector,
Block or Chip Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Product Identification
4
The Product Identification mode identifies the devices as
the SST39VF800Q, SST39VF800 and manufacturer as
SST.Thismodemaybeaccessedbyhardwareorsoftware
operations. The hardware operation is typically used by a
programmer to identify the correct algorithm for the
SST39VF800Q/VF800. Users may wish to use the Soft-
ware Product Identification operation to identify the part
(i.e., using the device code) when using multiple manufac-
turers in the same socket. For details, see Table 3 for
hardware operation or Table 4 for software operation,
Figure 11 for the Software ID Entry and Read timing
diagramandFigure18fortheIDEntrycommandsequence
flowchart.
5
6
7
Data Protection
The SST39VF800Q/VF800 provide both hardware and
softwarefeaturestoprotectnonvolatiledatafrominadvert-
ent writes.
8
TABLE 1: PRODUCT IDENTIFICATION TABLE
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
Address
0000H
Data
00BFH
2781H
9
Manufacturer’s Code
Device Code
0001H
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
10
11
12
13
14
15
16
343 PGM T1.0
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command se-
quence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
notreadcorrectly.PleasenotethattheSoftwareIDExit/CFI
Exit command is ignored during an internal Program or
Eraseoperation.SeeTable4forsoftwarecommandcodes,
Figure13fortimingwaveformandFigure18foraflowchart.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
highwillinhibittheWriteoperation.Thispreventsinadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
TheSST39VF800Q/VF800providetheJEDECapproved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down.AnyEraseoperationrequirestheinclusionof
six-byte sequence. The SST39VF800Q/VF800 devices
areshippedwiththesoftwaredataprotectionpermanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode within TRC. The
contents of DQ15-DQ8 are “Don’t Care” during any SDP
command sequence.
VDDQ - I/O Power Supply
This feature is available only on the SST39VF800Q. This
pinfunctionsaspowersupplypinforinput/outputbuffers. It
should be tied to VDD (2.7-3.6V) in a 3.0V-only system. It
should be tied to a 5.0V±10% (4.5-5.5V) power supply in a
mixed voltage system environment where flash memory
has to be interfaced with 5V system chips. The VDDQ pin is
not offered on the SST39VF800, instead it is a No Connect
pin.
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
3
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
FUNCTIONAL BLOCK DIAGRAM
8,388,608 bit
EEPROM
Cell Array
X-Decoder
A
- A
0
18
Address Buffer & Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ - DQ
15
V
0
DDQ
343 ILL B1.0
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
2
2
DDQ
3
V
3
V
SS
SS
4
DQ15
DQ7
4
DQ15
DQ7
5
5
6
DQ14
DQ6
6
DQ14
DQ6
7
7
A8
8
DQ13
DQ5
A8
8
DQ13
DQ5
Standard Pinout
Standard Pinout
Top View
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
9
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
Top View
Die Up
V
V
DD
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A6
A6
A5
A5
A4
A4
A3
V
A3
V
SS
SS
A2
CE#
A2
CE#
A1
A0
A1
A0
SST39VF800Q
SST39VF800
343 ILL1.0
343 ILL1a.0
FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES
A
B
C
D
E
F
A
B
C
D
E
F
TOP
TOP
VIEW
VIEW
1
2
3
4
5
6
7
8
1
A3
A4
A2
A1
A7
NC WE# A9
NC A8
A13
A12
A3
A4
A2
A1
A7
NC WE# A9
NC A8
A13
A12
2
3
4
5
6
7
8
A17 NC
A17 NC
A6
A5
A18 NC A10 A14
NC NC A11 A15
A6
A5
A18 NC A10 A14
NC NC A11 A15
A0 DQ0 DQ2 DQ5 DQ7 A16
CE# DQ8 DQ10 DQ12 DQ14 V
A0 DQ0 DQ2 DQ5 DQ7 A16
CE# DQ8 DQ10 DQ12 DQ14 NC
DDQ
OE# DQ9 DQ11
V
DQ13 DQ15
DD
OE# DQ9 DQ11
V
DQ13 DQ15
DD
V
DQ1 DQ3 DQ4 DQ6
V
SS
V
DQ1 DQ3 DQ4 DQ6
V
SS
SS
SS
SST39VF800Q
SST39VF800
343 ILL2.3
343 ILL2a.2
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
4
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A18-A0
Address Inputs
To provide memory addresses. During sector erase A18-A11 address lines
will select the sector. During block erase A18-A15 address lines will select
the block.
1
DQ15-DQ0
Data Input/output
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
2
CE#
OE#
WE#
VDD
Chip Enable
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations.
3
Output Enable
Write Enable
4
Power Supply
I/O Power Supply
To provide 3-volt supply (2.7-3.6V)
VDDQ
Supplies power for input/output buffers. It should be either tied to VDD
(2.7 - 3.6V) for 3V I/O or to a 5.0V (4.5 - 5.5V) power supply to
support 5V I/O. (Not offered on SST39VF800 device, instead it is a NC)
5
Vss
NC
Ground
No Connection
Unconnected pins.
6
343 PGM T2.0
TABLE 3: OPERATION MODES SELECTION
7
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
A9 DQ
AIN DOUT
AIN DIN
Address
AIN
8
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
X
X
Sector or block address,
XXh for chip erase
X
9
Standby
VIH
X
X
X
X
X
X
High Z
Write Inhibit
VIL
X
X
High Z/ DOUT
High Z/ DOUT
X
X
X
VIH
10
11
12
13
14
15
16
Product Identification
Hardware Mode
VIL
VIL
VIL
VIL
VIH
VIH
VH Manufacturer Code (00BF) A18 - A1 = VIL, A0 = VIL
Device Code (2781)
A18 - A1 = VIL, A0 = VIH
See Table 4
Software Mode
AIN
343 PGM T3.0
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
5
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
Addr(1) Data Addr(1) Data
2nd Bus
Write Cycle
3rd Bus
Write Cycle
Addr(1) Data Addr(1) Data
4th Bus
Write Cycle
5th Bus
Write Cycle
Addr(1) Data Addr(1) Data
6th Bus
Write Cycle
Word Program
Sector Erase
Block Erase
Chip Erase
5555H AAH
5555H AAH
5555H AAH
5555H AAH
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
5555H A0H
5555H 80H
5555H 80H
5555H 80H
5555H 90H
5555H 98H
WA(3)
Data
5555H AAH
5555H AAH
5555H AAH
2AAAH 55H SAx(2)
2AAAH 55H BAx(2)
30H
50H
2AAAH 55H 5555H 10H
Software ID Entry 5555H AAH
CFI Query Entry
5555H AAH
XXH F0H
Software ID Exit/
CFI Exit
Software ID Exit/
CFI Exit
5555H AAH
2AAAH 55H
5555H F0H
343 PGM T4.0
(1)
Notes:
Address format A14-A0 (Hex), Addresses A15, A16, A17 and A18 are “Don’t Care” for Command sequence.
(2)
SAx for Sector Erase; uses A18-A11 address lines
BAx, for Block Erase; uses A18-A15 address lines
(3)
(4)
(5)
WA = Program word address
Both Software ID Exit operations are equivalent
DQ15 - DQ8 are “Don’t Care” for Command sequence
Notes for Software ID Entry Command Sequence
1. With A18 -A1 =0; SST Manufacturer Code = 00BFH, is read with A0 = 0,
SST39VF800Q/VF800 Device Code = 2781H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
1
TABLE 5: CFI QUERY IDENTIFICATION STRING
Address
Data
Data
10H
11H
12H
0051H
0052H
0059H
Query Unique ASCII string “QRY”
Primary OEM command set
13H
14H
0001H
0007H
15H
16H
0000H
0000H
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
17H
18H
0000H
0000H
19H
1AH
0000H
0000H
343 PGM T5.1
Note 1: Refer to CFI publication 100 for more details.
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
6
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 6: SYSTEM INTERFACE INFORMATION
Address
Data
Data
1BH
0027H
VDD Min. (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: millivolts
1
1CH
0036H
VDD Max. (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: millivolts
2
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
VPP min. (00H = no VPP pin)
VPP max. (00H = no VPP pin)
3
Typical time out for Word Program 2N µs (24 = 16 µs)
Typical time out for min. size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block Erase 2N ms (24 = 16 ms)
Typical time out for Chip Erase 2N ms (26 = 64 ms)
Maximum time out for Word Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
4
5
Maximum time out for individual Sector/Block Erase 2N times typical
(21 x 24 = 32 ms)
6
26H
0001H
Maximum time out for Chip Erase 2N times typical (21 x 26 = 128 ms)
343 PGM T6.2
7
TABLE 7: DEVICE GEOMETRY INFORMATION
8
Address
Data
Data
27H
0014H
Device size = 2N Bytes (14H = 20; 220 = 1M Bytes)
28H
29H
0001H
0000H
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
9
2AH
2BH
0000H
0000H
10
11
12
13
14
15
16
2CH
0002H
2DH
2EH
2FH
30H
00FFH
0000H
0010H
0000H
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 255 + 1 = 256 sectors (00FFH = 255)
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H
32H
33H
34H
000FH
0000H
0000H
0001H
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 15 + 1 = 16 blocks (000FH = 15)
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
343 PGM T7.2
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
7
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ...................................................................... -0.5V to VDDQ (2) + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential.................................................. -1.0V to VDDQ (2) + 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
(2) The absolute maximum stress ratings for SST39VF800 are referenced to VDD
.
OPERATING RANGE
Range
Ambient Temp
0 °C to +70 °C
-40 °C to +85 °C
VDD
VDDQ
Commercial
Industrial
2.7 - 3.6V
2.7 - 3.6V
VDD or 4.5 - 5.5V
VDD or 4.5 - 5.5V
AC CONDITIONS OF TEST
Input Rise/Fall Time......... 10 ns
Output Load..................... CL = 100 pF
See Figures 14 and 15
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
8
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V AND VDDQ = VDD OR 4.5V - 5.5V
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
1
IDD
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Address input = VIL/VIH, at f=1/TRC Min.
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max.
Read
20
25
mA
mA
Program and Erase
2
ISB
Standby VDD Current
Auto Low Power Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
10
1
µA
µA
µA
µA
V
CE#=VIHC, VDD = VDD Max.
CE#=VIHC, VDD = VDD Max.
VIN =GND to VDD, VDD = VDD Max.
VOUT =GND to VDD, VDD = VDD Max.
VDD = VDD Min.
IALP
ILI
3
ILO
1
VIL
0.8
4
VILC
VIH
VIHC
VOL
VOH
VH
Input Low Voltage (CMOS)
Input High Voltage
0.3
2.0
V
VDD = VDD Max.
V
VDD = VDD Max.
5
Input High Voltage (CMOS) VDD-0.3
Output Low Voltage
V
VDD = VDD Max.
0.4
V
IOL = 100 µA, VDD = VDD Min.
IOH = -100 µA, VDD = VDD Min.
CE# = OE# =VIL, WE# = VIH
CE# = OE# = VIL, WE# = VIH, A9 = VH Max.
Output High Voltage
2.4
V
6
Supervoltage for A9 pin
11.4
12.6
200
V
IH
Supervoltage Current
for A9 pin
µA
7
343 PGM T9.1
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
8
Symbol
Parameter
Minimum
Units
(1)
TPU-READ
Power-up to Read Operation
100
100
µs
µs
(1)
9
TPU-WRITE
Power-up to Program/Erase
Operation
343 PGM T10.0
10
11
12
13
14
15
16
TABLE 10: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
(1)
CI/O
I/O Pin Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6 pF
343 PGM T11.1
Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
(1)
NEND
Endurance
10,000
100
Cycles
Years
Volts
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
(1)
TDR
Data Retention
(1)
VZAP_HBM
ESD Susceptibility
Human Body Model
1000
(1)
VZAP_MM
ESD Susceptibility
Machine Model
200
Volts
mA
JEDEC Standard A115
JEDEC Standard 78
(1)
ILTH
Latch Up
100 + IDD
343 PGM T12.1
Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
9
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
AC CHARACTERISTICS
TABLE 12: SST39VF800Q/VF800 READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST39VF800Q/VF800-70 SST39VF800Q/VF800-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
Read Cycle time
70
90
ns
TCE
Chip Enable Access Time
Address Access Time
70
70
30
90
90
40
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
(1)
TCLZ
0
0
0
0
ns
(1)
TOLZ
ns
ns
(1)
TCHZ
20
20
30
30
(1)
TOHZ
ns
(1)
TOH
0
0
ns
343 PGM T13.0
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word Program time
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
20
TAS
0
30
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
TWPH (1)
TCPH (1)
TDS
ns
ns
ns
TDH (1)
TIDA (1)
TSE
Data Hold Time
ns
Software ID Access and Exit Time
Sector Erase
150
25
ns
ms
ms
ms
343 PGM T14.1
TBE
Block Erase
25
TSCE
Chip Erase
100
Note 1: This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
10
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
T
T
AA
RC
ADDRESS A
18-0
2
T
CE
CE#
OE#
3
T
OE
4
T
T
OHZ
V
OLZ
IH
WE#
5
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
6
343 ILL3.0
7
FIGURE 3: READ CYCLE TIMING DIAGRAM
8
9
INTERNAL PROGRAM OPERATION STARTS
T
BP
10
11
12
13
14
15
16
5555
2AAA
5555
ADDR
ADDRESS A
18-0
T
AH
T
DH
T
WP
WE#
OE#
CE#
T
T
AS
DS
T
WPH
T
CH
T
CS
DQ
15-0
XXAA
XX55
SW1
XXA0
SW2
DATA
SW0
WORD
(ADDR/DATA)
343 ILL4.0
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
11
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
18-0
CE#
T
AH
T
DH
T
CP
T
T
AS
DS
T
CPH
OE#
T
CH
WE#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
343 ILL5.0
(ADDR/DATA)
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
18-0
T
CE
CE#
T
OES
T
OEH
OE#
WE#
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
343 ILL6.1
FIGURE 6: DATA# POLLING TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
12
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
ADDRESS A
18-0
2
T
CE
CE#
3
T
OES
T
T
OE
OEH
OE#
WE#
4
5
DQ
6
6
TWO READ CYCLES
WITH SAME OUTPUTS
343 ILL7.1
7
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
8
9
T
SCE
SIX-BYTE CODE FOR CHIP ERASE
5555 5555 2AAA
10
11
12
13
14
15
16
5555
2AAA
5555
ADDRESS A
18-0
CE#
OE#
T
WP
WE#
DQ
7-0
AA
55
80
AA
55
10
SW0
SW1
SW2
SW3
SW4
SW5
343 ILL8.0
Note: The device also supports CE# controlled chip erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
FIGURE 8: WE# CONTROLLED CHIP ERASE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
13
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
T
BE
SIX-BYTE CODE FOR BLOCK ERASE
5555 5555 2AAA
5555
2AAA
BA
X
ADDRESS A
18-0
CE#
OE#
T
WP
WE#
DQ
7-0
AA
55
80
AA
55
50
SW0
SW1
SW2
SW3
SW4
SW5
343 ILL17.0
Note: The device also supports CE# controlled block erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
BAX = Block Address
FIGURE 9: WE# CONTROLLED BLOCK ERASE TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR ERASE
2AAA 5555 5555 2AAA
5555
SA
X
ADDRESS A
18-0
CE#
OE#
T
WP
WE#
DQ
7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
343 ILL18.0
Note: The device also supports CE# controlled sector erase operation. The WE# and CE# signals
are interchangeable as long as minimum timings are met. (See Table 13)
SAX = Sector Address
FIGURE 10: WE# CONTROLLED SECTOR ERASE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
14
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
2
14-0
3
CE#
4
OE#
WE#
T
IDA
T
WP
5
T
WPH
XX55
SW1
T
AA
DQ
6
15-0
XXAA
SW0
XX90
SW2
00BF
2781
343 ILL9.1
7
FIGURE 11: SOFTWARE ID ENTRY AND READ
8
9
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
10
11
12
13
14
15
16
ADDRESS A
5555
2AAA
5555
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
XX55
SW1
T
AA
DQ
15-0
XXAA
SW0
XX98
SW2
343 ILL20.1
FIGURE 12: CFI QUERY ENTRY AND READ
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
15
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
14-0
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
343 ILL10.0
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
16
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
V
IHT
1
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
2
V
ILT
343 ILL11.0
3
AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT–VHIGH Test
VLT–VLOW Test
4
VIHT–VINPUT HIGH Test
V
ILT–VINPUT LOW Test
5
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
6
7
TEST LOAD EXAMPLE
8
V
DD
TO TESTER
9
R
L HIGH
10
11
12
13
14
15
16
TO DUT
C
L
R
L LOW
343 ILL12.0
FIGURE 15: A TEST LOAD EXAMPLE
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
17
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Start
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: A0
Address: 5555
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
343 ILL13.1
FIGURE 16: WORD PROGRAM ALGORITHM
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
18
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
2
Program/Erase
Initiated
Program/Erase
Initiated
3
Read DQ
7
Read word
4
Wait T
,
BP
T
T
SCE, SE
or T
BE
5
Read same
word
Is DQ =
7
No
true data?
6
Program/Erase
Completed
Yes
7
No
Does DQ
match?
Program/Erase
Completed
6
8
Yes
9
Program/Erase
Completed
343 ILL14.1
10
11
12
13
14
15
16
FIGURE 17: WAIT OPTIONS
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
19
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
CFI Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXF0
Address: XX
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Wait T
IDA
Write data: XX98
Address: 5555
Write data: XX90
Address: 5555
Write data: XXF0
Address: 5555
Return to normal
operation
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read CFI data
Read Software ID
343 ILL15.0
FIGURE 18: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
20
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Chip Erase
Command Sequence
Sector Erase
Command Sequence
Block Erase
Command Sequence
1
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
2
3
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
4
Write data: XX80
Address: 5555
Write data: XX80
Address: 5555
Write data: XX80
Address: 5555
5
6
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
7
8
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
9
Write data: XX10
Address: 5555
Write data: XX30
Write data: XX50
10
11
12
13
14
15
16
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFH
Sector erased
to FFH
Block erased
to FFH
343 ILL16.1
FIGURE 19: ERASE COMMAND SEQUENCE
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
21
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Device
Speed Suffix1
- XXX XX
Suffix2
SST39VF800Q
-
-
XX
Package Modifier
K = 48 leads
Numeric = Die modifier
Package Type
E = TSOP (12mm x 20mm)
B = TFBGA (0.8 mm pitch; 8mm x 10mm)
U = Unencapsulated die
Temperature Range
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns, 90 = 90 ns
Version
Q = VDDQ pin for I/O power supply
Voltage
V = 2.7-3.6V
SST39VF800Q Valid combinations
SST39VF800Q-70-4C-EK
SST39VF800Q-70-4C-BK
SST39VF800Q-90-4C-EK
SST39VF800Q-90-4C-BK
SST39VF800Q-90-4C-U1
SST39VF800Q-70-4I-EK
SST39VF800Q-90-4I-EK
SST39VF800Q-70-4I-BK
SST39VF800Q-90-4I-BK
SST39VF800 Valid combinations
SST39VF800-70-4C-EK
SST39VF800-70-4C-BK
SST39VF800-90-4C-EK
SST39VF800-90-4C-BK
SST39VF800-90-4C-U1
SST39VF800-70-4I-EK
SST39VF800-90-4I-EK
SST39VF800-70-4I-BK
SST39VF800-90-4I-BK
Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
22
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
PACKAGING DIAGRAMS
1.05
0.95
1.10
0.90
PIN # 1 IDENT. DIA. 1.00
1
.50
BSC
2
.270
.170
3
12.20
11.80
4
5
0.15
0.05
18.50
18.30
6
0.70
0.50
20.20
19.80
7
Note:
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
48.TSOP-EK-ILL.0
8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: EK
9
BOTTOM VIEW
PIN 1 CORNER
0.30 ± 0.05 (48X)
TOP VIEW
PIN 1 CORNER
10
11
12
13
14
15
16
1
2 3 4 5 6
6
5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
0.80
4.00
SIDE VIEW
8.00 ± 0.20
SEATING PLANE
48pn TFBGA.8x10-ILL.2
48-BALL THIN FINE-PITCH BALL GRID ARRAY (TFBGA)
SST PACKAGE CODE: BK
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
23
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