SST89E564RD-25-I-TQJ [SST]
FlashFlex51 MCU; FlashFlex51 MCU
| 型号： | SST89E564RD-25-I-TQJ |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | FlashFlex51 MCU |
| 文件： | 总62页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
SST89E/V564RD SST89E/VE554RC FlashFlex51 MCU
Preliminary Specifications
FEATURES:
•
8-bit 8051 Family Compatible Microcontroller
(MCU) with Embedded SuperFlash Memory
•
•
•
Three High-Current Drive Pins (16 mA each)
Three 16-bit Timers/Counters
•
SST89E564RD/SST89E554RC is 5V Operation
– 0 to 40 MHz Operation at 5V
Full-Duplex Enhanced UART
– Framing error detection
•
•
SST89V564RD/SST89V554RC is 3V Operation
– 0 to 25 MHz Operation at 3V
– Automatic address recognition
•
•
•
•
•
•
•
•
•
•
Nine Interrupt Sources at 4 Priority Levels
Watchdog Timer (WDT)
Fully Software and Development Toolset
Compatible as well as Pin-For-Pin Package
Compatible with Standard 8xC5x Microcontrollers
Programmable Counter Array (PCA)
Four 8-bit I/O Ports (32 I/O Pins)
Second DPTR register
•
•
1 KByte Register/Data RAM
Dual Block SuperFlash EEPROM
Reduce EMI Mode (Inhibit ALE through AUXR SFR)
SPI Serial Interface
– SST89E564RD/SST89V564RD: 64 KByte pri-
mary block + 8 KByte secondary block
(128-Byte sector size)
– SST89E554RC/SST89V554RC: 32 KByte pri-
mary block + 8 KByte secondary block
(128-Byte sector size)
– Individual Block Security Lock
– Concurrent Operation during In-Application
Programming (IAP)
TTL- and CMOS-Compatible Logic Levels
Brown-out Detection
Extended Power-Saving Modes
– Idle Mode
– Power Down Mode with External Interrupt Wake-up
– Standby (Stop Clock) Mode
•
•
PDIP-40, PLCC-44 and TQFP-44 Packages
Temperature Ranges:
– Block Address Re-mapping
•
Support External Address Range up to 64
KByte of Program and Data Memory
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
firmware for SST’s device. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
In-Application Programming (IAP) operation. The device is
designed to be programmed “In-System” and “In-Applica-
tion” on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of bootstrap
loader in the memory, demonstrating the initial user pro-
gram code loading or subsequent user code updating via
the “IAP” operation. An example of bootstrap loader is for
the user’s reference and convenience only. SST does not
guarantee the functionality or the usefulness of the sample
bootstrap loader. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
PRODUCT DESCRIPTION
SST89E564RD, SST89V564RD, SST89E554RC, and
SST89V554RC are members of the FlashFlex51 family of 8-
bit microcontrollers. The FlashFlex51 is a family of microcon-
troller products designed and manufactured on the state-of-
the-art SuperFlash CMOS semiconductor process technol-
ogy. The device uses the same powerful instruction set and
is pin-for-pin compatible with standard 8xC5x microcontroller
devices.
The device comes with 72/40 KByte of on-chip flash
EEPROM program memory using SST’s patented and pro-
prietary CMOS SuperFlash EEPROM technology with the
SST’s field-enhancing, tunneling injector, split-gate mem-
ory cells. The SuperFlash memory is partitioned into 2
independent program memory blocks. The primary Super-
Flash Block 0 occupies 64/32 KByte of internal program
memory space and the secondary SuperFlash Block 1
occupies 8 KByte of internal program memory space. The
8-KByte secondary SuperFlash block can be mapped to
the lowest location of the 64/32 KByte address space; it
can also be hidden from the program counter and used as
an independent EEPROM-like data memory. The flash
memory blocks can be programmed via a standard 87C5x
OTP EPROM programmer fitted with a special adapter and
In addition to 72/40 KByte of SuperFlash EEPROM pro-
gram memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 1024 x 8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST’s highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S71207-00-000 9/01
1
555
FlashFlex, In-Application Programming, IAP, and SoftLock are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE OF CONTENTS
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.1 Reset Configuration of Program Memory Block Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Dual Data Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 External Host Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2 Arming Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.3 Detail Explanation of the External Host Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.4 External Host Mode Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.5 Flash Operation Status Detection Via External Host Handshake . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.6 Step-by-step instructions to perform
External Host Mode commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode . . . . . . . . . . . . . . . . . . 31
4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.1 In-Application Programming Mode Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.2 Memory Bank Selection for In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.3 IAP Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.4 In-Application Programming Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.5 Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.6 Interrupt Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1 Enhanced Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.1 Framing Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.2 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
2
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.0 PROGRAMMABLE COUNTER ARRAY (PCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2 PCA Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.1 Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.2 16-Bit Software Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.3 High Speed Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.4 Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.5 Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.0 SECURITY LOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.5 Power-Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.5.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.5.2 Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.5.3 Standby Mode (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.6 Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.7 Recommended Capacitor Values for Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Absolute Maximum Stress Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 Operation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2 Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
3
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
LIST OF FIGURES
FIGURE 2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 3-1: Program Memory Organization for SST89E564RD and SST89V564RD . . . . . . . . . . . . . . . . 10
FIGURE 3-2: Program Memory Organization for SST89E554RC and SST89V554RC . . . . . . . . . . . . . . . . 11
FIGURE 4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FIGURE 4-2: Read-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 4-3: Select-Block1 / Select-Block0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 4-4: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 4-5: Block-Erase for SST89E564RD/SST89V564RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 4-6: Block-Erase for SST89E554RC/SST89V554RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 4-7: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 4-8: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 4-9: Prog-SB1 / Prog-SB2 / Prog-SB3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 4-10: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 4-11: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 6-1: SPI Master-slave Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FIGURE 6-2: SPI Transfer Format with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FIGURE 6-3: SPI Transfer Format with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FIGURE 7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FIGURE 9-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
FIGURE 10-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FIGURE 10-2: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FIGURE 11-1: IDD Test Condition, Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIGURE 11-2: IDD Test Condition, Idle Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIGURE 11-3: IDD Test Condition, Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIGURE 11-4: IDD Test Condition, Standby (Stop Clock) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIGURE 11-5: AC Testing Input/Output, Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
FIGURE 11-6: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FIGURE 11-7: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FIGURE 11-8: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FIGURE 11-9: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FIGURE 11-10: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
4
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
LIST OF TABLES
TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E564RD/SST89V564RD . . . 11
TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E554RC/SST89V554RC . . . 12
TABLE 3-3: SFCF Values Under Different Reset Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 3-4: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 3-5: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 3-6: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 3-7: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 3-8: Timer/Counters SFRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 3-9: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 3-10: PCA SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 3-11: PCA Module Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 4-1: External Host Mode Commands for SST89E564RD/SST89V564RD . . . . . . . . . . . . . . . . . . 27
TABLE 4-2: External Host Mode Commands for SST89E554RC/SST89V554RC . . . . . . . . . . . . . . . . . . 28
TABLE 4-3: Signature Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TABLE 4-4: IAP Address Resolution for SST89E564RD/SST89V564RD . . . . . . . . . . . . . . . . . . . . . . . . . 36
TABLE 4-5: In-Application Programming Mode Commands for SST89E564RD/SST89V564RD . . . . . . . 38
TABLE 4-6: In-Application Programming Mode Commands for SST89E554RC/SST89V554RC . . . . . . . 38
TABLE 4-7: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TABLE 8-1: Count Pulse Selected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TABLE 8-2: Possible Modes and Associated Values for CCAPMn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TABLE 9-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TABLE 9-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TABLE 10-1: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TABLE 10-2: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TABLE 11-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TABLE 11-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TABLE 11-3: DC Electrical Characteristics: 40MHz devices; 4.5-5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
TABLE 11-4: DC Electrical Characteristics: 25MHz devices; 2.7-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TABLE 11-5: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TABLE 11-6: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TABLE 11-7: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
5
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
1.0 FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
Interrupt
Control
Watchdog Timer
9 Interrupts
8051
CPU Core
SuperFlash
EEPROM
Primary
Block
32K/64K x81
RAM
1K x8
Secondary
Block
8K x8
I/O
I/O
I/O
I/O
I/O Port 0
8
8
8
I/O Port 1
I/O Port 2
I/O Port 3
SPI
Security
Lock
Timer 0 (16-bits)
Timer 1 (16-bits)
Timer 2 (16-bits)
PCA
8-bit
Enhanced
UART
555 ILL B1.0
1. 64K x8 for SST89E564RD and SST89V564RD
32K x8 for SST89E554RC and SST89V554RC
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
6
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2.0 PIN ASSIGNMENTS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
(T2) P1.0
(T2 Ex) P1.1
P1.2
1
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA#
2
3
P1.3
4
(SS#) P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
5
6
44 43 42 41 40 39 38 37 36 35 34
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA#
1
33
32
31
30
29
28
27
26
25
24
23
7
40-pin PDIP
Top View
2
8
3
9
4
(RXD) P3.0
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
(T1) P3.5
(WR#) P3.6
(RD#) P3.7
XTAL2
10
11
12
13
14
15
16
17
18
19
20
(RXD) P3.0
Reserved
5
44-lead TQFP
Top View
ALE/PROG#
PSEN#
Reserved
ALE/PROG#
PSEN#
6
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
7
8
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
9
10
11
(T1) P3.5
12 13 14 15 16 17 18 19 20 21 22
XTAL1
555 ILL F1b.0
V
SS
555 ILL F1a.0
FIGURE
2-1: PIN ASSIGNMENTS FOR 40-PIN PDIP
FIGURE
2-2: PIN ASSIGNMENTS FOR 44-LEAD TQFP
6
5
4
3
2
1
44 43 42 41 40
7
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA#
39
8
38
37
36
35
34
33
32
31
30
29
9
10
11
12
13
14
15
16
17
(RXD) P3.0
Reserved
44-lead PLCC
Top View
Reserved
ALE/PROG#
PSEN#
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
(T1) P3.5
18 19 20 21 22 23 24 25 26 27 28
555 ILL F01c.0
FIGURE
2-3: PIN ASSIGNMENTS FOR 44-LEAD PLCC
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
7
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2.1 Pin Descriptions
TABLE
Symbol
2-1: PIN DESCRIPTIONS (1 OF 2)
Type1
Name and Functions
P0[7:0]
I/O
Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can
sink several LS TTL inputs. Port 0 pins float that have “1”s written to them, and in this state
can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this application, it uses strong internal pull-
ups when transitioning to VOH. Port 0 also receives the code bytes during the external host
mode programming, and outputs the code bytes during the external host mode verification.
External pull-ups are required during program verification.
P1[7:0]
I/O with internal Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
pull-ups
can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when “1”s are
written to them and can be used as inputs in this state. As inputs, Port 1 pins that are exter-
nally pulled low will source current (IIL, see Tables 11-3 and 11-4) because of the internal pull-
ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address
bytes during the external host mode programming and verification.
P1[0]
P1[1]
P1[2]
I/O
T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2
T2EX: Timer/Counter 2 capture/reload trigger and direction control
I
I
ECI: PCA Timer/Counter External Input:
This signal is the external clock input for the PCS timer/counter.
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]
P2[7:0]
I/O
I/O
I/O
I/O
I/O
CEX0: Compare/Capture Module External I/O
Each compare/capture module connects to a Port 1 pin for external I/O. When not used by
the PCA, this pin can handle standard I/O.
SS#: Master Input or Slave Output for SPI.
OR
CEX1: Compare/Capture Module External I/O
MOSI: Master Output line, Slave Input line for SPI
OR
CEX2: Compare/Capture Module External I/O
MISO: Master Input line, Slave Output line for SPI
OR
CEX3: Compare/Capture Module External I/O
SCK: Master clock output, slave clock input line for SPI
OR
CEX4: Compare/Capture Module External I/O
I/O with internal Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled
pull-ups
high by the internal pull-ups when “1”s are written to them and can be used as inputs in this
state. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Tables
11-3 and 11-4) because of the internal pull-ups. Port 2 sends the high-order address byte
during fetches from external Program memory and during accesses to external Data Memory
that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups
when transitioning to VOH. Port 2 also receives some control signals and a partial of high-
order address bits during the external host mode programming and verification.
P3[7:0]
I/O with internal Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
pull-ups
can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when “1”s are
written to them and can be used as inputs in this state. As inputs, Port 3 pins that are exter-
nally pulled low will source current (IIL, see Tables 11-3 and 11-4) because of the internal pull-
ups. Port 3 also receives some control signals and a partial of high-order address bits during
the external host mode programming and verification.
P3[0]
P3[1]
P3[2]
I
O
I
RXD: Serial input line
TXD: Serial output line
INT0#: External Interrupt 0 Input
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
8
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
Symbol
2-1: PIN DESCRIPTIONS (CONTINUED) (2 OF 2)
Type1
Name and Functions
P3[3]
P3[4]
I
I
INT1#: External Interrupt 1 Input
T0: External count input to Timer/Counter 0
T1: External count input to Timer/Counter 1
WR#: External Data Memory Write strobe
RD#: External Data Memory Read strobe
P3[5]
I
P3[6]
O
O
I/O
P3[7]
PSEN#
Program Store Enable: PSEN# is the Read strobe to External Program Store. When the
device is executing from Internal Program Memory, PSEN# is inactive (VOH). When the
device is executing code from External Program Memory, PSEN# is activated twice each
machine cycle, except when access to External Data Memory while one PSEN# activation is
skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while
the RST input is continually held high for more than ten machine cycles will cause the device
to enter External Host mode for programming.
RST
EA#
I
I
Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will
reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition
while the RST input pin is held high, the device will enter the External Host mode, otherwise
the device will enter the Normal operation mode.
External Access Enable: EA# must be driven to VIL in order to enable the device to fetch
code from the External Program Memory. EA# must be driven to VIH for internal program exe-
cution. However, Security lock level 4 will disable EA#, and program execution is only possi-
ble from internal program memory. The EA# pin can tolerate a high voltage2 of 12V
(see “Absolute Maximum Stress Ratings” on page 51).
ALE/PROG#
I/O
Address Latch Enable: ALE is the output signal for latching the low byte of the address dur-
ing accesses to external memory. This pin is also the programming pulse input (PROG#) for
the external host mode. ALE is activated twice each machine cycle, except when access to
External Data Memory, one ALE activation is skipped in the second machine cycle. However,
if AO is set to 1, ALE is disabled. (see “Auxiliary Register (AUXR)” on page 20)
XTAL1
XTAL2
I
O
Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal
clock generation circuits from an external clock source.
VDD
I
I
Power Supply: Supply voltage during normal, Idle, Power Down, and Standby Mode opera-
tions.
VSS
Ground: Circuit ground. (0V reference)
T2-1.0 555
1. I = Input; O = Output
2. It is not necessary to receive a 12V programming supply voltage during flash programming.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
9
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
3.0 MEMORY ORGANIZATION
The device has separate address spaces for program and
data memory.
Bank Selection. Please refer to Figure 3-1 and Figure 3-2
for the program memory configurations. Program Bank
Select is described in the next section.
3.1 Program Memory
The 64K/32K x8 primary SuperFlash block is organized as
512/256 sectors, each sector consists of 128 Bytes.
There are two internal flash memory blocks in the device.
The primary flash memory block (Block 0) has 64/32
KByte. The secondary flash memory block (Block 1) has 8
KByte. Since the total program address space is limited to
64/32 KByte, the SFCF[1:0] bit are used to control Program
The 8K x8 secondary SuperFlash block is organized as 64
sectors, each sector consists also of 128 Bytes.
For both blocks, the 7 least significant program address bits
select the byte within the sector. The remainder of the pro-
gram address bits select the sector within the block.
EA# = 1
SFCF[1:0] = 00
EA# = 1
SFCF[1:0] = 01, 10, 11
EA# = 0
FFFFH
FFFFH
FFFFH
56 KByte
Block 0
64 KByte
Block 0
External
64 KByte
2000H
1FFFH
8 KByte
Block 1
0000H
0000H
0000H
555 ILL F02.0
FIGURE
3-1: PROGRAM MEMORY ORGANIZATION FOR SST89E564RD AND SST89V564RD
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
10
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
EA# = 1
SFCF[1:0] = 00
EA# = 1
SFCF[1:0] = 01
EA# = 1
SFCF[1:0] = 10, 11
EA# = 0
FFFFH
FFFFH
FFFFH
FFFFH
8 KByte
Block 1
8 KByte
Block 1
E000H
DFFFH
E000H
DFFFH
External
32 KByte
External
24 KByte
External
24 KByte
External
64 KByte
8000H
7FFFH
8000H
7FFFH
8000H
7FFFH
24 KByte
Block 0
2000H
1FFFH
32 KByte
Block 0
32 KByte
Block 0
8 KByte
Block 1
0000H
0000H
0000H
0000H
555 ILL F03.2
FIGURE
3-2: PROGRAM MEMORY ORGANIZATION FOR SST89E554RC AND SST89V554RC
3.2 Program Memory Block Switching
The program memory block switching feature of the device
allows either Block 1 or the lowest 8 KByte of Block 0 to be
used for the lowest 8 KByte of the program address space.
SFCF[1:0] controls program memory block switching.
TABLE
SFCF[1:0]
01, 10, 11
3-1: SFCF VALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST89E564RD/SST89V564RD
Program Memory Block Switching
Block 1 is not visible to the PC;
Block 1 is reachable only via In-Application Programming from 000H - 1FFFH.
00
Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.
When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0.
Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through
In-Application Programming.
T3-1.0 555
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
11
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
SFCF[1:0]
10, 11
3-2: SFCF VALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST89E554RC/SST89V554RC
Program Memory Block Switching
Block 1 is not visible to the PC;
Block 1 is reachable only via In-Application Programming from E000H - FFFFH.
01
00
Both Block 0 and Block 1 are visible to the PC.
Block 0 is occupied from 0000H - 7FFFH. Block 1 is occupied from E000H - FFFFH.
Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.
When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0.
Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through
In-Application Programming.
T3-2.0 555
3.2.1 Reset Configuration of Program Memory
Block Switching
3.3 Data Memory
The device has 1024 x8 bits of on-chip RAM and can
address up to 64 KByte of external data memory.
Program memory block switching is initialized after reset
according to the state of the Start-up Configuration bit SC0.
The SC0 bit is programmed via an External Host Mode
command or an IAP Mode command. See Table 4-2 and
Table 4-6.
The device has four sections of internal data memory:
1. The lower 128 Bytes of RAM (00H to 7FH) are
directly and indirectly addressable.
Once out of reset, the SFCF[0] bit can be changed dynam-
ically by the program for desired effects. Changing SFCF[0]
will not change the SC0 bit.
2. The higher 128 Bytes of RAM (80H to FFH) are
indirectly addressable.
3. The Special Function Registers (SFRs, 80H to
FFH) are directly addressable only.
Caution must be taken when dynamically changing the
SFCF[0] bit. Since this will cause different physical memory
to be mapped to the logical program address space. The
user must avoid executing block switching instructions
within the address range 0000H to 1FFFH.
4. The expanded RAM of 768 Bytes (00H to 2FFH) is
indirectly addressable by the move external
instruction (MOVX) and clearing the EXTRAM bit.
(See “Auxiliary Register (AUXR)” on page 20)
TABLE
3-3: SFCF VALUES UNDER DIFFERENT
RESET CONDITIONS
3.4 Dual Data Pointers
The device has two 16-bit data pointers. The DPTR Select
(DPS) bit in AUXR1 determines which of the two data
pointers is accessed. When DPS=0, DPTR0 is selected;
when DPS=1, DPTR1 is selected. Quickly switching
between the two data pointers can be accomplished by a
single INC instruction on AUXR1.
State of SFCF[1:0] after:
WDT
Power-on
or
Reset
or
External
Reset
Brown-out
Reset
Software
Reset
SC11
SC0
1
1
00
x0
10
(default)
3.5 Special Function Registers (SFR)
1
0
0
0
1
0
01
10
11
x1
10
11
11
10
Most of the unique features of the FlashFlex51 microcon-
troller family are controlled by bits in special function regis-
ters (SFRs) located in the SFR Memory Map shown in
Table 3-4. Individual descriptions of each SFR are provided
and Reset values indicated in Tables 3-5 to 3-9.
11
T3-3.0 555
1. SC1 only applies to SST89E554RC and SST89V554RC.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
12
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-4: FLASHFLEX51 SFR MEMORY MAP
8 BYTES
F8H
F0H
E8H
E0H
D8H
D0H
C8H
C0H
B8H
B0H
A8H
A0H
98H
90H
88H
80H
IPA1
B1
IEA1
ACC1
CCON1
PSW1
T2CON1
WDTC1
IP1
P31
IE1
P21
SCON1
P11
CH
CL
CCAP0H
CCAP0L
CCAP1H
CCAP2H
CCAP3H
CCAP3L
CCAP4H
CCAP4L
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
IPAH
CCAP1L
CCAP2L
CMOD
T2MOD
CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4
SPCR
RCAP2L
RCAP2H
TL2
TH2
SADEN
SFCF
SFCM
SPSR
SFAL
SFAH
SFDT
SFST
IPH
SADDR
AUXR1
SBUF
TCON1
P01
TMOD
SP
TL0
TL1
TH0
TH1
AUXR
SPDR
DPL
DPH
WDTD
PCON
87H
T3-4.1 555
1. SFRs are bit addressable.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
13
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-5: CPU RELATED SFRS
Bit Address, Symbol, or Alternative Port Function
Direct
Address
RESET
Value
Symbol Description
MSB
LSB
ACC1
B1
PSW1
Accumulator
B Register
E0H
F0H
D0H
ACC[7:0]
B[7:0]
00H
00H
00H
Program Status
Word
CY
AC
F0
RS1
RS0
OV
F1
P
SP
Stack Pointer
81H
82H
SP[7:0]
07H
00H
DPL
Data Pointer
Low
DPL[7:0]
DPH[7:0]
DPH
Data Pointer
High
83H
00H
IE1
IEA1
Interrupt Enable
A8H
E8H
EA
-
EC
-
ET2
-
ES0
ET1
EX1
-
ET0
-
EX0
-
40H
Interrupt
Enable A
-
EBO
xxxx0xxxb
IP1
Interrupt Priority
Reg
B8H
B7H
F8H
F7H
-
-
-
-
PPC
PT2
PS
PT1
PX1
PT0
PX0 x0000000b
PX0H x0000000b
IPH
IPA1
IPAH
Interrupt Priority
Reg High
PPCH PT2H PSH PT1H PX1H
PT0H
Interrupt Priority
Reg A
-
-
-
-
-
-
PBO
-
-
-
-
-
-
xxxx0xxxb
xxxx0xxxb
Interrupt Priority
Reg A High
PBO
H
PCON
AUXR
Power Control
Auxiliary Reg
87H
8EH
A2H
SMOD1 SMOD0 BOF
POF
GF1
-
GF0
PD
IDL
AO
00010000b
xxxxxxx00b
-
-
-
-
-
-
-
-
-
EXTRAM
-
AUXR1 Auxiliary Reg 1
GF2
0
DPS
xxxx00x0b
T3-5.1 555
1. Bit Addressable SFRs
TABLE
3-6: FLASH MEMORY PROGRAMMING SFRS
Bit Address, Symbol, or Alternative Port Function
Direct
Address
RESET
Value
Symbol Description
MSB
SECD1 SECD2 SECD3
LSB
SFST
SFCF
SFCM
SFDT
SFAL
SFAH
SuperFlash
Status
B6H
B1H
B2H
B5H
B3H
B4H
-
-
-
-
FLASH_BUSY
-
-
-
xxxxx0xxb
SuperFlash
Configuration
-
IAPEN
-
SWR BSEL x0xxxxxxb
SuperFlash
Command
FIE
FCM
SuperFlash Data Register
00H
00H
SuperFlash
Data
SuperFlash
Address Low
SuperFlash Low Order Byte Address Register - A7 to A0 (SFAL)
SuperFlash High Order Byte Address Register - A15 to A8 (SFAH)
00H
SuperFlash
00H
Address High
T3-6.0 555
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
14
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-7: WATCHDOG TIMER SFRS
Bit Address, Symbol, or Alternative Port Function
Direct
Address MSB
RESET
Value
Symbol Description
LSB
WDTC1 Watchdog Timer
Control
C0H
-
-
-
WDOUT WDRE WDTS WDT SWDT xxx00x00b
WDTD Watchdog Timer
Data/Reload
85H
Watchdog Timer Data/Reload 00H
T3-7.0 555
1. Bit Addressable SFRs
TABLE
3-8: TIMER/COUNTERS SFRS
Direct
Bit Address, Symbol, or Alternative Port Function
RESET
Value
Symbol Description
Address MSB
LSB
TMOD
Timer/Counter
Mode Control
89H
Timer 1
Timer 0
00H
GATE C/T#
TF1 TR1
M1
M0
GATE C/T#
IE1 IT1
M1
IE0
M0
IT0
TCON1
Timer/Counter
Control
88H
TF0
TR0
00H
TH0
TL0
TH1
TL1
Timer 0 MSB
Timer 0 LSB
Timer 1 MSB
Timer 1 LSB
8CH
8AH
8DH
8BH
C8H
TH0[7:0]
TL0[7:0]
TH1[7:0]
TL1[7:0]
00H
00H
00H
00H
00H
T2CON1 Timer / Counter 2
Control
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MOD# Timer2
Mode Control
C9H
-
-
-
-
-
-
T2OE
DCEN
xxxxxx00b
TH2
TL2
Timer 2 MSB
Timer 2 LSB
CDH
CCH
CBH
CAH
TH2[7:0]
TL2[7:0]
00H
00H
00H
RCAP2H Timer 2 Capture MSB
RCAP2L Timer 2 Capture LSB
RCAP2H[7:0]
RCAP2L[7:0]
00H
T3-8.0 555
1. Bit Addressable SFRs
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
15
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
3-9: INTERFACE SFRS
Bit Address, Symbol, or Alternative Port Function
Direct
Address
RESET
Value
Symbol Description
MSB
LSB
SBUF
Serial Data Buffer
99H
98H
A9H
B9H
SBUF[7:0]
Indeterminate
00H
SCON1 Serial Port Control
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SADDR Slave Address
SADDR#[7:0]
SADEN#[7:0]
00H
SADEN Slave Address
Mask
00H
SPCR
SPI Control
Register
D5H
AAH
SPIE
SPIF
SPD7
SPE DORD MSTR CPOL CPHA SPR1 SPR0
WCOL
04H
00H
SPSR
SPI Status
Register
SPDR
P01
P11
P21
P31
SPI Data Register
Port 0
86H
80H
90H
A0H
B0H
SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
P0[7:0]
00H
FFH
FFH
FFH
Port 1
-
-
-
-
-
-
T2EX
T2
Port 2
P2[7:0]
Port 3
RD#
WR#
T1
T0
INT1# INT0# TXD
RXD
FFH
T3-9.0 555
1. Bit Addressable SFRs
TABLE 3-10: PCA SFRS
Bit Address, Symbol, or Alternative Port Function
Direct
Address MSB
RESET
Value
Symbol Description
LSB
PCA Timer/Counter
CH
CL
F9H
E9H
CH[7:0]
CL[7:0]
00H
00H
CCON1
D8H
CF
CR
-
-
CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b
PCA Timer/Counter
Control Register
PCA Timer/Counter
Mode Register
CMOD
D9H
CIDL WDTE
-
-
CPS1 CPS0
ECF
00xxx000b
CCAP0H PCA Module 0
FAH
EAH
CCAP0H[7:0]
CCAP0L[7:0]
00H
00H
Compare/Capture
CCAP0L
Registers
CCAP1H PCA Module 1
FBH
EBH
CCAP1H[7:0]
CCAP1L[7:0]
00H
00H
Compare/Capture
CCAP1L
Registers
CCAP2H PCA Module 2
FCH
ECH
CCAP2H[7:0]
CCAP2L[7:0]
00H
00H
Compare/Capture
CCAP2L
Registers
CCAP3H PCA Module 3
FDH
EDH
CCAP3H[7:0]
CCAP3L[7:0]
00H
00H
Compare/Capture
CCAP3L
Registers
CCAP4H PCA Module 4
FEH
EEH
CCAP4H[7:0]
CCAP4L[7:0]
00H
00H
Compare/Capture
CCAP4L
Registers
CCAPM0 PCA
DAH
DBH
DCH
DDH
DEH
-
-
-
-
-
ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x000 0000b
ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x000 0000b
ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x000 0000b
ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x000 0000b
Compare/Capture
CCAPM1
Module Mode
CCAPM2
Registers
CCAPM3
CCAPM4
ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 x000 0000b
T3-10.1 555
1. Bit Addressable SFRs
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
16
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SuperFlash Status Register (SFST) (Read Only Register)
Location
7
6
5
4
3
2
1
0
Reset Value
FLASH_BUSY
0B6H
SECD1
SECD2
SECD3
-
-
-
-
xxxxx0xxb
Symbol
SECD1
SECD2
SECD3
Function
Security bit 1.
Security bit 2.
Security bit 3.
Please refer to Table 4-6 for security lock options.
FLASH_BUSY Flash operation completion polling bit.
1: Device is busy with flash operation.
0: Device has fully completed the last command.
SuperFlash Configuration Register (SFCF)
Location
7
6
5
4
3
2
1
0
Reset Value
SWR
BSEL
0B1H
-
IAPEN
-
-
-
-
x0xxxxxxb
Symbol
Function
Enable IAP operation
IAPEN
0: IAP commands are disabled
1: IAP commands are enabled
SWR
BSEL
Software Reset
See “10.2 Software Reset” on page 47
Program memory block switching bit
See Figures 3-1 and 3-2.
SuperFlash Command Register (SFCM)
Location
7
6
5
4
3
2
1
0
Reset Value
0B2H
FIE
FCM6
FCM5
FCM4
FCM3
FCM2
FCM1
FCM0
00000000b
Symbol
Function
FIE
Flash Interrupt Enable.
0: INT1# is not reassigned.
1: INT1# is re-assigned to signal IAP operation completion.
External INT1# interrupts are ignored.
FCM[6:0]
Flash operation command
000_1011b Sector-Erase
000_1101b Block-Erase
000_1100b Byte-Verify1
000_1110b Byte-Program
000_1111b Prog-SB1
000_0011b Prog-SB2
000_0101b Prog-SB3
000_1001b Prog-SC0
All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of
FIE.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
17
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SuperFlash Data Register (SFDT)
Location
7
6
5
4
3
2
1
0
Reset Value
0B5H
SuperFlash Data Register
00000000b
Symbol
Function
SFDT
Mailbox register for interfacing with flash memory block. (Data register).
SuperFlash Address Registers (SFAL)
Location
7
6
5
4
3
2
1
0
Reset Value
0B3H
SuperFlash Low Order Byte Address Register
00000000b
Symbol
Function
Mailbox register for interfacing with flash memory block. (Low order address register).
SFAL
SuperFlash Address Registers (SFAH)
Location
7
6
5
4
3
2
1
0
Reset Value
0B4H
SuperFlash High Order Byte Address Register
00000000b
Symbol
Function
Mailbox register for interfacing with flash memory block. (High order address register).
SFAH
Interrupt Enable (IE)
Location
7
6
5
4
3
2
1
0
Reset Value
A8H
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
00H
Symbol
Function
EA
Global Interrupt Enable.
0 = Disable
1 = Enable
EC
PCA Interrupt Enable.
ET2
ES
Timer 2 Interrupt Enable.
Serial Interrupt Enable.
Timer 1 Interrupt Enable.
External 1 Interrupt Enable.
Timer 0 Interrupt Enable.
External 0 Interrupt Enable.
ET1
EX1
ET0
EX0
Interrupt Enable A (IEA)
Location
7
6
5
4
3
2
1
0
Reset Value
E8H
-
-
-
-
EBO
-
-
-
xxxx0xxxb
Symbol
Function
EBO
Brown-out Interrupt Enable.
1 = Enable the interrupt
0 = Disable the interrupt
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
18
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Interrupt Priority (IP)
Location
7
6
5
4
3
2
1
0
Reset Value
B8H
-
PPC
PT2
PS
PT1
PX1
PT0
PX0
x0000000b
Symbol
PPC
PT2
Function
PCA interrupt priority bit.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
PS
PT1
PX1
PT0
PX0
Interrupt Priority High (IPH)
Location
7
6
5
4
3
2
1
0
Reset Value
B7H
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
x0000000b
Symbol
PPCH
PT2H
PSH
Function
PCA interrupt priority bit high.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
PT1H
PX1H
PT0H
PX0H
Interrupt Priority A (IPA)
Location
7
6
5
4
3
2
1
0
Reset Value
F8H
-
-
-
-
PBO
-
-
-
xxxx0xxxb
Symbol
Function
PBO
Brown-out interrupt priority bit.
Interrupt Priority A High (IPAH)
Location
7
6
5
4
3
2
1
0
Reset Value
F7H
-
-
-
-
PBOH
-
-
-
xxxx0xxxb
Symbol
Function
PBOH
Brown-out Interrupt priority bit high.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
19
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Auxiliary Register (AUXR)
Location
7
6
5
4
3
2
1
0
Reset Value
8EH
-
-
-
-
-
-
EXTRAM
AO
xxxxxx00b
Symbol
Function
EXTRAM
0: Internal Expanded RAM access. For details, refer to “Data Memory” on page 12.
1: External data memory access.
AO
0: Normal ALE
1: ALE is normally off. ALE is active only during a MOVX or MOVC instruction. This will reduce
EMI.
Auxiliary Register 1 (AUXR1)
Location
7
6
5
4
3
2
1
0
Reset Value
A2H
-
-
-
-
GF2
0
-
DPS
xxxx00x0b
Symbol
GF2
Function
General purpose user-defined flag.
DPS
DPTR registers select bit.
0: DPTR0 is selected.
1: DPTR1 is selected.
Watchdog Timer Control Register (WDTC)
Location
7
6
5
4
3
2
1
0
Reset Value
0C0H
-
-
-
WDOUT
WDRE
WDTS
WDT
SWDT
xxx00x00b
Symbol
Function
WDOUT
Watchdog output enable.
0: Watchdog reset will not be exported on Reset pin.
1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.
WDRE
WDTS
Watchdog timer reset enable.
0: Disable watchdog timer reset.
1: Enable watchdog timer reset.
Watchdog timer reset flag.
0: External hardware reset clears the flag.
Flag can also be cleared by writing a 1.
Flag survives if chip reset happened because of watchdog timer overflow.
1: Hardware sets the flag on watchdog overflow.
WDT
Watchdog timer refresh.
0: Hardware resets the bit when refresh is done.
1: Software sets the bit to force a watchdog timer refresh.
SWDT
Start watchdog timer.
0: Stop WDT.
1: Start WDT.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
20
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Watchdog Timer Data/Reload Register (WDTD)
Location
7
6
5
4
3
2
1
0
Reset Value
085H
Watchdog Timer Data/Reload
00000000b
Symbol
Function
WDTD
Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.
PCA Timer/Counter Control Register (CCON)
Location
7
6
5
4
3
2
1
0
Reset Value
CR
-
CCF4
D8H
CF
CCF3
CCF2
CCF1
CCF0
00x00000b
Symbol
Function
PCA Timer/Counter Overflow Flag:
CF
Set by hardware when the PCA timer/counter rolls over. This generates an interrupt
request if the ECF interrupt enable bit in CMOD is set. CF can be set by hardware or
software but can be cleared only by software.
CR
PCA Timer/Counter Run Control Bit:
Set and Cleared by software to turn the PCA timer/counter on and off.
CCF[4:0]
PCA Module Compare/Capture Flags:
Set by hardware when a match or capture occurs. This generates a PCA interrupt
request if the ECCFx interrupt enable bit in the corresponding CCAPMx register is set.
Must be cleared by software.
PCA Timer/Counter Mode Register (CMOD)
Location
7
6
5
4
3
2
1
0
Reset Value
WDTE
-
-
D9H
CIDL
-
CPS1
CPS0
ECF
00xxx000b
Symbol
Function
PCA Timer/Counter Idle Control:
CIDL
0: Allows the PCA timer/counter to run during idle mode.
1: Disables the PCA timer/counter during idle mode.
WDTE
Watchdog Timer Enable:
0: Disables the PCA watchdog timer output.
1: Enables the PCA watchdog timer output on PCA module 4.
CPS1,CPS0
PCA Timer/Counter Input Select:
CPS1
CPS0
0
0
1
1
0
1
0
1
fOSC /12
fOSC /4
Timer 0 overflow
External clock at ECI pin (maximum rate = fOSC /8)
ECF
PCA Timer/Counter Interrupt Enable:
0: Disables the CF bit in the CCON register.
1: Enables the CF bit in the CCON register to generate an interrupt request.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
21
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 3-11: PCA MODULE MODES
ECOMy1 CAPPy1 CAPNy1 MATy1 TOGy1 PWNy1 ECCFy1 Module Code
0
-
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
-
No Operation
16-bit capture on positive-edge trigger at CEX[4:0]
16-bit capture on negative-edge trigger at CEX[4:0]
-
-
-
-
16-bit capture on positive-/negative-edge trigger
at CEX[4:0]
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
-
0
0
1
0
-
-
Compare: software timer
Compare: high-speed output
Compare: 8-bit PWM
0
-
Compare: PCA WDT (CCAPM4 only)2
T3-11.0 555
1. y = 0, 1, 2, 3, 4
2. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
22
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
PCA Compare/Capture Module Mode Register (CCAPM[4:0])
Location
DAH
7
-
-
-
-
-
6
5
4
3
2
1
0
Reset Value
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0 x0000000b
ECCF1 x0000000b
ECCF2 x0000000b
ECCF3 x0000000b
ECCF4 x0000000b
DBH
DCH
DDH
DEH
Symbol
Function
Compare Modes:
0: Disables the module comparator function.
ECOM[4:0]
1: Enables the module comparator function. The comparator is used to implement the
software timer, high-speed output, pulse width modulation, and watchdog timer modes.
CAPP[4:0]
CAPN[4:0]
MAT[4:0]
0: Disables the capture function with capture triggered by a positive edge on pin
CEX[4:0].
1: Enables the capture function with capture triggered by a positive edge on pin
CEX[4:0].
0: Disables the capture function with capture triggered by a negative edge on pin
CEX[4:0].
1: Enables the capture function with capture triggered by a negative edge on pin
CEX[4:0].
Match: Set ECOM[4:0] and MAT[4:0] to implement the software timer mode.
0: Disable the software timer mode
1: A match of the PCA timer/counter with the compare/capture register sets the
CCF[4:0] bit in the CCON register, flagging an interrupt.
TOG[4:0]
Toggle: Set ECOM[4:0], MAT[4:0], and TOG[4:0] to implement the high-speed output
mode.
0: Disable the toggle function
1: A match of the PCA timer/counter with the compare/capture register toggles the
CEX[4:0] pin.
PWM[4:0]
ECCF[4:0]
Pulse Width Modulation Mode:
0: Disable the pulse width modulation mode
1: Configures the module for operation as an 8-bit pulse width modulator with output
waveform on the CEX[4:0] pin.
Enable CCF[4:0] Interrupt:
0: Disables compare/capture flag CCF[4:0] in the CCON register to generate an
interrupt request.
1: Enables compare/capture flag CCF[4:0] in the CCON register to generate an
interrupt request.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
23
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SPI Control Register (SPCR)
Location
7
6
5
4
3
2
1
0
Reset Value
SPE
DORD
MSTR
D5H
SPIE
CPOL
CPHA
SPR1
SPR0
00000100b
Symbol
SPIE
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7].
DORD
MSTR
CPOL
CPHA
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPR1, SPR0 SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, fOSC, is as follows:
SPR1
SPR0
SCK = fOSC divided by
0
0
1
1
0
1
0
1
4
16
64
128
SPI Status Register (SPSR)
Location
7
6
5
4
3
2
1
0
Reset Value
WCOL
-
-
AAH
SPIF
-
-
-
-
00xxxxxxb
Symbol
Function
SPIF
Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt
is then generated. To clear, read SPSR and then access SPDR.
WCOL
Set if the SPI data register is written to during data transfer. To clear, read SPSR and
then access SPDR.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
24
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SPI Data Register (SPDR)
Location
7
6
5
4
3
2
1
0
Reset Value
SPD6
SPD5
SPD4
86H
SPD7
SPD3
SPD2
SPD1
SPD0
00H
Power Control Register (PCON)
Location
7
6
5
4
3
2
1
0
Reset Value
SMOD0
BOF
POF
87H
SMOD1
GF1
GF0
PD
IDL
00010000b
Symbol
SMOD1
SMOD0
Function
Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate.
FE/SM0 Selection bit.
0: SCON[7] = SM0
1: SCON[7] = FE,
BOF
POF
Brown-out detection status bit, this bit will not be affected by any other reset. BOF
should be cleared by software. Power-on reset will also clear the BOF bit.
0: No Brown-out.
1: Brown-out occurred
Power-on reset status bit, this bit will not be affected by any other reset. POF should be
cleared by software.
0: No Power-on reset.
1: Power-on reset occurred
GF1
GF0
PD
General-purpose flag bit.
General-purpose flag bit.
Power-down bit.
0: Power-down mode is not activated.
1: Activates Power-down mode.
IDL
Idle mode bit.
0: Idle mode is not activated.
1: Activates Idle mode.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
25
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
Serial Port Control Register (SCON)
Location
7
6
5
4
3
2
1
0
Reset Value
SM1
SM2
REN
98H
SM0/FE
TB8
RB8
TI
RI
00000000b
Symbol
Function
FE
Set SMOD0 = 1 to access FE bit.
0: No framing error
1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to
be cleared by software.
SM0
SM1
SMOD0 = 0 to access SM0 bit.
Serial Port Mode Bit 0
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate1
0
0
0
Shift Register
fOSC/6 (6 clock mode) or fOSC
12 (12 clock mode)
Variable
/
0
1
1
0
1
2
8-bit UART
9-bit UART
f
OSC/32 or fOSC/16 (6 clock
mode) or fOSC/64 or
OSC/32 (12 clock mode)
Variable
f
1
1
3
9-bit UART
1. fOSC = oscillator frequency
SM2
REN
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI
will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and
the received byte is a Given or broadcast Address. In Mode 1, if SM2 = 1 then RI will
not be activated unless a valid stop bit was received, and the received byte is a Given
or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception.
0: to disable reception.
1: to enable reception.
TB8
RB8
TI
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired.
In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 - 0, RB8 is the
stop bit that was received. In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission, Must be
cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
26
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.0 FLASH MEMORY PROGRAMMING
The device internal flash memory can be programmed or
erased using the following two methods:
logic high to a logic low while RST input is being held con-
tinuously high. The device will stay in External Host Mode
as long as RST = 1 and PSEN# = 0.
•
•
External Host Mode
A Read-ID operation is necessary to “arm” the device in
External Host Mode, and no other External Host Mode com-
mands can be enabled until a Read-ID is performed. In
External Host Mode, the internal Flash memory blocks are
accessed through the re-assigned I/O port pins (see Figure
4-1 for details) by an external host, such as a MCU program-
mer, a PCB tester or a PC-controlled development board.
In-Application Programming (IAP) Mode
4.1 External Host Programming Mode
External Host Programming Mode allows the user to pro-
gram the Flash memory directly without using the CPU.
External Host Mode is entered by forcing PSEN# from a
TABLE
4-1: EXTERNAL HOST MODE COMMANDS FOR SST89E564RD/SST89V564RD
P3[5:4]
PROG#/
ALE
Operation
RST PSEN#
EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P2[5:0]
P1[7:0]
Read-ID
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIH
VIl
VIL
VIL
VIL
VIH
VIH
VIL
VIl
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
DO
X
AH
X
AL
X
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Select-Block0
Select-Block1
Prog-SC0
X
X
X
X
AH
AH
AH
55H
A5H
5AH
X
AL
AL
AL
X
DI
DO
X
VIH
VIl
VIl
X
X
VIL
VIH
VIL
VIH
VIL
VIH
VIH
VIL
X
X
Prog-SB1
X
X
Prog-SB2
X
X
X
Prog-SB3
X
X
X
T4-1.0 555
Note: Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of
the above input pins are invalid and may result in unexpected behaviors.
Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
27
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
4-2: EXTERNAL HOST MODE COMMANDS FOR SST89E554RC/SST89V554RC
P3[5:4]
PROG#/
ALE
Operation
Read-ID
RST PSEN#
EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P2[5:0]
P1[7:0]
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIH
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
VIH
DO
X
AH
X
AL
X
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SC0
X
A[15:13]
AH
AH
AH
5AH
AAH
X
X
X
AL
AL
AL
X
DI
DO
X
VIH
Prog-SC1
X
X
Prog-SB1
X
X
Prog-SB2
X
X
X
Prog-SB3
X
X
X
T4-2.0 555
Note: Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1
VSS VDD RST
Input/
Output
Data
Bus
0
XTAL1
Port 0
6
7
XTAL2
0
1
0
2
Address Bus
A13-A8
1
2
3
4
3
4
5
Port 2
Port 1
Ready/Busy#
A14
Port 3
Address Bus
A15-A14
6
7
0
Flash
Control Signals
A15
5
6
Flash
Control Signals
7
Address Bus
A7-A0
6
7
EA# ALE / PSEN#
PROG#
555 ILL F04.0
FIGURE
4-1: I/O PIN ASSIGNMENTS FOR EXTERNAL HOST MODE
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
28
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.1.1 Product Identification
Following is a detailed description of the External Host
Mode commands:
The Read-ID command accesses the Signature Bytes that
identify the device and the manufacturer as SST. External
programmers primarily use these Signature Bytes in the
selection of programming algorithms. The Read-ID com-
mand is selected by the command code of 0H on P3[7:6]
and P2[7:6]. See Figure 4-2 for timing waveforms.
The Select-Block0 command enables Block 0 to be pro-
grammed in External Host Mode. Once this command is
executed, all subsequent External Host Commands will be
directed at Block 0. See Figure 4-3 for timing waveforms.
This
command
applies
to
SST89E564RD/
SST89V564RD only.
TABLE
4-3: SIGNATURE BYTES
The Select-Block1 command enables Block 1 (8 KByte
Block) to be programmed. Once this command is exe-
cuted, all subsequent External Host Commands that are
directed to the address range below 2000H will be directed
at Block 1. The Select-Block1 command only affects the
lowest 8 KByte of the program address space. For
addresses greater than or equal to 2000H, Block 0 is
accessed by default. Upon entering External Host Mode,
Block 1 is selected by default. See Figure 4-3 for timing
waveforms. This command applies to SST89E564RD/
SST89V564RD only.
Address
Data
Manufacturer’s ID
Device ID
30H
BFH
SST89E564RD
SST89V564RD
SST89E554RC
SST89V554RC
31H
31H
31H
31H
91H
90H
99H
98H
T4-3.0 555
4.1.2 Arming Command
The Chip-Erase, Block-Erase, and Sector-Erase com-
mands are used for erasing all or part of the memory
array. Erased data bytes in the memory array will be
erased to FFH. Memory locations that are to be pro-
grammed must be in the erased state prior to program-
ming.
An arming command sequence must take place before
any External Host Mode sequence command is recog-
nized by the device. This prevents accidental triggering of
External Host Mode Commands due to noise or program-
mer error. The arming command is as follows:
1. PSEN# goes low while RST is high. This will get
the machine in External Host Mode, re-configuring
the pins, and turning on the on-chip oscillator.
The Chip-Erase command erases all bytes in both memory
blocks, regardless of any previous Select-Block0 or Select-
Block1 commands. Chip-Erase ignores the Security Lock
status and will erase the Security Lock, returning the device
to its Unlocked state. The Chip-Erase command will also
erase the SC0 bit. Upon completion of Chip-Erase com-
mand, Block 1 will be the selected block. See Figure 4-4 for
timing waveforms.
2. A Read-ID command is issued, and after 1 ms the
External Host Mode commands can be issued.
After the above sequence, all other External Host Mode
commands are enabled. Before the Read-ID command is
received, all other External Host Mode commands
received are ignored.
The Block-Erase command erases all bytes in the selected
memory blocks. This command will not be executed if the
security lock is enabled. The selection of the memory block
to be erased is determined by the prior execution Select-
Block0 or Select-Block1 command. See Figure 4-6 for the
timing waveforms.
4.1.3 Detail Explanation of the External Host Mode
Commands
The External Host Mode commands are Read-ID, Chip-
Erase, Block-Erase, Sector-Erase, Byte-Program, Byte-
Verify, Prog-SB1, Prog-SB2, Prog-SB3, Prog-SC0, Prog-
SC1, Select-Block0, Select-Block1. See Tables 4-1 and 4-2
for all signal logic assignments, Figure 4-1 for I/O pin
assignments, and Table 4-7 for the timing parameters. The
critical timing for all Erase and Program commands is gen-
erated by an on-chip flash memory controller. The high-to-
low transition of the PROG# signal initiates the Erase or
Program commands, which are synchronized internally.
The Read commands are asynchronous reads, indepen-
dent of the PROG# signal level.
The Sector-Erase command erases all of the bytes in a
sector. The sector size for the flash memory is 128 Bytes.
This command will not be executed if the Security lock is
enabled. See Figure 4-7 for timing waveforms.
The Byte-Program command is used for programming new
data into the memory array. Programming will not take
place if any security locks are enabled. See Figure 4-8 for
timing waveforms.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
29
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
The Byte-Verify command allows the user to verify that the
4.1.5.2 Data# Polling (P0[3])
device correctly performed an Erase or Program com-
mand. This command will be disabled if any security locks
are enabled. See Figure 4-11 for timing waveforms.
During a Program operation, any attempts to read (Byte-
Verify), while the device is busy, will receive the comple-
ment of the data of the last byte loaded (logic low, i.e. “0” for
an erase) on P0[3] with the rest of the bits “0”. During a Pro-
gram operation, the Byte-Verify command is reading the
data of the last byte loaded, not the data at the address
specified.
The Prog-SB1, Prog-SB2, Prog-SB3 commands program
the security bits, the functions of these bits are described in
the Security Lock section and also in Table 9-1. Once pro-
grammed, these bits can only be erased through a Chip-
Erase command. See Figure 4-9 for timing waveforms.
4.1.6 Step-by-step instructions to perform
External Host Mode commands
Prog-SC0 command programs SC0 bit, which determines
the state of SFCF[0] out of reset. Once programmed, SC0
can only be restored to an erased state via a Chip-Erase
command. See Figure 4-10 for timing waveforms.
To program data into the memory array, apply power
supply voltage (VDD) to VDD and RST pins, and per-
form the following steps:
Prog-SC1 command programs SC1 bit, which determines
the state of SFCF[1] out of reset. Once programmed, SC1
can only be restored to an erased state via a Chip-Erase
command. See Figure 4-10 for timing waveforms. Prog-
SC1 is for SST89E554RC/SST89V554RC only.
1. Maintain RST high and set PSEN# from logic high
to low, in sequence according to the appropriate
timing diagram.
2. Raise EA# High (VIH).
3. Issue Read-ID command to enable the External
Host Mode.
4.1.4 External Host Mode Clock Source
In External Host Mode, an internal oscillator will provide
clocking for the device. The on-chip oscillator will be turned
on as the device enters External Host Mode; i.e. when
PSEN# goes low while RST is high. During External Host
Mode, the CPU core is held in reset. Upon exit from Exter-
nal Host Mode, the internal oscillator is turned off.
4. Verify that the memory blocks or sectors for pro-
gramming is in the erased state, FFH. If they are
not erased, then erase them using the appropriate
Erase command.
5. Select the memory location using the address
lines (P3[5:4], P2[5:0], P1[7:0]).
4.1.5 Flash Operation Status Detection Via External
Host Handshake
6. Present the data in on P0[7:0].
7. Pulse ALE/PROG#, observing minimum pulse
width.
The device provides two methods for an external host to
detect the completion of a flash memory operation to opti-
mize the Program or Erase time. The end of a flash mem-
ory operation cycle can be detected by:
8. Wait for low to high transition on READY/BUSY#
(P3[3]).
1. monitoring the Ready/Busy# bit at P3[3];
2. monitoring the Data# Polling bit at P0[3].
9. Repeat steps 5 - 8 until programming is finished.
10. Verify the flash memory contents.
4.1.5.1 Ready/Busy# (P3[3])
The progress of the flash memory programming can be
monitored by the Ready/Busy# output signal. P3[3] is
driven low, some time after ALE/PROG# goes low during a
flash memory operation to indicate the Busy# status of the
Flash Control Unit (FCU). P3[3] is driven high when the
Flash programming operation is completed to indicate the
Ready status.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
30
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode
T
SU
RST
PSEN#
T
ES
ALE/PROG#
EA#
T
T
RD
RD
P2[7:6] ,P3[7:6]
P3[5:4] ,P2[5:0] ,P1
P0
0000b
0030H
BFH
0000b
0031H
Device ID
555 ILL F05.1
Device ID = 91H for SST89E564RD
90H for SST89V564RD
99H for SST89E554RC
98H for SST89V554RC
FIGURE
4-2: READ-ID
Reads chip signature and identification registers at the addressed location.
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
P3[3]
T
PSB
P3[5:4], P2[5:0]
P3[7:6], P2[7:6]
A5H/55H
1001b
555 ILL F06.1
FIGURE
4-3: SELECT-BLOCK1 / SELECT-BLOCK0
Enables the selection of either of the flash memory blocks prior to issuing a Byte-Verify, Block-Erase, Sector-
Erase, or Byte-Program. These commands apply to SST89E564RD/SST89V564RD only.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
31
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
DH
T
PROG
EA#
T
CE
P3[3]
P3[7:6], P2[7:6]
0001b
555 ILL F07.1
FIGURE
4-4: CHIP-ERASE
Erases both flash memory blocks. Security lock is ignored and the security bits are erased too.
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
T
BE
P3[3]
P3[7:6], P2[7:6]
1101b
555 ILL F08.1
FIGURE
4-5: BLOCK-ERASE FOR SST89E564RD/SST89V564RD
Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
32
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
T
BE
P3[3]
P3[7:6], P2[7:6]
P3[5:4], P2[5:0]
1101b
AH
555 ILL F09.1
FIGURE
4-6: BLOCK-ERASE FOR SST89E554RC/SST89V554RC
Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
P3[3]
T
SE
P3[7:6], P2[7:6]
P3[5:4], P2[5:0]
1011b
AH
P1
AL
555 ILL F10.1
FIGURE
4-7: SECTOR-ERASE
Erases the addressed sector if the security lock is not activated on that flash memory block.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
33
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
P3[3]
T
PS
P3[5:4], P2[5:0]
P1
AH
AL
P0
DI
P3[7:6], P2[7:6]
1110b
555 ILL F11.1
FIGURE
4-8: BYTE-PROGRAM
Programs the addressed code byte if the byte location has been successfully erased and not yet programmed.
Byte-Program operation is only allowed when the security lock is not activated on that flash memory block.
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
P3[3]
T
PS
P3[7:6], P2[7:6]
1111b / 0011b / 0101b
555 ILL F12.1
FIGURE
4-9: PROG-SB1 / PROG-SB2 / PROG-SB3
Programs the Security bits SB1, SB2 and SB3 respectively. Only a Chip-Erase will erase a programmed security bit.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
34
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
T
SU
RST
T
ES
PSEN#
T
ADS
ALE/PROG#
T
T
DH
PROG
EA#
P3[3]
T
PS
P3[5:4], P2[5:0]
P3[7:6], P2[7:6]
5AH / AAH
1001b
555 ILL F13.1
FIGURE 4-10: PROG-SC0 / PROG-SC1
Programs the start-up configuration bit SC0/SC1. Only a Chip-Erase will erase a programmed SC0/SC1 bit.
Prog-SC1 applies to SST89E554RC/SST89V554RC only.
T
SU
RST
T
ES
PSEN#
ALE/PROG#
EA#
T
OA
1100b
P3[7:6], P2[7:6]
P0
T
AHA
DO
T
ALA
AL
P1
AH
P3[5:4], P2[5:0]
555 ILL F14.1
FIGURE 4-11: BYTE-VERIFY
Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash
memory block.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
35
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4.2.2 Memory Bank Selection for In-Application
Programming Mode
4.2 In-Application Programming Mode
The device offers either 72 or 40 KByte of In-Application
Programmable flash memory. During In-Application Pro-
gramming, the CPU of the microcontroller enters IAP
Mode. The two blocks of flash memory allow the CPU to
execute user code from one block, while the other is being
erased or reprogrammed concurrently. The CPU may also
fetch code from an external memory while all internal flash
is being reprogrammed. The mailbox registers (SFST,
SFCM, SFAL, SFAH, SFDT and SFCF) located in the Spe-
cial Function Register (SFR), control and monitor the
device’s erase and program process.
With the addressing range limited to 16 bit, only 64 KByte
of program address space is “visible” at any one time. As
shown in Table 4-4, Bank Selection (the configuration of
EA# and SFCF[1:0]), allows Block 1 memory to be overlaid
on the lowest 8 KByte of Block 0 memory, making Block 1
reachable. The same concept is employed to allow both
Block 0 and Block 1 Flash to be accessible to IAP opera-
tions. Code from a block that is not visible may not be used
as a source to program another address. However, a block
that is not “visible” may be programmed by code from the
other block through mailbox registers.
Table 4-6 outlines the commands and their associated
mailbox register settings.
The device allows IAP code in one block of memory to pro-
gram the other block of memory, but may not program any
location in the same block. If an IAP operation originates
physically from Block 0, the target of this operation is implic-
itly defined to be in Block 1. If the IAP operation originates
physically from Block 1, then the target address is implicitly
defined to be in Block 0. If the IAP operation originates from
External program space, then, the target will depend on the
address and the state of Bank Select.
4.2.1 In-Application Programming Mode Clock
Source
During IAP Mode, both the CPU core and the flash control-
ler unit are driven off the external clock. However, an inter-
nal oscillator will provide timing references for Program and
Erase operations. The internal oscillator is only turned on
when required, and is turned off as soon as the Flash oper-
ation is completed.
TABLE
EA#
4-4: IAP ADDRESS RESOLUTION FOR SST89E564RD/SST89V564RD
SFCF[1:0]
00
Address of IAP Inst.
>= 2000H (Block 0)
>= 2000H (Block 0)
< 2000H (Block 1)
Any (Block 0)
Target Address
>= 2000H (Block 0)
< 2000H (Block 1)
Any (Block 0)
Block Being Programmed
1
1
1
1
1
0
0
0
None1
Block 1
Block 0
None1
00
00
01, 10, 11
01, 10, 11
00
>= 2000H (Block 0)
< 2000H (Block 1)
>= 2000H (Block 0)
< 2000H (Block 1)
Any (Block 0)
Any (Block 0)
Block 1
Block 0
Block 1
Block 0
From external
00
From external
01, 10, 11
From external
T4-4.0 555
1. No operation is performed because code from one block may not program the same originating block
4.2.3 IAP Enable Bit
The Program command is for programming new data into
the memory array. The portion of the memory array to be
programmed should be in the erased state, FFH. If the
memory is not erased, it should first be erased with an
appropriate Erase command. Warning: Do not attempt to
write (program or erase) to a block that the code is cur-
rently fetching from. This will cause unpredictable pro-
gram behavior and may corrupt program data.
The IAP Enable Bit, SFCF[6], enables In-Application Pro-
gramming mode. Until this bit is set all flash programming
IAP commands will be ignored.
4.2.4 In-Application Programming Mode Commands
All of the following commands can only be initiated in the
IAP Mode. In all situations, writing the control byte to the
SFCM register will initiate all of the operations. All com-
mands will not be enabled if the security locks are enabled
on the selected memory block.
The Block-Erase command erases all bytes in one of the
two memory blocks. The selection of the memory block to
be erased is determined by the source of Block-Erase
Command, as defined in Table 4-4.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
36
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
The Sector-Erase command erases all of the bytes in a
sector. The sector size for the flash memory Blocks is 128
Bytes. The selection of the sector to be erased is deter-
mined by the contents of SFAH and SFAL.
Prog-SC1 command is used to program the SC1 bit. This
command only changes the SC1 bit and has no effect on
BSEL bit until after a reset cycle.
SC1 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC1 command
should reside only in Block 1.
The Byte-Program command programs data into a single
byte. The address is determined by the contents of SFAH
and SFAL. The data byte is in SFDT.
There are no IAP counterparts for the External Host com-
mands Select-Block0 and Select-Block1.
The Byte-Verify command allows the user to verify that the
device has correctly performed an Erase or Program com-
mand.
4.2.5 Polling
A command that uses the polling method to detect flash
operation completion should poll on the FLASH_BUSY bit
(SFST[2]). When FLASH_BUSY de-asserts (logic 0), the
device is ready for the next operation.
Byte-Verify command returns the data byte in SFDT if the
command is successful. The user is required to check that
the previous Flash operation has fully completed before
issuing a Byte-Verify. Byte-Verify command execution time
is short enough that there is no need to poll for command
completion and no interrupt is generated.
MOVC instruction may also be used for verification of the
Programming and Erase operation of the flash memory.
MOVC instruction will fail if it is directed at a flash block that
is still busy.
Prog-SB3, Prog-SB2, Prog-SB1 commands are used to
program the Security bits (see Table 9-1). Completion of
any of these commands, the security options will be
updated immediately.
4.2.6 Interrupt Termination
If interrupt termination is selected, (SFCM[7] is set), then
an interrupt (INT1) will be generated to indicate flash opera-
tion completion. Under this condition, the INT1 becomes an
internal interrupt source. The INT1# pin can now be used
as a general purpose port pin and it cannot be the source
of External Interrupt 1 during In-Application Programming.
Security bits previously in un-programmed state can be
programmed by these commands. Prog-SB3, Prog-SB2
and Prog-SB1 commands should only reside in Block 1.
Prog-SC0 command is used to program the SC0 bit. This
command only changes the SC0 bit and has no effect on
BSEL bit until after a reset cycle.
In order to use an interrupt to signal flash operation termi-
nation. EX1 and EA bits of IE register must be set. The IT1
bit of TCON register must also be set for edge trigger
detection.
SC0 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC0 command
should reside only in Block 1.
.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
37
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
1
TABLE
4-5: IN-APPLICATION PROGRAMMING MODE COMMANDS FOR SST89E564RD/SST89V564RD
Operation
SFCM [6:0]2
0DH
SFDT [7:0]
55H
SFAH [7:0]
SFAL [7:0]
Block-Erase3
Sector-Erase3
Byte-Program3
Byte-Verify (Read)3
Prog-SB19
Prog-SB29
Prog-SB39
Prog-SC09
X4
AH5
AH
AH
X
X
AL6
AL
AL
X
0BH
X
DI7
DO8
0EH
0CH
0FH
AAH
AAH
AAH
AAH
03H
X
X
05H
X
X
09H
5AH
X
T4-5.0 555
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] =1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Refer to Table 4-4 for address resolution
4. X can be VIL or VIH, but no other value.
5. AH = Address high order byte
6. AL = Address low order byte
7. DI = Data Input
8. DO = Data Output
All other values are in hex
9. Instruction must be located in Block 1
.
1
TABLE
4-6: IN-APPLICATION PROGRAMMING MODE COMMANDS FOR SST89E554RC/SST89V554RC
Operation
SFCM [6:0]2
0DH
SFDT [7:0]
55H
SFAH [7:0]
SFAL [7:0]
Block-Erase3
Sector-Erase3
Byte-Program3
Byte-Verify (Read)3
Prog-SB110
Prog-SB210
Prog-SB310
Prog-SC010
Prog-SC110
AH4
AH6
AH
AH
X
X5
AL7
AL
AL
X
0BH
X
DI8
DO9
0EH
0CH
0FH
AAH
AAH
AAH
AAH
AAH
03H
X
X
05H
X
X
09H
5AH
AAH
X
09H
X
T4-6.0 555
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] =1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Refer to Table 4-4 for address resolution
4. SFAH[7]=0: Selects Block 0; SFAH[7:5] = 111b selects Block 1
5. X can be VIL or VIH, but no other value.
6. AH = Address high order byte
7. AL = Address low order byte
8. DI = Data Input
9. DO = Data Output
All other values are in hex
10. Instruction must be located in Block 1
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
38
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
4-7: FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS
Parameter1,2
Symbol
TSU
Min
Max
Units
µs
Reset Setup Time
3
1
Read-ID Command Width
PSEN# Setup Time
TRD
µs
TES
1.125
0
µs
Address, Command, Data Setup Time
Chip-Erase Time
TADS
TCE
ns
125
100
30
ms
ms
ms
µs
Block-Erase Time
TBE
Sector-Erase Time
TSE
Program Setup Time
TPROG
TDH
1.2
0
Address, Command, Data Hold
Byte-Program Time3
ns
TPB
50
500
80
µs
Select-Block Program Time
Security bit Program Time
Verify Command Delay Time
Verify High Order Address Delay Time
Verify Low Order Address Delay Time
TPSB
TPS
ns
µs
TOA
50
ns
TAHA
TALA
50
ns
50
ns
T4-7.0 555
1. Program and Erase times will scale inversely proportional to programming clock frequency.
2. All timing measurements are from the 50% of the input to 50% of the output.
3. Each byte must be erased before programming.
that uses the SBUF register as a destination register.
Reception is initiated in mode 0 when the Receive Interrupt
(RI) flag bit of the Serial Port Control (SCON) SFR is
cleared and the Reception Enable/ Disable (REN) bit of the
SCON register is set. Reception is initiated in the other
modes by the incoming start bit if the REN bit of the SCON
register is set.
5.0 TIMERS/COUNTERS
The device has three 16-bit registers that can be used as
either timers or event counters. The three Timers/Counters
are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2).
Each is designated a pair of 8-bit registers in the SFRs.
The pair consists of a most significant (high) byte and least
significant (low) byte. The respective registers are TL0,
TH0, TL1, TH1, TL2, and TH2.
6.1.1 Framing Error Detection
Framing Error Detection allows the serial port to auto-
matically check for valid stop bits in Modes 1, 2 or 3. If
a stop bit is missing the Framing Error bit (FE) will be
set. The software can then check this bit after a recep-
tion to detect communication errors. The FE bit must
be cleared by software.
6.0 SERIAL I/O
6.1 Enhanced Universal Asynchronous
Receiver/Transmitter (UART)
The device Serial I/O port is a full duplex port that allows
data to be transmitted and received simultaneously in
hardware by the transmit and receive registers, respec-
tively, while the software is performing other tasks. The
transmit and receive registers are both located in the
Serial Data Buffer (SBUF) special function register. Writ-
ing to the SBUF register loads the transmit register, and
reading from the SBUF register obtains the contents of
the receive register.
The FE bit is located in SCON and shares the same bit
address as SM0. The SMOD0 bit located in the PCON reg-
ister determines which of these two bits is accessed. When
SMOD0 = 0, SCON[7] will act as SM0. When SMOD0 = 1,
SCON[7] will act as FE.
6.1.2 Automatic Address Recognition
Automatic Address Recognition (AAR) reduces the CPU
time required to service the serial port in a multiprocessor
environment. When using AAR, the serial port hardware
will only generate an interrupt when it receives its own
address, thus eliminating the software overhead required to
compare addresses.
The UART has four modes of operation which are selected
by the Serial Port Mode Specifier (SM0 and SM1) bits of
the Serial Port Control (SCON) special function register. In
all four modes, transmission is initiated by any instruction
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
39
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
AAR is only available when using the serial port in either
Slave 2 will not respond to an address that has bit 0 set to 0
while Slave 1 will. Both slaves will respond to an address of
1111 0x01b so this is the Broadcast Address. The Broad-
cast Addresses is formed by the logical OR of SADDR and
SADEN with 0s treated as don’t-care bits.
mode 2 or 3. Setting the SM2 bit in SCON enables AAR.
Each slave must have its SM2 bit set when waiting for an
address (9th bit = 1). The Receive Interrupt (RI) flag will only
be set when the received byte matches either the Given or
Broadcast Address. The slave then clears its SM2 bit to
enable reception of data bytes (9th bit = 0) from the master.
6.2 Serial Peripheral Interface (SPI)
The master can selectively communicate with groups of
slaves by sending the Given Address. Addressing all
slaves is also possible by sending the Broadcast address.
The SADDR and SADEN special function registers define
these addresses for each slave.
The device SPI allows for high-speed full-duplex synchro-
nous data transfer between the device and other compati-
ble SPI devices.
Figure 6-1 shows the correspondence between master
and slave SPI devices. The SCK pin is the clock output and
input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master
devices SPI data register. The written data is then shifted
out of the MOSI pin on the master device into the MOSI pin
of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and
the SPIF flag is set. An SPI interrupt request will be gener-
ated if the SPI interrupt enable bit (SPIE) and the serial port
interrupt enable bit (ES) are both set.
SADDR specifies a slaves individual address and SADEN
is a mask byte that defines don’t-care bits to form the Given
address when combined with SADDR. The following is an
example:
UART Slave 1
SADDR
SADEN
GIVEN
=
=
=
1111 0001
1111 1010
1111 0x0x
An external master drives the Slave Select input pin, SS#/
P1[4], low to select the SPI module as a slave. If SS#/P1[4]
has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an
input port pin.
UART Slave 2
SADDR
SADEN
GIVEN
=
=
=
1111 0011
1111 1001
1111 0xx1
CPHA and CPOL control the phase and polarity of the SPI
clock. Figures 6-2 and 6-3 show the four possible combina-
tions of these two bits.
In this example Slave 1 can be distinguished from Slave 2
by using bits 0 and 1. Slave 1 will not respond to an
address that has bit 1 set to 1 while Slave 2 will. Similarly,
MSB MASTER LSB
8-bit Shift Register
MSB SLAVE LSB
8-bit Shift Register
MISO MISO
MOSI MOSI
SCK
SS#
SCK
SS#
SPI
Clock Generator
V
IH
555 ILL F15.0
FIGURE
6-1: SPI MASTER-SLAVE INTERCONNECTION
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
40
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SCK Cycle #
(for reference)
SCK (CPOL=0)
1
2
3
4
5
6
7
8
SCK (CPOL=1)
MOSI
MSB
6
5
4
3
2
1
LSB
LSB
(from Master)
MISO
(from Slave)
MSB
6
5
4
3
2
1
*
SS# (to Slave)
555 ILL F16.0
* Not defined, but normally MSB of next received byte
FIGURE
6-2: SPI TRANSFER FORMAT WITH CPHA = 0
SCK Cycle #
(for reference)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
MSB
6
5
4
3
2
2
1
1
LSB
(from Master)
MISO
(from Slave)
6
5
4
3
LSB
*
SS# (to Slave)
555 ILL F17.0
* Not defined but normally LSB of previously transmitted character
FIGURE
6-3: SPI TRANSFER FORMAT WITH CPHA = 1
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
41
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and auto-
matic recovery.
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily sus-
pended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDT) * 344064 * 1/fOSC
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will incre-
ment every 344064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
where WDT is the value loaded into the WDT register and
fOSC is the oscillator frequency.
344064
clks
WDT Reset
CLK (XTAL1)
Internal Reset
Counter
WDT Upper Byte
Ext. RST
WDTC
WDTD
555 ILL F18.0
FIGURE
7-1: BLOCK DIAGRAM OF PROGRAMMABLE WATCHDOG TIMER
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
42
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
8.0 PROGRAMMABLE COUNTER ARRAY (PCA)
The device is equipped with an integrated Program
Counter Array (PCA). The PCA consists of a dedicated
timer/counter that serves as the common time base for an
array of 5 compare/capture modules. Each of the modules
can be programmed in 1 of 4 modes. Additionally, the 5th
module can be programmed as a Watchdog Timer.
TABLE
8-2: POSSIBLE MODES AND ASSOCIATED
VALUES FOR CCAPMN
CCAPMn Value
without
interrupt
enabled
with
interrupt
enabled
Module Function
Capture Positive Edge Only
Capture Negative Edge Only
Capture Both Edges
16-Bit Software Timer
High Speed Output
20H
10H
21H
11H
31H
49H
4DH
43H
8.1 PCA Timer/Counter
The timer/counter for the PCA is a free-running 16 timer
and consists of registers CH and CL (the high and low
bytes of the count values). These registers can be read and
written to at any time. The Count Pulse Select bits (CPS1 &
CPS0) in the CMOD register configure the timer/counter to
operate in 1 of 4 modes. See Table 8-1. The CMOD regis-
ter also contains the Counter Idle (CIDL) bit. When CIDL =
1 the PCA timer/counter will be turned off when the MCU
enters Idle Mode
30H
48H
4CH
Pulse Width Modulator
Watchdog Timer1
42H
48H or 4CH
-
T8-2.0 555
1. Only for Module 4
Additionally each of the five modules has two 8-bit capture/
compare registers (CCAPnH & CCAPnL) and an external
input/output pin associated with it. The external input/output
pins are P1.3 for Module 0, P1.4 for Module 1, P1.5 for
Module 2, P1.6 for Module 3 and P1.7 for Module 4. Each
module also has an associated event flag CCFn located in
CCON register. These flags must be cleared by software.
.
TABLE
8-1: COUNT PULSE SELECTED BITS
CPS0 PCA Count Pulse Selected
CPS1
0
0
1
1
0
1
0
1
Internal Clock, FOSC / 12
Internal Clock, FOSC / 4
Timer 0 Overflow
Writing to CCAPnL will disable the compare feature of the
corresponding module and writing to CCAPnH will re-
enable it. Therefore, when using the compare feature (16-
Bit Software Timer, High Speed Output, Pulse Width Mod-
ulator & Watchdog Timer modes) the software should
always write to CCAPnL first and then write to CCAPnH
second.
External Clock at P1.2
T8-1.0 555
The Counter Run bit (CR) in CCON register turns the timer/
counter on and off. When CR = 1 the timer/counter is run-
ning and when CR = 0 the timer/counter will be disabled.
When the PCA timer/counter overflows the CF bit in CCON
register will be set and if the ECF bit in CMOD register is
set an interrupt will be generated.
8.2.1 Capture Mode
Capture Mode is used to capture the PCA timer/counter
value into a module’s capture registers (CCAPnH &
CCAPnL). The capture will occur on a positive edge, a neg-
ative edge or both edges of the input signal on the corre-
sponding external input pin depending on which mode is
selected. Also, the event flag (CCFn) is set and an interrupt
is generated if ECCFn is set.
8.2 PCA Compare/Capture Modules
Each of the 5 Compare/Capture modules has a mode reg-
ister called CCAPMn (n = 0, 1, 2, 3, or 4) which selects the
function it will perform. The seven possible modes and their
associated values for CCAPMn are shown in Table 8-2.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
43
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
8.2.2 16-Bit Software Timer Mode
9.0 SECURITY LOCK
In the 16-bit Software Timer mode the PCA timer/counter
value is compared with the 16-bit value pre-loaded into the
module’s compare registers (CCAPnH & CCAPnL). When
a match occurs, the event flag (CCFn) is set and an inter-
rupt is generated if ECCFn is set.
The Security Lock protects against software piracy and
prevents the contents of the flash from being read by unau-
thorized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory. There are two different types of
security locks in the device security lock system: Hard Lock
and SoftLock.
8.2.3 High Speed Output Mode
In the High Speed Output mode, the PCA timer/counter is
compared with the 16-bit value pre-loaded into the module’s
compare registers (CCAPnH & CCAPnL). When a match
occurs, the modules corresponding output pin is toggled.
Additionally the event flag (CCFn) is set and an interrupt is
generated if ECCFn is set. The frequency of the output is
only dependent on the PCA timer/counter and will be the
same for all 5 modules but the duty cycle can vary depend-
ing on the value pre-loaded into the compare registers.
9.1 Hard Lock
When Hard Lock is activated, MOVC or IAP instructions
executed from an unlocked or SoftLocked program
address space, are disabled from reading code bytes in
Hard Locked memory blocks (See Table 9-2). Hard Lock
can either lock both flash memory blocks or just lock the 8
KByte flash memory block (Block 1). All External Host and
IAP commands except for Chip-Erase are ignored for
memory blocks that are Hard Locked.
8.2.4 Pulse Width Modulator
The Pulse Width Modulator mode generates 1-bit PWMs
by comparing the low byte of the PCA timer (CL) with the
low byte of the compare registers (CCAPnL). When CL <
CCAPnL the corresponding output pin is low. When CL >
CCAPnL the corresponding output pin is high. The fre-
quency of the PWM is only dependent on the PCA timer/
counter and will be the same for all 5 modules. The duty
cycle will vary depending on the value in CCAPnL.
CCAPnL can be changed dynamically by loading a new
value into CCAPnH. This new value will be shifted into
CCAPnL when CL rolls over from FFH to 00H.
9.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the SoftLocked memory block through In-
Application Programming Mode under a predetermined
secure environment. For example, if Block 1 (8K) memory
block is locked (Hard Locked or SoftLocked), and Block 0
(64K for SST89E564RD/SST89V564RD) memory block is
SoftLocked, code residing in Block 1 can program Block 0.
The following IAP mode commands issued through the
command mailbox register, SFCM, executed from a
Locked (Hard Locked or SoftLocked) block, can be oper-
ated on a SoftLocked block: Block-Erase, Sector-Erase,
Byte-Program and Byte-Verify.
8.2.5 Watchdog Timer
Only Module 4 can be programmed as a Watchdog Timer
(but it can still be programmed to the other modes if the
Watchdog Timer mode is not used). The Watchdog Timer
compares the PCA timer/counter value (CH & CL) with
Module 4’s compare registers (CCAP4H & CCAP4L).
When a match occurs, an internal reset will be generated if
the WDTE bit in CMOD register is set. This internal reset
will not cause the RST pin to be driven high. In order to
hold of the reset the user must periodically change the
compare value so it will never match the PCA timer.
In External Host Mode, SoftLock behaves the same as a
Hard Lock.
9.3 Security Lock Status
The three bits that indicate the device security lock
status are located in SFST[7:5]. As shown in Figure 9-
1 and Table 9-1, the three security lock bits control the
lock status of the primary and secondary blocks of
memory. There are four distinct levels of security lock
status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the
second level, although both blocks are now locked and
cannot be programmed, they are available for read
operation via Byte-Verify. In the third level, three differ-
ent options are available: Block 1 Hard Lock / Block 0
SoftLock, SoftLock on both blocks, and Hard Lock on
both blocks. Locking both blocks is the same as Level
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
44
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
2 except read operation isn’t available. The fourth level
of security is the most secure level. It doesn’t allow
read/program of internal memory or boot from external
memory. Please note that for unused combinations of
the security lock bits, the chip will default to Level 4
status. For details on how to program the security lock
bits refer to the External Host Mode and In-Application
Programming Section.
Level 1
Level 2
UUU/NN
PUU/SS
UPU/SS
UUP/LS
Level 3
UPP/LL
PPU/LS
PUP/LL
UPP/LL
Level 4
PPP/LL
555 ILL F19.0
FIGURE
9-1: SECURITY LOCK LEVELS
Note: P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked
.
TABLE
9-1: SECURITY LOCK OPTIONS
Security Lock Bits1,2
Security Status of:
Block 1 Block 0
Unlock Unlock
Level
SFST[7:5]
000
SB1
U
SB21
U
SB31
U
Security Type
1
2
No Security Features are Enabled.
100
P
U
U
SoftLock
SoftLock
MOVC instructions executed from
external program memory are dis-
abled from fetching code bytes from
internal memory, EA# is sampled and
latched on Reset, and further pro-
gramming of the flash is disabled.
3
4
011
101
U
P
P
U
P
P
Hard Lock
SoftLock
Hard Lock
SoftLock
Level 2 plus Verify disabled, both
blocks locked.
010
U
P
U
Level 2 plus Verify disabled. Code in
Block 1 may program Block 0 and vice
versa.
110
001
P
U
P
U
U
P
Hard Lock
Hard Lock
SoftLock
Level 2 plus Verify disabled. Code in
Block 1 may program Block 0.
111
P
P
P
Hard Lock
Same as Level 3 Hard Lock/Hard
Lock, but MCU will start code execu-
tion from the internal memory regard-
less of EA#.
T9-1.0 555
1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1).
2. SFST[7:5] = Security Lock Decoding Bits (SECD)
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
45
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE
9-2: SECURITY LOCK ACCESS TABLE
Source
External Host
Byte-Verify
Allowed2
IAP
Byte-Verify
Allowed
MOVC
Allowed
on 564RD on 554RC
MOVC
Allowed
Target
Level
SFST[7:5]
Address Address1
Block 0/1
Block 0/1
N
N/A
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
Y
N
Y
N
N
N
N
N
Y
N
Y
N
N
N
N
N
Y
N
Y
N
N
Y
N
Y
N
N
N
Y
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
N
Y
Y
N
N
Y
Y
Y
N
Y
Y
N
N
Y
Y
Y
N
Y
Y
N
N
Y
Y
N
N
N
Y
Y
N
Y
Y
N
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
External
111b
4
(Hard Lock on both blocks)
Block 0/1
External
External
N/A
N
Block 0/1
Block 0/1
External
N
011b/101b
(Hard Lock on both blocks)
Block 0/1
External
N
External
N/A
N
Block 0
Block 0
Block 1
External
Block 0
Block 1
External
Block 0/1
External
Block 0
Block 1
External
Block 0
Block 1
External
Block 0/1
External
Block 0
Block 1
External
Block 0
Block 1
External
Block 0/1
External
Block 0
Block 1
External
Block 0
Block 1
External
Block 0/1
External
N
N/A
N
001b/110b
(Block 0 = SoftLock,
Block 1 = Hard Lock)
Block 1
External
Block 0
N
N/A
N
3
N/A
N
N
N/A
N
010b
(SoftLock on both blocks)
Block 1
External
Block 0
N
N/A
N
N/A
Y
Y
N/A
Y
100b
2
(SoftLock on both blocks)
Block 1
External
Block 0
Y
N/A
Y
N/A
Y
Y
N/A
Y
000b
(Unlock)
1
Block 1
Y
N/A
Y
External
N/A
Y
T9-2.0 555
1. Location of MOVC instruction
2. External Host Byte-Verify access does not depend on a source address.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
46
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
10.0 RESET
A system reset initializes the MCU and begins program
V
DD
execution at program memory location 0000H. The reset
input for the device is the RST pin. In order to reset the
device, a logic level high must be applied to the RST pin for
at least two machine cycles (24 clocks), after the oscillator
becomes stable. ALE, PSEN# are weakly pulled high dur-
ing reset. During reset, ALE and PSEN# output a high level
in order to perform a proper reset. This level must not be
affected by external element. A system reset will not affect
the 1 KByte of on-chip RAM while the device is running,
however, the contents of the on-chip RAM during power up
are indeterminate. Following reset, all Special Function
Registers (SFR) return to their reset values outlined in
Tables 3-5 to 3-9.
+
-
10µF
8.2K
V
DD
RST
SST89E5x4/V5x4
C
2
XTAL2
XTAL1
C
1
555 ILL F20.0
FIGURE 10-1: POWER-ON RESET CIRCUIT
10.1 Power-On Reset
At initial power up, the port pins will be in a random state
until the oscillator has started and the internal reset algo-
rithm has weakly pulled all pins high. Powering up the
device without a valid reset could cause the MCU to
start executing instructions from an indeterminate
location. Such undefined states may inadvertently cor-
rupt the code in the flash.
10.2 Software Reset
The software reset is executed by changing SFCF[1]
(SWR) from “0” to “1”. A software reset will reset the pro-
gram counter to address 0000H. All SFR registers will be
set to their reset values, except SFCF[1] (SWR), WDTC[2]
(WDTS), and RAM data will not be altered.
When power is applied to the device, the RST pin must be
held high long enough for the oscillator to start up (usually
several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid Power-On Reset. An
example of a method to extend the RST signal is to imple-
ment a RC circuit by connecting the RST pin to VDD
through a 10 µF capacitor and to VSS through an 8.2KΩ
resistor as shown in Figure 10-1. Note that if an RC circuit
is being used, provisions should be made to ensure the
VDD rise time does not exceed 1 millisecond and the oscil-
lator start-up time does not exceed 10 milliseconds.
10.3 Brown-out Detection Reset
The device includes a Brown-out detection circuit to protect
the system from severe VDD fluctuations. For Brown-out
voltage parameters, please refer to Tables 11-3 and 11-4.
Brown-out interrupt can be enabled by setting the EBO bit
in IEA register (address E8H, bit 3). If EBO bit is set and a
Brown-out condition occurs, a Brown-out interrupt will be
generated to execute the program at location 004BH. It is
required that the EBO bit be cleared by software after the
Brown-out interrupt is serviced. Clearing EBO bit when the
Brown-out condition is active will properly reset the device.
For a low frequency oscillator with slow start-up time the
reset signal must be extended in order to account for the
slow start-up time. This method maintains the necessary
relationship between VDD and RST to avoid programming
at an indeterminate location, which may cause corruption
in the code of the flash. For more information on system
level design techniques, please review Design Consider-
ations for the SST FlashFlex51 Family Microcontroller
Application Note.
If Brown-out interrupt is not enabled, a Brown-out condition
will reset the program to resume execution at location 0000H.
10.4 Interrupt Priority and Polling
Sequence
The device supports eight interrupt sources under a four
level priority scheme. Table 10-1 summarizes the polling
sequence of the supported interrupts. Note that the SPI
serial interface and the UART share the same interrupt
vector.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
47
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 10-1: INTERRUPT POLLING SEQUENCE
Vector
Address
Interrupt
Enable
Interrupt
Priority
Arbitration
Ranking
Wake-Up
Power Down
Description
Ext. Int0
Brown-out
T0
Interrupt Flag
IE0
0003H
004BH
000BH
0013H
001BH
0023H
002BH
EX0
EBO
ET0
EX1
ET1
ES
PX0/H
PBO/H
PT0/H
PX1/H
PT1/H
PS/H
1(highest)
yes
no
BOF
2
3
4
5
6
7
TF0
no
Ext. Int1
T1
IE1
yes
no
TF1
UART/SPI
T2
TI/RI/SPIF
TF2, EXF2
no
ET2
PT2/H
no
T10-1.0 555
The device exits Power Down mode through either an
enabled external level sensitive interrupt or a hardware
reset. The start of the interrupt clears the PD bit and exits
Power Down. Holding the external interrupt pin low restarts
the oscillator, the signal must hold low at least 1024 clock
cycles before bringing back high to complete the exit. After
exit the interrupt service routine program execution
resumes beginning at the instruction immediately following
the instruction which invoked Power Down mode. A hard-
ware reset starts the device similar to power-on reset.
10.5 Power-Saving Modes
The device provides three power saving modes of opera-
tion for applications where power consumption is critical.
The three power saving modes are: Idle, Power Down and
Standby (Stop Clock).
10.5.1 Idle Mode
Idle mode is entered setting the IDL bit in the PCON regis-
ter. In Idle mode, the program counter (PC) is stopped. The
system clock continues to run and all interrupts and periph-
erals remain active. The on-chip RAM and the special func-
tion registers hold their data during this mode.
To exit properly out of Power Down, the reset or external
interrupt should not be executed before the VDD line is
restored to its normal operating voltage. Be sure to hold
VDD voltage long enough at its normal operating level for
the oscillator to restart and stabilize (normally less than
10 ms).
The device exits Idle mode through either a system inter-
rupt or a hardware reset. Exiting Idle mode via system
interrupt, the start of the interrupt clears the IDL bit and
exits Idle mode. After exit the Interrupt Service Routine, the
interrupted program resumes execution beginning at the
instruction immediately following the instruction which
invoked the Idle mode. A hardware reset starts the device
similar to a power-on reset.
10.5.3 Standby Mode (Stop Clock)
Standby mode is similar to Power Down mode, except that
Power Down mode is initiated by a software command and
Standby mode is initiated by external hardware gating off
the external clock to the device.The on-chip SRAM and
SFR data are maintained in Standby mode. The device
resumes operation at the next instruction when the clock is
reapplied to the part.
10.5.2 Power Down Mode
The Power Down mode is entered by setting the PD bit in
the PCON register. In the Power Down mode, the clock is
stopped and external interrupts are active for level sensitive
interrupts only. To retain the on-chip RAM and all of the spe-
cial function registers’ values, the minimum VDD level is 2.0V.
Table 10-2 outlines the different power-saving modes,
including entry and exit procedures and MCU functionality.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
48
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 10-2: POWER SAVING MODES
Mode
Initiated by
State of MCU
CLK is running.
Interrupts, serial port and tim- Start of interrupt clears IDL bit and
ers/counters are active. Pro- exits Idle mode, after the ISR RETI
Exited by
Idle Mode
Software
(Set IDL bit in
PCON)
Enabled interrupt or hardware reset.
gram Counter is stopped.
ALE and PSEN# signals at a tion beginning at the instruction follow-
HIGH level during Idle. All ing the one that invoked Idle mode. A
instruction, program resumes execu-
registers remain unchanged. user could consider placing two or
three NOP instructions after the
instruction that invokes idle mode to
eliminate any problems. A hardware
reset restarts the device similar to a
power-on reset.
Power Down
Mode
Software
(Set PD bit in
PCON)
CLK is stopped. On-chip
SRAM and SFR data is main- rupt or hardware reset. Start of inter-
tained. ALE and PSEN# sig- rupt clears PD bit and exits Power
Enabled external level sensitive inter-
nals at a LOW level during
Down mode, after the ISR RETI
Power Down. External Inter- instruction program resumes execution
rupts are only active for level beginning at the instruction following
sensitive interrupts, if
enabled.
the one that invoked Power Down
mode. A user could consider placing
two or three NOP instructions after the
instruction that invokes Power Down
mode to eliminate any problems. A
hardware reset restarts the device sim-
ilar to a power-on reset.
Standby (Stop
Clock) Mode
External hardware gates OFF
the external clock input to the
MCU. This gating should be
synchronized with an input
clock transition (low-to-high or
high-to-low).
CLK is frozen. On-chip SRAM Gate ON external clock. Program exe-
and SFR data is maintained. cution resumes at the instruction fol-
ALE and PSEN# are main-
tained at the levels prior to
the clock being frozen.
lowing the one during which the clock
was gated off.
T10-2.0 555
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
49
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
10.6 Clock Input Options
10.7 Recommended Capacitor Values for
Crystal Oscillator
Shown in Figure 10-2 are the input and output of an inter-
nal inverting amplifier (XTAL1, XTAL2), which can be con-
figured for use as an on-chip oscillator.
Crystal manufacturer, supply voltage, and other factors
may cause circuit performance to differ from one applica-
tion to another. C1 and C2 should be adjusted appropri-
ately for each design. The table below, shows the typical
values for C1 and C2 at a given frequency. If following the
satisfactory selection of all external components, the circuit
is still over driven, a series resistor, Rs, may be added.
When driving the device from an external clock source,
XTAL2 should be left disconnected and XTAL1 should be
driven.
At start-up, the external oscillator may encounter a higher
capacitive load at XTAL1 due to interaction between the
amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal
meets the VIL and VIH specifications.
RECOMMENDED VALUES FOR CRYSTAL OSCILLATOR
Frequency
< 8MHz
C1 and C2
90-110pF
18-22pF
RS (Optional)
100Ω
8-12MHz
>12MHz
200Ω
18-22pF
200Ω
More specific information about on-chip oscillator design
can be found in FlashFlex 51 Oscillator Circuit Design Con-
siderations Application Note.
R
S
XTAL2
C
C
NC
XTAL2
XTAL1
2
EXTERNAL
OSCILLATOR
SIGNAL
1
XTAL1
Vss
Vss
555 ILL F21.0
External Clock Drive
Using the On-Chip Oscillator
FIGURE 10-2: OSCILLATOR CHARACTERISTICS
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
50
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.0 ELECTRICAL SPECIFICATION
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to + 150°C
Voltage on EA# Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
Transient Voltage (<20ns) on Any Other Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +6.5V
Maximum IOL per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
Maximum IOL per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
(Based on package heat transfer limitations, not device power consumption.
Note: This specification contains preliminary information on new products in production.
The specifications are subject to change without notice.
11.1 Operation Range
TABLE 11-1: OPERATING RANGE
Symbol
Description
Min.
Max
Unit
Ta
Ambient Temperature Under Bias
Standard
0
-40
2.7
0
+70
+85
5.5
40
°C
°C
Industrial
VDD
fOSC
Supply Voltage
V
Oscillator Frequency
MHz
MHz
For In-Application Programming
0.25
40
T11-1.0 555
11.2 Reliability Characteristics
TABLE 11-2: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T11-2.0 555
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
51
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.3 DC Electrical Characteristics
TABLE 11-3: DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C TO +70°C OR -40°C TO +85°C, 40MHZ DEVICES; 4.5-5.5V; VSS = 0V
Symbol Parameter
Test Conditions
4.5 < VDD < 5.5
4.5 < VDD < 5.5
4.5 < VDD < 5.5
VDD = 4.5V
Min
-0.5
Max
Units
VIL
Input Low Voltage
0.2VDD - 0.1
VDD + 0.5
VDD + 0.5
V
V
V
VIH
VIH1
VOL
Input High Voltage
0.2VDD + 0.9
0.7VDD
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
IOL = 16mA
1.0
V
VOL
Output Low Voltage (Ports 1, 2, 3)1
VDD = 4.5V
IOL = 100µA2
IOL = 1.6mA2
IOL = 3.5mA2
VDD = 4.5V
0.3
0.45
1.0
V
V
V
VOL1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
IOL = 200µA2
IOL = 3.2mA2
VDD = 4.5V
0.3
V
V
0.45
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
IOH = -10µA
IOH = -30µA
IOH = -60µA
VDD = 4.5V
VDD - 0.3
VDD - 0.7
VDD - 1.5
V
V
V
VOH1
Output High Voltage (Port 0 in External Bus Mode)4
IOH = -200µA
IOH = -3.2mA
VDD - 0.3
VDD - 0.7
3.85
V
V
VBOD
IIL
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
Input Leakage Current (Port 0)
RST Pull-down Resistor
Pin Capacitance6
Power Supply Current7
In-Application Mode
@ 20 MHz
4.15
-75
V
VIN = 0.4V
VIN = 2V
-1
µA
µA
µA
kΩ
pF
ITL
-650
±10
225
15
ILI
0.45 < VIN < VDD-0.3
RRST
CIO
IDD
40
@ 1 MHz, 25°C
70
88
mA
mA
@ 40 MHz
Active Mode
@ 20 MHz
25
45
mA
mA
@ 40 MHz
Idle Mode
@ 20 MHz
9.5
20
mA
mA
µA
@ 40 MHz
Standby (Stop Clock) Mode
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Minimum VDD = 2V
100
125
µA
Power Down Mode
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
40
50
µA
µA
T11-3.0 555
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
52
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 11-4: DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C TO +70°C OR -40°C TO +85°C, 25MHZ DEVICES; 2.7-3.6V; VSS = 0V
Symbol Parameter
Test Conditions
2.7 < VDD < 3.3
2.7 < VDD < 3.3
2.7 < VDD < 3.3
VDD = 2.7V
Min
Max
Units
VIL
Input Low Voltage
-0.5
0.7
V
V
V
VIH
VIH1
VOL
Input High Voltage
0.2VDD + 0.9 VDD + 0.5
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
0.7VDD
VDD + 0.5
1.0
IOL = 16mA
V
VOL
Output Low Voltage (Ports 1, 2, 3)1
VDD = 2.7V
I
OL = 100µA2
0.3
0.45
1.0
V
V
V
IOL = 1.6mA2
IOL = 3.5mA2
VDD = 2.7V
IOL = 200µA2
IOL = 3.2mA2
VDD = 2.7V
IOH = -10µA
IOH = -30µA
IOH = -60µA
VDD = 2.7V
IOH = -200µA
IOH = -3.2mA
VOL1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
0.3
V
V
0.45
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
VDD - 0.3
VDD - 0.7
VDD - 1.5
V
V
V
VOH1
Output High Voltage (Port 0 in External Bus Mode)4
VDD - 0.3
VDD - 0.7
2.25
V
V
VBOD
IIL
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
Input Leakage Current (Port 0)
RST Pull-down Resistor
Pin Capacitance6
2.55
-75
V
VIN = 0.4V
VIN = 2V
-1
µA
µA
µA
kΩ
pF
ITL
-650
±10
225
15
ILI
0.45 < VIN < VDD-0.3
RRST
CIO
IDD
@ 1 MHz, 25°C
Power Supply Current7
In-Application Mode
70
22
6.5
70
88
mA
mA
mA
µA
Active Mode
Idle Mode
Standby (Stop Clock) Mode
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Minimum VDD = 2V
µA
Power Down Mode
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
40
50
µA
µA
T11-4.1 555
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
15mA
26mA
Maximum IOL total for all outputs: 71mA
If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due
to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
53
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
4. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when
the address bits are stabilizing.
5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
7. See Figures 11-1, 11-2, 11-3 and 11-4 for test conditions. Minimum VDD for Power Down is 2.0V.
V
V
DD
I
DD
I
V
DD = 2V
V
DD
DD
V
V
DD
V
DD
P0
DD
P0
DD
V
DD
RST
EA#
RST
EA#
89x564
89x564
XTAL2
XTAL1
XTAL2
XTAL1
(NC)
(NC)
CLOCK
SIGNAL
V
V
SS
SS
555 ILL F24.0
555 ILL F22.0
All other pins disconnected
All other pins disconnected
FIGURE 11-3: IDD TEST CONDITION,
POWER-DOWN MODE
FIGURE 11-1: IDD TEST CONDITION,
ACTIVE MODE
V
V
DD
I
DD
I
V
DD = 5V
DD
DD
V
V
V
V
DD
P0
DD
DD
P0
DD
RST
EA#
RST
89x564
EA#
89x564
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
V
V
SS
SS
555 ILL F25.0
555 ILL F23.0
All other pins disconnected
All other pins disconnected
FIGURE 11-2: IDD TEST CONDITION,
IDLE MODE
FIGURE 11-4: IDD TEST CONDITION,
STANDBY (STOP CLOCK) MODE
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
54
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
11.4 AC Electrical Characteristics
AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load
Capacitance for All Other Outputs = 80pF)
TABLE 11-5: AC ELECTRICAL CHARACTERISTICS (1 OF 2)
Tamb = 0°C TO +70°C OR -40°C TO +85°C, VDD = 2.7-3.6V @25MHZ, 4.5-5.5V @ 40MHZ, VSS = 0
Oscillator
25MHz
40MHz
Variable
Symbol
1/TCLCL
TLHLL
Parameter
Min Max Min Max
Min
Max
Units
MHz
ns
0
40
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
65
15
35
10
10
2TCLCL - 15
TCLCL - 25 (3V)
TCLCL - 15 (5V)
TCLCL - 25 (3V)
TCLCL - 15 (5V)
ns
TAVLL
ns
15
ns
TLLAX
TLLIV
TLLPL
Address Hold After ALE Low
ALE Low to Valid Instr In
ALE Low to PSEN# Low
ns
95
65
4TCLCL - 65 (3V)
4TCLCL - 45 (5V)
ns
55
ns
15
95
TCLCL - 25 (3V)
ns
10
60
T
CLCL - 15 (5V)
ns
3TCLCL - 25 (3V)
3TCLCL - 15 (5V)
ns
TPLPH
TPLIV
PSEN# Pulse Width
3TCLCL - 55 (3V)
3TCLCL - 50 (5V)
ns
ns
ns
ns
ns
ns
ns
ns
ns
PSEN# Low to Valid Instr In
25
10
0
TPXIX
TPXIZ
Input Instr Hold After PSEN#
Input Instr Float After PSEN#
35
120
10
TCLCL - 5 (3V)
TCLCL - 15 (5V)
5TCLCL - 80 (3V)
5TCLCL - 60 (5V)
10
TAVIV
Address to Valid Instr In
65
10
TPLAZ
TRLRH
PSEN# Low to Address Float
RD# Pulse Width
200
200
6TCLCL - 40 (3V)
6TCLCL - 30 (5V)
120
120
6TCLCL - 40 (3V)
6TCLCL - 30 (5V)
ns
TWLWH
TRLDV
Write Pulse Width (WE#)
RD# Low to Valid Data In
110
5TCLCL - 90 (3V)
5TCLCL - 50 (5V)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75
0
0
0
TRHDX
TRHDZ
Data Hold After RD#
Data Float After RD#
55
2TCLCL - 25 (3V)
2TCLCL - 12 (5V)
8TCLCL - 90 (3V)
8TCLCL - 50 (5V)
9TCLCL - 90 (3V)
9TCLCL - 75 (5V)
38
230
270
145
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TWHQX
ALE Low to Valid Data In
Address to Valid Data In
150
150
90
95
85
3TCLCL - 25 (3V)
3TCLCL - 15 (5V)
3TCLCL + 25 (3V)
3TCLCL + 15 (5V)
ALE Low to RD# or WR# Low
Address to RD# or WR# Low
60
70
4TCLCL - 75 (3V)
4TCLCL - 30 (5V)
ns
ns
Data Valid to WR# High to Low
Transition
0
0
0
ns
ns
ns
13
TCLCL - 27 (3V)
TCLCL - 20 (5V)
Data Hold After WR#
5
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
55
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 11-5: AC ELECTRICAL CHARACTERISTICS (CONTINUED) (2 OF 2)
Tamb = 0°C TO +70°C OR -40°C TO +85°C, VDD = 2.7-3.6V @25MHZ, 4.5-5.5V @ 40MHZ, VSS = 0
Oscillator
25MHz
40MHz
Variable
Symbol
Parameter
Min Max Min Max
Min
Max
Units
ns
433
7TCLCL - 70 (3V)
7TCLCL - 50 (5V)
TQVWH
Data Valid to WR# High
125
ns
RD# Low to Address Float
0
0
0
ns
TRLAZ
RD# to WR# High to ALE High
43
123
TCLCL - 25 (3V)
TCLCL - 15 (5V)
TCLCL + 25 (3V)
TCLCL + 15 (5V)
ns
TWHLH
10
40
ns
T11-5.0 555
11.5 AC Characteristics
Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for
time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that
signal. The following is a list of all the characters and what they stand for.
A: Address
Q: Output data
C: Clock
R: RD# signal
D: Input data
T: Time
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW or ALE
P: PSEN#
V: Valid
W: WR# signal
X: No longer a valid logic level
Z: High Impedance (Float)
For example:
AVLL = Time from Address Valid to ALE Low
T
TLLPL = Time from ALE Low to PSEN# Low
V
V
+0.1V
-0.1V
IHT
LOAD
V
V
-0.1V
V
OH
OL
HT
Timing Reference
Points
V
LOAD
V
V
LT
+0.1V
V
LOAD
ILT
555 ILL F26a.0
555 ILL F26b.0
AC Inputs during testing are driven at V
(V
-0.5V) for Logic "1" and
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, and begins to float when a 100 mV
IHT DD
V
(0.45V) for a Logic "0". Measurement reference points for inputs and
ILT
outputs are at V
(0.2V
+ 0.9) and V (0.2V
- 0.1)
change from the loaded V /V
level occurs. I /I = ± 20mA.
HT
DD
LT
DD
OH OL
OL OH
Note: V - V
Test
Test
HIGH Test
LOW Test
HT HIGH
V
V
V
- V
-V
LT
LOW
IHT INPUT
- V
ILT INPUT
FIGURE 11-5: AC TESTING INPUT/OUTPUT, FLOAT WAVEFORM
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
56
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
T
LHLL
ALE
T
PLPH
T
T
LLIV
AVLL
T
LLPL
T
PLIV
PSEN#
T
PLAZ
T
PXIZ
PXIX
INSTR IN
T
LLAX
T
A7 - A0
PORT 0
PORT 2
A7 - A0
T
AVIV
A15 - A8
A15 - A8
555 ILL F27.0
FIGURE 11-6: EXTERNAL PROGRAM MEMORY READ CYCLE
T
LHLL
ALE
T
WHLH
PSEN#
T
LLDV
T
RLRH
T
LLWL
RD#
T
LLAX
T
T
RHDZ
RLDV
T
AVLL
T
RLAZ
T
RHDX
A7-A0 FROM PCL
A7-A0 FROM RI or DPL
DATA IN
INSTR IN
PORT 0
PORT 2
T
AVWL
T
AVDV
P2[7:0] or A15-A8 FROM DPH
A15-A8 FROM PCH
555 ILL F28.0
FIGURE 11-7: EXTERNAL DATA MEMORY READ CYCLE
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
57
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
T
LHLL
ALE
T
WHLH
PSEN#
T
T
WLWH
LLWL
WR#
T
T
LLAX
T
WHQX
T
QVWX
AVLL
T
QVWH
A7-A0 FROM RI or DPL
PORT 0
PORT 2
DATA OUT
A7-A0 FROM PCL
INSTR IN
T
AVWL
P2[7:0] or A15-A8 FROM DPH
A15-A8 FROM PCH
555 ILL F29.0
FIGURE 11-8: EXTERNAL DATA MEMORY WRITE CYCLE
TABLE 11-6: EXTERNAL CLOCK DRIVE
25MHz
Oscillator
40MHz
Variable
Symbol
1/TCLCL
TCHCX
TCLCX
Parameter
Oscillator Frequency
High Time
Min
Max
Min
Max
Min
Max
40
Units
MHz
ns
0
0.35TCLCL
0.35TCLCL
0.65TCLCL
0.65TCLCL
Low Time
ns
TCLCH
Rise Time
20
20
10
10
ns
TCHCL
Fall Time
ns
T11-6.0 555
V
DD = -0.5
0.7 V
DD
-0.1
T
CHCX
0.2 V
0.45 V
DD
T
T
CLCH
CLCX
T
CLCL
T
CHCL
555 ILL F30.0
FIGURE 11-9: EXTERNAL CLOCK DRIVE WAVEFORM
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
58
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
TABLE 11-7: SERIAL PORT TIMING
Oscillator
25MHz
40MHz
Variable
Symbol Parameter
Min Max Min Max
Min
Max
Units
ms
ns
TXLXL
TQVXH
TXHQX
Serial Port Clock Cycle Time
0
0.36
117
12TCLCL
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
700
50
10TCLCL - 133
2TCLCL - 117
2TCLCL - 50
0
ns
0
0
ns
TXHDX
TXHDV
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
0
ns
700
117
10TCLCL - 133
ns
T11-7.0 555
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
T
XLXL
CLOCK
T
XHQX
T
QVXH
0
1
2
3
4
5
6
7
OUTPUT DATA
T
XHDX
T
SET TI
WRITE TO SBUF
INPUT DATA
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET R I
CLEAR RI
555 ILL F31.0
FIGURE 11-10: SHIFT REGISTER MODE TIMING WAVEFORMS
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
59
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
12.0 PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST89x5x4xx
-
XX
-
X
-
X X
Package Modifier
I = 40 pins
J = 44 pins
Package Type
P = PDIP
N = PLCC
TQ = TQFP
Operation Temperature
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Operating Frequency
25 = 0-25MHz
40 = 0-40MHz
Feature Set and Flash Memory Size
564RD = C52 feature set + 64(72)* KByte
554RC = C52 feature set + 32(40)* KByte
* = 8K additional flash can be enabled
Voltage Range
E = 4.5-5.5V
V = 2.7-3.6V
Device Family
89 = C51 Core
12.1 Valid Combinations
Valid combinations for SST89E564RD
SST89E564RD-40-C-PI
SST89E564RD-40-I-PI
SST89E564RD-40-C-NJ
SST89E564RD-40-I-NJ
SST89E564RD-40-C-TQJ
SST89E564RD-40-I-TQJ
Valid combinations for SST89V564RD
SST89V564RD-25-C-PI
SST89V564RD-25-I-PI
SST89V564RD-25-C-NJ
SST89V564RD-25-I-NJ
SST89V564RD-25-C-TQJ
SST89V564RD-25-I-TQJ
Valid combinations for SST89E554RC
SST89E554RC-40-C-PI
SST89E554RC-40-I-PI
SST89E554RC-40-C-NJ
SST89E554RC-40-I-NJ
SST89E554RC-40-C-TQJ
SST89E554RC-40-I-TQJ
Valid combinations for SST89V554RC
SST89V554RC-25-C-PI
SST89V554RC-25-I-PI
SST89V554RC-25-C-NJ
SST89V554RC-25-I-NJ
SST89V554RC-25-C-TQJ
SST89V554RC-25-I-TQJ
Note: Valid combinations are those products in mass production or will be in mass production.
Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
60
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
13.0 PACKAGING DIAGRAMS
40
C
L
.600
.625
1
Pin #1 Identifier
.530
.557
2.020
2.070
.065
.075
12˚
4 places
.220 Max.
Base Plane
Seating Plane
.015 Min.
0˚
15˚
.008
.012
.100 †
.200
.063
.090
.045
.055
.015
.022
.100 BSC
.600 BSC
Note:
1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is .115; SST min is less stringent
2. All linear dimensions are in inches (min/max).
40.pdipPI-ILL.7
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
40-PIN PLASTIC DUAL IN-LINE PINS (PDIP)
SST PACKAGE CODE: PI
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.685
.695
Optional
.646 †
.147
.158
Pin #1 Identifier
.020 R.
MAX.
.656
.042
.048
.025
.045
.042
.056
R.
x45˚
1
44
.042
.048
.013
.021
.685
.695
.646 †
.656
.500 .590
REF. .630
.026
.032
.050
BSC.
.020 Min.
.100
.112
.050
BSC.
.026
.032
.165
.180
44.PLCC.NJ-ILL.7
Note:
1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is .650; SST min is less stringent
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
44-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NJ
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
61
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
34
44
Pin #1 Identifier
1
33
.30
.45
10.00
BSC
12.00
.80 BSC
BSC
11
23
.95
1.05
12
.09
.20
22
10.00
BSC
12.00
BSC
0˚- 7˚
.45
.75
.05
.15
1.2
max.
1.00 ref
44.tqfp-TQJ-ILL.6
Note:
1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±0.05) mm.
4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.
44-LEAD THIN QUAD FLAT PACK (TQFP)
SST PACKAGE CODE: TQJ
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01 555
62
相关型号：
SST89E564RD-33-C-NI
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-
SST
SST89E564RD-33-C-NJ
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-
SST
SST89E564RD-33-C-PI
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-
SST
SST89E564RD-33-C-PJ
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-
SST
SST89E564RD-33-C-TQI
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-
SST
SST89E564RD-33-C-TQJ
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-
SST
SST89E564RD-33-I-NI
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-
SST
SST89E564RD-33-I-NJ
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