SSY39L800704IB32_技术文档

2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories

Data Sheet

FEATURES:

•

Organized as 128K x16 / 256K x16 / 512K x16

Single Voltage Read and Write Operations

•

Fast Erase and Word-Program

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time:

– 3.0-3.6V for SST39LF200A/400A/800A

– 2.7-3.6V for SST39VF200A/400A/800A

•

Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

2 seconds (typical) for SST39LF/VF200A

4 seconds (typical) for SST39LF/VF400A

8 seconds (typical) for SST39LF/VF800A

Low Power Consumption

•

Automatic Write Timing

– Internal V_PPGeneration

End-of-Write Detection

– Active Current: 20 mA (typical)

– Standby Current: 3 µA (typical)

•

Sector-Erase Capability

– Uniform 2 KWord sectors

Block-Erase Capability

– Uniform 32 KWord blocks

Fast Read Access Time

– Toggle Bit

– Data# Polling

•

CMOS I/O Compatibility

JEDEC Standard

– Flash EEPROM Pinouts and command sets

Packages Available

– 45 and 55 ns for SST39LF200A/400A

– 55 ns for SST39LF800A

– 70 and 90 ns for SST39VF200A/400A/800A

•

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

•

Latched Address and Data

PRODUCT DESCRIPTION

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A devices are 128K x16 / 256K x16 / 512K x16 CMOS

Multi-Purpose Flash (MPF) manufactured with SST’s pro-

prietary, high performance CMOS SuperFlash technology.

The split-gate cell design and thick oxide tunneling injector

attain better reliability and manufacturability compared with

alternate approaches. The SST39LF200A/400A/800A

write (Program or Erase) with a 3.0-3.6V power supply. The

SST39VF200A/400A/800A write (Program or Erase) with a

2.7-3.6V power supply. These devices conform to JEDEC

standard pinouts for x16 memories.

cantly improve performance and reliability, while lowering

power consumption. They inherently use less energy dur-

ing Erase and Program than alternative flash technologies.

When programming a flash device, the total energy con-

sumed is a function of the applied voltage, current, and

time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and

has a shorter erase time, the total energy consumed during

any Erase or Program operation is less than alternative

flash technologies. These devices also improve flexibility

while lowering the cost for program, data, and configuration

storage applications.

Featuring high performance Word-Program, the

SST39LF200A/400A/800A and SST39VF200A/400A/

800A devices provide a typical Word-Program time of 14

µsec. The devices use Toggle Bit or Data# Polling to detect

the completion of the Program or Erase operation. To pro-

tect against inadvertent write, they have on-chip hardware

and software data protection schemes. Designed, manu-

factured, and tested for a wide spectrum of applications,

these devices are offered with a guaranteed endurance of

10,000 cycles. Data retention is rated at greater than 100

years.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet surface mount requirements, the SST39LF200A/

400A/800A and SST39VF200A/400A/800A are offered in

both 48-lead TSOP packages and 48-ball TFBGA pack-

ages. See Figures 1 and 2 for pinouts.

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A devices are suited for applications that require conve-

nient and economical updating of program, configuration,

or data memory. For all system applications, they signifi-

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

S71117-04-000 6/01

1

360

These specifications are subject to change without notice.

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (50H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (30H or 50H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figures 9 and 10 for tim-

ing waveforms. Any commands issued during the Sector-

or Block-Erase operation are ignored.

Read

The Read operation of the SST39LF200A/400A/800A and

SST39VF200A/400A/800A is controlled by CE# and OE#,

both have to be low for the system to obtain data from the

outputs. CE# is used for device selection. When CE# is

high, the chip is deselected and only standby power is con-

sumed. OE# is the output control and is used to gate data

from the output pins. The data bus is in high impedance

state when either CE# or OE# is high. Refer to the Read

cycle timing diagram for further details (Figure 3).

Chip-Erase Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide a Chip-Erase operation, which allows the

user to erase the entire memory array to the “1” state. This

is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 8 for timing diagram,

and Figure 19 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Word-Program Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A are programmed on a word-by-word basis. Before

programming, one must ensure that the sector, in which

the word which is being programmed exists, is fully erased.

The Program operation consists of three steps. The first

step is the three-byte load sequence for Software Data Pro-

tection. The second step is to load word address and word

data. During the Word-Program operation, the addresses

are latched on the falling edge of either CE# or WE#,

whichever occurs last. The data is latched on the rising

edge of either CE# or WE#, whichever occurs first. The

third step is the internal Program operation which is initi-

ated after the rising edge of the fourth WE# or CE#, which-

ever occurs first. The Program operation, once initiated, will

be completed within 20 µs. See Figures 4 and 5 for WE#

and CE# controlled Program operation timing diagrams

and Figure 16 for flowcharts. During the Program opera-

tion, the only valid reads are Data# Polling and Toggle Bit.

During the internal Program operation, the host is free to

perform additional tasks. Any commands issued during the

internal Program operation are ignored.

Write Operation Status Detection

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide two software means to detect the completion

of a write (Program or Erase) cycle, in order to optimize the

system write cycle time. The software detection includes

two status bits: Data# Polling (DQ₇) and Toggle Bit (DQ₆).

The End-of-Write detection mode is enabled after the rising

edge of WE#, which initiates the internal Program or Erase

operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ₇or DQ₆. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the write cycle, otherwise the rejec-

tion is valid.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39LF200A/400A/800A and

SST39VF200A/400A/800A offers both Sector-Erase and

Block-Erase mode. The sector architecture is based on

uniform sector size of 2 KWord. The Block-Erase mode is

based on uniform block size of 32 KWord. The Sector-

S71117-04-000 6/01 360

2

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Data# Polling (DQ₇)

Software Data Protection (SDP)

When the SST39LF200A/400A/800A and SST39VF200A/

400A/800A are in the internal Program operation, any

attempt to read DQ₇will produce the complement of the

true data. Once the Program operation is completed, DQ₇

will produce true data. The device is then ready for the next

operation. During internal Erase operation, any attempt to

read DQ₇will produce a ‘0’. Once the internal Erase opera-

tion is completed, DQ₇will produce a ‘1’. The Data# Polling

is valid after the rising edge of fourth WE# (or CE#) pulse

for Program operation. For Sector-, Block- or Chip-Erase,

the Data# Polling is valid after the rising edge of sixth WE#

(or CE#) pulse. See Figure 6 for Data# Polling timing dia-

gram and Figure 17 for a flowchart.

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide the JEDEC approved Software Data Protec-

tion scheme for all data alteration operations, i.e., Program

and Erase. Any Program operation requires the inclusion of

the three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte sequence. This group of

devices are shipped with the Software Data Protection per-

manently enabled. See Table 4 for the specific software

command codes. During SDP command sequence, invalid

commands will abort the device to Read mode within TRC.

The contents of DQ₁₅-DQ₈can be V_ILor V_IH, but no other

value, during any SDP command sequence.

Toggle Bit (DQ₆)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ₆will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ₆bit will

stop toggling. The device is then ready for the next opera-

tion. The Toggle Bit is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Toggle Bit is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle

Bit timing diagram and Figure 17 for a flowchart.

Common Flash Memory Interface (CFI)

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A also contain the CFI information to describe the char-

acteristics of the device. In order to enter the CFI Query

mode, the system must write three-byte sequence, same

as Software ID Entry command with 98H (CFI Query com-

mand) to address 5555H in the last byte sequence. Once

the device enters the CFI Query mode, the system can

read CFI data at the addresses given in Tables 5 through 9.

The system must write the CFI Exit command to return to

Read mode from the CFI Query mode.

Data Protection

The SST39LF200A/400A/800A and SST39VF200A/400A/

800A provide both hardware and software features to pro-

tect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a write cycle.

V_DDPower Up/Down Detection: The Write operation is

inhibited when V_DDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

S71117-04-000 6/01 360

3

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Product Identification

Product Identification Mode Exit/

CFI Mode Exit

The Product Identification mode identifies the devices as

the SST39LF/VF200A, SST39LF/VF400A and SST39LF/

VF800A and manufacturer as SST. This mode may be

accessed by software operations. Users may use the

Software Product Identification operation to identify the part

(i.e., using the device ID) when using multiple

manufacturers in the same socket. For details, see Table 4

for software operation, Figure 11 for the Software ID Entry

and Read timing diagram, and Figure 18 for the Software

ID Entry command sequence flowchart.

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figure 13 for timing waveform and Figure 18 for a

flowchart.

TABLE 1: PRODUCT IDENTIFICATION TABLE

Address

Data

Manufacturer’s ID

Device ID

0000H

00BFH

SST39LF/VF200A

SST39LF/VF400A

SST39LF/VF800A

0001H

2789H

2780H

2781H

T1.3 360

S71117-04-000 6/01 360

4

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

SuperFlash

Memory

X-Decoder

Memory Address

Address Buffer & Latches

Y-Decoder

CE#

I/O Buffers and Data Latches

Control Logic

OE#

WE#

DQ - DQ

15

0

360 ILL B1.2

SST39LF/VF800A SST39LF/VF400A SST39LF/VF200A

SST39LF/VF200A SST39LF/VF400A SST39LF/VF800A

A15

A14

A13

A12

A11

A10

A9

A15

A14

A13

A12

A11

A10

A9

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

NC

A16

NC

A16

NC

2

3

V

SS

4

DQ15

DQ7

DQ15

DQ7

DQ15

DQ7

5

6

DQ14

DQ6

DQ14

DQ6

DQ14

DQ6

7

A8

8

DQ13

DQ5

DQ13

DQ5

DQ13

DQ5

Standard Pinout

NC

WE#

NC

A18

A17

A7

NC

WE#

NC

A17

A7

NC

WE#

NC

A7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

DQ12

DQ4

DQ12

DQ4

Top View

Die Up

V

DD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

A6

A5

A4

A3

V

SS

A2

CE#

A0

CE#

A1

A0

SST39LF200A/400A/800A

SST39VF200A/400A/800A

360 ILL F01.2

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

S71117-04-000 6/01 360

5

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TOP VIEW (balls facing down)

SST39LF/VF200A

6

5

4

3

2

1

A13 A12 A14 A15 A16 NC DQ15 V

SS

A9

A8 A10 A11 DQ7 DQ14 DQ13 DQ6

WE# NC

NC NC

A7 NC

NC

A6

A2

NC DQ5 DQ12

V

DQ4

DD

NC DQ2 DQ10 DQ11 DQ3

A5 DQ0 DQ8 DQ9 DQ1

A3

A4

A1

A0 CE# OE# V

SS

A

B

C

D

E F G H

TOP VIEW (balls facing down)

SST39LF/VF400A

TOP VIEW (balls facing down)

SST39LF/VF800A

6

5

4

3

2

1

6

A13 A12 A14 A15 A16 NC DQ15 V

SS

5

4

3

2

1

A9

A8 A10 A11 DQ7 DQ14 DQ13 DQ6

A9

WE# NC

NC NC A18 NC DQ2 DQ10 DQ11 DQ3

A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

A8 A10 A11 DQ7 DQ14 DQ13 DQ6

WE# NC

NC NC

NC

NC DQ5 DQ12

V

DQ4

NC NC DQ5 DQ12 DQ4

V

DD

NC DQ2 DQ10 DQ11 DQ3

A5 DQ0 DQ8 DQ9 DQ1

A7 A17 A6

A3

A4

A2

A1

A0 CE# OE#

V

A3

A4

A2

A1

A0 CE# OE# V

SS

A

B

C

D

E

F

G

H

A

B

C

D

E F G H

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

S71117-04-000 6/01 360

6

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol

Pin Name

Functions

A_MS¹-A₀

Address Inputs

To provide memory addresses. During Sector-Erase A_MS-A₁₁address lines will select the

sector. During Block-Erase A_MS-A₁₅address lines will select the block.

DQ₁₅-DQ₀

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE#

OE#

WE#

V_DD

Chip Enable

Output Enable

Write Enable

Power Supply

To activate the device when CE# is low.

To gate the data output buffers.

To control the Write operations.

To provide power supply voltage:

3.0-3.6V for SST39LF200A/400A/800A

2.7-3.6V for SST39VF200A/400A/800A

V_SS

NC

Ground

No Connection

Unconnected pins.

T2.2 360

1. A_MS= Most significant address

_MS= A₁₆for SST39LF/VF200A, A₁₇for SST39LF/VF400A, and A₁₈for SST39LF/VF800A

A

TABLE 3: OPERATION MODES SELECTION

Mode

Read

CE#

V_IL

OE#

V_IL

WE#

V_IH

V_IL

DQ

D_OUT

D_IN

X¹

Address

A_IN

Program

Erase

V_IL

V_IH

A_IN

V_IL

Sector or Block address,

XXH for Chip-Erase

Standby

V_IH

X

V_IL

X

High Z

X

Write Inhibit

High Z/ D_OUT

X

V_IH

Product Identification

Software Mode

V_IL

V_IH

See Table 4

T3.4 360

1. X can be V_ILor V_IH, but no other value.

S71117-04-000 6/01 360

7

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²

5555H AAH 2AAAH 55H 5555H A0H Data

WA³

Word-Program

Sector-Erase

Block-Erase

Chip-Erase

4

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H

SA_X

BA_X

30H

50H

4

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry^5,65555H AAH 2AAAH 55H 5555H 90H

CFI Query Entry⁵

Software ID Exit⁷/

CFI Exit

5555H AAH 2AAAH 55H 5555H 98H

XXH F0H

Software ID Exit⁷/

CFI Exit

5555H AAH 2AAAH 55H 5555H F0H

T4.2 360

1. Address format A₁₄-A₀(Hex),

Addresses A₁₅and A₁₆can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF200A.

Addresses A₁₅, A₁₆, and A₁₇can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF400A.

Addresses A₁₅, A₁₆, A₁₇, and A₁₈can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF800A.

2. DQ₁₅- DQ₈can be V_ILor V_IH, but no other value, for the Command sequence

3. WA = Program word address

4. SA_Xfor Sector-Erase; uses A_MS-A₁₁address lines

BA_X, for Block-Erase; uses A_MS-A₁₅address lines

A_MS= Most significant address

A_MS= A₁₆for SST39LF/VF200A, A₁₇for SST39LF/VF400A and A₁₈for SST39LF/VF800A

5. The device does not remain in Software Product ID Mode if powered down.

6. With A_MS-A₁=0; SST Manufacturer’s ID= 00BFH, is read with A₀= 0,

SST39LF/VF200A Device ID = 2789H, is read with A₀= 1.

SST39LF/VF400A Device ID = 2780H, is read with A₀= 1.

SST39LF/VF800A Device ID = 2781H, is read with A₀= 1.

7. Both Software ID Exit operations are equivalent

1

TABLE 5: CFI QUERY IDENTIFICATION STRING FOR SST39LF200A/400A/800A AND SST39VF200A/400A/800A

Address

10H

11H

12H

13H

14H

15H

16H

17H

Data

0051H

0052H

0059H

0001H

0007H

0000H

Query Unique ASCII string “QRY”

Primary OEM command set

Address for Primary Extended Table

Alternate OEM command set (00H = none exists)

Address for Alternate OEM extended Table (00H = none exits)

18H

19H

1AH

T5.0 360

1. Refer to CFI publication 100 for more details.

S71117-04-000 6/01 360

8

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF200A/400A/800A AND SST39VF200A/400A/800A

Address

Data

1BH

0027H¹

0030H¹

0036H

V_DDMin. (Program/Erase)

DQ₇-DQ₄: Volts, DQ₃-DQ₀: 100 millivolts

1CH

V_DDMax. (Program/Erase)

DQ₇-DQ₄: Volts, DQ₃-DQ₀: 100 millivolts

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

0000H

0004H

0000H

0004H

0006H

0001H

0000H

0001H

V_PPmin. (00H = no V_PPpin)

V_PPmax. (00H = no V_PPpin)

Typical time out for Word-Program 2^Nµs (2⁴= 16 µs)

Typical time out for min. size buffer program 2^Nµs (00H = not supported)

Typical time out for individual Sector/Block-Erase 2^Nms (2⁴= 16 ms)

Typical time out for Chip-Erase 2^Nms (2⁶= 64 ms)

Maximum time out for Word-Program 2^Ntimes typical (2¹x 2⁴= 32 µs)

Maximum time out for buffer program 2^Ntimes typical

Maximum time out for individual Sector/Block-Erase 2^Ntimes typical (2¹x 2⁴= 32 ms)

Maximum time out for Chip-Erase 2^Ntimes typical (2¹x 2⁶= 128 ms)

T6.2 360

1. 0030H for SST39LF200A/400A/800A and 0027H for SST39VF200A/400A/800A

TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF200A

Address

27H

28H

Data

0012H

0001H

0000H

Device size = 2^NByte (12H = 18; 2¹⁸= 256 KBytes)

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

Maximum number of byte in multi-byte write = 2^N(00H = not supported)

0002H

003FH

0000H

0010H

0000H

0003H

0000H

0001H

Number of Erase Sector/Block sizes supported by device

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

y = 63 + 1 = 64 sectors (003FH = 63)

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

Block Information (y + 1 = Number of blocks; z x 256B = block size)

y = 3 + 1 = 4 blocks (0003H = 3)

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

T7.2 360

S71117-04-000 6/01 360

9

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 8: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF400A

Address

27H

28H

Data

0013H

0001H

0000H

0002H

007FH

0000H

0010H

0000H

0007H

0000H

0001H

Device size = 2^NByte (13H = 19; 2¹⁹= 512 KBytes)

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

Maximum number of byte in multi-byte write = 2^N(00H = not supported)

Number of Erase Sector/Block sizes supported by device

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

y = 127 + 1 = 128 sectors (007FH = 127)

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

Block Information (y + 1 = Number of blocks; z x 256B = block size)

y = 7 + 1 = 8 blocks (0007H = 7)

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

T8.1 360

TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF800A

Address

27H

28H

Data

0014H

0001H

0000H

0002H

00FFH

0000H

0010H

0000H

000FH

0000H

0001H

Device size = 2^NByte (14H = 20; 2²⁰= 1 MByte)

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

Maximum number of byte in multi-byte write = 2^N(00H = not supported)

Number of Erase Sector/Block sizes supported by device

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

y = 255 + 1 = 256 sectors (00FFH = 255)

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

Block Information (y + 1 = Number of blocks; z x 256B = block size)

y = 15 + 1 = 16 blocks (000FH = 15)

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

T9.0 360

S71117-04-000 6/01 360

10

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V_DD+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V_DD+ 1.0V

Voltage on A₉Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current¹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE: SST39LF200A/400A/800A

Range

Ambient Temp

V_DD

Commercial

0°C to +70°C

3.0-3.6V

OPERATING RANGE: SST39VF200A/400A/800A

Range

Ambient Temp

0°C to +70°C

V_DD

Commercial

Extended

Industrial

2.7-3.6V

-20°C to +85°C

-40°C to +85°C

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C_L= 30 pF for SST39LF200A/400A/800A

Output Load . . . . . . . . . . . . . . . . . . . . C_L= 100 pF for SST39VF200A/400A/800A

See Figures 14 and 15

S71117-04-000 6/01 360

11

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 10: DC OPERATING CHARACTERISTICS

V_DD= 3.0-3.6V FOR SST39LF200A/400A/800A AND 2.7-3.6V FOR SST39VF200A/400A/800A

Limits

Symbol Parameter

Min

Max Units Test Conditions

Address input = V_IL/V_IH, at f=1/T_RCMin.,

I_DD

Power Supply Current

V_DD=V_DDMax.

Read

30

20

1

mA

µA

CE#=OE#=V_IL,WE#=V_IH, all I/Os open

CE#=WE#=V_IL, OE#=V_IH

CE#=V_IHC, V_DD= V_DDMax.

V_IN=GND to V_DD, V_DD= V_DDMax.

V_OUT=GND to V_DD, V_DD= V_DDMax.

V_DD= V_DDMin.

Program and Erase

Standby V_DDCurrent

Input Leakage Current

Output Leakage Current

Input Low Voltage

Input High Voltage

Input High Voltage (CMOS)

Output Low Voltage

Output High Voltage

I_SB

I_LI

I_LO

10

0.8

V_IL

V_IH

V_IHC

V_OL

V_OH

0.7V_DD

V

V_DD= V_DDMax.

V_DD-0.3

V_DD= V_DDMax.

0.2

I_OL= 100 µA, V_DD= V_DDMin.

I_OH= -100 µA, V_DD= V_DDMin.

V_DD-0.2

T10.5 360

TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Minimum

100

Units

1

T_PU-READ

Power-up to Read Operation

Power-up to Program/Erase Operation

µs

1

T_PU-WRITE

100

T11.0 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 12: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

V_I/O= 0V

Maximum

1

C_I/O

I/O Pin Capacitance

Input Capacitance

12 pF

6 pF

1

C_IN

V_IN= 0V

T12.0 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 13: RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Data Retention

Latch Up

Minimum Specification

Units

Test Method

1

N_END

10,000

100

Cycles JEDEC Standard A117

1

T_DR

Years

mA

JEDEC Standard A103

JEDEC Standard 78

1

I_LTH

100 + I_DD

T13.1 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71117-04-000 6/01 360

12

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

AC CHARACTERISTICS

TABLE 14: READ CYCLE TIMING PARAMETERS V_DD= 3.0-3.6V

SST39LF200A/400A-45

SST39LF200A/400A/800A-55

Symbol Parameter

Min

Max

Min

Max

Units

ns

T_RC

T_CE

T_AA

Read Cycle Time

45

55

Chip Enable Access Time

Address Access Time

45

30

55

30

ns

T_OE

T_CLZ

T_OLZ

Output Enable Access Time

CE# Low to Active Output

OE# Low to Active Output

CE# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

ns

1

0

ns

1

T_CHZ

T_OHZ

15

ns

1

ns

1

T_OH

0

ns

T14.7 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 15: READ CYCLE TIMING PARAMETERS V_DD= 2.7-3.6V

SST39VF200A/400A/800A-70

SST39VF200A/400A/800A-90

Symbol Parameter

Min

Max

Min

Max

Units

ns

T_RC

T_CE

T_AA

Read Cycle Time

70

90

Chip Enable Access Time

Address Access Time

70

35

90

45

ns

T_OE

T_CLZ

T_OLZ

Output Enable Access Time

CE# Low to Active Output

OE# Low to Active Output

CE# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

ns

1

0

ns

1

T_CHZ

20

30

ns

T_OHZ

ns

1

T_OH

0

ns

T15.6 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71117-04-000 6/01 360

13

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter

Min

Max

Units

µs

T_BP

Word-Program Time

20

T_AS

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OE# High Setup Time

OE# High Hold Time

CE# Pulse Width

0

30

0

ns

T_AH

ns

T_CS

ns

T_CH

T_OES

T_OEH

T_CP

0

ns

0

ns

10

40

30

0

ns

T_WP

T_WPH

WE# Pulse Width

ns

1

WE# Pulse Width High

CE# Pulse Width High

Data Setup Time

ns

1

T_CPH

T_DS

ns

1

T_DH

Data Hold Time

ns

1

T_IDA

Software ID Access and Exit Time

Sector-Erase

150

25

ns

T_SE

ms

T_BE

Block-Erase

25

T_SCE

Chip-Erase

100

T16.0 360

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71117-04-000 6/01 360

14

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

T

AA

RC

ADDRESS A

MS-0

CE#

OE#

WE#

T

CE

T

OE

T

OHZ

V

OLZ

IH

T

CHZ

T

OH

T

HIGH-Z

CLZ

HIGH-Z

DQ

15-0

DATA VALID

Note:

A

= Most significant address

360 ILL F03.2

MS

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16

17

18

FIGURE 3: READ CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

MS-0

T

AH

T

DH

T

WP

WE#

T

AS

DS

T

WPH

OE#

CE#

T

CH

T

CS

DQ

15-0

XXAA

SW0

XX55

SW1

XXA0

SW2

DATA

WORD

360 ILL F04.4

(ADDR/DATA)

Note:

A

= Most significant address

MS

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16 17 18

X can be V or V , but no other value.

IL IH

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

S71117-04-000 6/01 360

15

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

MS-0

T

AH

T

DH

T

CP

CE#

T

AS

DS

T

CPH

OE#

WE#

T

CH

T

CS

DQ

15-0

XXAA

SW0

XX55

SW1

XXA0

SW2

DATA

WORD

(ADDR/DATA)

360 ILL F05.4

Note:

A

= Most significant address

MS

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16 17 18

X can be V or V , but no other value.

IL IH

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

T

CE

CE#

OE#

WE#

T

OES

T

OEH

T

OE

DQ

7

DATA

DATA#

DATA

360 ILL F06.3

Note:

A

= Most significant address

MS

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16 17 18

FIGURE 6: DATA# POLLING TIMING DIAGRAM

S71117-04-000 6/01 360

16

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

ADDRESS A

MS-0

T

CE

CE#

OE#

WE#

T

OES

T

OE

OEH

DQ

6

TWO READ CYCLES

WITH SAME OUTPUTS

360 ILL F07.3

Note:

A

= Most significant address

MS

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16 17 18

FIGURE 7: TOGGLE BIT TIMING DIAGRAM

T

SCE

SIX-BYTE CODE FOR CHIP-ERASE

5555 5555 2AAA

5555

2AAA

5555

ADDRESS A

MS-0

CE#

OE#

WE#

T

WP

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX10

SW5

360 ILL F08.7

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

A

= Most significant address

MS

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16

17

18

X can be V or V , but no other value.

IL IH

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

S71117-04-000 6/01 360

17

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

T

BE

SIX-BYTE CODE FOR BLOCK-ERASE

5555 5555 2AAA

5555

2AAA

BA

X

ADDRESS A

MS-0

CE#

OE#

WE#

T

WP

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX50

SW5

360 ILL F17.9

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

BA = Block Address

X

MS

A

= Most significant address

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16

17

18

X can be V or V , but no other value.

IL IH

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

T

SE

SIX-BYTE CODE FOR SECTOR-ERASE

5555

2AAA

5555

2AAA

SA

X

ADDRESS A

MS-0

CE#

OE#

WE#

T

WP

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX30

SW5

360 ILL F18.8

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 16)

SA = Sector Address

X

MS

A

= Most significant address

= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A

16

17

18

X can be V or V , but no other value.

IL IH

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

S71117-04-000 6/01 360

18

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

ADDRESS A

5555

2AAA

5555

0000

0001

14-0

CE#

OE#

WE#

T

IDA

T

WP

T

WPH

XX55

SW1

T

AA

DQ

15-0

XXAA

SW0

XX90

SW2

00BF

Device ID

360 ILL F09.4

Device ID = 2789H for SST39LF/VF200A, 2780H for SST39LF/VF400A and 2781H for SST39LF/VF800A

Note: X can be V or V , but no other value.

IL

IH

FIGURE 11: SOFTWARE ID ENTRY AND READ

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS A

5555

2AAA

5555

14-0

CE#

OE#

WE#

T

IDA

T

WP

T

WPH

XX55

SW1

T

AA

DQ

15-0

XXAA

SW0

XX98

SW2

360 ILL F20.1

Note: X can be V or V , but no other value.

IL IH

FIGURE 12: CFI QUERY ENTRY AND READ

S71117-04-000 6/01 360

19

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

5555

2AAA

5555

ADDRESS A

DQ

14-0

XXAA

XX55

XXF0

15-0

T

IDA

CE#

OE#

T

WP

WE#

T

WHP

SW0

SW1

SW2

360 ILL F10.1

Note: X can be V or V , but no other value.

IL IH

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

S71117-04-000 6/01 360

20

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

V

IHT

V

INPUT

REFERENCE POINTS

OUTPUT

OT

IT

V

ILT

360 ILL F11.1

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic “1” and V_ILT(0.1 V_DD) for a logic “0”. Measurement reference points

for inputs and outputs are V_IT(0.5 V_DD) and V_OT(0.5 V_DD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: V_IT- V_INPUTTest

V_OT- V_OUTPUTTest

V_IHT- V_INPUTHIGH Test

V

_ILT- V_INPUTLOW Test

FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

C

L

360 ILL F12.1

FIGURE 15: A TEST LOAD EXAMPLE

S71117-04-000 6/01 360

21

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load Word

Address/Word

Data

Wait for end of

Program (T

Data# Polling

,

BP

bit, or Toggle bit

operation)

Program

Completed

Note: X can be V or V , but no other value.

IL

IH

360 ILL F13.4

FIGURE 16: WORD-PROGRAM ALGORITHM

S71117-04-000 6/01 360

22

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Toggle Bit

Data# Polling

Internal Timer

Program/Erase

Initiated

Program/Erase

Initiated

Program/Erase

Initiated

Read DQ

7

Read word

Wait T

BP

,

T

SCE, SE

or T

BE

Read same

word

Is DQ =

7

No

true data?

Program/Erase

Completed

Yes

No

Does DQ

match?

Program/Erase

Completed

6

Yes

Program/Erase

Completed

360 ILL F14.0

FIGURE 17: WAIT OPTIONS

S71117-04-000 6/01 360

23

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

CFI Query Entry

Command Sequence

Software ID Entry

Command Sequence

Software ID Exit/CFI Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXF0H

Address: XXH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Wait T

IDA

Load data: XX98H

Address: 5555H

Load data: XX90H

Address: 5555H

Load data: XXF0H

Address: 5555H

Return to normal

operation

Wait T

IDA

Wait T

IDA

Wait T

IDA

Return to normal

operation

Read CFI data

Read Software ID

360 ILL F15.4

Note: X can be V or V , but no other value.

IL IH

FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS

S71117-04-000 6/01 360

24

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Chip-Erase

Sector-Erase

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX80H

Address: 5555H

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XX30H

Load data: XX50H

Address: SA

Address: BA

X

Wait T

SCE

Wait T

SE

Wait T

BE

Chip erased

to FFFFH

Sector erased

to FFFFH

Block erased

to FFFFH

360 ILL F16.5

Note: X can be V or V , but no other value.

IL

IH

FIGURE 19: ERASE COMMAND SEQUENCE

S71117-04-000 6/01 360

25

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

PRODUCT ORDERING INFORMATION

Device

Speed

Suffix1

Suffix2

XX

SST39xFxxxA

-

XX

-

XX

-

Package Modifier

K = 48 leads or balls

Numeric = Die modifier

Package Type

E = TSOP (12mm x 20mm)

B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

U = Unencapsulated die

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

Device Density

200 = 2 Megabit

400 = 4 Megabit

800 = 8 Megabit

Voltage

L = 3.0-3.6V

V = 2.7-3.6V

S71117-04-000 6/01 360

26

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Valid combinations for SST39LF200A

SST39LF200A-45-4C-EK SST39LF200A-45-4C-B3K

SST39LF200A-55-4C-EK SST39LF200A-55-4C-B3K

Valid combinations for SST39VF200A

SST39VF200A-70-4C-EK SST39VF200A-70-4C-B3K

SST39VF200A-90-4C-EK SST39VF200A-90-4C-B3K

SST39VF200A-90-4C-U1

SST39VF200A-70-4I-EK

SST39VF200A-90-4I-EK

SST39VF200A-70-4I-B3K

SST39VF200A-90-4I-B3K

Valid combinations for SST39LF400A

SST39LF400A-45-4C-EK SST39LF400A-45-4C-B3K

SST39LF400A-55-4C-EK SST39LF400A-55-4C-B3K

Valid combinations for SST39VF400A

SST39VF400A-70-4C-EK SST39VF400A-70-4C-B3K

SST39VF400A-90-4C-EK SST39VF400A-90-4C-B3K

SST39VF400A-90-4C-U1

SST39VF400A-70-4I-EK

SST39VF400A-90-4I-EK

SST39VF400A-70-4I-B3K

SST39VF400A-90-4I-B3K

Valid combinations for SST39LF800A

SST39LF800A-55-4C-EK SST39LF800A-55-4C-B3K

Valid combinations for SST39VF800A

SST39VF800A-70-4C-EK SST39VF800A-70-4C-B3K

SST39VF800A-90-4C-EK SST39VF800A-90-4C-B3K

SST39VF800A-90-4C-U1

SST39VF800A-70-4I-EK

SST39VF800A-90-4I-EK

SST39VF800A-70-4I-B3K

SST39VF800A-90-4I-B3K

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

S71117-04-000 6/01 360

27

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

PACKAGING DIAGRAMS

1.05

0.95

Pin # 1 Identifier

.50

BSC

.270

.170

12.20

11.80

0.15

0.05

18.50

18.30

0.70

0.50

48-TSOP-EK-ILL.6

20.20

19.80

Note:

1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max). Scale is 1:5 mm.

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM

SST PACKAGE CODE: EK

S71117-04-000 6/01 360

28

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

BOTTOM VIEW

8.00 ± 0.20

5.60

0.80

TOP VIEW

6

5

4

3

2

1

6

5

4.00

6.00 ± 0.20

4

3

2

1

0.80

0.45 ± 0.05

(48X)

H

G F E D C B A

A

B C D E F G H

A1 CORNER

1.10 ± 0.10

SIDE VIEW

0.15

48ba-TFBGA-B3K-6x8-450mic-ILL.0

1mm

SEATING PLANE

0.35 ± 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM

SST PACKAGE CODE: B3K

S71117-04-000 6/01 360

29

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com

S71117-04-000 6/01 360

30


型号：	SSY39L800704IB32
厂家：	SILICON STORAGE TECHNOLOGY, INC
描述：	2 MBIT / 4 MBIT / 8 MBIT ( X 16 ) MULTI - PURPOSE FLASH 2兆位/ 4兆位/ 8兆比特（X 16 ） - 多目的FLASH
文件：	总30页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SSY39L800704IB32 [SST]

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