74AC163 [STMICROELECTRONICS]
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER; 同步可预置4位计数器
| 型号： | 74AC163 |
| 厂家： | 
ST |
| 描述： | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
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HIGH SPEED:
MAX =200MHz (TYP.)atVCC =5V
LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25 oC
HIGH NOISEIMMUNITY:
f
VNIH = VNIL =28% VCC (MIN.)
B
M
50Ω TRANSMISSIONLINEDRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
OPERATING VOLTAGERANGE:
(Plastic Package)
(Micro Package)
ORDER CODES :
74AC163B
74AC163M
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine
the mode of operation as shown in the Truth
Table. A LOW signal on CLEAR overrides
counting and parallel loading and allows all
output to go LOW on the next rising edge of
CLOCK. A LOW signal on LOAD overrides
counting and allows information on Parallel Data
Qn inputs to be loaded into the flip-flops on the
next rising edge of CLOCK. With LOAD and
CLEAR, PE and TE permit counting when both
are HIGH. Conversely, a LOW signal on either
PE and TE inhibits counting.
VCC (OPR)= 2V to 6V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES163
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC163
is
a
high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTERS
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL. It is a 4 bit binary counter with
SynchronousClear.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
The circuits have four fundamental modes of
operation, in order of preference: synchronous
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/12
December 1998
74AC163
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
2
CLEAR
CLOCK
Master Reset
Clock Input (LOW-to-HIGH,
Edge- Triggered)
3, 4, 5, 6
A, B, C, D Data Inputs
7
10
9
ENABLE P Count Enable Input
ENABLE T Count Enable Carry Input
LOAD
Parallel Enable Input
14, 13, 12,
11
QA to QD Flip-Flop Outpus
10
8
ENABLE T Count Enable Carry Input
GND
VCC
Ground (0V)
16
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
L
LD
X
PE
X
TE
X
CK
QA
L
QB
L
QC
QD
L
L
RESET TO ”0”
PRESET DATA
NO COUNT
NO COUNT
COUNT
H
L
X
X
A
B
C
D
H
H
X
L
NO CHANGE
NO CHANGE
COUNT UP
H
H
L
X
H
H
H
X
H
X
X
X
NO CHANGE
NO COUNT
NOTE:
X:Don’t Care
A,B, C,D: Logic level ofdata input
CARRY=TE• QA• QB• QC• QD
LOGIC DIAGRAMS
2/12
74AC163
TIMING CHART
3/12
74AC163
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC OutputVoltage
DC Input Diode Current
DC OutputDiode Current
DC OutputCurrent
V
IIK
mA
mA
mA
mA
oC
IOK
± 20
IO
50
±
ICC or IGND DC VCC or Ground Current
300
±
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
oC
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 6
Unit
V
Supply Voltage
Input Voltage
0 to VCC
0 to VCC
-40 to +85
8
V
VO
Output Voltage
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V(note 1)
ns/V
1)VIN from30% to70%of VCC
4/12
74AC163
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
High LevelInput Voltage
Low Level Input Voltage
High LevelOutputVoltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
5.5
VO = 0.1V or
VCC - 0.1 V
2.1
1.5
2.25
2.75
1.5
2.1
V
V
3.15
3.85
3.15
3.85
VIL
VO = 0.1V or
VCC - 0.1 V
0.9
0.9
2.25 1.35
2.75 1.65
2.99
1.35
1.65
VOH
IO=-50 µA
2.9
4.4
5.4
2.9
4.4
VI(*)
VIH or
VIL
=
IO=-50 µA
IO=-50 µA
4.49
5.49
5.4
V
IO=-12 mA 2.56
IO=-24 mA 3.86
IO=-24 mA 4.86
IO=50 µA
2.46
3.76
4.76
VOL
Low Level Output Voltage
0.002 0.1
0.001 0.1
0.001 0.1
0.36
0.1
0.1
0.1
0.44
0.44
0.44
±1
VI(*)
=
IO=50 µA
I =50
A
VIH or
VIL
µ
V
O
IO=12 mA
IO=24 mA
IO=24 mA
0.36
0.36
II
Input Leakage Current
VI = VCC or GND
VI = VCC or GND
VOLD = 1.65 V max
VOHD = 3.85 V min
±0.1
µA
ICC
Quiescent Supply Current
4
40
A
µ
IOLD
IOHD
Dynamic Output Current
(note 1, 2)
75
mA
mA
-75
1) Maximum test duration 2ms, one output loaded attime
2)Incident wave switchingis guaranteed ontransmission lines withimpedances aslowas50 Ω.
(*) All outputs loaded.
5/12
74AC163
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, RL = 500 Ω, Input tr = t =3 ns)
f
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
tPLH
tPHL
Propagation Delay Time
CKto Q
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
7.0
5.0
8.0
6.0
5.5
4.0
2.0
2.0
2.0
2.0
2.0
1.5
-1.5
-1.0
1.0
1.0
-0.5
-0.3
3.0
2.5
-2.5
-1.5
3.0
2.0
-2.0
-1.5
200
200
12.0
9.0
14.0
10.5
9.5
6.5
4.5
4.0
3.0
2.5
4.0
3.0
-0.5
0.5
3.0
3.5
0.5
0.5
5.0
6.0
-1.0
0
13.0
9.5
15.0
11.5
11.0
7.5
7.5
4.5
3.5
3.0
5.0
4.0
0
ns
ns
tPLH
tPHL
Propagation Delay Time
CKto CARRY OUT
tPLH
tPHL
Propagation Delay Time
TE to CARRY OUT
ns
tw
tw
ts
CKpulse Width, (Count)
HIGH or LOW
ns
CKpulse Width (Load)
HIGH or LOW
ns
Setup Time HIGH or LOW
(INPUT to CLOCK)
ns
th
Hold TimeHIGH or LOW
(INPUT to CK)
ns
1.0
4.0
4.5
1.0
1.0
8.0
7.0
-0.5
0.5
7.0
5.0
0
ts
Setup Time HIGH or LOW
(CLEAR to CK)
ns
th
Hold TimeHIGH or LOW
(CLEAR to CK)
ns
ts
Setup Time HIGH or LOW
(LOAD to CK)
ns
th
Hold TimeHIGH or LOW
(LOAD to CK)
ns
ts
Setup Time HIGH or LOW
(PE or TE to CK)
6.0
4.0
-0.5
0
ns
th
Hold TimeHIGH or LOW
(PE or TE to CK)
ns
0.5
fMAX
Maximum Clock Frequency
70
60
95
MHz
110
(*) Voltagerangeis3.3V ± 0.3V
(**) Voltagerange is 5V± 0.5V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
5.0
5.0
4.5
35
pF
pF
CPD
Power Dissipation
fIN = 10 MHz
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/n(per circuit)
6/12
74AC163
TEST CIRCUIT
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL =R1 =500Ω orequivalent
RT = ZOUT ofpulse generator (typically50Ω)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
7/12
74AC163
WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE
(f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle)
8/12
74AC163
WAVEFORM 4: PROPAGATION DELAYS COUNTEABLE MODE
(f=1MHz; 50% duty cycle)
WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle)
9/12
74AC163
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
0.77
TYP.
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
0.335
0.100
0.700
2.54
17.78
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
10/12
74AC163
SO-16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8 (max.)
P013H
11/12
74AC163
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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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12/12
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