74AC573 [STMICROELECTRONICS]
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING; 八D型具有三态输出的非反相锁存
| 型号： | 74AC573 |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 文件： | 总10页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
■
■
HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
HIGH NOISE IMMUNITY:
■
■
■
■
■
■
■
VNIH = VNIL = 28% VCC (MIN.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL =24 mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH tPHL
OPERATING VOLTAGE RANGE:
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74AC573B
74AC573M
latch enable input (LE) and an output enable
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The AC573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power applications
mantaining high speed operation similar to
equivalentBipolar Schottky TTL.
These 8 bit D-Type latches are controlled by a
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
April 1997
74AC573
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 3, 4,
5, 6, 7,
8, 9
D0 to D7 Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7 3 State Latch Outputs
11
LE
Latch Enable
Input
10
20
GND
VCC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
L
LE
X
D
X
X
L
Q
Z
L
NO CHANGE *
L
H
L
L
H
H
H
X:Don’t care
Z: High impedance
* Q output are latched at the time when the LE inputs taken low logic level.
LOGIC DIAGRAM
2/10
74AC573
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
oC
IOK
± 20
IO
± 50
ICC or IGND DC VCC or Ground Current
± 400
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 6
Unit
V
Supply Voltage
Input Voltage
Output Voltage
0 to VCC
0 to VCC
-40 to +85
8
V
VO
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5 V(note 1)
ns/V
1) VIN from30% to 70% of VCC
3/10
74AC573
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
High Level Input Voltage
Low Level Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
VO = 0.1 V or
2.1
1.5
2.25
2.75
1.5
2.1
V
CC - 0.1 V
V
V
3.15
3.85
3.15
3.85
VIL
VO = 0.1 V or
0.9
0.9
V
CC - 0.1 V
2.25 1.35
2.75 1.65
2.99
1.35
1.65
VOH
High Level Output
Voltage
IO=-50 µA
2.9
4.4
2.9
4.4
(*)
IO=-50 µA
IO=-50 µA
IO=-12 mA
IO=-24 mA
IO=-24 mA
IO=50 µA
IO=50 µA
IO=50 µA
IO=12 mA
IO=24 mA
IO=24 mA
4.49
VI
=
5.4
5.49
5.4
VIH or
VIL
V
V
2.56
3.86
4.86
2.46
3.76
4.76
VOL
Low Level Output
Voltage
0.002
0.001
0.001
0.1
0.1
0.1
0.1
(*)
VI
=
0.1
0.1
VIH or
VIL
0.36
0.36
0.36
±0.1
±0.5
0.44
0.44
0.44
±1
II
Input Leakage Current
VI = VCC or GND
µA
µA
IOZ
3-State Output Off-state
Current
VI = VCC or GND
VO = VCC or GND
±5
V
I(OE) = VIH
ICC
Quiescent Supply
Current
5.5
5.5
VI = VCC or GND
8
80
µA
IOLD
IOHD
Dynamic Output Current
(note 1, 2)
VOLD = 1.65 V max
VOHD = 3.85 V min
75
mA
mA
-75
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.
(*) All outputs loaded.
4/10
74AC573
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
tPLH
tPHL
Propagation Delay Time
LE to Q
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
6
4.5
5.5
4.5
6.5
5
10
8
12
9
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay Time
D to Q
10
8
12
9
tPZL
tPZH
Output EnableTime
11
9
13
10
14
11
4.5
4
tPLZ
tPHZ
Output Disable Time
7
12
10
4
6
tw
Clock Pulse Width HIGH
or LOW
1.5
1.5
0.5
0
3.5
3
ts
Setup Time Q to CK
HIGH or LOW
3.5
3
2.5
3
th
Hold Time Q to CK
HIGH or LOW
-0.5
0
3.5
3
2.5
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is5V ± 0.5V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
COUT Output Capacitance
8
4
5.0
5.0
5.0
pF
pF
pF
CIN
Input Capacitance
CPD
Power Dissipation
20
Capacitance (note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN +ICC/n (per circuit)
5/10
74AC573
TEST CIRCUIT
TEST
SWITCH
Open
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
2VCC
Open
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL =R1 = 500Ω or equivalent
RT =ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH,
Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74AC573
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74AC573
Plastic DIP20 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.254
1.39
TYP.
MAX.
MIN.
0.010
0.055
MAX.
a1
B
b
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
2.54
22.86
0.335
0.100
0.900
e3
F
7.1
0.280
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
P001J
8/10
74AC573
SO20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45° (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8° (max.)
P013L
9/10
74AC573
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise underany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics productsare notauthorized for use as criticalcomponents in life supportdevices or systems withoutexpress
written approval of SGS-THOMSON Microelectonics.
1997 SGS-THOMSON Microelectronics - Printedin Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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10/10
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