74ACT174 [STMICROELECTRONICS]
HEX D-TYPE FLIP FLOP WITH CLEAR; HEX D型触发器与Clear FLOP
| 型号： | 74ACT174 |
| 厂家： | 
ST |
| 描述： | HEX D-TYPE FLIP FLOP WITH CLEAR |
| 文件： | 总10页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ACT174
HEX D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
■
■
■
■
■
■
■
■
■
HIGH SPEED:
fMAX = 200 MHz (TYP.) at VCC =5V
LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), V = 0.8V (MAX)
B
M
IL
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL =24 mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH tPHL
OPERATING VOLTAGE RANGE:
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT174B
74ACT174M
TTL.
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT174 is an high-speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to eqivalent Bipolar Schottky
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
May 1997
74ACT174
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
CLEAR
Asyncronous Master Reset
(Active LOW)
2, 5, 7, 10,
12, 15
Q0 to Q5 Flip-Flop Outpus
3, 4, 6, 11,
13, 14
D0 to D5 Data Inputs
9
CLOCK
Clock Input (LOW-to-HIGH,
Edge- Triggered)
8
GND
VCC
Ground (0V)
16
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
X
L
CLOCK
Q
L
L
H
H
H
X
CLEAR
L
H
X
H
Qn
NO CHANGE
X:Don’t Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/10
74ACT174
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
oC
IOK
± 20
IO
± 50
ICC or IGND DC VCC or Ground Current
± 300
Tstg
TL
Storage Temperature
-65 to +150
Lead Temperature (10 sec)
300
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to VCC
0 to VCC
-40 to +85
8
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
ns/V
1) VIN from0.8 V to2.0 V
3/10
74ACT174
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
VO = 0.1 V or
2.0
2.0
1.5
1.5
2.0
2.0
V
V
V
V
CC - 0.1 V
VO = 0.1 V or
VCC - 0.1 V
1.5
0.8
0.8
0.8
0.8
1.5
VOH
IO=-50 µA
4.4
5.4
4.49
5.49
4.4
5.4
(*)
VI
=
IO=-50 µA
IO=-24 mA
IO=-24 mA
IO=50 µA
IO=50 mA
IO=24 mA
IO=24 mA
VIH or
VIL
3.86
4.86
3.76
4.76
VOL
Low Level Output Voltage
0.001
0.001
0.1
0.1
0.1
0.1
0.44
0.44
±1
(*)
V
VI
=
VIH or
VIL
0.36
0.36
±0.1
II
Input Leakage Current
Max ICC /Input
VI = VCC or GND
VI = VCC -2.1 V
µA
mA
µA
ICCT
ICC
IOLD
IOHD
0.6
1.5
80
Quiescent Supply Current
VI = VCC or GND
VOLD = 1.65 V max
VOHD = 3.85 V min
8
Dynamic Output Current
(note 1, 2)
75
mA
mA
-75
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.
(*) All outputs loaded.
4/10
74ACT174
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
5.0(*)
-40 to 85 oC
tPLH
tPHL
tPLH
tPHL
twL
tw
Propagation Delay Time
CK to Q
1.5
7.0
10.5
11.5
ns
ns
Propagation Delay Time
CLR to Q
5.0(*)
1.5
6.5
9.5
11.0
CLR pulse Width, LOW
CK pulse Width
5.0(*)
5.0(*)
5.0(*)
1.5
1.5
0.5
3.0
3.0
1.5
3.5
3.5
1.5
ns
ns
ts
Setup Time Q to CK HIGH
or LOW
ns
ns
th
Hold Time Q to CK HIGH
or LOW
5.0(*)
1.0
2.0
0.5
2.0
0.5
tREM
fMAX
Recovery Time CLR to CK
Maximum Clock Frequency
5.0(*)
5.0(*)
-1.0
200
ns
165
140
MHz
(*) Voltage range is 5V ± 0.5V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
4
5.0
5.0
pF
pF
CPD
Power Dissipation
fIN = 10 MHz
TBD
Capacitance (note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN +ICC/n (percircuit)
5/10
74ACT174
TEST CIRCUIT
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL =R1 = 500Ω or equivalent
RT =ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74ACT174
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
7/10
74ACT174
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
0.77
TYP.
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
8/10
74ACT174
SO-16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8 (max.)
P013H
9/10
74ACT174
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise underany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics productsare notauthorized for use as criticalcomponents in life supportdevices or systems withoutexpress
written approval of SGS-THOMSON Microelectonics.
1997 SGS-THOMSON Microelectronics - Printedin Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia- Brazil - Canada - China - France - Germany - Hong Kong - Italy- Japan- Korea - Malaysia- Malta- Morocco - TheNetherlands -
Singapore - Spain- Sweden- Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
.
10/10
相关型号：
74ACT174FC
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CDFP16, CERAMIC, FP-16
FAIRCHILD
74ACT174FCTR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CDFP16, CERAMIC, FP-16
FAIRCHILD
74ACT174LC
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT174LCTR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT174LCXR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT174PCQR
IC ACT SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16, FF/Latch
NSC
©2020 ICPDF网 联系我们和版权申明