74ACT574 [STMICROELECTRONICS]
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING; 八路D型触发器具有三态输出的非反相FLOP
| 型号： | 74ACT574 |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING |
| 文件： | 总11页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ACT574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
■
■
■
■
■
■
■
■
■
HIGH SPEED:
fMAX =250MHz(TYP.) at VCC =3.3V
LOW POWER DISSIPATION:
o
µ
I
CC =8 A (MAX.) at TA =25 C
COMPATIBLEWITH TTL OUTPUTS
VIH =2V (MIN), VIL = 0.8V(MAX)
DIP
SOP
TSSOP
Ω
50 TRANSMISSIONLINEDRIVING
ORDER CODES
TUBE
CAPABILITY
PACKAGE
DIP
T & R
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
M74ACT574B
M74ACT574M
SOP
M74ACT574MTR
M74ACT574TTR
TSSOP
OPERATING VOLTAGERANGE:
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
VCC (OPR)= 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES574
IMPROVED LATCH-UP IMMUNITY
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
The device is designed to interface directly High
Speed CMOS system with TTL and NMOS
components.
DESCRIPTION
The ACT574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK)and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11
February 2000
74ACT574
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 3, 4,
5, 6, 7,
8, 9
D0 to D7 Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7 3 State Outputs
11
CLOCK
Clock Input (LOW to
HIGH, edge triggered)
10
20
GND
VCC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
L
CK
D
X
X
L
Q
X
Z
NO CHANGE
L
L
L
H
H
X:DON’TCARE
Z:HIGHIMPEDANCE
LOGIC DIAGRAMS
2/11
74ACT574
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
IOK
± 20
IO
50
±
ICC or IGND DC VCC or Ground Current
400
±
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
oC
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to VCC
0 to VCC
-40 to +85
8
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
ns/V
1)VIN from0.8V to2.0V
3/11
74ACT574
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
VO = 0.1V or
VCC - 0.1 V
2.0
2.0
1.5
1.5
2.0
2.0
V
V
VO = 0.1V or
VCC - 0.1 V
1.5
0.8
0.8
0.8
0.8
1.5
VOH
High Level Output
Voltage
I =-50
A
4.4
5.4
4.49
5.49
4.4
5.4
µ
O
VI(*)
VIH or
VIL
=
IO=-50 µA
V
V
IO=-24 mA 3.86
IO=-24 mA 4.86
IO=50 µA
3.76
4.76
VOL
Low Level Output
Voltage
0.001 0.1
0.001 0.1
0.36
0.1
0.1
0.44
0.44
±1
VI(*)
VIH or
VIL
=
IO=50 mA
IO=24 mA
IO=24 mA
0.36
II
Input Leakage Current
VI = VCC or GND
±0.1
µA
µA
IOZ
3 State Output Leakage
Current
VI = VIH or VIL
VO = VCC or GND
±0.5
±5
ICCT
ICC
Max ICC /Input
5.5
5.5
VI = VCC -2.1 V
0.6
1.5
80
mA
Quiescent Supply
Current
VI = VCC or GND
8
µA
IOLD
IOHD
Dynamic Output Current
(note 1, 2)
5.5
VOLD = 1.65 V max
VOHD = 3.85 V min
75
mA
mA
-75
1) Maximum test duration 2ms, one output loaded attime
2)Incident wave switchingis guaranteed ontransmission lines withimpedances aslowas50 Ω.
(*) All outputs loaded.
4/11
74ACT574
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, RL = 500 Ω, Input tr = t =3 ns)
f
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
tPLH
tPHL
tPZL
tPZH
tPLH
tPHL
tw
Propagation Delay Time
CK to Q
5.0(*)
5.0
10.0
11.0
ns
Output Enable Time
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.5
5.0
1.5
1.0
-1.0
250
9.0
8.5
3.0
2.5
2.5
10.0
9.0
4.0
3.0
3.0
ns
ns
Output Disable Time
CK Pulse Width, HIGH
or LOW
ns
ts
Setup Time Q to CK
HIGH or LOW
ns
th
Hold Time Q to CK
HIGH or LOW
ns
fMAX
Maximim Clock
Frequency
100
85
MHz
(*) Voltagerangeis5V ± 0.5V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
COUT Output Capacitance
5.0
5.0
5.0
8
4
pF
pF
pF
CIN
Input Capacitance
CPD
Power Dissipation
26
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operating current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/n(per circuit)
5/11
74ACT574
TEST CIRCUIT
TEST
SWITCH
Open
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
2VCC
Open
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL =R1 =500Ω orequivalent
RT = ZOUT ofpulse generator (typically50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/11
74ACT574
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES
(f=1MHz; 50% duty cycle)
WAVEFORM 3: PULSE WIDTH
7/11
74ACT574
Plastic DIP-20 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.254
1.39
TYP.
MAX.
MIN.
0.010
0.055
MAX.
a1
B
b
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
0.335
0.100
0.900
2.54
22.86
e3
F
7.1
0.280
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
P001J
8/11
74ACT574
SO-20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45 (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8 (max.)
P013L
9/11
74ACT574
TSSOP20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.260
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
6.4
0.10
0.9
0.15
0.95
0.30
0.2
0.002
0.335
0.0075
0.0035
0.252
0.246
0.169
0.004
0.354
c
D
6.5
6.4
6.6
0.256
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
10/11
74ACT574
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
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subject to change without notice. Thispublication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in lifesupport devices or systems withoutexpress written approval of STMicroelectronics.
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11/11
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