74ACT74B [STMICROELECTRONICS]
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR; 带预置和清除两个D型触发器
| 型号： | 74ACT74B |
| 厂家： | 
ST |
| 描述： | DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR |
| 文件： | 总11页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
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HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC =5V
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), V = 0.8V (MAX)
B
M
IL
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL =24 mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH tPHL
OPERATING VOLTAGE RANGE:
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT74B
74ACT74M
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
SchottkyTTL.
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The ACT74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and
double-layer metal
wiring
C2MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11
April 1997
74ACT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
3, 11
1D, 2D
Data Inputs
1CK, 2CK Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR Asyncronous Set - Direct
Input
5, 9
6, 8
1Q, 2Q
1Q, 2Q
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
7
GND
VCC
Ground (0V)
14
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
L
PR
H
L
D
X
X
X
L
CK
X
Q
L
Q
H
L
CLEAR
H
X
H
H
L
PRESET
L
L
X
H
H
L
H
H
H
H
H
H
X
H
Qn
H
Qn
NO CHANGE
X:Don’t Care
LOGIC DIAGRAMS
This logic diagram has not be used to estimate propagation delays
2/11
74ACT74
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
oC
IOK
± 20
IO
± 50
ICC or IGND DC VCC or Ground Current
± 200
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to VCC
0 to VCC
-40 to +85
8
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage
V
oC
Top
Operating Temperature:
dt/dv
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
ns/V
1) VIN from0.8 V to2.0 V
3/11
74ACT74
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
VO = 0.1 V or
2.0
2.0
1.5
1.5
2.0
2.0
V
V
V
V
CC - 0.1 V
VO = 0.1 V or
VCC - 0.1 V
1.5
0.8
0.8
0.8
0.8
1.5
VOH
High Level Output
Voltage
IO=-50 µA
4.4
5.4
4.49
5.49
4.4
5.4
(*)
VI
=
IO=-50 µA
IO=-24 mA
IO=-24 mA
IO=50 µA
IO=50 mA
IO=24 mA
IO=24 mA
VIH or
VIL
3.86
4.86
3.76
4.76
VOL
Low Level Output
Voltage
0.001
0.001
0.1
0.1
0.1
0.1
0.44
0.44
±1
(*)
VI
=
V
VIH or
VIL
0.36
0.36
±0.1
II
Input Leakage Current
Max ICC /Input
VI = VCC or GND
VI = VCC -2.1 V
VI = VCC or GND
µA
mA
µA
ICCT
ICC
0.6
1.5
40
Quiescent Supply
Current
4
IOLD
IOHD
Dynamic Output Current
(note 1, 2)
5.5
VOLD = 1.65 V max
VOHD = 3.85 V min
75
mA
mA
-75
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.
(*) All outputs loaded.
4/11
74ACT74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
tPLH
tPHL
Propagation Delay Time
CK to Q
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0
10.0
10.0
5.0
11.0
11.0
6.0
ns
ns
tPLH
tPHL
Propagation Delay Time
PR or CLR to Q or Q
5.0
tw
CK Pulse Width, HIGH
or LOW
1.5
ns
ts
Setup Time Q to CK
HIGH or LOW
0.5
3.0
3.5
ns
th
Hold Time Q to CK
HIGH or LOW
-0.5
-0.7
250
1.0
1.0
ns
trem
fMAX
Removal Time PR or
CLR to CK
1.0
1.0
ns
Maximim Clock
Frequency
100
85
MHz
(*) Voltage range is 5V ± 0.5V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
4
5.0
5.0
pF
pF
CPD
Power Dissipation
43
Capacitance (note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN +ICC/n (per circuit)
5/11
74ACT74
TEST CIRCUIT
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL =R1 = 500Ω or equivalent
RT =ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/11
74ACT74
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
7/11
74ACT74
WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PULSE WIDTH
8/11
74ACT74
Plastic DIP14 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
1.39
TYP.
MAX.
MIN.
0.020
0.055
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
15.24
0.335
0.100
0.600
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
2.54
0.050
0.100
P001A
9/11
74ACT74
SO14 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
8.55
5.8
8.75
6.2
0.336
0.228
0.344
0.244
E
e
1.27
7.62
0.050
0.300
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.026
G
L
1.27
0.68
M
S
8 (max.)
P013G
10/11
74ACT74
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise underany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics productsare notauthorized for use as criticalcomponents in life supportdevices or systems withoutexpress
written approval of SGS-THOMSON Microelectonics.
1997 SGS-THOMSON Microelectronics - Printedin Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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11/11
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