74LCX373MTR [STMICROELECTRONICS]
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS; 八D型锁存器同相（ 3 -STATE ） ，容许5V输入和输出
| 型号： | 74LCX373MTR |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS |
| 文件： | 总10页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LCX373
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
■
■
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
= 8.0 ns (MAX.) at V = 3V
t
PD
CC
■
■
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
SOP
TSSOP
|I | = I = 24mA (MIN) at V = 3V
OH
OL
CC
■
■
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
ORDER CODES
PACKAGE
t
t
PLH
PHL
TUBE
T & R
■
OPERATING VOLTAGE RANGE:
(OPR) = 2.0V to 3.6V (1.5V Data
V
SOP
74LCX373M
74LCX373MTR
74LCX373TTR
CC
Retention)
TSSOP
■
■
■
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched precisely
at the logic level of D input data. While the (OE)
input is low, the 8 outputs will be in a normal logic
state (high or low logic level) and while (OE) is in
high level, the outputs will be in a high impedance
state.
DESCRIPTION
The 74LCX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C MOS
3
STATE OUTPUT
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
2
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
September 2001
1/10
74LCX373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
PIN No
SYMBOL
NAME AND FUNCTION
INPUT
OUTPUT
Q
1
OE
3 State Output Enable
Input (Active LOW)
OE
LE
D
H
L
L
L
X
L
X
X
L
Z
2, 5, 6, 9, 12,
15, 16,19
D0 to D7
Q0 to Q7
Data Inputs
NO CHANGE*
H
H
L
3, 4, 7, 8, 13,
14, 17, 18
3-State Outputs
H
H
11
10
20
LE
Latch Enable Input
Ground (0V)
X : Don’t Care
Z : High Impedance
* : Q Outputs are latched at the time when the LE input is taken
LOW.
GND
V
Positive Supply Voltage
CC
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/10
74LCX373
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
V
O
O
V
I
-0.5 to V + 0.5
V
CC
- 50
- 50
mA
mA
mA
mA
mA
°C
°C
IK
I
DC Output Diode Current (note 2)
DC Output Current
OK
I
± 50
O
I
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
± 100
± 100
-65 to +150
300
CC
I
GND
T
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I absolute maximum rating must be observed
O
2) V < GND
O
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
2.0 to 3.6
0 to 5.5
0 to 5.5
V
V
CC
V
I
V
Output Voltage (OFF State)
V
O
V
Output Voltage (High or Low State)
0 to V
V
O
CC
I
I
, I
High or Low Level Output Current (V = 3.0 to 3.6V)
± 24
± 12
mA
mA
°C
ns/V
OH OL
CC
, I
High or Low Level Output Current (V = 2.7V)
OH OL
CC
T
Operating Temperature
-55 to 125
0 to 10
op
dt/dv
Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.5V to 3.6V
2) V from 0.8V to 2V at V = 3.0V
IN
CC
3/10
74LCX373
DC SPECIFICATIONS
Test Condition
Value
Symbol
Parameter
-40 to 85 °C
Min. Max.
-55 to 125 °C
Unit
V
(V)
CC
Min.
Max.
V
High Level Input
Voltage
IH
2.0
2.0
V
V
2.7 to 3.6
V
Low Level Input
Voltage
IL
0.8
0.8
V
High Level Output
Voltage
I =-100 µA
V
-0.2
V
-0.2
CC
2.7 to 3.6
2.7
OH
O
CC
I =-12 mA
2.2
2.4
2.2
2.2
O
V
V
I =-18 mA
2.4
2.2
O
3.0
I =-24 mA
O
V
Low Level Output
Voltage
I =100 µA
2.7 to 3.6
2.7
0.2
0.4
0.2
0.4
OL
O
I =12 mA
O
I =16 mA
0.4
0.4
O
3.0
I =24 mA
0.55
0.55
O
I
Input Leakage
Current
I
V = 0 to 5.5V
2.7 to 3.6
0
± 5
± 5
µA
µA
I
I
Power Off Leakage
Current
off
V or V = 5.5V
10
10
I
O
I
I
High Impedance
Output Leakage
Current
OZ
CC
V = V or V
I
IH
IL
2.7 to 3.6
± 5
± 5
µA
V
= 0 to V
O
CC
Quiescent Supply
Current
V = V or GND
I CC
10
10
2.7 to 3.6
2.7 to 3.6
µA
µA
V or V = 3.6 to 5.5V
± 10
500
± 10
500
I
O
∆I
I
incr. per Input
V
= V - 0.6V
CC
CC
IH
CC
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Value
T
= 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
V
Dynamic Low Level Quiet
Output (note 1)
0.8
C = 50pF
OLP
L
3.3
V
V
= 0V, V = 3.3V
V
-0.8
IL
IH
OLV
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
4/10
74LCX373
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
-55 to 125 °C
Symbol
Parameter
-40 to 85 °C
Unit
V
C
R
t = t
CC
L
L
s
r
(V)
(pF)
(Ω)
500
500
(ns)
Min.
Max.
Min.
Max.
t
t
t
t
Propagation Delay
Time (Dn to Qn)
2.7
3.0 to 3.6
2.7
1.5
1.5
1.5
1.5
1.5
9.0
8.0
9.5
8.5
9.5
1.5
1.5
1.5
1.5
1.5
9.0
8.0
9.5
8.5
9.5
PLH PHL
50
2.5
ns
ns
t
Propagation Delay
Time (LE to Qn)
PLH PHL
50
2.5
3.0 to 3.6
2.7
t
Output Enable Time
to HIGH and LOW
level
PZL PZH
50
50
50
50
500
500
500
500
2.5
2.5
2.5
2.5
ns
ns
ns
ns
3.0 to 3.6
2.7
1.5
1.5
1.5
2.5
2.5
1.5
1.5
8.5
8.5
7.5
1.5
1.5
1.5
2.5
2.5
1.5
1.5
8.5
8.5
7.5
t
t
Output Disable Time
from HIGH to LOW
level
PLZ PHZ
3.0 to 3.6
2.7
t
Set-Up Time, HIGH
or LOW level
(Dn to LE)
S
3.0 to 3.6
2.7
t
Hold Time, HIGH or
LOW level
(Dn to LE)
h
3.0 to 3.6
t
LE Pulse Width,
HIGH
2.7
3.3
3.3
3.3
3.3
W
50
50
500
500
2.5
2.5
ns
ns
3.0 to 3.6
3.0 to 3.6
t
t
Output To Output
Skew Time (note1,
2)
1.0
1.0
OSLH
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
= | t
- t
|, t
= | t
- t
|)
OSLH
PLHm PLHn OSHL
PHLm PHLn
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T
= 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
C
Input Capacitance
Output Capacitance
V
V
= 0 to V
3.3
3.3
3.3
6
pF
pF
IN
IN
IN
CC
C
= 0 to V
12
50
OUT
CC
C
Power Dissipation Capacitance
(note 1)
f
V
= 10MHz
= 0 or V
CC
PD
IN
IN
pF
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /8 (per latch)
CC(opr)
PD CC IN CC
5/10
74LCX373
TEST CIRCUIT
TEST
SWITCH
t
t
t
, t
Open
6V
PLH PHL
, t
PZL PLZ
, t
GND
PZH PHZ
C
R
R
= 50 pF or equivalent (includes jig and probe capacitance)
L
L
T
= R1 = 500Ω or equivalent
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74LCX373
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74LCX373
SO-20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
2.65
0.2
MIN.
MAX.
0.104
0.008
0.096
0.019
0.012
A
a1
a2
b
0.1
0.004
2.45
0.49
0.32
0.35
0.23
0.014
0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.020
0.300
0.050
0.029
L
M
S
8° (max.)
PO13L
8/10
74LCX373
TSSOP20 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0089
0.260
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
6.6
0.002
0.031
0.007
0.004
0.252
0.244
0.169
0.004
0.039
1
0.19
0.09
6.4
c
D
6.5
6.4
0.256
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0°
8°
0°
8°
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
9/10
74LCX373
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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systems without express written approval of STMicroelectronics.
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10/10
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