74LVQ08T [STMICROELECTRONICS]

QUAD 2-INPUT AND GATE; 四2输入与门
74LVQ08T
型号: 74LVQ08T
厂家: ST    ST
描述:

QUAD 2-INPUT AND GATE
四2输入与门

栅极 触发器 逻辑集成电路 光电二极管 输入元件
文件: 总11页 (文件大小:217K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74LVQ08  
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE  
HIGH SPEED:  
= 5.6 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 2µA(MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SOP  
TSSOP  
V
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12 mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ08MTR  
74LVQ08TTR  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 08  
V
technology. It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 2 stages  
including buffer output, which enables high noise  
immunity and stable output.  
CC  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ08 is a low voltage CMOS QUAD  
2-INPUT AND GATE fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/11  
July 2004  
74LVQ08  
Figure 2: Input And Output Equivalent Circuit  
Table 2: Pin Description  
PIN N°  
SYMBOL  
NAME AND FUNCTION  
1, 4, 9, 12  
2, 5, 10, 13  
3, 6, 8, 11  
7
1A to 4A  
1B to 4B  
1Y to 4Y  
GND  
Data Inputs  
Data Inputs  
Data Outputs  
Ground (0V)  
V
14  
Positive Supply Voltage  
CC  
Table 3: Truth Table  
A
B
Y
L
L
L
H
L
L
L
H
H
L
H
H
Table 4: Absolute Maximum Ratings  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
-0.5 to +7  
V
V
CC  
V
DC Input Voltage  
-0.5 to V + 0.5  
I
CC  
V
DC Output Voltage  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
-0.5 to V + 0.5  
V
O
CC  
I
± 20  
± 20  
mA  
mA  
mA  
mA  
°C  
°C  
IK  
I
OK  
I
± 50  
O
I
or I  
DC V or Ground Current  
± 200  
CC  
GND  
CC  
T
Storage Temperature  
-65 to +150  
300  
stg  
T
Lead Temperature (10 sec)  
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is  
not implied  
Table 5: Recommended Operating Conditions  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage (note 1)  
Input Voltage  
2 to 3.6  
V
V
CC  
V
0 to V  
I
CC  
V
Output Voltage  
0 to V  
V
O
CC  
T
Operating Temperature  
-55 to 125  
0 to 10  
°C  
ns/V  
op  
Input Rise and Fall Time V = 3.0V (note 2)  
dt/dv  
CC  
1) Truth Table guaranteed: 1.2V to 3.6V  
2) V from 0.8V to 2V  
IN  
2/11  
74LVQ08  
Table 6: DC Specifications  
Test Condition  
Value  
-40 to 85°C -55 to 125°C Unit  
Min. Typ. Max. Min. Max. Min. Max.  
T = 25°C  
Symbol  
Parameter  
A
V
CC  
(V)  
V
High Level Input  
Voltage  
IH  
2.0  
2.0  
2.0  
V
V
3.0 to  
3.6  
V
Low Level Input  
Voltage  
IL  
0.8  
0.8  
0.8  
V
High Level Output  
Voltage  
I =-50 µA  
2.9  
2.99  
2.9  
2.48  
2.2  
2.9  
2.48  
2.2  
OH  
O
I =-12 mA  
3.0  
3.0  
2.58  
V
V
O
I =-24 mA  
O
V
Low Level Output  
Voltage  
I =50 µA  
0.002 0.1  
0.1  
0.1  
OL  
O
I =12 mA  
0
0.36  
0.44  
0.55  
0.44  
0.55  
O
I =24 mA  
O
I
Input Leakage  
Current  
I
V = V or GND  
3.6  
3.6  
± 0.1  
± 1  
± 1  
µA  
µA  
I
CC  
I
Quiescent Supply  
Current  
CC  
V = V or GND  
2
20  
20  
I
CC  
I
V
= 0.8 V max  
= 2 V min  
36  
25  
mA  
mA  
OLD  
OLD  
Dynamic Output  
Current (note 1, 2)  
3.6  
I
V
OHD  
-25  
-25  
OHD  
1) Maximum test duration 2ms, one output loaded at time  
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75  
Table 7: Dynamic Switching Characteristics  
Test Condition  
Value  
T = 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
Min. Typ. Max. Min. Max. Min. Max.  
A
V
(V)  
CC  
V
Dynamic Low  
0.3  
0.8  
OLP  
Voltage Quiet  
Output (note 1, 2)  
3.3  
3.3  
V
V
V
-0.8  
2
-0.3  
OLV  
V
Dynamic High  
Voltage Input  
(note 1, 3)  
IHD  
C = 50 pF  
L
V
Dynamic Low  
Voltage Input  
(note 1, 3)  
3.3  
0.8  
V
ILD  
1) Worst case package.  
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.  
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ), 0V to threshold  
ILD  
(V ), f=1MHz.  
IHD  
3/11  
74LVQ08  
Table 8: AC Electrical Characteristics (C = 50 pF, R = 500 , Input t = t = 3ns)  
L
L
r
f
Test Condition  
Value  
T = 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
t
t
Propagation Delay  
Time  
2.7  
.
6.8  
5.6  
0.5  
0.5  
12.0  
8.5  
1.0  
1.0  
13.0  
9.0  
15.0  
10.5  
1.0  
PLH PHL  
ns  
ns  
(*)  
3.3  
2.7  
t
t
Output To Output  
Skew Time  
(note1, 2)  
1.0  
OSLH  
OSHL  
(*)  
1.0  
1.0  
3.3  
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-  
ing in the same direction, either HIGH or LOW (t  
2) Parameter guaranteed by design  
(*) Voltage range is 3.3V ± 0.3V  
= |t  
- t  
|, t  
= |t  
- t  
|)  
OSLH  
PLHm PLHn OSHL  
PHLm PHLn  
Table 9: Capacitive Characteristics  
Test Condition  
Value  
T = 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
C
Input Capacitance  
3.3  
4
pF  
pF  
IN  
C
Power Dissipation  
Capacitance  
(note 1)  
PD  
f
= 10MHz  
3.3  
32  
IN  
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without  
PD  
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I  
= C x V x f + I /4 (per gate)  
CC(opr)  
PD CC IN CC  
Figure 3: Test Circuit  
C
L
R
L
R
T
= 50pF or equivalent (includes jig and probe capacitance)  
= 500or equivalent  
= Z  
of pulse generator (typically 50)  
OUT  
4/11  
74LVQ08  
Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)  
5/11  
74LVQ08  
SO-14 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
MIN.  
MAX.  
A
A1  
A2  
B
1.35  
1.75  
0.053  
0.069  
0.1  
1.10  
0.33  
0.19  
8.55  
3.8  
0.25  
1.65  
0.51  
0.25  
8.75  
4.0  
0.004  
0.043  
0.013  
0.007  
0.337  
0.150  
0.010  
0.065  
0.020  
0.010  
0.344  
0.157  
C
D
E
e
1.27  
0.050  
H
5.8  
0.25  
0.4  
0°  
6.2  
0.50  
1.27  
8°  
0.228  
0.010  
0.016  
0°  
0.244  
0.020  
0.050  
8°  
h
L
k
ddd  
0.100  
0.004  
0016019D  
6/11  
74LVQ08  
TSSOP14 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
1.2  
MIN.  
MAX.  
0.047  
0.006  
0.041  
0.012  
0.0089  
0.201  
0.260  
0.176  
A
A1  
A2  
b
0.05  
0.8  
0.15  
1.05  
0.30  
0.20  
5.1  
0.002  
0.031  
0.007  
0.004  
0.193  
0.244  
0.169  
0.004  
0.039  
1
0.19  
0.09  
4.9  
c
D
5
6.4  
0.197  
0.252  
E
6.2  
6.6  
E1  
e
4.3  
4.4  
4.48  
0.173  
0.65 BSC  
0.0256 BSC  
K
0˚  
8˚  
0˚  
8˚  
L
0.45  
0.60  
0.75  
0.018  
0.024  
0.030  
A2  
A
K
L
b
e
A1  
c
E
D
E1  
PIN 1 IDENTIFICATION  
1
0080337D  
7/11  
74LVQ08  
Tape & Reel SO-14 MECHANICAL DATA  
mm.  
TYP  
inch  
TYP.  
DIM.  
MIN.  
MAX.  
330  
MIN.  
MAX.  
12.992  
0.519  
A
C
12.8  
20.2  
60  
13.2  
0.504  
0.795  
2.362  
D
N
T
22.4  
6.6  
9.2  
2.3  
4.1  
8.1  
0.882  
0.260  
0.362  
0.090  
0.161  
0.319  
Ao  
Bo  
Ko  
Po  
P
6.4  
9
0.252  
0.354  
0.082  
0.153  
0.311  
2.1  
3.9  
7.9  
8/11  
74LVQ08  
Tape & Reel TSSOP14 MECHANICAL DATA  
mm.  
TYP  
inch  
TYP.  
DIM.  
MIN.  
MAX.  
330  
MIN.  
MAX.  
12.992  
0.519  
A
C
12.8  
20.2  
60  
13.2  
0.504  
0.795  
2.362  
D
N
T
22.4  
6.9  
5.5  
1.8  
4.1  
8.1  
0.882  
0.272  
0.217  
0.071  
0.161  
0.319  
Ao  
Bo  
Ko  
Po  
P
6.7  
5.3  
1.6  
3.9  
7.9  
0.264  
0.209  
0.063  
0.153  
0.311  
9/11  
74LVQ08  
Table 10: Revision History  
Date  
Revision  
Description of Changes  
Ordering Codes Revision - pag. 1.  
29-Jul-2004  
5
10/11  
74LVQ08  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
All other names are the property of their respective owners  
© 2004 STMicroelectronics - All Rights Reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America  
www.st.com  
11/11  

相关型号:

74LVQ08TTR

QUAD 2-INPUT AND GATE
STMICROELECTR

74LVQ08_01

Low Voltage Quad 2-Input AND Gate
FAIRCHILD

74LVQ10

TRIPLE 3-INPUT NAND GATE
STMICROELECTR

74LVQ10M

LOGIC GATE|3 3-INPUT NAND|LVQ-CMOS|SOP|14PIN|PLASTIC
ETC

74LVQ10MTR

TRIPLE 3-INPUT NAND GATE
STMICROELECTR

74LVQ10TTR

TRIPLE 3-INPUT NAND GATE
STMICROELECTR

74LVQ11

TRIPLE 3-INPUT AND GATE
STMICROELECTR

74LVQ11M

TRIPLE 3-INPUT AND GATE
STMICROELECTR

74LVQ11MTR

TRIPLE 3-INPUT AND GATE
STMICROELECTR

74LVQ11TTR

TRIPLE 3-INPUT AND GATE
STMICROELECTR

74LVQ125

Low Voltage Quad Buffer with 3-STATE Outputs
FAIRCHILD

74LVQ125

QUAD BUS BUFFERS 3-STATE
STMICROELECTR