74LVQ245 [STMICROELECTRONICS]
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER 3-STATE; 低压CMOS八路总线收发器3 -STATE
| 型号： | 74LVQ245 |
| 厂家： | 
ST |
| 描述： | LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER 3-STATE |
| 文件： | 总8页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVQ245
LOW VOLTAGE CMOS OCTAL BUS
TRANSCEIVER (3-STATE)
■
■
■
HIGH SPEED:tPD =6 ns (TYP.) atVCC =3.3V
COMPATIBLEWITH TTL OUTPUTS
LOW POWER DISSIPATION:
o
µ
I
CC =5 A (MAX.) at TA =25 C
LOWNOISE:VOLP = 0.5V(TYP.) at VCC =3.3V
75Ω TRANSMISSIONLINEDRIVING
CAPABILITY
■
■
M
T
(Micro Package)
(TSSOPPackage)
ORDER CODES :
■
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
74LVQ245M
74LVQ245T
■
■
PCI BUSLEVELSGUARANTEED AT 24mA
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
This IC is intended for two-way asynchronous
communication between data buses; the direction
of data trasmission is determined by DIR input.
The enable input G can be used to disable the
device so that the buses are effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
■
■
■
OPERATING VOLTAGERANGE:
VCC (OPR)= 2V to 3.6V (1.2VData Retention)
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES245
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ245 is a low voltage CMOS OCTAL BUS
TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low
power and low noise 3.3V applications.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
IT IS PROHIBITED TO APPLY A SIGNAL TO A
TERMINAL WHEN IT IS IN OUTPUT MODE
AND WHEN A BUS TERMINAL IS FLOATING
(HIGH IMPEDANCE STATE) IT IS REQUESTED
TO FIX THE INPUT LEVEL BY MEANS OF
EXTERNAL PULL DOWN OR PULL UP
RESISTOR.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/8
March 1999
74LVQ245
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
DIR Directional Control
1
2, 3, 4, 5,
6, 7, 8, 9
A1 to A8 Data Inputs/Outputs
18, 17, 16,
15, 14, 13,
12, 11
B1 to B8 Data Inputs/Outputs
19
10
20
G
Output Enable Input
Ground (0V)
GND
VCC
Positive Supply Voltage
TRUTH TABLE
INPUT
FUNCTION
OUTPUT
G
L
DIR
A BUS
OUTPUT
INPUT
Z
B BUS
INPUT
OUTPUT
Z
L
H
X
A = B
B = A
Z
L
H
X:”H” or”L”
Z:Highimpedance
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
Unit
Supply Voltage
V
V
DC Input Voltage (DIR, G)
DC Bus I/O Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
VI/O
IIK
V
20
mA
mA
mA
mA
oC
oC
±
IOK
± 20
± 50
IO
ICC or IGND DC VCC or Ground Current
± 400
Tstg
Storage Temperature
-65 to +150
TL
Lead Temperature (10 sec)
300
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Supply Voltage (note 1)
Value
2 to 3.6
0 to VCC
0 to VCC
-40 to +85
0 to 10
Unit
V
Input Voltage (DIR, G)
V
VI/O
Bus I/O Voltage
V
oC
Top
Operating Temperature:
tr, tf
Input Rise and Fall Time (VCC = 3V) (note 2)
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2)VIN from0.8Vto2V
2/8
74LVQ245
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VO = 0.1V or
VCC - 0.1 V
2.0
2.0
V
V
3.0 to
3.6
0.8
0.8
VOH
High Level Output
Voltage
3.0
VI(*)
VIH or
VIL
=
IO=-50 µA
2.9
IO=-12 mA 2.58
IO=-24 mA
2.99
2.9
2.48
2.2
V
VOL
Low Level Output
Voltage
3.0
VI(*)
VIH or
VIL
=
IO=50 µA
0.002 0.1
0.1
0.44
0.55
±1
V
IO=12 mA
0
0.36
IO=24 mA
II
Input Leakage Current
VI = VCC or GND
±0.1
µA
3.6
3.6
3.6
IOZ
3 State Output Leakage
Current
VI = VIH or VIL
VO = VCC or GND
0.3
±
3
±
A
µ
ICC
Quiescent Supply
Current
VI = VCC or GND
4
40
µA
IOLD
IOHD
Dynamic Output Current
(note 1, 2)
3.6
VOLD = 0.8 V max
VOHD = 2 V min
36
mA
mA
-25
1) Maximum test duration 2ms, one output loaded attime
2)Incident wave switchingis guaranteed ontransmission lines withimpedances aslowas75 Ω.
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
VOLP Dynamic Low Voltage
3.3
0.5
0.8
Quiet Output (note 1, 2)
VOLV
-0.8
-0.5
VIHD
VILD
Dynamic High Voltage
Input (note 1, 3)
3.3
3.3
2
CL = 50 pF
V
Dynamic Low Voltage
Input (note 1, 3)
0.8
1)Worstcase package
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.3V, (n -1)outputs switching andone outputatGND
3)max number ofdatainputs (n)switching.(n-1)switching 0Vto3.3V. Inputsunder testswitching: 3.3Vtothreshold (VILD),0V tothreshold (VIHD).f=1MHz
3/8
74LVQ245
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, RL = 500 Ω, Input tr = t =3 ns)
f
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
-40 to 85 oC
tPLH
tPHL
Propagation Delay Time
Output Enable Time
Output Disable Time
2.7
3.3(*)
2.7
7.5
6.0
9.5
7.5
10
14.0
10.0
18.0
13.0
20.0
14.5
1.0
15.0
10.5
19.0
13.5
21.0
15.0
1.5
ns
ns
tPZL
tPZH
3.3(*)
tPLZ
tPHZ
2.7
ns
ns
3.3(*)
2.7
7.5
0.5
0.5
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
3.3(*)
1.0
1.5
1) Skewis defined astheabsolute value ofthe difference between theactual propagation delay for any twooutputs of thesame device switching inthe
same direction, either HIGHor LOW (tOSLH = |tPLHm -tPLHn|,tOSHL =|tPHLm -tpHLn|)
2) Parameter guaranteed bydesign
(*) Voltagerangeis3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Ci/o
CPD
Input Capacitance
3.3
3.3
3.3
5
pF
pF
pF
Input/Output Capacitance
10
16
Power Dissipation
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/8(per circuit)
TEST CIRCUIT
TEST
SWITCH
Open
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
2VCC
Open
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL =R1 =500Ω orequivalent
Ω
)
RT = ZOUT ofpulse generator (typically50
4/8
74LVQ245
WAVEFORM 1: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
5/8
74LVQ245
SO-20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45 (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8 (max.)
P013L
6/8
74LVQ245
TSSOP20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.260
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
6.4
0.10
0.9
0.15
0.95
0.30
0.2
0.002
0.335
0.0075
0.0035
0.252
0.246
0.169
0.004
0.354
c
D
6.5
6.4
6.6
0.256
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
7/8
74LVQ245
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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8/8
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