74LVQ280 [STMICROELECTRONICS]
9 BIT PARITY GENERATOR; 9位奇偶校验发生器
| 型号： | 74LVQ280 |
| 厂家： | 
ST |
| 描述： | 9 BIT PARITY GENERATOR |
| 文件： | 总8页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVQ280
9 BIT PARITY GENERATOR
■
HIGH SPEED:
= 8 ns (TYP.) at V = 3.3 V
t
PD
CC
■
■
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
= 2µA(MAX.) at T =25°C
CC
A
■
■
■
LOW NOISE:
= 0.3V (TYP.) at V = 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
V
SOP
TSSOP
OLP
CC
ORDER CODES
PACKAGE
|I | = I = 12mA (MIN) at V = 3.0 V
OH
OL
CC
TUBE
T & R
■
■
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
SOP
74LVQ280M
74LVQ280MTR
74LVQ280TTR
TSSOP
t
t
PHL
PLH
■
■
■
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
V
data inputs control the output conditions. When
the number of high level input is odd, ΣODD
output is kept high and ΣEVEN output low.
Conversely, when the number of high level is
even, ΣEVEN output is kept high and ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
CC
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C MOS
technology. It is ideal for low power and low noise
3.3V applications.
2
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and ΣEVEN). The nine
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/8
74LVQ280
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
5
6
ΣEVEN
ΣODD
A to I
Even Parity Output
Odd Parity Output
Data Inputs
8, 9, 10, 11,
12, 13, 1, 2,
4
3
7
NC
No Connection
GND
Ground (0V)
V
14
Positive Supply Voltage
CC
TRUTH TABLE
OUTPUTS
NUMBER OF INPUTS A - I THAT ARE HIGH
ΣEVEN
ΣODD
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H
L
L
H
LOGIC DIAGRAM
2/8
74LVQ280
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 50
O
I
or I
T
DC V
or Ground Current
CC
± 300
CC
GND
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
2 to 3.6
V
V
CC
V
0 to V
I
CC
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
°C
op
1) Truth Table guaranteed: 1.2V to 3.6V
DC SPECIFICATIONS
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T = 25°C
Symbol
Parameter
A
V
CC
(V)
V
High Level Input
Voltage
IH
2.0
2.0
2.0
V
V
3.0 to
3.6
V
Low Level Input
Voltage
IL
0.8
0.8
0.8
V
High Level Output
Voltage
I =-50 µA
2.9
2.99
2.9
2.48
2.2
2.9
2.48
2.2
OH
O
I =-12 mA
3.0
3.0
2.58
V
V
O
I =-24 mA
O
V
Low Level Output
Voltage
I =50 µA
0.002 0.1
0.1
0.1
OL
O
I =12 mA
0
0.36
0.44
0.55
0.44
0.55
O
I =24 mA
O
I
Input Leakage
Current
I
V = V
or GND
3.6
3.6
± 0.1
± 1
± 1
µA
µA
I
CC
CC
I
Quiescent Supply
Current
CC
V = V
or GND
2
20
20
I
I
V
= 0.8 V max
= 2 V min
36
25
mA
mA
OLD
OLD
Dynamic Output
Current (note 1, 2)
3.6
I
V
OHD
-25
-25
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
3/8
74LVQ280
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
Voltage Quiet
Output (note 1, 2)
0.3
0.8
OLP
3.3
3.3
V
V
V
-0.8
2
-0.3
OLV
V
Dynamic High
Voltage Input
(note 1, 3)
IHD
C = 50 pF
L
V
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
V
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, R = 500 Ω, Input t = t = 3ns)
L
L
r
f
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
t
t
Propagation Delay
Time
2.7
9.9
8.0
0.5
0.5
16.0
11.5
1.0
19.0
13.5
1.0
22.0
16.0
1.0
PLH PHL
ns
ns
(*)
3.3
2.7
t
t
Output To Output
Skew Time
(note1, 2)
OSLH
OSHL
(*)
1.0
1.0
1.0
3.3
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
= |t
- t
|, t
= |t
- t
|)
OSLH
PLHm PLHn OSHL
PHLm PHLn
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
3.3
4
pF
pF
IN
C
Power Dissipation
Capacitance
(note 1)
PD
f
= 10MHz
3.3
59
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /n (per circuit)
CC(opr)
PD CC IN CC
4/8
74LVQ280
TEST CIRCUIT
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)
L
L
T
= 500Ω or equivalent
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
5/8
74LVQ280
SO-14 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
8.55
5.8
8.75
6.2
0.336
0.228
0.344
0.244
E
e
1.27
7.62
0.050
0.300
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.026
G
L
1.27
0.68
M
S
8° (max.)
PO13G
6/8
74LVQ280
TSSOP14 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0°
8°
0°
8°
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
7/8
74LVQ280
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom
© http://www.st.com
8/8
相关型号：
74LVQ299M
LVQ SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, SOP-20
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明