74VHCT125AMTR [STMICROELECTRONICS]
QUAD BUS BUFFERS (3-STATE); 四路总线缓冲器（三态）
| 型号： | 74VHCT125AMTR |
| 厂家： | 
ST |
| 描述： | QUAD BUS BUFFERS (3-STATE) |
| 文件： | 总12页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHCT125A
QUAD BUS BUFFERS (3-STATE)
■
■
HIGH SPEED: t = 3.8 ns (TYP.) at V = 5V
PD CC
LOW POWER DISSIPATION:
I
= 2 µA (MAX.) at T =25°C
CC
A
■
■
■
■
■
■
COMPATIBLE WITH TTL OUTPUTS:
= 2V (MIN.), V = 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
V
IH
IL
SOP
TSSOP
T & R
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 8 mA (MIN)
OH
OL
Table 1: Order Codes
PACKAGE
BALANCED PROPAGATION DELAYS:
t
t
PLH
PHL
OPERATING VOLTAGE RANGE:
(OPR) = 4.5V to 5.5V
SOP
74VHCT125AMTR
74VHCT125ATTR
V
CC
TSSOP
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
■
■
IMPROVED LATCH-UP IMMUNITY
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
LOW NOISE: V
= 0.8V (MAX.)
OLP
DESCRIPTION
The 74VHCT125A is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
2
wiring C MOS technology.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
Figure 1: Pin Connection And IEC Logic Symbols
Rev. 6
1/12
December 2004
74VHCT125A
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
1G to 4G
1A to 4A
1Y to 4Y
GND
Output Enable Inputs
Data Inputs
Data Outputs
Ground (0V)
V
14
Positive Supply Voltage
CC
Table 3: Truth Table
A
G
Y
X
L
H
L
L
Z
L
H
H
X : Don‘t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage (see note 1)
DC Output Voltage (see note 2)
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
O
V
-0.5 to V + 0.5
V
O
CC
I
- 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 25
O
I
or I
DC V or Ground Current
± 50
CC
GND
CC
T
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) Output in OFF State
2) High or Low State
Table 3: RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
4.5 to 5.5
0 to 5.5
0 to 5.5
V
V
CC
V
Input Voltage
I
V
Output Voltage (see note 1)
Output Voltage (see note 2)
Operating Temperature
V
O
V
0 to V
V
O
CC
T
-55 to 125
0 to 20
°C
ns/V
op
Input Rise and Fall Time (see note 3) (V = 5.0 ± 0.5V)
dt/dv
CC
1) Output in OFF State
2) High or Low State
3) V from 0.8V to 2V
IN
2/12
74VHCT125A
Table 4: DC Specifications
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T = 25°C
Symbol
Parameter
A
V
CC
(V)
V
High Level Input
Voltage
4.5 to
5.5
IH
2
2
2
V
V
V
Low Level Input
Voltage
4.5 to
5.5
IL
0.8
0.8
0.8
V
High Level Output
Voltage
I =-50 µA
4.5
4.5
4.5
4.5
4.4
4.5
0.0
4.4
3.8
4.4
3.7
OH
O
V
V
I =-8 mA
3.94
O
V
Low Level Output
Voltage
I =50 µA
0.1
0.1
0.1
OL
OZ
O
I =8 mA
0.36
0.44
0.55
O
I
High Impedance
Output Leakage
Current
V = V or V
4.5 to
5.5
I
IH
IL
±0.25
± 2.5
± 2.5
µA
V
= 0V to 5.5V
O
I
Input Leakage
Current
0 to
5.5
I
V = 5.5V or GND
± 0.1
± 1.0
± 1.0
µA
µA
I
I
Quiescent Supply
Current
CC
V = V or GND
5.5
5.5
0
2
20
20
I
CC
+I
Additional Worst
Case Supply
Current
One Input at 3.4V,
CC
other input at V
1.35
0.5
1.5
5.0
1.5
5.0
mA
CC
or GND
I
Output Leakage
Current
OPD
V
= 5.5V
µA
OUT
Table 5: AC Electrical Characteristics (Input t = t = 3ns)
r
f
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
A
V
C
L
CC
(V) (pF)
(*)
t
Propagation Delay
Time
15
50
15
50
RL = 1 KΩ
RL = 1 KΩ
RL = 1 KΩ
RL = 1 KΩ
3.8
5.3
3.6
5.1
5.5
7.5
5.1
7.1
1.0
1.0
1.0
1.0
6.5
8.5
6.0
8.0
1.0
1.0
1.0
1.0
6.5
8.5
6.0
8.0
PLH
5.0
5.0
5.0
5.0
ns
t
PHL
(*)
(*)
(*)
t
t
Output Disable
Time
PZL
ns
ns
PZH
t
t
Output Enable
Time
PLZ
PHZ
(*)
50
6.1
8.8
1.0
10.0
1.0
10.0
RL = 1 KΩ
5.0
(*) Voltage range is 5.0V ± 0.5V
3/12
74VHCT125A
Table 6: Capacitive Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
4
10
10
10
pF
pF
IN
Output
Capacitance
C
10
OUT
C
Power Dissipation
Capacitance
(note 1)
PD
18
pF
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /4 (per circuit)
CC(opr)
PD CC IN CC
Table 7: Dynamic Switching Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
Voltage Quiet
Output (note 1, 2)
0.3
0.8
0.8
OLP
5.0
V
-0.8
2.0
-0.3
OLV
Dynamic High
Voltage Input
(note 1, 3)
V
C = 50 pF
L
5.0
5.0
V
IHD
Dynamic Low
Voltage Input
(note 1, 3)
V
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
4/12
74VHCT125A
Figure 5: Test Circuit
TEST
SWITCH
Open
t
t
t
, t
PLH PHL
, t
V
CC
PZL PLZ
, t
GND
PZH PHZ
C
R
R
=15/50pF or equivalent (includes jig and probe capacitance)
L
L
T
= R1 = 1KΩ or equivalent
= Z
of pulse generator (typically 50Ω)
OUT
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
5/12
74VHCT125A
Figure 7: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)
6/12
74VHCT125A
SO-14 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
MIN.
MAX.
A
A1
A2
B
1.35
1.75
0.053
0.069
0.1
1.10
0.33
0.19
8.55
3.8
0.25
1.65
0.51
0.25
8.75
4.0
0.004
0.043
0.013
0.007
0.337
0.150
0.010
0.065
0.020
0.010
0.344
0.157
C
D
E
e
1.27
0.050
H
5.8
0.25
0.4
0°
6.2
0.50
1.27
8°
0.228
0.010
0.016
0°
0.244
0.020
0.050
8°
h
L
k
ddd
0.100
0.004
0016019D
7/12
74VHCT125A
TSSOP14 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
8/12
74VHCT125A
Tape & Reel SO-14 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.6
9.2
2.3
4.1
8.1
0.882
0.260
0.362
0.090
0.161
0.319
Ao
Bo
Ko
Po
P
6.4
9
0.252
0.354
0.082
0.153
0.311
2.1
3.9
7.9
9/12
74VHCT125A
Tape & Reel TSSOP14 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.9
5.5
1.8
4.1
8.1
0.882
0.272
0.217
0.071
0.161
0.319
Ao
Bo
Ko
Po
P
6.7
5.3
1.6
3.9
7.9
0.264
0.209
0.063
0.153
0.311
10/12
74VHCT125A
Table 8: Revision History
Date
Revision
Description of Changes
Order Codes Revision - pag. 1.
16-Dec-2004
6
11/12
74VHCT125A
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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12/12
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