74VHCT257A [STMICROELECTRONICS]
QUAD 2 CHANNEL MULTIPLEXER 3-STATE; QUAD 2通道多路复用器3 -STATE
| 型号： | 74VHCT257A |
| 厂家： | 
ST |
| 描述： | QUAD 2 CHANNEL MULTIPLEXER 3-STATE |
| 文件： | 总10页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHCT257A
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
PRELIMINARY DATA
■
■
HIGH SPEED: tPD =5.8 ns (TYP.)at VCC =5V
LOWPOWER DISSIPATION:
ICC = 4 µA (MAX.)at TA =25 oC
COMPATIBLEWITH TTL OUTPUTS:
VIH = 2V (MIN), VIL =0.8V(MAX)
POWER DOWN PROTECTION ON INPUTS&
OUTPUTS
SYMMETRICALOUTPUT IMPEDANCE:
|IOH| = IOL =8 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
■
■
■
■
■
■
SOP
TSSOP
ORDER CODES
TUBE
PACKAGE
SOP
T & R
74VHCT257AM 74VHCT257AMTR
74VHCT257ATTR
TSSOP
OPERATINGVOLTAGERANGE:
VCC (OPR)= 4.5Vto 5.5V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES257
The 74VHCT257A is a non inverting multiplexer.
When the ENABLE INPUT is held ”High”, all
outputs become high impedance state. If
SELECT INPUT is held ”Low”, ”A” data is
selected, when SELECT INPUT is ”High”, ”B”
data is chosen.
■
■
IMPROVEDLATCH-UP IMMUNITY
LOWNOISE:VOLP =0.8V(Max.)
Power down protection is provided on all inputs
and output and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHCT257A is an advanced high-speed
CMOS QUAD 2 CHANNEL MULTIPLEXER
(3-STATE) fabricated with sub-micron silicon gate
and
double-layer metal
wiring
C2MOS
technology.
It is composed of four independent 2 channel
multiplexers with common SELECT and ENABLE
INPUT.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/9
March 2000
74VHCT257A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
SYMBOL NAME AND FUNCTION
SELECT Common Data Select Input
1A to 4A Data Inputs from Source A
1B to 4B Data Inputs from Source B
1Y to 4Y 3 State Multiplexer Outputs
2, 5, 14, 11
3, 6, 13, 10
4, 7, 12, 9
15
OE
3 State Output Enable
Input (Active LOW)
8
GND
VCC
Ground (0V)
16
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
L
SELECT
A
X
L
B
X
X
X
L
Y
Z
L
X
L
L
L
H
X
X
H
L
L
H
H
L
H
H
X= DON’T CARE Z = HIGHIMPEDANCE
LOGIC DIAGRAM
Thislogic diagram has notbe used to estimate propagation delays
2/9
74VHCT257A
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to VCC + 0.5
- 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage (see note 1)
DC Output Voltage (see note 2)
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
VO
V
IIK
mA
mA
mA
mA
oC
oC
IOK
20
25
±
±
IO
ICC or IGND DC VCC or Ground Current
± 50
-65 to +150
300
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
1)Outputin OFFState
2)High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to 5.5
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage (see note 1)
Output Voltage (see note 2)
Operating Temperature
0 to 5.5
V
VO
0 to VCC
-40 to +85
0 to 20
V
oC
Top
dt/dv
ns/V
Input Rise and Fall Time (see note 3) (VCC = 5.0 0.5V)
±
1)Outputin OFFState
2)High or Low State
3)VIN from0.8Vto2 V
3/9
74VHCT257A
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
VCC
(V)
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
-40 to 85 oC
VIH
VIL
High Level Input
Voltage
4.5 to 5.5
2
2
V
V
Low Level Input
Voltage
4.5 to 5.5
0.8
0.8
VOH
High Level Output
Voltage
4.5
4.5
IO=-50 µA
4.4
4.5
0.0
4.4
3.8
V
IO=-8 mA
3.94
VOL
Low Level Output
Voltage
4.5
IO=50
A
0.1
0.36
±0.25
0.1
µ
V
4.5
IO=8 mA
0.44
±2.5
IOZ
High Impedance
Output Leakage
Current
4.5 to 5.5
VI = VIH or VIL
VO = 0V to 5.5V
µA
II
Input Leakage Current
0 to 5.5
5.5
VI = 5.5V or GND
VI = VCC or GND
±0.1
±1.0
µA
µA
ICC
Quiescent Supply
Current
4
40
∆ICC
Additional Worst Case
Supply Current
5.5
0
One Input at 3.4V,
other input at VCC or
GND
1.35
0.5
1.5
5.0
mA
IOPD
Output Leakage
Current
VOUT = 5.5V
µA
AC ELECTRICAL CHARACTERISTICS
(Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Unit
VCC
CL
-40 to 85 oC
(pF)
(V)
Min. Typ. Max. Min. Max.
tPLH
tPHL
Propagation Delay
Time A, B to Y
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
15
50
15
50
15
50
5.8
8.3
7.0
9.5
6.7
9.2
8.6
9.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
11.0
14.5
13.0
16.5
12.5
16.0
13.5
ns
ns
ns
ns
12.8
11.0
14.5
10.5
14.0
12.0
tPLH
tPHL
Propagation Delay
Time SELECT to Y
tPZL
tPZH
Output Enable Time
tPLZ
tPHZ
Output Disable Time
50
(*) Voltagerangeis5V ± 0.5V
4/9
74VHCT257A
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
-40 to 85 oC
CIN
Input Capacitance
4
6
10
10
pF
pF
pF
COUT Output Capacitance
CPD
Power Dissipation
23
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operating current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/4 (per Channel)
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
VCC
(V)
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
-40 to 85 oC
VOLP Dynamic Low Voltage
5.0
0.3
0.8
Quiet Output (note 1, 2)
VOLV
-0.8
2.0
-0.3
VIHD
VILD
Dynamic High Voltage
Input (note 1, 3)
5.0
5.0
CL = 50 pF
V
Dynamic Low Voltage
Input (note 1, 3)
0.8
1)Worstcase package.
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.0V, (n -1)outputs switching andone outputatGND.
3)Max number ofdatainputs (n)switching.(n-1)switching 0Vto3.0V. Inputsunder testswitching: 3.0Vtothreshold (VILD),0V tothreshold (VIHD),f=1MHz.
TEST CIRCUIT
TEST
SWITCH
Open
VCC
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL =R1 =1KΩ orequivalent
RT = ZOUT ofpulse generator (typically50Ω)
5/9
74VHCT257A
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING CONDITIONS
(f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING CONDITIONS (f=1MHz; 50% duty
cycle)
6/9
74VHCT257A
WAVEFORM 3: OUTPUT ENABLE AND DISABLE TIME
(f=1MHz; 50% duty cycle)
7/9
74VHCT257A
SO-16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8 (max.)
P013H
8/9
74VHCT257A
TSSOP16 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
4.9
0.10
0.9
0.15
0.95
0.30
0.20
5.1
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0.004
0.354
c
D
5
6.4
0.197
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
9/9
74VHCT257A
Information furnished isbelieved to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. Thispublication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in lifesupport devices or systems withoutexpress written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan- Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
.
10/9
相关型号：
©2020 ICPDF网 联系我们和版权申明