BLUENRG-355VT [STMICROELECTRONICS]
Programmable Bluetooth® Low Energy wireless SoC;型号: | BLUENRG-355VT |
厂家: | ST |
描述: | Programmable Bluetooth® Low Energy wireless SoC |
文件: | 总72页 (文件大小:4328K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BlueNRG-LP
Datasheet
Programmable Bluetooth® Low Energy wireless SoC
Features
•
Bluetooth Low Energy system-on-chip supporting Bluetooth 5.2 specifications
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2 Mbps data rate
Long range (Coded PHY)
Advertising extensions
Channel selection algorithm #2
GATT caching
•
Radio
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RX sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps (long
range)
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–
–
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Programmable output power up to +8 dBm (at antenna connector)
Data rate supported: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps
128 physical connections
Integrated balun
Support for external PA
BlueNRG core coprocessor (DMA based) for Bluetooth Low Energy timing
critical operation
–
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2.4 GHz proprietary radio driver
Suitable for systems requiring compliance with the following radio
frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part 15,
ARIB STD-T66
•
Ultra-low power radio performance
Product status link
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10 nA in SHUTDOWN mode (1.8 V)
BlueNRG-LP
0.6 uA in DEEPSTOP mode (with external LSE and BLE wake-up sources,
1.8 V)
Product summary
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0.9 uA in DEEPSTOP mode (with internal LSI and BLE wake-up sources,
1.8 V)
Order code
BlueNRG-3x5yz
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4.3 mA peak current in TX (@ 0 dBm, 3.3 V)
3.4 mA peak current in RX (@ sensitivity level, 3.3V)
•
•
•
•
•
High performance and ultra-low power Cortex-M0+ 32-bit, running up to 64 MHz
Dynamic current consumption: 18 µA/MHz
Operating supply voltage: from 1.7 to 3.6 V
-40 ºC to 105 ºC temperature range
Supply and reset management
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High efficiency embedded SMPS step-down converter with intelligent
bypass mode
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Ultra-low power power-on-reset (POR) and power-down-reset (PDR)
Programmable voltage detector (PVD)
•
Clock sources
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–
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Fail safe 32 MHz crystal oscillator with integrated trimming capacitors
32 kHz crystal oscillator
Internal low-power 32 kHz RO
•
•
On-chip non-volatile Flash memory of 256 kB
On-chip RAM of 64 kB or 32 kB
DS13282 - Rev 2 - September 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
BlueNRG-LP
•
•
•
•
•
One-time-programmable (OTP) memory area of 1 kB
Embedded UART bootloader
Ultra-low power modes with or without timer and RAM retention
Quadrature decoder
Enhanced security mechanisms such as:
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–
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Flash read/write protection
SWD disabling
Secure bootloader
•
•
Security features
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–
–
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True random number generator (RNG)
Hardware encryption AES maximum 128-bit security co-processor
HW public key accelerator (PKA)
CRC calculation unit
48-bit unique ID
System peripherals
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1x DMA controller with 8 channels supporting ADC, SPI, I2C, USART and
LPUART
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1x SPI
2x SPI/I2S
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–
–
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2x I2C (SMBus/PMBus)
1x PDM (digital microphone interface)
1x LPUART
1x USART (ISO 7816 smartcard mode, IrDA, SPI Master and Modbus)
1x independent WDG
1x real time clock (RTC)
1x independent SysTick
1x 16-bit, 6 channel advanced timer
•
•
Up to 32 fast I/Os
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28 of them with wake-up capability
31 of them 5 V tolerant
Analog peripherals
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12-bit ADC with 8 input channels, up to 16 bits with a decimation filter
Battery monitoring
Analog watchdog
Analog Mic I/F with PGA
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Development support
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Serial wire debug (SWD)
4 breakpoints and 2 watchpoints
All packages are ECOPACK2 compliant
Applications
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Industrial
Home and industrial automation
Smart lighting
Fitness,wellness and sports
Healthcare, consumer medical
Security/proximity
Remote control
Assisted living
DS13282 - Rev 2
page 2/72
BlueNRG-LP
•
•
Mobile phone peripherals
PC peripherals
Description
The BlueNRG-LP is an ultra-low power programmable Bluetooth® Low Energy
wireless SoC solution. It embeds STMicroelectronics’s state-of-art 2.4 GHz RF radio
IPs combining unparalleled performance with extremely long-battery lifetime. It is
compliant with Bluetooth® Low Energy SIG core specification version 5.2 addressing
point-to-point connectivity and Bluetooth Mesh networking and allows large-scale
device networks to be established in a reliable way. The BlueNRG-LP is also suitable
for 2.4 GHz proprietary radio wireless communication to address ultra-low latency
applications.
The BlueNRG-LP embeds a Cortex®-M0+ microcontroller that can operate up to 64
MHz and also the BlueNRG core coprocessor (DMA based) for Bluetooth Low
Energy timing critical operations.
The main Bluetooth® Low Energy 5.2 specification supported features are:
2 Mbps data rate, long range (Coded PHY), advertising extensions, channel selection
algorithm #2, GATT caching, hardware support for simultaneous connection, master/
slave and multiple roles simultaneously, extended packet length support.
In addition, the BlueNRG-LP provides enhanced security hardware support by
dedicated hardware functions:
True random number generator (RNG), encryption AES maximum 128-bit security
co-processor, public key accelerator (PKA), CRC calculation unit, 48-bit unique ID,
Flash memory read and write protection.
The BlueNRG-LP can be configured to support standalone or network processor
applications. In the first configuration, the BlueNRG-LP operates as single device in
the application for managing both the application code and the Bluetooth Low Energy
stack.
The BlueNRG-LP embeds high-speed and flexible memory types:
Flash memory of 256 kB, RAM memory of 64 kB, one-time-programmable (OTP)
memory area of 1 kB, ROM memory of 7 kB.
Direct data transfer between memory and peripherals and from memory-to-memory
is supported by eight DMA channels with a full flexible channel mapping by the
DMAMUX peripheral.
The BlueNRG-LP embeds a 12-bit ADC, allowing measurements of up to eight
external sources and up to three internal sources, including battery monitoring and a
temperature sensor.
The BlueNRG-LP has a low-power RTC and one advanced 16-bit timer.
The BlueNRG-LP features standard and advanced communication interfaces:
1x SPI, 2x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode),
IrDA and Modbus mode, 2x I2C supporting SMBus/PMBus, 1x channel PDM.
The BlueNRG-LP operates in the -40 to +105 °C temperature range from a 1.7 V to
3.6 V power supply. A comprehensive set of power-saving modes enables the design
of low-power applications.
The BlueNRG-LP integrates a high efficiency SMPS step-down converter and an
integrated PDR circuitry with a fixed threshold that generates a device reset when the
VDD drops under 1.65 V.
The BlueNRG-LP comes in different package versions supporting up to:
32 I/Os for the QFN48 package, 20 I/Os for the QFN32 package, 30 I/Os for the
WCSP49 package.
DS13282 - Rev 2
page 3/72
BlueNRG-LP
Figure 1. The BlueNRG-LP block diagram
256 kB Flash
NVIC
SRAM0
Cortex-M0+
SRAM1
SRAM2
DMA (8 ch)
SRAM3
DMAMUX
PKA + RAM
RNG
PWRC
MR_BLE
RCC
GPIO0
GPIO1
CRC
LSE
32 kHz
LSI
32 kHz
SYSCFG
ADC
APB
HSE
I2C1
I2C2
32 MHz
RTC
SPI1
IWDG
SPI2/I2S2
RC64MPLL
USART
LPUART
TIM1
SPI3/I2S3
Power supply/POR/
PDR/PVD
DS13282 - Rev 2
page 4/72
BlueNRG-LP
Functional overview
1
Functional overview
1.1
System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
•
Three masters:
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–
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CPU (Cortex®-M0+) core S-bus
DMA1
Radio system
•
Nine slaves:
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–
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–
–
–
–
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Internal Flash memory on CPU (Cortex®-M0+) S bus
Internal SRAM0 (16 kB)
Internal SRAM1 (16 kB)
Internal SRAM2 (16 kB)
Internal SRAM3 (16 kB)
APB0 peripherals (through an AHB to APB bridge)
APB1 peripherals (through an AHB to APB bridge)
AHB0 peripherals
AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even
when several high-speed peripherals work simultaneously.
DS13282 - Rev 2
page 5/72
BlueNRG-LP
ARM Cortex–M0+ core with MPU
Figure 2. Bus matrix
1.2
ARM Cortex–M0+ core with MPU
The BlueNRG-LP contains an ARM Cortex-M0+ microcontroller core. The Cortex-M0+ was developed to provide
a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-power
consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The Cortex-M0+ can run from 1 MHz up to 64 MHz.
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage
pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but
powerful instruction set and extensively optimized design, providing high-end processing hardware including a
single-cycle multiplier.
The interrupts are handled by the Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls
specific Cortex-M0+ interrupts as well as the BlueNRG-LP peripheral interrupts. With its embedded ARM core, the
BlueNRG-LP family is compatible with all ARM tools and software.
1.3
Memories
1.3.1
Embedded Flash memory
The Flash controller implements the erase and program Flash memory operation. The flash controller also
implements the read and write protection.
The Flash memory features are:
•
Memory organization:
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1 bank of 256 kB
Page size: 2 kB
Page number 128
•
32-bit wide data read/write
DS13282 - Rev 2
page 6/72
BlueNRG-LP
Security and safety
•
Page erase and mass erase
The Flash controller features are:
•
•
•
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Flash memory read operations
Flash memory write operations: single data write or 4x32-bits burst write
Flash memory erase operations
Page write protect mechanism
1.3.2
Embedded SRAM
The BlueNRG-LP has a total of 64 kB of embedded SRAM, split into four banks as shown in the following table:
Table 1. SRAM overview
SRAM bank
SRAM0
Size
16 kB
16 kB
16 kB
16 kB
Address
Retained in DEEPSTOP
Always
0x2000 0000
0x2000 4000
0x2000 8000
0x2000 C000
SRAM1
Programmable by the user
Programmable by the user
Programmable by the user
SRAM2
SRAM3
1.3.3
1.3.4
Embedded ROM
The BlueNRG-LP has a total of 7 kB of embedded ROM. This area is ST reserved and contains:
•
•
The UART bootloader from which the CPU boots after each reset (first 6 kB of ROM memory)
Some ST reserved values including the ADC trimming values (the last 1 kB of ROM memory)
Embedded OTP
The one-time-programmable (OTP) is a memory of 1 kB dedicated for user data. The OTP data cannot be
erased.
The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a
system reset. This operation freezes the OTP memory from further unwanted write operations.
1.3.5
Memory protection unit (MPU)
The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or
resources used by any other active task. This memory area is organized into up to 8 protected areas. The
protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the
misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program
accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area settings, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
1.4
Security and safety
The BlueNRG-LP contains many security blocks for the BLE and the host application.
It includes:
•
•
•
•
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Flash read/write protections
As protection against potential hacker attacks, the SWD access can be disabled
Secure bootloader (refer to the dedicated BlueNRG-LP UART bootloader protocol application note AN5471)
Customer storage of the BLE keys
True random number generator (RNG)
DS13282 - Rev 2
page 7/72
BlueNRG-LP
RF subsystem
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Private key accelerator (PKA) including:
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Elliptic curve Diffie-Hellman (ECDH) public-private key pair calculation accelerator
Based on the Montgomery method for fast modular multiplications
Built-in Montgomery domain inward and outward transformations
◦
AMBA AHB lite slave interface with a reduced command set
Cyclic redundancy check calculation unit (CRC)
1.5
RF subsystem
The BlueNRG-LP embeds an ultra-low power radio, compliant with Bluetooth® Low Energy (BLE) specification.
The BLE features 1 Mbps and 2 Mbps transfer rates as well as long range options (125 kbps, 500 kbps), supports
multiple roles simultaneously acting at the same time as Bluetooth® Low Energy sensor and hub device.
The BLE protocol stack is implemented by an efficient system partitioned as follows:
•
•
Hardware part: BlueCore handling time critical and time consuming BLE protocol parts
Firmware part: Arm® Cortex®-M0+ core handling non time critical BLE protocol parts
1.5.1
RF front-end block diagram
The RF front-end is based on a direct modulation of the carrier in TX, and uses a low IF architecture in RX mode.
Thanks to an internal transformer with RF pins, the circuit directly interfaces the antenna (single ended
connection, impedance close to 50 Ω). The natural band pass behavior of the internal transformer simplifies
outside circuitry aimed at harmonic filtering and out of band interferer rejection.
In transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the
power amplifier. A linearized, smoothed analog control offers a clean power ramp-up.
In receive mode, the automatic gain control (AGC) can reduce the chain gain at both RF and IF locations, for
optimized interferer rejections. Thanks to the use of complex filtering and highly accurate I/Q architecture, high
sensitivity and excellent linearity can be achieved.
DS13282 - Rev 2
page 8/72
BlueNRG-LP
Power supply management
Figure 3. BlueNRG-LP RF block diagram
Timer and Power
control
AGC
control
AGC
TX_SEQUENCE
RX_SEQUENCE
RF control
ADC
G
BP
filter
LNA
Interrupt
Wakeup
BLE
modulator
ADC
G
BLE
RF1
AHB
APB
controller
BLE
demodulator
PLL
See
notes
PA
Adjust
HSE
Adjust
Max PA
level
Trimmed
bias
SMPS
LDO
LDO
LDO
VDDSD
VSSSD VLXSD
VFBSD
VDDRF
Notes: QFN42 and QFN48: VSS through exposed pad,
and VSSRF pins must be connected to ground plane CSP49: VSSRF pins must be connected to ground plane.
1.6
Power supply management
1.6.1
SMPS step-down regulator
The device integrates a step-down converter to improve low power performance when the VDD voltage is high
enough. The SMPS output voltage can be programmed from 1.2 V to 1.90 V. It is internally clocked at 4 MHz or 8
MHz.
The device can be operated without the SMPS by just wiring its output to VDD. This is the case for applications
where the voltage is low, or where the power consumption is not critical.
Except for the configuration SMPS OFF, an L/C BOM must be present on the board and connected to the VFBSD
pad.
DS13282 - Rev 2
page 9/72
BlueNRG-LP
Power supply management
Figure 4. Power supply configuration
DS13282 - Rev 2
page 10/72
BlueNRG-LP
Power supply management
1.6.2
Power supply schemes
The BlueNRG-LP embeds three power domains:
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VDD33 (VDDIO or VDD):
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the voltage range is between 1.7 V and 3.6 V
it supplies a part of the I/O ring, the embedded regulators and the system analog IPs as power
management block and embedded oscillators
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VDD12o:
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always-on digital power domain
this domain is generally supplied at 1.2 V during active phase of the device
this domain is supplied at 1.0 V during low power mode (DEEPSTOP)
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VDD12i:
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–
interruptible digital power domain
this domain is generally supplied at 1.2 V during active phase of the device
this domain is shut down during low power mode (DEEPSTOP)
Figure 5. Power supply domain overview
VDDIO
VFBSD
SMPS
MLDO
VREG PAD
CMDNO
CMDNI
VGATEP
VGATEN
LP-Reg
RFLDOs
VRF
VDD12O
VDD12I
AlwaysOn
Domain
(VDD12O)
HSI
Interruptible domain
(VDD12I)
V33 Domain
(VDDIO)
Analog
RF
CPU
RF_FSM
BLE
Peripherals
RCCi
HSE, LSI, LSE
PDR, POR, PVD
PWRC33,
BLE_wakeup,
RTC, WDOG,
PWRCo,
RCC33
RCCo
1.6.3
Linear voltage regulators
The digital power supplies are provided by different regulators:
•
The main LDO (MLDO):
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–
it provides 1.2 V from a 1.4-3.3 V input voltage
it supplies both VDD12i and VDD12o when the device is active
it is disabled during the low power mode (DEEPSTOP)
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Low power LDO (LPREG):
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it stays enabled during both active and low power phases
it provides 1.0 V voltage
it is not connected to the digital domain when the device is active
it is connected to the VDD12o domain during low power mode (DEEPSTOP)
•
A dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block
An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).
DS13282 - Rev 2
page 11/72
BlueNRG-LP
Operating modes
1.6.4
Power supply supervisor
The BlueNRG-LP device embeds several power voltage monitoring:
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•
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Power-on-reset (POR): during the power-on, the device remains in reset mode if VDDIO is below a VPOR
threshold (typically 1.65 V)
Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply voltage
(VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always enabled
Power voltage detector (PVD): can be used to monitor the VDDIO (against a programmed threshold) or an
external analog input signal. When the feature is enabled and the PVD measures a voltage below the
comparator, an interrupt is generated (if unmasked)
1.7
Operating modes
Several operating modes are defined for the BlueNRG-LP:
•
•
•
RUN mode
DEEPSTOP mode
SHUTDOWN mode
Table 2. Relationship between the low power modes and functional blocks
Mode
CPU
SHUTDOWN
OFF
DEEPSTOP
IDLE
RUN
OFF
OFF
ON
Flash
OFF
OFF
ON
ON/OFF
ON/OFF
ON ( DC-DC ON/OFF)
ON
ON
RAM
OFF
ON/OFF granularity 16 kB
ON/OFF
Radio
OFF
OFF
OFF
ON/OFF
Supply system
Register retention
HS clock
OFF
ON ( DC-DC ON/OFF)
OFF
ON
ON
ON
OFF
OFF
ON
LS clock
OFF
ON/OFF
OFF
ON
ON
Peripherals
Wake-on RTC
Wake-on GPIOs
Wake-on reset pin
OFF
ON/OFF
ON/OFF
ON/OFF
ON
ON/OFF
NA
OFF
ON/OFF
ON/OFF
ON
OFF
NA
ON
NA
1.7.1
RUN mode
In RUN mode the BlueNRG-LP is fully operational:
•
•
•
•
All interfaces are active
The internal power supplies are active
The system clock and the bus clock are running
The CPU core and the radio can be used
The power consumption may be reduced by gating the clock of the unused peripherals.
1.7.2
DEEPSTOP mode
The DEEPSTOP is the only low power mode of the BlueNRG-LP allowing the restart from a saved context
environment and the application at wake-up to go on running.
The conditions to enter the DEEPSTOP mode are:
•
•
•
•
The radio is sleeping (no radio activity)
The CPU is sleeping (WFI with SLEEPDEEP bit activated)
No unmasked wake-up sources are active
The low power mode selection (LPMS) bit of the power controller unit is 0 (default)
DS13282 - Rev 2
page 12/72
BlueNRG-LP
Reset management
In DEEPSTOP mode:
•
•
•
•
•
The system and the bus clocks are stopped
Only the essential digital power domain is ON and supplied at 1.0 V
The bank RAM0 is kept in retention
The other banks of RAM can be in retention or not, depending on the software configuration
The low speed clock can be running or stopped, depending on the software configuration:
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ON or OFF
Sourced by LSE or by LSI
•
•
•
The RTC and the IWDG stay active, if enabled and the low speed clock is ON
The radio wake-up block, including its timer, stay active (if enabled and the low speed clock is ON)
Eight I/Os (PA4/ PA5/ PA6/ PA7/ PA8/ PA9/ PA10/ PA11) can be in output driving:
–
–
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A static low or high level
The low speed clock
The RTC output
Possible wake-up sources are:
•
The radio block is able to generate two events to wake up the system through its embedded wake-up timer
running on low speed clock:
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Radio wake-up time is reached
CPU host wake-up time is reached
•
•
•
The RTC can generate a wake-up event
The IWDG can generate a reset event
Up to 28 GPIOs are able to wake up the system (PA0 to PA15 and PB0 to PB11)
At the wake-up, all the hardware resources located in the digital power domain that are OFF during the
DEEPSTOP mode, are reset. The CPU reboots. The wake-up reason is visible in the register of the power
controller.
1.7.3
SHUTDOWN mode
The SHUTDOWN mode is the least power consuming mode.
The conditions to enter SHUTDOWN mode are the same conditions needed to enter DEEPSTOP mode except
that the LPMS bit of the power controller unit is 1.
In SHUTDOWN mode, the BlueNRG-LP is in ultra-low power consumption: all voltage regulators, clocks and the
RF interface are not powered. The BlueNRG-LP can enter shutdown mode by internal software sequence. The
only way to exit shutdown mode is by asserting and deasserting the RSTN pin.
In SHUTDOWN mode:
•
•
•
•
The system is powered down as both the regulators are OFF
The VDDIO power domain is ON
All the clocks are OFF, LSI and LSE are OFF
The I/Os pull-up and pull-down can be controlled during SHUTDOWN mode, depending on the software
configuration
•
The only wake-up source is a low pulse on the RSTN pin
The exit from SHUTDOWN is similar to a POR startup. The PDR feature can be enabled or disabled during
SHUTDOWN.
1.8
Reset management
The BlueNRG-LP offers two different resets:
•
The PORESETn: this reset is provided by the low power management unit (LPMU) analog block and
corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset
impacts all resources of the BlueNRG-LP. The exit from SHUTDOWN mode is equivalent to a POR and thus
generates a PORESETn. The PORESETn signal is active when the power supply of the device is below a
threshold value or when the regulator does not provide the target voltage.
DS13282 - Rev 2
page 13/72
BlueNRG-LP
Clock management
•
The PADRESETn (system reset): this reset is built through several sources:
–
–
PORESETn
Reset due to the watchdog
The BlueNRG-LP device embeds a watchdog timer, which may be used to recover from software
crashes
–
–
Reset due to CPU Lockup
The Cortex-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an
unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex-M0+
Software system reset
The system reset request is generated by the debug circuitry of the Cortex®-M0+. The debugger sets
the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system
reset request through the AIRCR can also be done by the embedded software (into the hardfault
handler for instance)
–
Reset from the RSTN external pin
The RSTN pin toggles to inform that a reset has occurred
This PADRESETn resets all resources of the BlueNRG-LP, except:
Debug features
•
•
•
•
•
Flash controller key management
RTC timer
Power controller unit
Part of the RCC registers
The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case
of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.
1.9
Clock management
Three different clock sources may be used to drive the system clock of the BlueNRG-LP:
•
•
•
HSI: high speed internal 64 MHz RC oscillator
PLL64M: 64 MHz PLL clock
HSE: high speed 32 MHz external crystal
The BlueNRG-LP has also a low speed clock tree used by some timers in the radio, RTC and IWDG.
Four different clock sources can be used for this low speed clock tree:
•
Low speed internal (LSI): low speed and low drift internal RC with a fixed frequency between 24 kHz and 49
kHz depending on the sample
•
Low speed external (LSE) from:
–
–
An external crystal 32.768 kHz
A single-ended 32.738 kHz input signal
•
•
A 32 kHz clock (CLK_16 MHz/512 in Figure 6. Clock tree) obtained by dividing HSI or HSE. In this case, the
slow clock is not available in DEEPSTOP low power mode
LSI_LPMU: 32 kHz clock used by the low power management unit (LPMU) analog block.
By default, after a system reset, all low speed sources are OFF.
Both the activation and the selection of the slow clock are relevant during the DEEPSTOP mode and at wakeup
as slow clock generates a clock for the timers involved in wake-up event generation.
The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock
output by this block can be:
•
•
A non-accurate clock when no external XO provides an input clock to this block (HSI)
An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)
This fast clock source is used to generate all the fast clock of the device through dividers. After reset, the
CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories and peripherals).
This fast clock source is also used to generate several internal fast clocks in the system:
•
Always 32 MHz requested by a few peripherals like the radio
DS13282 - Rev 2
page 14/72
BlueNRG-LP
Clock management
•
Always 16 MHz requested by a few peripherals like serial interfaces (to maintain fixed the baud rate while
system clock is switching from one frequency to another) or like the Flash controller and radio (to have a
fixed reference clock to manage delays)
Figure 6. Clock tree
LSI RCO
32kHz
LSI_LPMU
RCO 32kHz
CLKSLOWSEL
LCOSEL
LCO
CK_RTC,
CK_WDG,
CK_BLEWKUP
CLK_16MHz/512
OSC32k_OUT
OSC32k_IN
CLK_TIM1
LSE OSC
32kHz
SYSCLKDIV
SYSCLK PRE
/1, /2, .. , /32
CLK_SYS
to CPU,
AHB0,
APB0,
APB1,
SRAM,
PKA,
CLK_SPI1
OSC_OUT
OSC_IN
HSE OSC
32MHz
1
0
1
0
SYSCLK PRE
/1, /2, .. , /64
HSESEL
HSI
RCO+PLL
64MHz
HSESEL
SYSCLKDIV
/4
/2
1
0
CLKANA_ADC
CLK_SMPS
CLK_SMPS
CLK_SYS
HSE
CLKANA_ADC,
CLK_USART,
CLK_I2C,
CLK_BLE16,
CLK_FLASH,
CLK_PWR,
SMPSDIV
/2
/4
1
0
CLK_16MHz
/1, /2, .. , /16
MCO
CLK_RNG
CLK_LPUART
HSI
1
0
HSESEL
CLKSYS_BLE
CLK_16MHz/512
MCOSEL
BLECLKDIV
1
0
CLK_32MHz
CLK_BLE32,
CLKDIG_ADC
/2
1
0
HSESEL
CLK_SPI2/I2S2
CLK_16MHz
SP2CKSEL
1
0
CLK_SPI3/I2S3
SP3CKSEL
It is possible to output some internal clocks on external pads:
•
•
the low speed clocks can be output on the LCO I/O
the high speed clocks can be output on the MCO I/O
This is possible by programming the associated I/O in the correct alternate function.
Most of the peripherals only use the system clock except:
•
I2C, USART, LPUART: they always use a16 MHz clock to have a fixed reference clock for baud rate
management. The goal is to allow the CPU to boost or slow down the system clock (depending on on-going
activities) without impacting a potential on-going serial interface transfer on external I/Os
DS13282 - Rev 2
page 15/72
BlueNRG-LP
Boot mode
•
SPI: when the I2S mode is used, the baud rate is always managed through the 16 MHz or 32 MHz clock.
When modes other than the I2S run, the baud rate is managed by the system clock. This implies its baud
rate is impacted by dynamic system clock frequency changes
•
•
RNG: in parallel to the system clock, the RNG always uses 16 MHz clock to generate at a constant
frequency the random number whatever the system clock frequency
Flash controller: in parallel to the system clock, the Flash controller always uses 16 MHz clock to generate
specific delays required by the Flash memory during programming and erase operations for example
•
•
PKA: in parallel to the system clock, the PKA uses a clock at half of the system clock frequency
Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a
potential divider (1 or 2 or 4). In parallel, the radio always uses 16 MHz and always 32 MHz for modulator,
demodulator and to have a fixed reference clock to manage specific delays
•
ADC: in parallel to the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz
1.10
1.11
Boot mode
Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This
modification is performed by programming the REMAP bit in the Flash controller.
The following memory can be remapped:
•
•
Main Flash memory
SRAM0 memory
Embedded UART bootloader
The BlueNRG-LP has a pre-programmed bootloader supporting UART protocol with automatic baud rate
detection. The main features of the embedded bootloader are:
•
•
•
•
Auto baud rate detection up to 1 Mbps
Flash mass erase, section erase
Flash programming
Flash readout protection enable/disable
The pre-programmed bootloader is an application, which is stored in the BlueNRG-LP internal ROM at
manufacturing time by STMicroelectronics. This application allows upgrading the device Flash with a user
application using a serial communication channel (UART).
Bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application residing in
Flash is launched.
Note:
Bootloader protocol is described in a separate application note (the BlueNRG-LP UART bootloader protocol,
AN5471)
1.12
General purpose inputs/outputs (GPIO)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without
pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
1.13
Direct memory access (DMA)
The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as
memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources
are free for other operations.
The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests.
DMA main features are:
•
•
Eight independently configurable channels (requests)
Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also
supported on each channel. This configuration is done by software
DS13282 - Rev 2
page 16/72
BlueNRG-LP
Nested vectored interrupt controller (NVIC)
•
•
Priorities among requests from channels of DMA are software programmable (four levels consisting of very
high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)
Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking.
Source/destination addresses must be aligned on the data size
•
•
Support for circular buffer management
Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed
together in a single interrupt request for each channel
•
•
•
•
Memory-to-memory transfer (RAM only)
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
Access to SRAMs and APB1 peripherals as source and destination
Programmable number of data to be transferred: up to 65536
1.14
Nested vectored interrupt controller (NVIC)
The interrupts are handled by the Cortex®-M0+ nested vector interrupt controller (NVIC). NVIC controls specific
Cortex®-M0+ interrupts as well as the BlueNRG-LP peripheral interrupts.
The NVIC benefits are the following:
•
•
•
•
•
•
•
•
Nested vectored interrupt controller that is an integral part of the ARM® Cortex®-M0+
Tightly coupled interrupt controller provides low interrupt latency
Control system exceptions and peripheral interrupts
NVIC supports 32 vectored interrupts
Four programmable interrupt priority levels with hardware priority level masking
Software interrupt generation using the ARM® exceptions SVCall and PendSV
Support for NMI
ARM® Cortex® M0+ vector table offset register VTOR implemented
NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.
1.15
Analog digital converter (ADC)
The BlueNRG-LP embeds a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-to-digital
converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources and up to
two internal sources.
It embeds a PDM interface integrating a digital filter for processing PDM stream coming from a digital microphone.
It also embeds a dedicated ECM microphone feature with which it is possible to connect an analog microphone
directly to the ADC port of the BlueNRG-LP.
The ADC main features are:
•
•
•
•
Conversion frequency is up to 1 Msps
Three input voltage ranges are supported (0 - 1.2 V, 0 - 2.4 V, 0 - 3.6 V)
Up to eight analog single-ended channels or four analog differential inputs or a mix of both
One analog microphone supported through two GPIOs configured in analog mode (an input for the analog
microphone and a Vbias output for the analog microphone)
•
•
•
•
Temperature sensor conversion
Battery level conversion up to 3.6 V
Continuous or single acquisition
Digital decimation filter to process a digital audio PDM stream provided by 2 GPIOs and for ADC post-
processing, especially for analog audio stream
•
Five modes of conversion are possible:
–
–
–
–
–
ADC continuous or single mode
Analog continuous audio mode
Occasional conversions
Digital continuous audio mode
Full mode
DS13282 - Rev 2
page 17/72
BlueNRG-LP
True random number generator (RNG)
•
•
ADC down-sampler for multi-purpose applications to improve analog performance while off-loading the CPU
(ratio adjustable from 1 to 128)
A watchdog feature to inform when data is outside thresholds (available for all modes except the digital
audio mode)
•
•
DMA capability
Interrupt sources with flags
1.15.1
Digital microphone MEMS interface
The digital microphone MEMS interface aims to interconnect with an external digital MEMS microphone. The
BlueNRG-LP can configure two GPIOs as PDM interface. The PDM_CLK provides the clock output signal,
programmable in frequency, to the microphone, while the PDM_DATA receives the PDM output data from the
microphone. The decimation filter and the digital control resources are used to handle the PDM data stream.
1.15.2
1.15.3
Analog microphone interface
The analog microphone interface is dedicated to the analog microphone signal. The input audio signal is amplified
with a programmable gain amplifier (PGA) from 0 dB to 30 dB, then the data stream is sampled by ADC and
processed through the decimation filter.
Temperature sensor
The temperature sensor (TS) generates a voltage that varies linearly with temperature. The temperature sensor is
internally connected to the ADC input channel, which is used to convert the sensor output voltage into a digital
value.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by
ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in
read-only mode.
1.16
True random number generator (RNG)
RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the host
when read. The minimum period is 1.25 us, corresponding to 20 RNG clock cycles between two consecutive
random number.
1.17
Timers and watchdog
The BlueNRG-LP includes one advanced 16-bit timer, one watchdog timer and a SysTick timer.
1.17.1
Advanced control timer (TIM1)
The advanced-control timer can be considered as a three-phase PWM multiplexed on six channels. The six
channels have complementary PWM outputs with programmable inserted dead-times.
They can also be used as general-purpose timers for:
•
•
•
•
Input capture (except channels 5 and 6)
Output compare
PWM generation (edge and center-aligned mode)
One-pulse mode output
1.17.2
1.17.3
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from the LS clock
and it can operate in DEEPSTOP mode. It can also be used as a watchdog to reset the device when a problem
occurs.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It
features:
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
DS13282 - Rev 2
page 18/72
BlueNRG-LP
Real-time clock (RTC)
1.18
Real-time clock (RTC)
The RTC is an independent BCD timer/counter. The RTC provides a time of day/clock/calendar with
programmable alarm interrupt. RTC includes also a periodic programmable wake-up flag with interrupt capability.
The RTC provides an automatic wake-up to manage all low power modes.
Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of
month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also
available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the
programmable alarm sub seconds, seconds, minutes, hours, day, and date.
A digital calibration circuit with 0.95 ppm resolution is available to compensate for quartz crystal inaccuracy. After
power-on reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply
voltage remains in the operating range, the RTC never stops, regardless of the device status (RUN mode, low
power mode or under system reset). The RTC counter does not freeze when CPU is halted by a debugger.
2
1.19
Inter-integrated circuit interface (I C)
The BlueNRG-LP embeds two I2Cs. The I2C bus interface handles communications between the microcontroller
and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C bus specification and user manual rev. 5 compatibilities:
–
–
–
–
–
–
–
–
–
–
–
–
–
Slave and master modes
Multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (fm+), with a bitrate up to 1 Mbit/s and 20 mA output driver I/Os
7-bit and 10-bit addressing mode
Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
All 7-bit address acknowledge mode
General call
Programmable setup and hold times
Easy to use event management
Optional clock stretching
Software reset
•
System management Bus (SMBus) specification rev 2.0 compatibility:
–
–
–
–
–
Hardware PEC (Packet Error Checking) generation and verification with ACK control
Address resolution protocol (ARP) support
Host and device support
SMBus alert
Timeouts and idle condition detection
•
•
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent from the PCLK reprogramming
•
•
Programmable analog and digital noise filters
1-byte buffer with DMA capability
1.20
Universal synchronous/asynchronous receiver transmitter (USART)
USART offers flexible full-duplex data exchange with external equipment requiring an industry standard NRZ
asynchronous serial data format. USART is able to communicate with a speed up to 2 Mbit/s. Furthermore,
USART is able to detect and automatically set its own baud rate, based on the reception of a single character.
The USART peripheral supports:
•
Synchronous one-way communication
DS13282 - Rev 2
page 19/72
BlueNRG-LP
LPUART
•
•
•
•
•
•
•
•
Half-duplex single wire communication
Local interconnection network (LIN) master/slave capability
Smart card mode, ISO 7816 compliant protocol
IrDA (infrared data association) SIR ENDEC specifications
Modem operations (CTS/RTS)
RS485 driver enable
Multiprocessor communications
SPI-like communication capability
High speed data communication is possible by using DMA (direct memory access) for multibuffer configuration.
1.21
1.22
LPUART
LPUART is a UART which allows bidirectional UART communications. It supports half-duplex single wire
communications and modem operations (CTS/RTS). It also supports multiprocessor communications. DMA (direct
memory access) can be used for data transmission/reception.
Serial peripheral interface (SPI)
The BlueNRG-LP has three SPI interfaces (SPI1, SPI2, SPI3) allowing communication up to 32 Mbit/s in both
master and slave modes. The SPI peripheral supports:
•
•
•
•
•
•
•
Master or slave operation
Multimaster support
Full-duplex synchronous transfers on three lines
Half-duplex synchronous transfer on two lines (with bidirectional data line)
Simplex synchronous transfers on two lines (with unidirectional data line)
Serial communication with external devices
NSS management by hardware or software for both master and slave: dynamic change of master/slave
operations
•
•
•
SPI Motorola support
SPI TI mode support
Hardware CRC feature for reliable communication
All SPI interfaces can be served by the DMA controller.
1.23
Inter-IC sound (I2S)
The BlueNRG-LP SPI interfaces: SPI2 and SPI3 support the I2S protocol. The I2S interface can operate in slave
or master mode with full duplex and half-duplex communication. It can address four different audio standards:
•
•
•
•
Philips I2S standard
MSB-justified standards (left-justified)
LSB-justified standards (right-justified)
PCM standard.
The I2S interfaces DMA capability for transmission and reception.
1.24
1.25
Serial wire debug port
The BlueNRG-LP embeds an ARM SWD interface that allows interactive debugging and programming of the
device. The interface is composed of only two pins: SWDIO and SWCLK. The enhanced debugging features for
developers allow up to 4 breakpoints and up to 2 watchpoints.
TX and RX event alert
The BlueNRG-LP is provided with the TX_SEQUENCE and RX_SEQUENCE signals which alert, respectively,
transmission and reception activities.
A signal can be enabled for TX and RX on two pins, through alternate functions:
DS13282 - Rev 2
page 20/72
BlueNRG-LP
TX and RX event alert
•
•
TX_SEQUENCE is available on PA10 (AF2) or PB15 (AF1).
RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2).
The signal is high when radio is in TX (or RX), low otherwise.
The signals can be used to control external antenna switching and support coexistence with other wireless
technologies.
DS13282 - Rev 2
page 21/72
BlueNRG-LP
Pinouts and pin description
2
Pinouts and pin description
The BlueNRG-LP comes in three package versions: QFN48 offering 32 GPIOs, WCSP49 offering 30 GPIOs and
QFN32 offering 20 GPIOs.
Figure 7. Pinout top view (QFN48 package)
PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 VDDA VDD1 RSTN VDD3
48
47
46
45
44
43
42
41
40
39
38
37
PB3
PB2
VDDSD
VLXSD
VSS
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PB1
3
PB0
NC
4
PA15
PA14
PA13
PA12
PA11
PA10
PA9
VFBSD
VCAP
5
6
GND
pad
PB12/XTAL0
PB13/XTAL1
PB14
7
8
9
PB15
10
11
12
VDD4
PA8
OSCIN
13
14
15
16
17
18
19
20
21
22
23
24
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VDD2
DS13282 - Rev 2
page 22/72
BlueNRG-LP
Pinouts and pin description
Figure 8. Pinout top view (QFN32 package)
VDD1 PB4 PB5 PB6 PB7 VCAP RSTN VDDSD
32
31
30
29
28
27
26
25
PB3
PB2
PB1
PB0
PA11
PA10
PA9
VLXSD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VFBSD
PB12/XTAL0
PB13/XTAL1
PB14
GND
pad
PB15
PA8
OSCIN
9
10
11
12
13
14
15
16
PA0 PA1 PA2 PA3
VDD2
DS13282 - Rev 2
page 23/72
BlueNRG-LP
Pinouts and pin description
Figure 9. Pinout top view (WLCSP49 package)
1
2
3
4
5
6
7
5
A
B
VDDSD VLXSD
VSSIO
VDD3
RSTN
VDDA
VSSA
VSSSD
PB7
PB6
PB5
PB4
PB3
PB2
C
D
E
VFBSD
VCAP
PB12
PB13
PB9
PA11
PA4
PB1
PB8
PA3
PB0
PA13
PA2
PA15
PA12
PA10
PA14
PA9
PA8
OSCOUT PB14
VSS
IFADC
F
OSCIN
PB15
VSSRF
PA5
PA7
PA0
PA1
VSSIO
VDD2
VSSRFT
RX
G
VSSSX VDDRF
RF1
Table 3. Pin description
Pin number
Pin name
(function
after reset)
Pin
type
I/O
structure
Alternate functions
Additional functions
QFN48
QFN32 WLCSP49
USART_CTS,
LPUART_TX, TIM1_CH4
1
1
2
3
B6
B7
C4
PB3
I/O
I/O
I/O
FT_a
FT_a
FT_a
ADC_VINP0, wakeup
USART_RTS_DE,
PDM_DATA, TIM1_CH3
2
3
PB2
PB1
ADC_VINM0, wakeup
ADC_VINP1, wakeup
SPI1_NSS, PDM_CLK,
TIM1_ETR
USART_RX,
LPUART_RTS_DE,
TIM1_CH2N
4
4
C5
PB0
I/O
FT_a
ADC_VINM1, wakeup
I2C2_SMBA, SPI1_MOSI,
TIM1_BKIN2
5
6
-
-
C6
C7
PA15
PA14
I/O
I/O
FT_a
FT_a
ADC_VINP2, wakeup
ADC_VINM2, wakeup
I2C2_SDA, SPI1_MISO,
TIM1_BKIN
I2C2_SCL, SPI1_SCK,
SPI2_MISO, TIM1_ETR,
I2S2_MISO
7
8
-
-
D5
D6
PA13
PA12
I/O
I/O
FT_a
FT_a
ADC_VINP3, wakeup
ADC_VINM3, wakeup
I2C1_SMBA, SPI1_NSS,
SPI2_MOSI,TIM1_CH1,
I2S2_SD
DS13282 - Rev 2
page 24/72
BlueNRG-LP
Pinouts and pin description
Pin number
Pin name
(function
after reset)
Pin
type
I/O
structure
Alternate functions
Additional functions
QFN48
QFN32 WLCSP49
MCO, SPI1_NSS,
RX_SEQUENCE,
SPI3_MOSI, TIM1_CH6,
I2S3_SD
Wakeup, GPIO in
DEEPSTOP, RTC_OUT
9
5
D3
PA11
I/O
FT
LCO, SPI1_MISO,
TX_SEQUENCE,
SPI3_MCK, TIM1_CH5,
I2S3_MCK
BOOT, wakeup, GPIO
in DEEPSTOP, LCO
10
11
12
6
7
8
E6
D7
E7
PA10
PA9
I/O
I/O
I/O
FT
FT
FT
USART_TX, SPI1_SCK,
RTC_OUT, SPI3_NSS,
TIM1_CH4, I2S3_WS
Wakeup, GPIO in
DEEPSTOP, LCO
USART_RX, SPI1_MOSI,
RX_SEQUENCE,
SPI3_MISO, TIM1_CH3,
I2S3_MISO
Wakeup, GPIO in
DEEPSTOP, RTC_OUT
PA8
I2C1_SCL, USART_CTS,
SPI2_MCK, TIM1_CH3,
I2S2_MCK
13
14
15
16
17
18
9
10
11
12
-
F6
G6
E5
E4
E3
F5
PA0
PA1
PA2
PA3
PA4
PA5
I/O
I/O
I/O
I/O
I/O
I/O
FT_f
FT_f
FT
Wakeup
Wakeup
Wakeup
Wakeup
I2C1_SDA, SPI2_MISO,
USART_TX, TIM1_CH4,
I2S2_MISO
SWDIO, USART_CK,
TIM_BKIN, SPI3_MCK,
TIM1_CH5, I2S3_MCK
SWCLK, USART_RTS_DE,
TIM_BKIN2, SPI3_SCK,
TIM1_CH6, I2S3_SCK
FT
LCO, SPI2_NSS,
LPUART_TX, TIM1_CH1,
I2S2_WS
Wakeup, GPIO in
DEEPSTOP, LCO
FT
MCO, SPI2_SCK,
LPUART_RX, TIM1_CH2,
I2S2_SCK
Wakeup, GPIO in
DEEPSTOP, LCO
-
FT
LPUART_CTS,
SPI2_MOSI, SPI2_NSS,
TIM1_CH1, I2S2_SD,
I2S2_WS
Wakeup, GPIO in
DEEPSTOP, LCO
19
20
-
-
-
PA6
PA7
I/O
I/O
FT
FT
LPUART_RTS_DE,
SPI2_MISO, SPI2_SCK,
TIM1_CH2, I2S2_MISO,
I2S2_SCK
Wakeup, GPIO in
DEEPSTOP, RTC_OUT
G5
1.7-3.6 battery voltage
input
21
22
23
13
14
15
G7
G4
G2
VDD2
RF1
S
I/O
S
-
RF
-
--
-
RF input/output.
Impedance 50 Ω
1.7-3.6 battery voltage
input
VDDRF
-
24
25
16
17
E1
F1
OSCOUT
OSCIN
I/O
I/O
RF
RF
-
-
32 MHz crystal
32 MHz crystal
1.7-3.6 battery voltage
input
26
-
-
VDD4
S
-
-
DS13282 - Rev 2
page 25/72
BlueNRG-LP
Pinouts and pin description
Pin number
Pin name
(function
after reset)
Pin
type
I/O
structure
Alternate functions
Additional functions
QFN48
QFN32 WLCSP49
I2C1_SMBA,
TX_SEQUENCE, MCO,
TIM1_CH4N, TIM1_CH6,
USART_TX
27
18
F2
PB15
I/O
FT
-
SPI1_MOSI, I2C2_SDA,
TIM1_ETR, TIM1_CH3N,
TIM1_CH5, USART_RX
28
29
30
19
20
21
E2
D2
C2
PB14
PB13
PB12
I/O
I/O
I/O
FT_a
FT
VIN_PVD
SXTAL1
SXTAL0
SPI1_MISO, I2C2_SCL,
PDM_CLK, TIM1_BKIN2,
TIM1_CH4
SPI1_SCK, LCO,
PDM_DATA, TIM1_BKIN,
TIM1_CH3
FT
31
32
33
34
35
27
22
D1
C1
VCAP
VFBSD
NC
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
1.2 Vdigital core
SMPS output
-
23
24
B1
A2
VSSSD
VLXSD
SMPS Ground
SMPS input/output
1.7-3.6 battery voltage
input
36
25
A1
VDDSD
S
-
-
1.7-3.6 battery voltage
input
37
38
39
40
-
A4
A5
-
VDD3
RSTN
VDD1
VDDA
S
I/O
S
-
-
-
-
-
26
32
-
RST
Reset pin
1.7-3.6 battery voltage
input
-
-
A6
S
1.2 V analog ADC core
SPI1_SCK, SPI2_NSS,
I2C1_SCL, TIM1_CH1,
TIM1_CH4N, I2S2_WS
41
42
-
-
-
-
PB11
PB10
I/O
I/O
FT
FT
Wakeup
SPI1_NSS, SPI2_SCK,
I2C1_SDA, TIM1_CH2,
TIM1_CH3N, I2S2_SCK
Wakeup
Wakeup
USART_TX,
LPUART_CTS, SPI2_MCK,
TIM1_CH1N, TIM1_CH2N,
I2S2_MCK
43
-
C3
PB9
I/O
FT
USART_CK, LPUART_RX,
TIM1_CH4, TIM1_CH1N
44
45
-
D4
B2
PB8
PB7
I/O
I/O
FT
Wakeup
Wakeup
I2C2_SDA, SPI2_SCK,
LPUART_RX, TIM1_CH2,
I2S2_SCK
28
FT_f
I2C2_SCL, SPI2_NSS,
LPUART_TX, TIM1_CH1,
I2S2_WS
46
29
B3
PB6
I/O
FT_f
Wakeup
PGA_VBIAS_MIC(1)
wakeup
,
LPUART_RX, SPI2_MOSI,
PDM_CLK, I2S2_SD
47
48
-
30
31
-
B4
B5
A7
PB5
PB4
I/O
I/O
S
TT
FT
-
LPUART_TX, SPI2_MISO,
PDM_DATA, I2S2_MISO
PGA_VIN, wakeup
Ground analog ADC
core
VSSA
-
DS13282 - Rev 2
page 26/72
BlueNRG-LP
Pinouts and pin description
Pin number
Pin name
(function
after reset)
Pin
type
I/O
structure
Alternate functions
Additional functions
QFN48
QFN32 WLCSP49
-
-
-
-
-
-
-
-
-
-
-
-
A3
F7
F4
G1
G3
F3
VSSIO
VSSIO
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
Ground I/O
Ground I/O
VSSIFADC
VSSSX
Ground analog RF
Ground analog RF
Ground analog RF
Ground analog RF
VSSRFTRX
VSSRF
Exposed Exposed
pad pad
-
GND
S
-
-
Ground
1. This pin is not 5 V tolerant.
Table 4. Legend/abbreviations used in the pinout table
Abbreviation
Name
Definition
Unless otherwise specified in brackets below, the pin name and the pin function during
and after reset are the same as the actual pin name
Pin name
S
Supply pin
Pin type
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TT
3.6 V tolerant I/O
RF
RST
RF I/O
Bidirectional reset pin with weak pull-up resistor
I/O structure
Options for TT or FT I/Os
_f(1)
.
I/O, Fm+ capable
I/O, with analog switch function supplied by IO
BOOSTER(3)
_a(2)
.
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
reset
Notes
Alternate functions Functions selected through GPIOx_AFR registers
Pin functions
Additional functions Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 3. Pin description are: FT_f
2. The related I/O structures in Table 3. Pin description are: FT_a
3. IO BOOSTER block allows the good behavior of those switches to be guaranteed when the VBAT goes below 2.7 V. Refer
to the BlueNRG-LP reference Manual (RM0479) for more details.
Table 5. Alternate function port A
AF0
AF1
AF2
AF3
AF4
AF5
AF6
-
AF7
SPI1/
SPI2/RTC
USART/
I2C1/I2C2/
SYS_AF
LPUART/ USART
SPI1/SPI2/
SYS_AF/
USART/I2S2
SPI2/ SPI3
LPUART/
I2S2/ I2S3
Port
TIM1
SYS_AF
SYS_AF
TIM/ I2S2
SPI2_MCK/
I2S2_MCK
Port
A
PA0
I2C1_SCL
USART_CTS
-
TIM1_CH3
-
-
-
DS13282 - Rev 2
page 27/72
BlueNRG-LP
Pinouts and pin description
AF0
AF1
AF2
AF3
AF4
AF5
AF6
-
AF7
SPI1/
SPI2/RTC
USART/
I2C1/I2C2/
SYS_AF
LPUART/ USART
SPI1/SPI2/
SYS_AF/
USART/I2S2
SPI2/ SPI3
LPUART/
I2S2/ I2S3
Port
TIM1
SYS_AF
SYS_AF
TIM/ I2S2
SPI2_MISO/
I2S2_MISO
PA1
I2C1_SDA
TMS_SWDIO
TCK_SWCLK
LCO
USART_TX
-
TIM1_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI3_MCK/
I2S3_MCK
PA2
PA3
PA4
PA5
PA6
USART_CK
TIM_BKIN
TIM1_CH5 TMS_SWDIO
TIM1_CH6 TCK_SWCLK
TMS_SWDIO
SPI3_SCK/
I2S3_SCK
USART_RTS_DE TIM_BKIN2
TCK_SWCLK
SPI2_NSS/
-
LPUART_TX TIM1_CH1
LPUART_RX TIM1_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2S2_WS
SPI2_SCK/
-
MCO
I2S2_SCK
SPI2_MOSI/
I2S2_SD
SPI2_NSS/
TIM1_CH1
I2S2_WS
LPUART_CTS
-
SPI2_MISO/
-
SPI2_SCK/
TIM1_CH2
I2S2_SCK
PA7 LPUART_RTS_DE
I2S2_MISO
Port
A
SPI3_MISO/
TIM1_CH3
I2S3_MISO
PA8
PA9
USART_RX
USART_TX
LCO
SPI1_MOSI
SPI1_SCK
-
SPI3_NSS/
TIM1_CH4
I2S3_WS
RTC_OUT
SPI3_MCK/
TIM1_CH5
I2S3_MCK
PA10
PA11
PA12
PA13
SPI1_MISO
SPI1_NSS
-
SPI3_MOSI/
TIM1_CH6
I2S3_SD
MCO
-
SPI2_MOSI/
TIM1_CH1
I2S2_SD
I2C1_SMBA
I2C2_SCL
TMS_SWDIO
TCK_SWCLK
SPI1_NSS
SPI1_SCK
SPI2_MISO/
TIM1_ETR
I2S2_MISO
PA14
PA15
I2C2_SDA
-
-
SPI1_MISO
SPI1_MOSI
TIM1_BKIN
-
-
-
-
-
-
I2C2_SMBA
-
TIM1_BKIN2
DS13282 - Rev 2
page 28/72
BlueNRG-LP
Pinouts and pin description
Table 6. Alternate function port B
AF0
AF1
AF2
AF3
AF4
AF5 AF6
AF7
SPI2/
I2C1/PDM
TIM1/
SYS_AF/
I2S2
Port
SPI1/I2C2
USART/LPUART LPUART/SPI2/I2S2
PDM/SYS_AF/I2C2
TIM1/PDM
LPUART
TIM1
-
-
USART
PB0
PB1
USART_RX
SPI1_NSS
LPUART_RTS_DE
PDM_CLK
-
-
-
-
TIM1_CH2N
TIM1_ETR
TIM1_CH3
TIM1_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PB2 USART_RTS_DE
PDM_DATA
PB3
PB4
USART_CTS
LPUART_TX
LPUART_TX
SPI2_MISO/
I2S2_MISO
-
-
-
PDM_DATA
PDM_CLK
-
-
-
-
-
-
-
-
-
-
-
SPI2_MOSI/
I2S2_SD
PB5
PB6
LPUART_RX
I2C2_SCL
SPI2_NSS/
I2S2_WS
LPUART_TX TIM1_CH1
SPI2_SCK/
IS2S_SCK
PB7
PB8
PB9
I2C2_SDA
USART_CK
USART_TX
-
-
LPUART_RX TIM1_CH2
TIM1_CH4 TIM1_CH1N
TIM1_CH1N TIM1_CH2N
-
-
-
-
-
-
-
-
-
Port
B
LPUART_RX
SPI2_MCK/
I2S2_MCK
LPUART_CTS
SPI2_SCK/
I2S2_SCKK
PB10
PB11
SPI1_NSS
SPI1_SCK
I2C1_SDA
I2C1_SCL
TIM1_CH2 TIM1_CH3N
TIM1_CH1 TIM1_CH4N
-
-
-
-
-
-
SPI2_NSS/
I2S2_WS
PB12
PB13
PB14
PB15
SPI1_SCK
SPI1_MISO
SPI1_MOSI
I2C1_SMBA
LCO
PDM_DATA
PDM_CLK
TIM1_ETR
MCO
TIM1_BKIN
TIM1_CH3
-
-
-
-
-
-
-
-
-
I2C2_SCL
TIM1_BKIN2 TIM1_CH4
TIM1_CH3N TIM1_CH5
TIM1_CH4N TIM1_CH6
-
I2C2_SDA
USART_RX
USART_TX
TX_SEQUENCE
DS13282 - Rev 2
page 29/72
BlueNRG-LP
Memory mapping
3
Memory mapping
Program memory, data memory and registers are organized within the same linear 4-Gbyte address space. The
detailed memory map and the peripheral mapping of the BlueNRG-LP can be found in the reference manual
(RM0479).
Figure 10. Memory map
0xFFFF FFFF
Reserved
0x8FFF FFFF
Reserved
0x6002 0000
0xE00F FFFF
CortexTM M0+
Internal
APB2 (RF)
0x6000 0000
Reserved
Peripherals
0xE000 0000
AHB0
0x4800 0000
Reserved
0x4100 2000
Reserved
APB1
0x4100 0000
Reserved
0x4002 0000
APB0
0x8FFF FFFF
0x4000 0000
0x2FFF FFFF
Reserved
0x2000 FFFF
SRAM3 (16 kB)
Peripherals
0x2000 C000
0x2000 8000
SRAM2 (16 kB)
SRAM1 (16 kB)
SRAM0 (16 kB)
0x2000 4000
0x2000 0000
0x4000 0000
Reserved
0x2FFF FFFF
0x2000 0000
Reserved
0x1007 FFFF
0x1004 0000
SRAM
Main FLASH (256 kB)
Reserved
0x1007 FFFF
0x0000 0000
Reserved
Reserved
0x1000 0000
0x0000 3FFF
CODE
CortexTM M0+
Flash or SRAM0,
depending on REMAP
configuration
0x0000 0000
DS13282 - Rev 2
page 30/72
BlueNRG-LP
Application circuits
4
Application circuits
The schematics below are purely indicative.
Figure 11. Application circuit: DC-DC converter, QFN48 package
1.7 V to 3.6 V Power Supply
C1
C4
C2
C3
C5
XTAL_LS
C7
C6
Q1
Q2
L1
C8
XTAL_HS
24
23
22
21
20 PA7
19 PA6
18 PA5
17 PA4
16 PA3
15 PA2
14 PA1
13 PA0
C9
37
C10
VDD3
OSCOUT
VDDRF
C11
L2
C15
L3
RSTN 38
RSTN
VDD1
VDDA
PB11
PB10
PB9
PB8
PB7
PB6
PB5
39
40
41
RF1
VDD2
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
C16
C12
PB11
PB10 42
C14
C13
PB9
PB8
PB7
PB6
PB5
PB4
43
44
45
46
47
48
BlueNRG-LP
PB4
49
GND
U1
DS13282 - Rev 2
page 31/72
BlueNRG-LP
Application circuits
Figure 12. Application circuit: DC-DC converter, WCSP49 package
C13
C10 C14
C9 C8
1.7 V to 3.6 V Power Supply
C5
RSTN
C1
U1
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
F6
G6
E5
E4
E3
F5
G5
E7
D7
E6
D3
D6
D5
C7
C6
C5
C4
B7
B6
B5
B4
B3
B2
D4
C3
C2
D2
E2
F2
L1
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA8
A2
VLXSD
VFBSD
C1
C6
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB12
PB13
PB14
PB15
C11
L2
L3
G4
RF1
BlueNRG-LP
C15
C16
C12
Q2
C3
PB7
PB8
PB9
F1
E1
OSCIN
OSCOUT
XTAL_HS
Q1
PB14
PB15
XTAL_LS
C2
Figure 13. Application circuit: DC-DC converter, QFN32 package
1.7 V to 3.6 V Power Supply
C1
C20
C19
XTAL_LS
C7
C23
Q1
Q2
L4
C8
XTAL_HS
25
16
15
14
13
VDDSD
RSTN
VCAP
PB7
PB6
PB5
OSCOUT
VDDRF
RF1
VDD2
PA3
PA2
PA1
PA0
C11
L2
L3
RSTN 26
27
C5
PB7
PB6
PB5
PB4
28
29
30
31
32
BlueNRG-LP
PA3
12
C15
PA2
11
C16
C12
PA1
10
PB4
VDD1
PA0
9
C10
C14
33
GND
U1
DS13282 - Rev 2
page 32/72
BlueNRG-LP
Application circuits
Table 7. Application circuit external components
Component
C1
Description
Decoupling capacitor
C2
32 kHz crystal loading capacitor
32 kHz crystal loading capacitor
Decoupling capacitor
C3
C4
C5
Decoupling capacitor for digital regulator
DC – DC converter output capacitor
Decoupling capacitor
C6
C7
C8
Decoupling capacitor
C9
DC-DC converter output inductor
Decoupling capacitor
C10
C11
C12
C13
C14
C15
C16
L1
Decoupling capacitor
RF matching capacitor
Decoupling capacitor
Decoupling capacitor
RF matching capacitor
RF matching capacitor
DC-DC converter output inductor
RF matching inductor
L2
L3
RF matching capacitor
Low speed crystal
Q1
Q2
High speed crystal
U1
BlueNRG-LP
U2
Low/band pass filter
Note:
In order to make the board DC–DC OFF, the inductance L1 must be removed and the supply voltage must be
applied to the VFBSD pin.
DS13282 - Rev 2
page 33/72
BlueNRG-LP
Electrical characteristics
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to ground (GND).
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the following standard
conditions:
•
•
•
•
Ambient temperature is TA = 25 °C
Supply voltage is VDD: 3.3 V
System clock frequency is 32 MHz (clock source HSI)
SMPS clock frequency is 4 MHz
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes and are not tested in production. Based on characterization, the minimum and maximum values
refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V. They are given only as design
guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean ± 2σ).
5.1.3
5.1.4
Typical curves
Unless otherwise specified, all typical curves are only given as design guidelines and are not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in the figure below.
Figure 14. Pin loading conditions
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in the figure below.
DS13282 - Rev 2
page 34/72
BlueNRG-LP
Parameter conditions
Figure 15. Pin input voltage
DS13282 - Rev 2
page 35/72
BlueNRG-LP
Absolute maximum ratings
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in the tables below, may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 8. Voltage characteristics
Symbol
VDD1, VDD2, VDD3, VDD4, VDDRF, VDDSD
VCAP, VDDA
Ratings
Min. Max. Unit
-0.3 +3.9
DC-DC converter supply voltage input and output
DC voltage on linear voltage regulator
DC voltage on digital input/output pins
DC voltage on analog pins
-0.3 +1.32
PA0 to PA15, PB0 to PB4, PB6 to PB15
VLXSD, VFBSD
V
-0.3 +3.9
XTAL0/PB12, XTAL1/PB13, OSCIN, OSCOUT, PB5 DC voltage on XTAL pins and PGA_VBIAS_MIC
+3.6
-0.3
RF1
DC voltage on RF pin
+1.4
Variations between different V
DDX
|ΔV
|
50
mV
DD
power pins of the same domain
Note:
All the main power and ground pins must always be connected to the external power supply, in the permitted
range.
Table 9. Current characteristics
Symbol
Ratings
Max.
130
130
100
Unit
ΣIV
Total current into sum of all VDD power lines (source)
Total current out of sum of all ground lines (sink)
Maximum current into each VDD power pin (source)
DD
ΣIV
GND
IV
DD(PIN)
IV
Maximum current out of each ground pin (sink)
Output current sunk by any I/O and control pin
100
20
GND(PIN)
mA
I
IO(PIN)
Output current sourced by any I/O and control pin
20
Total output current sunk by sum of all I/Os and control pins
Total output current sourced by sum of all I/Os and control pins
100
100
ΣI
IO(PIN)
Table 10. Thermal characteristics
Symbol
Ratings
Value
-40 to -125
125
Unit
T
Storage temperature range
Maximum junction temperature
STG
°C
T
J
DS13282 - Rev 2
page 36/72
BlueNRG-LP
Operating conditions
5.3
Operating conditions
5.3.1
Summary of main performance
Table 11. Main performance SMPS ON
Typ.
Test conditions
Typ.
Symbol
Parameter
Unit
VDD = 1.8 V
VDD = 3.3 V
SHUTDOWN
8
19
nA
DEEPSTOP, no
timer, wake-up
GPIO, RAM0
retained
0.44
0.46
DEEPSTOP, no
timer, wakeup
GPIO, all RAM
retained
0.62
0.64
DEEPSTOP (32
kHz LSI), RAM0
retained
0.94
1.12
0.64
0.83
1.06
1.24
0.75
0.94
2719
2188
µA
DEEPSTOP (32
kHz LSI), all RAMs
retained
DEEPSTOP (32
kHz LSE), RAM0
retained
Core current
consumption
I
CORE
DEEPSTOP (32
kHz LSE), all RAM
retained
CPU in RUN (64
MHz). Dhrystone,
clock source PLL64
CPU in RUN (32
MHz). Dhrystone,
clock source PLL64
CPU in WFI (64
MHz), all
peripherals off,
clock source PLL64
uA
1708
Radio RX at
sensitivity level
3350
4300
Radio TX 0 dBm
output power
Computed value:
(CPU 64 MHz
Dhrystone - CPU
32 MHz
I
Dynamic current
18
µA/MHz
DYNAMIC
Dhrystone) / 32
DS13282 - Rev 2
page 37/72
BlueNRG-LP
Operating conditions
Table 12. Main performance SMPS bypassed
Typ.
Typ.
Symbol
Parameter
Test conditions
Unit
VDD = 1.8 V
VDD = 3.3 V
SHUTDOWN
8
19
nA
DEEPSTOP, no
timer, wake-up
GPIO, RAM0
retained
0.44
0.62
0.46
0.64
DEEPSTOP, no
timer, wake-up
GPIO, all RAM
retained
DEEPSTOP (32
kHz LSI), RAM0
retained
0.94
1.12
0.64
0.83
1.06
1.24
0.75
0.94
4482
DEEPSTOP (32
kHz LSI), all RAMs
retained
Core current
consumption
DEEPSTOP (32
kHz LSE ), RAM0
retained
I
CORE
µA
DEEPSTOP (32
kHz LSE), all RAM
retained
CPU in RUN (64
MHz). Dhrystone,
clock source PLL64
CPU in WFI (64
MHz), all
peripherals off,
clock source PLL64
2230
Radio RX at
sensitivity level
6700
8900
Radio TX 0 dBm
output power
Table 13. Peripheral current consumption at VDD = 3.3 V, sysclk at 32 MHz, SMPS on
Parameter
ADC
Test conditions
Typ.
80
39
2
Unit
DMA
GPIOA
GPIOB
I2C1
2
40
39
46
47
11
52
50
I2C2
µA
I2S2
Peripheral clock at 32 MHz
Peripheral clock at 32 MHz
I2S3
IWDG
LPUART
PKA
DS13282 - Rev 2
page 38/72
BlueNRG-LP
Operating conditions
Parameter
RNG
Test conditions
Typ.
Unit
64
14
35
40
42
8
RTC
SPI1
SPI2
Peripheral clock at 16 MHz
Peripheral clock at 16 MHz
SPI3
µA
Systick
TIM1
248
81
33
301
9
USART
SYSCFG
THSENS
CRC
5.3.2
General operating conditions
Table 14. General operating conditions
Conditions
Symbol
Parameter
Min.
1
Max.
64
Unit
f
Internal AHB clock frequency
HCLK
f
Internal APB0 clock
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
SMPS feedback voltage
Minimum RF voltage
1
64
PCLK0
MHz
f
1
64
PCLK1
f
16
1.7
1.4
1.7
-0.3
32
PCLK2
V
DD
3.6
V
3.6
FBSMPS
V
V
3.6
DDRF
V
I/O input voltage
VDD+0.3
IN
QFN48 package
QFN32 package
Power dissipation at T =105 °C(1)
P
30
mW
°C
D
A
T
A
Ambient temperature
Maximum power dissipation
-40
-40
105
105
T
Junction temperature range
J
1.
T cannot exceed the T max.
A J
5.3.3
RF general characteristics
All performance data are referred to a 50 Ω antenna connector, via reference design.
Table 15. Bluetooth Low Energy RF general characteristics
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Frequency range(1)
F
2400
2402
2483.5
2480
RANGE
MHz
MHz
RF channel center frequency(1)
RF channel spacing(1)
RF
CH
PLL
2
RES
DS13282 - Rev 2
page 39/72
BlueNRG-LP
Operating conditions
Symbol
ΔF
Parameter
Test conditions
Min. Typ. Max. Unit
Frequency deviation(1)
250
kHz
kHz
Frequency deviation average(1)
Δf1
450
550
During the packet and including
both initial frequency offset and drift
Center frequency deviation(1)
C
Fdev
±150
kHz
Frequency deviation Δf2 (average) / Δf1
(average)(1)
Δfa
0.80
1
On-air data rate(1)
Symbol time accuracy(1)
Modulation scheme
R
gfsk
2
Mbps
ppm
STacc
MOD
BT
±50
GFSK
0.5
Bandwidth-bit period product
Modulation index(1)
Mindex
0.45 0.5
+8
0.55
At antenna connector, VSMPS =
1.9 V, LDO code
PMAX
PMIN
Maximum output
Minimum output
dBm
dBm
At antenna connector
@ 27 °C
-20
±1.5
±2.5
PRFC
RF power accuracy
dB
All temperatures
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
5.3.4
RF transmitter characteristics
All performance data are referred to a 50 Ω antenna connector, via reference design.
Table 16. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps not coded
Symbol
Parameter
Test conditions
Min. Typ. Max.
Unit
6 dB bandwidth for modulated
carrier
P
Using resolution bandwidth of 100 kHz
500
kHz
dBm
dBm
dBm
kHz
kHz
kHz
BW1M
Using resolution bandwidth of 100 kHz and
average detector
In-band emission at ±2 MHz(1)
P
P
, 1 Ms/s
-20
-30
-41
RF1
RF2
In-band emission at ±[3+n]MHz,
where n=0,1,2..(1)
Using resolution bandwidth of 100 kHz and
average detector
, 1 Ms/s
Harmonics included. Using resolution
bandwidth of 1 MHz and average detector
PS
Spurious emission
Frequency drift(1)
PUR
Integration interval #n – integration interval
#0, where n=2,3,4..k
Freq
-50
-23
-20
-20
+50
+23
+20
+20
drift
Integration interval #1 – integration interval
#0
Initial carrier frequency drift(1)
IFreq
drift
Intermediate carrier frequency
drift(1)
Integration interval #n – integration interval
#(n-5), where n=6,7,8..k
Int
Freqdrift
Between any two 10-bit groups separated by
50 µs
kHz/50
µs
Maximum drift rate(1)
Drift Rate max
Optimum RF load
Z
@ 2440 MHz
40
Ω
RF1
(impedance at RF1 pin)
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
DS13282 - Rev 2
page 40/72
BlueNRG-LP
Operating conditions
Table 17. Bluetooth Low Energy RF transmitter characteristics at 2 Mbps not coded
Symbol
Parameter
Test conditions
Min. Typ. Max.
Unit
6 dB bandwidth for modulated
carrier
P
Using resolution bandwidth of 100 kHz
670
kHz
BW1M
Using resolution bandwidth of 100 kHz and
average detector
In-band emission at ±4 MHz(1)
In-band emission at±5 MHz(1)
P
P
P
, 2 Ms/s
-20
-20
-30
-41
dBm
dBm
dBm
dBm
RF1
Using resolution bandwidth of 100 kHz and
average detector
, 2 Ms/s
RF2
In-band emission at ±[6+n]MHz,
where n=0,1,2..(1)
Using resolution bandwidth of 100 kHz and
average detector
, 2 Ms/s
RF3
Harmonics included. Using resolution
bandwidth of 1 MHz and average detector
P
Spurious emission
SPUR
Integration interval #n – integration interval
#0, where n=2,3,4..k
Frequency drift(1)
Freq
-50
+50
+23
+20
kHz
kHz
kHz
drift
Initial carrier frequency drift(1)
IFreq
Integration interval #1 – integration interval #0 -23
drift
Intermediate carrier frequency
drift(1)
Integration interval #n – integration interval
IntFreq
-20
drift
#(n-5), where n=6,7,8..k
Between any two 20-bit groups separated by
Maximum drift rate(1)
DriftRate
-20
+20 kHz/50µs
Ω
max
50 µs
Optimum RF load
Z
@ 2440 MHz
40
RF1
(impedance at RF1 pin)
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
Table 18. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps LE coded (S=8)
Symbol
Parameter
Test conditions
Min. Typ. Max.
Unit
6 dB bandwidth for modulated
carrier
P
Using resolution bandwidth of 100 kHz
500
kHz
BW
Using resolution bandwidth of 100 kHz and
average detector
In-band emission at ±2 MHz(1)
P
P
coded
-20
-30
-41
dBm
dBm
dBm
kHz
kHz
kHz
RF1, LE
In-band emission at ±[3+n]
MHz, where n=0,1,2..(1)
Using resolution bandwidth of 100 kHz and
average detector
coded
RF2, LE
Harmonics included. Using resolution
bandwidth of 1 MHz and average detector
PS
Spurious emission
Frequency drift(1)
PUR
Integration interval #n – integration interval
#0, where n=1,2,3..k
Freq
-50
+50
drift
Integration interval #3 – integration interval
#0
Initial carrier frequency drift(1)
IFreq
-19.2
-19.2
-19.2
+19.2
+19.2
+19.2
drift
Intermediate carrier frequency
drift(1)
Integration interval #n – integration interval
#(n-3), where n=7,8,9..k
IntFreq
drift
Between any two 16-bit groups separated
by 48 µs
kHz/48
µs
Maximum drift rate(1)
DriftRate
max
Optimum RF load
Z
@ 2440 MHz
40
Ω
RF1
(Impedance at RF1 pin)
1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
5.3.5
RF receiver characteristics
All performance data are referred to a 50 Ω antenna connector, via reference design.
DS13282 - Rev 2
page 41/72
BlueNRG-LP
Operating conditions
Table 19. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s uncoded
Symbol
Parameter
Sensitivity
Saturation
Test conditions
PER < 30.8%
PER < 30.8%
Min. Typ. Max. Unit
RX
-
-97
8
dBm
dBm
SENS
P
SAT
Optimum RF source
Z
@ 2440 MHz
40
Ω
RF1
(impedance at RF1 pin)
RF selectivity with BLE equal modulation on interfering signal
Co-channel interference
= f
C/I
Wanted signal = -67 dBm, PER < 30.8%
Wanted signal = -67 dBm, PER < 30.8%
Wanted signal = -67 dBm, PER < 30.8%
8
dBc
dBc
dBc
CO-channel
f
RX
interference
Adjacent interference
= f ± 1 MHz
C/I
-1
1 MHz
f
f
interference
RX
Adjacent Interference
= f ± 2 MHz
C/I
-35
2 MHz
interference
RX
Adjacent interference
= f ± (3+n) MHz
C/I
f
interference
Wanted signal = -67 dBm, PER < 30.8%
-47
dBc
3 MHz
RX
[n = 0,1,2…]
Image frequency interference
= f
C/I
Wanted signal = -67 dBm, PER < 30.8%
Wanted signal= -67 dBm, PER < 30.8%
-25
-25
dBc
dBc
Image
f
interference
image
Adjacent channel-to-image frequency
= f ± 1 MHz
C/I
Image±1 MHz
f
interference
image
Out of band blocking (interfering signal CW)
Interfering signal frequency 30 MHz –
2000 MHz
Wanted signal = -67 dBm, PER < 30.8%,
measurement resolution 10 MHz
C/I
5
dBm
dBm
dBm
dBm
Block
Interfering signal frequency 2003 MHz – Wanted signal = -67 dBm, PER < 30.8%,
2399 MHz measurement resolution 3 MHz
C/I
-5
-5
10
Block
Interfering signal frequency 2484 MHz – Wanted signal = -67 dBm, PER < 30.8%,
2997 MHz measurement resolution 3 MHz
C/I
Block
Interfering signal frequency 3000 MHz – Wanted signal = -67 dBm, PER < 30.8%,
12.75 GHz measurement resolution 25 MHz
C/I
Block
Intermodulation characteristics (CW signal at f , BLE interfering signal at f )
1
2
Input power of IM interferer at 3 and 6
MHz distance from wanted signal
P_IM(3)
Wanted signal = -64 dBm, PER < 30.8%
Wanted signal = -64 dBm, PER < 30.8%
Wanted signal= -64 dBm, PER < 30.8%
Wanted signal = -64 dBm, PER < 30.8%
-27
-40
-32
-32
dBm
dBm
dBm
dBm
Input power of IM interferer at -3 and -6
MHz distance from wanted signal
P_IM(-3)
P_IM(4)
P_IM(5)
Input power of IM interferer at ±4 and ±8
MHz distance from wanted signal
Input power of IM interferer at ±5 and ±10
MHz distance from wanted signal
Table 20. Bluetooth Low Energy RF receiver characteristics at 2 Msym/s uncoded
Symbol
Parameter
Sensitivity
Saturation
Test conditions
PER < 30.8%
PER < 30.8%
Min. Typ. Max. Unit
RX
-94
8
dBm
dBm
SENS
P
SAT
DS13282 - Rev 2
page 42/72
BlueNRG-LP
Operating conditions
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Optimum RF source
Z
RF1
@ 2440 MHz
40
Ω
(impedance at RF1 pin)
RF selectivity with BLE equal modulation on interfering signal
Co-channel interference
= f
C/I
Wanted signal= -67 dBm, PER < 30.8%
8
dBc
dBc
dBc
CO-channel
f
RX
interference
Adjacent interference
= f ± 2 MHz
Wanted signal = -67 dBm, PER <
30.8%
C/I
-14
-41
2 MHz
f
f
interference
RX
Adjacent interference
= f ± 4 MHz
Wanted signal = -67 dBm, PER <
30.8%
C/I
4 MHz
interference
RX
Adjacent interference
= f ± (6+2n) MHz
Wanted signal = -67 dBm, PER <
30.8%
C/I
f
interference
-45
dBc
6 MHz
RX
[n = 0,1,2…]
Image frequency interference
= f
Wanted signal = -67 dBm, PER <
30.8%
C/I
-25
-14
dBc
dBc
Image
f
interference
image-2M
Adjacent channel-to-image frequency
= f ± 2 MHz
C/I
Wanted signal= -67 dBm, PER < 30.8%
Image±1 MHz
f
interference
image-2M
Out of band blocking (interfering signal CW)
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 10
MHz
Interfering signal frequency 30 MHz –
2000 MHz
C/I
5
dBm
Block
Interfering signal frequency 2003 MHz –
2399 MHz
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 3 MHz
C/I
-5
-5
dBm
dBm
Block
Interfering signal frequency 2484 MHz –
2997 MHz
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 3 MHz
C/I
Block
Wanted signal= -67 dBm, PER <
30.8%, measurement resolution 25
MHz
Interfering signal frequency 3000 MHz –
12.75 GHz
C/I
10
dBm
Block
Intermodulation characteristics (CW signal at f , BLE interfering signal at f )
1
2
Input power of IM interferer at 6 and 12
MHz distance from wanted signal
P_IM(6)
Wanted signal= -64 dBm, PER < 30.8%
Wanted signal= -64 dBm, PER < 30.8%
Wanted signal= -64 dBm, PER < 30.8%
Wanted signal= -64 dBm, PER < 30.8%
-27
-30
-30
-28
dBm
dBm
dBm
dBm
Input power of IM interferer at -6 and -12
MHz distance from wanted signal
P_IM(-6)
P_IM(8)
P_IM(10)
Input power of IM interferer at ±8 and ±16
MHz distance from wanted signal
Input power of IM interferer at ±10 and
±20 MHz distance from wanted signal
Table 21. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2)
Symbol
Parameter
Sensitivity
Saturation
Test conditions
PER < 30.8%
PER < 30.8%
Min. Typ. Max. Unit
RX
-100
8
dBm
dBm
SENS
P
SAT
-
Optimum RF source
Z
@ 2440 MHz
40
Ω
RF1
(impedance at RF1 pin)
DS13282 - Rev 2
page 43/72
BlueNRG-LP
Operating conditions
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
RF selectivity with BLE equal modulation on interfering signal
Co-channel interference
C/I -channel
Wanted signal = -79 dBm, PER < 30.8%
2
dBc
dBc
dBc
CO
f
RX
= f
interference
Adjacent interference
= f ± 1 MHz
C/I
Wanted signal = -79 dBm, PER < 30.8%
Wanted signal = -79 dBm, PER < 30.8%
-5
1 MHz
f
f
interference
RX
Adjacent interference
= f ± 2 MHz
C/I
-38
2 MHz
interference
RX
Adjacent interference
= f ± (3+n) MHz
C/I
f
interference
Wanted signal = -79 dBm, PER < 30.8%
-50
dBc
3 MHz
RX
[n = 0,1,2…]
Image frequency interference
= f
C/I
Wanted signal = -79 dBm, PER < 30.8%
Wanted signal = -79 dBm, PER < 30.8%
-30
-34
dBc
dBc
Image
f
interference
image
Adjacent channel-to-image frequency
= f ± 1 MHz
C/I
MHz
Image±1
f
interference
image
Table 22. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8)
Symbol
Parameter
Sensitivity
Saturation
Test conditions
PER < 30.8%
PER < 30.8%
Min. Typ. Max. Unit
RX
-104
8
dBm
dBm
SENS
P
SAT
-
Optimum RF source
Z
@ 2440 MHz
40
Ω
RF1
(impedance at RF1 pin)
RF selectivity with BLE equal modulation on interfering signal
Co-channel interference
C/I
Wanted signal = -79 dBm, PER < 30.8%
1
dBc
dBc
dBc
CO-channel
f
= f
interference
RX
Adjacent interference
= f ± 1 MHz
C/I
Wanted signal = -79 dBm, PER < 30.8%
Wanted signal = -79 dBm, PER < 30.8%
-4
1 MHz
f
f
interference
RX
Adjacent interference
= f ± 2 MHz
C/I
-39
2 MHz
interference
RX
Adjacent interference
= f ± (3+n) MHz
C/I
f
interference
Wanted signal = -79 dBm, PER < 30.8%
-53
dBc
3 MHz
RX
[n = 0,1,2…]
Image frequency interference
= f
C/I
Wanted signal = -79 dBm, PER < 30.8%
Wanted signal = -79 dBm, PER < 30.8%
-33
-32
dBc
dBc
Image
f
interference
image
Adjacent channel-to-image frequency
= f ± 1 MHz
C/I
± 1 MHz
Image
f
interference
image
DS13282 - Rev 2
page 44/72
BlueNRG-LP
Operating conditions
5.3.6
Embedded reset and power control block characteristics
Table 23. Embedded reset and power control block characteristics
Symbol
TRSTTEMPO
VPDR
Parameter
Reset temporization after PDR is detected
Power-down reset threshold
PVD threshold 0
Test conditions
Min. Typ. Max. Unit
500 us
VDD rising
1.63
2.02
2.17
2.33
2.49
2.61
2.78
2.87
VPVD0
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
V
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
5.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as: the operating voltage, ambient
temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program
location in memory and executed binary code.
The MCU is put under the following conditions:
•
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number
When the peripherals are enabled fPCLK = fHCLK
Table 24. Current consumption
Typ.
Symbol
Parameter
Conditions
= 64 MHz
Unit
25 °C 85 °C 105 °C
f
HCLK
2.40
1.98
1.62
2.49
2.03
1.67
2.54
2.08
1.71
All peripherals disabled
= 32 MHz
f
HCLK
I
(RUN)
DD
Supply current in RUN mode
mA
All peripherals disabled
= 16 MHz
f
HCLK
All peripherals disabled
Timer OFF
0.65
1.25
6.73
7.41
15.73
16.46
Timer source LSI
Timer source LSI
RTC ON
1.30
1.27
7.56
7.47
16.70
16.55
Supply current in DEEPSTOP(1)
I
(DEEPSTOP)
µA
DD
Timer source LSI
IWDG ON
Timer source LSI
RTC and IWDG ON
1.33
1.00
7.61
7.16
16.79
16.22
Timer source LSE
DS13282 - Rev 2
page 45/72
BlueNRG-LP
Operating conditions
Typ.
Unit
25 °C 85 °C 105 °C
Symbol
Parameter
Conditions
Timer source LSE
RTC ON
1.06
1.02
1.07
7.31
7.22
7.36
16.45
16.30
16.54
Timer source LSE
IWDG ON
Supply current in DEEPSTOP(1)
I
(DEEPSTOP)
DD
µA
Timer source LSE
RTC and IWDG ON
I
(SHUTDOWN)
Supply current in SHUTDOWN
Current under reset condition
0.02
1.34
0.46
1.45
1.36
1.55
DD
I
(RST)
DD
mA
1. The current consumption in DEEPSTOP is measured considering the entire SRAM retained.
5.3.8
Wake-up time from low power modes
The wake-up times reported are the latency between the event and the execution of the instruction. The device
goes to low-power mode after WFI (wait for interrupt) instructions.
Table 25. Low power mode wake-up timing
Symbol
Parameter
Conditions
Typ. Unit
Wake-up time from DEEPSTOP mode to RUN
mode
T
Wake-up from GPIO VDD = 3.3 V Flash memory 110 µs
WUDEEPSTOP
5.3.9
High speed crystal requirements
The high speed external oscillator must be supplied with an external 32 MHz crystal that is specified for a 6 to 8
pF loading capacitor. The BlueNRG-LP includes internal programmable capacitances that can be used to tune the
crystal frequency in order to compensate the PCB parasitic one. These internal load capacitors are made by a
fixed one, in parallel with a 6-bit binary weighted capacitor bank. Thanks to low CL step size (LSB is typically 0.07
pF), very fine crystal tuning is possible. With a typical XTAL sensitivity of -14 ppm/pF, it is possible to trim a 32
MHz crystal, with a resolution of 1 ppm.
The requirements for the external 32 MHz crystal are reported in the table below.
Table 26. HSE crystal requirements
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
f
Oscillator frequency
32
MHz
NOM
Includes initial accuracy, stability over temperature,
aging and frequency pulling due to incorrect load
capacitance
f
Frequency tolerance
±50 ppm
TOL
ESR
Equivalent series resistance
Drive level
100
Ω
P
D
100 µW
27 °C, typical corner
GMCONF = 3
5 (1) 7(2) 9.2(3)
CL
HSE crystal load capacitance
pF
pF
27 °C,
HSE crystal load capacitance LSB
value
CLstep
GMCONF = 3
0.07
XOTUNE code between 32 and 33
1. XOTUNE programed at minimum code = 0
2. XOTUNE programed at center code = 32
3. XOTUNE programed at maximum code = 63
DS13282 - Rev 2
page 46/72
BlueNRG-LP
Operating conditions
5.3.10
Low speed crystal requirements
Low speed clock can be supplied with an external 32.768 kHz crystal oscillator. Requirements for the external
32.768 kHz crystal are reported in the table below.
Table 27. LSE crystal requirements
Symbol
Parameter
Nominal frequency
Equivalent series resistance
Drive level
Conditions
Min.
Typ.
Max.
Unit
kHz
kΩ
f
32.768
NOM
ESR
90
P
0.1
µW
D
5.3.11
High speed ring oscillator characteristics
Table 28. HSI oscillator characteristics
Symbol
Parameter
Nominal frequency
Conditions
Min.
Typ.
64
Max.
Unit
f
MHz
NOM
5.3.12
Low speed ring oscillator characteristics
Table 29. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min.
Typ.
33
Max.
Unit
kHz
f
Nominal frequency
NOM
ΔF
/F
Frequency spread vs. temperature
Standard deviation
140
ppm/ºC
RO_ΔT RO
5.3.13
PLL characteristics
Characteristics measured over recommended operating conditions unless otherwise specified.
Table 30. PLL characteristics
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
At ±1 MHz offset from carrier
(measured at 2.4 GHz)
-110
dBc/Hz
At 2.4 GHz ±3 MHz offset from carrier
(measured at 2.4 GHz)
-114
-128
dBc/Hz
dBc/Hz
PN
RF carrier phase noise
SYNTH
At 2.4 GHz±6 MHz offset from carrier
(measured at 2.4 GHz)
At ±25 MHz offset from carrier
With calibration @2.5 ppm
With calibration @2.5 ppm
Without calibration @2.5 ppm
Without calibration @2.5 ppm
-135
150
110
47
dBc/Hz
µs
LOCK
PLL lock time to TX
PLL lock time to RX
TIMETX
LOCK
LOCK
µs
TIMERX
PLL lock time RX to TX
PLL lock time TX to RX
µs
TIMERXTX
TIMETXRX
LOCK
32
µs
DS13282 - Rev 2
page 47/72
BlueNRG-LP
Operating conditions
5.3.14
Flash memory characteristics
The characteristics below are guaranteed by design.
Table 31. Flash memory characteristics
Symbol
Parameter
Test conditions
Typ.
20
Max.
40
Unit
t
32-bit programming time
4x32-bit burst programming time
Page (2 kbyte) erase time
Mass erase time
prog
µs
t
20
40
prog_burst
t
20
40
ERASE
ms
t
20
3
40
ME
Write mode
Erase mode
Mass erase
I
Average consumption from VDD
3
mA
DD
5
Table 32. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Test conditions
Min.
10
Unit
N
END
T
= -40 to +105 ºC
kcycles
Years
A
t
T = 105 ºC
A
Data retention
10
RET
5.3.15
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each
sample according to each pin combination. The sample size depends on the number of supply pins in the device
(3 parts x (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard.
Table 33. ESD absolute maximum ratings
Max.(1)
Symbol
Parameter
Conditions
Class
Unit
Electrostatic discharge voltage (human body
model)
V
Conforming to ANSI/ESDA/JEDEC JS-001
2
2000
ESD(HBM)
ESD(CBM)
V
Electrostatic discharge voltage (charge
device model)
Conforming to ANSI/ESDA/STM5.3.1
JS-002
V
C2a
500
1. Guaranteed by design.
5.3.16
I/O port characteristics
Unless otherwise specified, the parameters given in the tables below are derived from tests performed under the
conditions summarized in Section 5.3.2 General operating conditions. All I/Os are designed as CMOS-compliant.
The characteristics below are guaranteed by characterization.
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
I/O input low level voltage
I/O input high level voltage
0.3 x VDD
IL
1.62 V < VDD < 3.6 V
V
V
0.7 x VDD
IH
0 <= VIN <= Max(VDDx)(1)
Max(VDDx)(1) <= VIN <= Max(VDDx)(1) +1 V
Max(VDDx)(1) + 1 V < VIN <= 5.5 V
+/-100
650
I
Input leakage current
nA
lkg
200
DS13282 - Rev 2
page 48/72
BlueNRG-LP
Operating conditions
Symbol
Parameter
Conditions
VIN = GND
VIN = VDD
Min.
25
Typ.
40
40
5
Max.
55
Unit
kΩ
R
PU
Pull-up resistor
R
PD
Pull-down resistor
I/O pin capacitance
25
55
C
IO
pF
1. Max(VDDx) is the maximum value among all the I/O supplies.
All I/Os are CMOS-compliant (no software configuration required).
GPIOs (general purpose input/outputs) can sink or source up to ±8 mA and sink or source up to ± 20 mA (with a
relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to respect the absolute
maximum rating specified.
•
The sum of currents sourced by all I/Os on VDD, plus the maximum consumption of MCU sourced on VDD,
cannot exceed the absolute maximum rating ΣIVDD
•
The sum of currents sunk by all I/Os on VSS, plus the maximum consumption of the MCU sunk on GND,
cannot exceed the absolute maximum rating ΣIVGND
The characteristics below are guaranteed by characterization.
Table 35. Output voltage characteristics
Symbol
Parameter
Conditions
Min.
Max. Unit
V
Output low level voltage for I/O pin
Output high level voltage for I/O pin
Output low level voltage for I/O pin
Output high level voltage for I/O pin
Output low level voltage for I/O pin
Output high level voltage for I/O pin
0.4
OL
CMOS port(1) |IIO| = 8 mA VDD ≥ 2.7 V
V
VDD -0.4
VDD -1.3
VDD-0.45
OH
V
OL
1.3
V
|IIO| = 20 mA VDD ≥ 2.7 V
|IIO| = 4 mA VDD ≥ 1.62 V
V
OH
V
0.4
OL
V
OH
1. CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
5.3.17
RSTN pin characteristics
The RSTN pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Section 5.3.2 General operating conditions.
The characteristics below are guaranteed by design.
Table 36. RSTN pin characteristics
Symbol
Parameter
Test conditions
Min.
0.7 x VDD
25
Typ.
Max.
Unit.
V
RSTN input low level voltage
RSTN input high level voltage
RSTN Schmitt trigger voltage hysteresis
Weak pull-up equivalent resistor
0.3 x VDD
IL(RSTN)
V
V
IH(RSTN)
V
200
40
mV
kΩ
hys(RSTN)
RPU
VIN=GND
55
DS13282 - Rev 2
page 49/72
BlueNRG-LP
Operating conditions
Figure 16. Recommended RSTN pin protection
Note:
The external reset circuit protects the device against parasitic resets.
The user must ensure that the level on the RSTN pin can go below the VIL(RSTN) max. level specified in the
table, otherwise the reset is not taken into account by the device. The external capacitor on RSTN must be
placed as close as possible to the device.
5.3.18
ADC characteristics
Table 37. ADC characteristics (HSI must be set to PLL mode)
Symbol
Parameter
Test conditions
Min. Typ. Max.
Units
Number of channels for
differential mode
Ch_diff_num
QFN48, WLCSP49
4
Number of channels for single
ended mode
Ch_se_num
QFN48, WLCSP49
Biasing blocks turned on
8
ADC biasing consumption at
battery
IBAT
145
mA
mA
ADCBIAS
ADC active consumption at
battery
IBAT
ADC activated in differential mode
185
ADCACTIVE
VDDA
Analog supply voltage
Input impedance
1.2
1.32
550
V
R
AIN
In DC
250
kΩ
R
in
Internal access resistance
Input sampling capacitor
Sampling period
VBOOST is enabled for VDD < 2.7 V
Ω
C
4
1
pF
in
T
µs
s
T
Sampling time
125
200
16
5
ns
k samples/s
bits
sw
DR
Output data rate
FRMT
Output data format
Latency time
output
TL
200 kSps
µs
T
Start-up time
From ADC enable to conversion start
1
µs
STARTUP
DNL
Differential non-linearity
±0.7
LSB
DS13282 - Rev 2
page 50/72
BlueNRG-LP
Operating conditions
Symbol
Parameter
Test conditions
Min. Typ. Max.
Units
INL
Integral non-linearity
±1
72
LSB
Differential input
@1 kHz, -1 dBFs
SNR Diff
STHD Diff
ENOB Diff
SNR SE
Signal to noise ratio
dB
dB
Differential input
@1 kHz, -1 dBFs
Signal to THD ratio (10
harmonics)
80
11.5
70
Differential input
@1 kHz, -1 dBFs
Effective number of bits
Signal-to-noise ratio
bits
dB
Single ended
@1 kHz, -1 dBFs
Single ended
Signal-to THD ratio (10
harmonics)
STHD SE
ENOB SE
75
dB
@1 kHz, -1 dBFs
Single ended
Effective number of bits
11
bits
@1 kHz, -1 dBFs
ADC_ERR_1V7
ADC_ERR_2V4
ADC_ERR_3V0
ADC_ERR_3V6
13
0
Absolute error when used for battery
measurements at 1.7 V, 2.4 V, 3.0 V, 3.6
V
mV
-9
-22
5.3.19
Temperature sensor characteristics
Table 38. Temperature sensor characteristics
Symbol
Parameter
Min.
Typ.
±4
Max.
Unit
°C
T
rERR
Error in temperature
T
Average temperature coefficient
Current consumption
8
LSB/°C
µA
SLOPE
T
415
2533
ICC
T
Output code at 30 °C (+/-5 °C)
LSB
TS-OUT
5.3.20
Timer characteristics
The characteristics below are guaranteed by design.
Table 39. TIM1 characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
15.625
16
Max.
Unit
t
f
= 64 MHz
Timer resolution time
Timer resolution
ns
bit
μs
s
res(TIM)
TIMxCLK
R
esTIM
t
f
= 64 MHz
16-bit counter clock period
Maximum possible count time
0.015625
1024
COUNTER
TIMxCLK
t
f
= 64
TIMxCLK
67.10
MAX_COUNT
DS13282 - Rev 2
page 51/72
BlueNRG-LP
Operating conditions
Table 40. IWDG min./max. timeout period at 32 kHz (LSE)
Prescaler divider
PR[2:0] bits
Min. timeout RL[11:0] = 0x000
Max. timeout RL[11:0] = 0xFFF
Unit
/4
/8
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
1
/16
/32
/64
/128
/256
2
3
4
ms
2.0
5
4.0
6 or 7
8.0
DS13282 - Rev 2
page 52/72
BlueNRG-LP
Operating conditions
2
5.3.21
I C interface characteristics
The I2C interface meets the timing requirements of the I2C-Bus specifications and user manual rev. 03 for:
•
•
•
Standard-mode (Sm): bit rate up to 100 kbit/s
Fast-mode (Fm): bit rate up to 400 kbit/s
Fast-mode plus (Fm+): bit rate up to 1 Mbit/s
SDA and SCL I/O requirements are met with the following restrictions: SDA and SCL I/O pins are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still
present. The 20 mA output drive requirement in fast-mode plus is supported partially.
This limits the maximum load Cload supported in fast-mode plus, given by these formulas:
•
•
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min.) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up.
All I2C SDA and SCL I/Os embed an analog filter.
The characteristics below are guaranteed by design.
Table 41. I2C analog filter characteristics
Symbol
Parameter
Min.
Max.
Unit
tAF
Maximum pulse width of spikes that are suppressed by the analog filter
50
110
ns
5.3.22
SPI characteristics
The parameters for SPI are derived from tests performed according to fPCLKx frequency and supply voltage
conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x VDD
The characteristics below are guaranteed by design.
Table 42. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Slave mode
Min.
Typ.
Max.
Units
32
f
SPI clock frequency
-
MHz
SCK
32(1)
4 / f
tsu(NSS)
th(NSS)
NSS setup time
NSS hold time
-
-
-
-
-
-
PCLK
2 / f
1 / f
PCLK
- 1.5
1 / f
1 / f
+1
+1
tw(SCKH)
PCLK
PCLK
PCLK
SCK high and low time
Master mode
1 / f
- 1.5
1 / f
1 / f
PCLK
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
PCLK
PCLK
Data input set-up time
Data input set-up time
Data input hold time
Data input hold time
Data output access time
Master mode
Slave mode
Master mode
Slave mode
Slave mode
1
1
3
1
5
-
-
-
-
-
-
-
-
ns
th(SI)
-
t
40
a(SO)
t
Data output disable time
Slave mode
Master mode
Slave mode
5
-
-
38
8
dis(SO)
t
2
v(MO)
Data output valid time
t
-
12
39
v(SO)
DS13282 - Rev 2
page 53/72
BlueNRG-LP
Operating conditions
Symbol
Parameter
Conditions
Master mode
Slave mode
Min.
Typ.
Max.
Units
t
2
4
h(MO)
ns
Data output hold time
-
t
h(SO)
1. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while duty(SCK) = 50 %.
Figure 17. SPI timing diagram - slave mode and CPHA = 0
Figure 18. SPI timing diagram - slave mode and CPHA = 1
DS13282 - Rev 2
page 54/72
BlueNRG-LP
Operating conditions
Figure 19. SPI timing diagram - master mode
DS13282 - Rev 2
page 55/72
BlueNRG-LP
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
6.1
QFN48 (6x6x0.9, pitch 0.4 mm) package information
Figure 20. QFN48 (6x6x0.9, pitch 0.4 mm) package outline
DS13282 - Rev 2
page 56/72
BlueNRG-LP
QFN48 (6x6x0.9, pitch 0.4 mm) package information
Table 43. QFN48 (6x6x0.9, pitch 0.4 mm) mechanical data
mm
Typ.
0.95
Symbol
Min.
0.90
0.0
Max.
1.00
0.05
A
A1
A3
b
0.20 Ref
0.20
0.17
5.95
4.40
0.25
6.05
4.60
D
6.00
D2
e
4.50
0.40 BSC
6.00
E
5.95
4.40
0.30
6.05
4.60
0.50
E2
L
4.50
0.40
K
0.50
Table 44. Tolerance of form and position
Symbol
aaa
Databook
0.10
bbb
0.10
ccc
0.008
0.10
ddd
Figure 21. QFN48 (6x6x0.9, pitch 0.4 mm) detail A package information
DS13282 - Rev 2
page 57/72
BlueNRG-LP
QFN48 (6x6x0.9, pitch 0.4 mm) package information
Figure 22. QFN48 (6x6x0.9, pitch 0.4 mm) recommended footprint
DS13282 - Rev 2
page 58/72
BlueNRG-LP
QFN32 (5x5x0.9, pitch 0.5 mm) package information
6.2
QFN32 (5x5x0.9, pitch 0.5 mm) package information
Figure 23. QFN32 (5x5x0.9, pitch 0.5 mm) package outline
DS13282 - Rev 2
page 59/72
BlueNRG-LP
QFN32 (5x5x0.9, pitch 0.5 mm) package information
Table 45. QFN32 (5x5x0.9, pitch 0.5 mm) package information mechanical data
mm
Typ.
0.95
Symbol
Min.
0.90
0
Max.
1.00
0.05
A
A1
A3
b
0.20
0.25
0.20
4.90
3.60
0.30
5.10
3.80
D
5.00
D2
c
3.70
0.50 BSC
5.00
E
4.90
3.60
0.30
5.10
3.80
0.50
E2
L
3.70
0.40
Note:
D and E, package outline exclusive of any mold flashes dimensions and metal burrs.
Table 46. Tolerance of form and position
Symbol
aaa
Databook
0.10
0.10
0.10
0.05
bbb
ccc
ddd
Figure 24. Detail A
DS13282 - Rev 2
page 60/72
BlueNRG-LP
QFN32 (5x5x0.9, pitch 0.5 mm) package information
Figure 25. QFN32 (5x5x0.9, pitch 0.5 mm) package information recommended footprint
DS13282 - Rev 2
page 61/72
BlueNRG-LP
WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) package information
6.3
WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) package information
Figure 26. WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) package outline (bumps view)
DS13282 - Rev 2
page 62/72
BlueNRG-LP
WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) package information
Table 47. WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) mechanical data
Milimeters
Typ.
Symbol
Min.
0.380
0.135
0.212
0.214
3.120
Max.
0.420
0.165
0.238
0.222
3.160
A
A1
A2
b
0.400
0.150
0.225
0.218
3.140
2.400
3.140
2.400
0.400
0.416
0.263
0.477
0.324
0.025
0.060
D
D1
E
3.120
3.160
E1
e
fD
fE
fG
fH
$
0.022
0.028
ccc
Figure 27. WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) recommended footprint
DS13282 - Rev 2
page 63/72
BlueNRG-LP
Thermal characteristics
6.4
Thermal characteristics
The maximum chip junction temperature (TJmax.) must never exceed the values in general operating conditions.
The maximum chip-junction temperature, TJ max., in degrees Celsius, can be calculated using the equation:
T max . = T max. + PDmax × θJA
(1)
J
A
where:
•
•
•
•
TA max. is the maximum ambient temperature in °C
ΘJA is the package junction-to-ambient thermal resistance, in °C/W
PD max. is the sum of PINT max. and PI/O max. (PD max. = PINT max. + PI/O max.)
PINT max. is the product of IDD and VDD, expressed in Watt. This is the maximum chip internal power
PI/O max represents the maximum power dissipation on output pins:
PI/O max. = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
•
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the applications.
Note:
Note:
Note:
When the SMPS is used, a portion of the power consumption is dissipated into the external inductor, therefore
reducing the chip power dissipation. This portion depends mainly on the inductor ESR characteristics.
As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the chip power
consumption.
RF characteristics (such as: sensitivity, Tx power, consumption) are provided up to 85 °C.
Table 48. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
QFN48 – 6 mm x 6 mm
25.1
Thermal resistance junction-ambient
QFN32 - 5 mm x 5 mm
ΘJA
26.9
-
ºC/W
Thermal resistance junction-ambient
WCSP49 – 0.4 mm pitch
DS13282 - Rev 2
page 64/72
BlueNRG-LP
Ordering information
7
Ordering information
Table 49. Ordering information
Order code
Package
Packing
BLUENRG-3x5yz
QFN32, QFN48, WLCSP49
Tape and reel
Figure 28. Ordering information
DS13282 - Rev 2
page 65/72
BlueNRG-LP
Revision history
Table 50. Document revision history
Date
Version
Changes
02-Jul-2020
1
Initial release.
Updated cover page.
Updated Table 3. Pin description, Table 10. Thermal characteristics,
Table 14. General operating conditions and Table 49. Ordering information.
24-Sep-2020
2
Updated Figure 6. Clock tree.
Added Table 4. Legend/abbreviations used in the pinout table.
DS13282 - Rev 2
page 66/72
BlueNRG-LP
Contents
Contents
1
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
1.2
1.3
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ARM Cortex–M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Embedded ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Embedded OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
1.5
Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.1
RF front-end block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6.1
1.6.2
1.6.3
1.6.4
SMPS step-down regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Linear voltage regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power supply supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.7
Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.7.1
1.7.2
1.7.3
RUN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DEEPSTOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SHUTDOWN mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8
1.9
Reset management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clock management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.10 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.11 Embedded UART bootloader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.12 General purpose inputs/outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.13 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.14 Nested vectored interrupt controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.15 Analog digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.15.1 Digital microphone MEMS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DS13282 - Rev 2
page 67/72
BlueNRG-LP
Contents
1.15.2 Analog microphone interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.15.3 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.16 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.17 Timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.17.1 Advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.17.2 Independent watchdog (IWDG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2
1.19 Inter-integrated circuit interface (I C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.20 Universal synchronous/asynchronous receiver transmitter (USART). . . . . . . . . . . . . . . . . . . 19
1.21 LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.22 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.23 Inter-IC sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.24 Serial wire debug port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.25 TX and RX event alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Pinouts and pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2
3
4
5
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
Minimum and maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2
5.3
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.3.1
5.3.2
5.3.3
5.3.4
Summary of main performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DS13282 - Rev 2
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BlueNRG-LP
Contents
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
RF receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Wake-up time from low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
High speed crystal requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.10 Low speed crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.11 High speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.12 Low speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.13 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.14 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.15 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.17 RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.18 ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.19 Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.20 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2
5.3.21 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.22 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6
7
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6.1
6.2
6.3
6.4
QFN48 (6x6x0.9, pitch 0.4 mm) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
QFN32 (5x5x0.9, pitch 0.5 mm) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) package information . . . . . . . . . . . . . . . . . . . . . . .62
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DS13282 - Rev 2
page 69/72
BlueNRG-LP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
SRAM overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Relationship between the low power modes and functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application circuit external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Main performance SMPS ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Main performance SMPS bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Peripheral current consumption at VDD = 3.3 V, sysclk at 32 MHz, SMPS on. . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. General operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Bluetooth Low Energy RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps not coded. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. Bluetooth Low Energy RF transmitter characteristics at 2 Mbps not coded. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps LE coded (S=8) . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s uncoded. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 20. Bluetooth Low Energy RF receiver characteristics at 2 Msym/s uncoded. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2). . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8). . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Low power mode wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. LSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 31. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 36. RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 37. ADC characteristics (HSI must be set to PLL mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 38. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 39. TIM1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 40. IWDG min./max. timeout period at 32 kHz (LSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 41. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 43. QFN48 (6x6x0.9, pitch 0.4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 44. Tolerance of form and position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. QFN32 (5x5x0.9, pitch 0.5 mm) package information mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 46. Tolerance of form and position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 47. WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 48. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 49. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 50. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DS13282 - Rev 2
page 70/72
BlueNRG-LP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
The BlueNRG-LP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BlueNRG-LP RF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power supply domain overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pinout top view (QFN48 package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinout top view (QFN32 package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pinout top view (WLCSP49 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application circuit: DC-DC converter, QFN48 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Application circuit: DC-DC converter, WCSP49 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Application circuit: DC-DC converter, QFN32 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Recommended RSTN pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
QFN48 (6x6x0.9, pitch 0.4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
QFN48 (6x6x0.9, pitch 0.4 mm) detail A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
QFN48 (6x6x0.9, pitch 0.4 mm) recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
QFN32 (5x5x0.9, pitch 0.5 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Detail A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
QFN32 (5x5x0.9, pitch 0.5 mm) package information recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . 61
WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) package outline (bumps view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
WLCSP49 (3.14x3.14x0.4, pitch 0.4 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DS13282 - Rev 2
page 71/72
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DS13282 - Rev 2
page 72/72
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