CRX14-MQP [STMICROELECTRONICS]
Low Cost ISO14443 type-B Contactless Coupler Chip with Anti-Collision, CRC Management and Anti-Clone Function; 低成本ISO14443 TYPE -B非接触耦合器芯片，防碰撞， CRC管理和防克隆功能
| 型号： | CRX14-MQP |
| 厂家： | 
ST |
| 描述： | Low Cost ISO14443 type-B Contactless Coupler Chip with Anti-Collision, CRC Management and Anti-Clone Function |
| 文件： | 总40页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CRX14
Low Cost ISO14443 type-B Contactless Coupler Chip
with Anti-Collision, CRC Management and Anti-Clone Function
FEATURES SUMMARY
■
■
■
Single 5V ±500mV Supply Voltage
SO16N package
Contactless Communication
Figure 1. Delivery Form
–
–
ISO14443 type-B protocol
13.56MHz Carrier Frequency using an
External Oscillator
16
–
–
–
106 Kbit/s Data Rate
36 Byte Input/Output Frame Register
Supports Frame Answer with/without
SOF/EOF
1
–
–
CRC Generation and Check
France Telecom Proprietary Anti-Clone
Function
SO16 (MQ)
150 mils width
–
Automated ST Anti-Collision Exchange
■
I²C Communication
–
–
–
–
Two Wire I²C Serial Interface
Supports 400kHz Protocol
3 Chip Enable Pins
Up to 8 CRX14 Connected on the Same
Bus
July 2005
1/40
CRX14
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Delivery Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. SO Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Oscillator (OSC1, OSC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Antenna Output Driver (RF ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OUT
Antenna Input Filter (RF ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IN
Transmitter Reference Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
REF
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Supply (V , GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CC
Figure 5. CRX14 Application Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
²
Figure 6. Maximum R Value versus Bus Capacitance (C
) for an I C Bus . . . . . . . . . . . . . . . . 8
L
BUS
CRX14 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. CRX14 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Parameter Register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Parameter Register Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Frame Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Input/Output Frame Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Authenticate Register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Slot Marker Register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Slot Marker Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CRX14 I²C PROTOCOL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Acknowledge Bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. I²C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I²C Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CRX14 I²C Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. CRX14 I²C Write Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. I²C Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CRX14 I²C Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/40
CRX14
Figure 10.CRX14 I²C Read Modes Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
APPLYING THE I²C PROTOCOL TO THE CRX14 REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I²C Parameter Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.Host-to-CRX14 Transfer: I²C Write to Parameter Register . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.CRX14-to-Host Transfer: I²C Random Address Read from Parameter Register . . . . . . 17
Figure 13.CRX14-to-Host Transfer: I²C Current Address Read from Parameter Register . . . . . . . 17
I²C Input/Output Frame Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14.Host-to-CRX14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B . . . 18
Figure 15.CRX14-to-Host Transfer: I²C Random Address Read
from Input/Output Frame Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16.CRX14-to-Host Transfer: I²C Current Address Read
from I/O Frame Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I²C Authenticate Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I²C Slot Marker Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17.Host-to-CRX14 Transfer: I²C Write to Slot Marker Register . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18.CRX14-to-Host Transfer: I²C Random Address Read from Slot Marker Register . . . . . 19
Figure 19.CRX14-to-Host Transfer: I²C Current Address Read from Slot Marker Register . . . . . . 19
Addresses above Location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CRX14 ISO14443 TYPE-B RADIO FREQUENCY DATA TRANSFER . . . . . . . . . . . . . . . . . . . . . . . . 21
Output RF Data Transfer from the CRX14 to the PICC (Request Frame) . . . . . . . . . . . . . . . . . 21
Figure 20.Wave Transmitted using ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Transmission Format of Request Frame Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21.CRX14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. CRX14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 22.Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 23.Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input RF Data Transfer from the PICC to the CRX14 (Answer Frame) . . . . . . . . . . . . . . . . . . . 23
Figure 24.Wave Received using BPSK Sub-carrier Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Transmission Format of Answer Frame Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25.Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Answer End Of Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 26.Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 27.Example of a Complete Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 28.CRC Transmission Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TAG ACCESS USING THE CRX14 COUPLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Standard TAG Command Access Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 29.Standard TAG Command: Request Frame Transmission. . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 30.Standard TAG Command: Answer Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/40
CRX14
Figure 31.Standard TAG Command: Complete TAG Access Description . . . . . . . . . . . . . . . . . . . 27
Anti-Collision TAG Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32.Anti-Collision ST short range memory Sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33.Anti-Collision ST short range memory Sequence Continued . . . . . . . . . . . . . . . . . . . . . 29
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. I²C AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 34.I²C AC Testing I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. I²C Input Parameters(1,2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11. I²C DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 35.I²C AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. I²C AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 36.CRX14 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. RF
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
OUT
Table 14. RF AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IN
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 37.SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Outline . . 36
Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX A.ISO14443 TYPE B CRC CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4/40
CRX14
SUMMARY DESCRIPTION
The CRX14 is a contactless coupler that is compli-
ant with the short range ISO14443 type-B stan-
dard. It is controlled using the two wire I²C bus.
antenna. The resulting field is 10% modulated
using ASK (amplitude shift keying) for
outgoing data.
The CRX14 generates a 13.56MHz signal on an
external antenna. Transmitted data are modulated
using Amplitude Shift Keying (ASK). Received
data are demodulated from the PICC (Proximity in-
tegrated Coupling Card) load variation signal, in-
duced on the antenna, using Bit Phase Shift
Keying (BPSK) of a 847kHz sub-carrier. The
Transmitted ASK wave is 10% modulated. The
Data transfer rate between the CRX14 and the
PICC is 106 Kbit/s in both transmission and recep-
tion modes.
■
The receiver. It demodulates the signal
generated on the antenna by the load variation
of the PICC. The resulting signal is decoded
by a 847kHz BPSK (binary phase shift keying)
sub-carrier decoder.
The CRX14 is designed to be connected to a digi-
tal host (Microcontroller or ASIC). This host has to
manage the entire communication protocol in both
transmit and receive modes, through the I²C serial
bus.
The CRX14 follows the ISO14443 type-B recom-
mendation for Radio frequency power and signal
interface.
The CRX14 is specifically designed for short range
applications that need disposable, or secure and
re-usable, products.
The CRX14 includes an automated anti-collision
mechanism that allows it to detect and select any
ST short range memories that are present at the
same time within its range. The anti-collision
mechanism is based on the STMicroelectronics
probabilistic scanning method.
Figure 2. Logic Diagram
V
V
REF
CC
RF
OUT
OSC1
OSC2
SCL
SDA
E0
CRX14
Antenna
The CRX14 provides an anti-clone function, from
E1
E2
FRANCE
TELECOM,
which
allows
the
authentication of the ST short range memories.
Using the CRX14 single chip coupler, therefore, it
is easy to design a reader, with authentication ca-
pability and to build an end application with a high
level of security at low cost.
RF
IN
GND
GND_RF
The CRX14 provides a complete analog interface,
AI06828B
compliant
with
the
ISO14443
type-B
recommendations for Radio-Frequency power
and signal interfacing. With it, any ISO14443 type-
B PICC products can be powered and have their
data transmission controlled via a simple antenna.
The CRX14 is fabricated in STMicroelectronics
High Endurance Single Poly-silicon CMOS tech-
nology.
Table 1. Signal Names
RF
RF
Antenna Output Driver
Antenna Input Filter
Oscillator Input
Oscillator Output
Chip Enable Inputs
I²C Bi-Directional Data
I²C Clock
OUT
IN
OSC1
OSC2
E0, E1, E2
SDA
The CRX14 is organized as 4 different blocks (see
Figure 3.):
■
The I²C bus controller. It handles the serial
connection with the application host. It is
compliant with the 400kHz I²C bus
specification, and controls the read/write
access to all the CRX14 registers.
SCL
■
■
The RAM buffer. It is bi-directional. . It stores
all the request frame Bytes to be transmitted to
the PICC, and all the received Bytes sent by
the PICC on the answer frame.
The transmitter. It powers the PICCs by
generating a 13.56MHz signal on an external
V
Power Supply
CC
GND
Ground
V
Transmitter Reference Voltage
Ground for RF circuitry
REF
GND_RF
5/40
CRX14
Figure 3. Logic Block Diagram
Figure 4. SO Pin Connections
SO16
V
V
REF
CC
1
2
3
4
5
6
7
8
V
16
V
REF
RF
CC
OUT
CRX14
15 RF
IN
OSC1
RF
OUT
E0
E1
14 GND_RF
13 OSC1
12 OSC2
11 GND
OSC2
E2
SCL
SDA
E0
E1
E2
Antenna
GND_RF
GND
10 SCL
GND
9
SDA
AI10911
RF
IN
GND GND_RF
AI10910
6/40
CRX14
SIGNAL DESCRIPTION
See Figure 2., and Table 1., for an overview of the
signals connected to this device.
resistor must be connected from the Serial Clock
(SCL) to V . ( Figure 6. indicates how the value
CC
of the pull-up resistor can be calculated).
Oscillator (OSC1, OSC2). The OSC1 and OSC2
pins are internally connected to the on-chip oscil-
lator circuit. The OSC1 pin is the input pin, the
OSC2 is the output pin. For correct operation of
the CRX14, it is required to connect a 13.56MHz
quartz crystal across OSC1 and OSC2. If an exter-
nal clock is used, it must be connected to OSC1
and OSC2 must be left open.
In most applications, though, this method of syn-
chronization is not employed, and so the pull-up
resistor is not necessary, provided that the master
has a push-pull (rather than open drain) output.
Serial Data (SDA). The SDA signal is bi-direc-
tional. It is used to transfer I²C data in and out of
the CRX14. It is an open drain output that may be
wire-OR’ed with other open drain or open collector
signals on the bus. A pull-up resistor must be con-
Antenna Output Driver (RF ). The Antenna
OUT
Output Driver pin, RF , generates the modulat-
OUT
nected from Serial data (SDA) to V . (Figure 6.
CC
ed 13.56MHz signal on the antenna. Care must be
taken as it will not withstand a short-circuit.
indicates how the value of the pull-up resistor can
be calculated).
RF
has to be connected to the antenna circuit-
OUT
ry as shown in Figure 5. The LRC antenna circuitry
Chip Enable (E0, E1, E2). The Chip Enable in-
puts E0, E1, E2 are used to set and reset the value
on the three least significant bits (b3, b2, b1) of the
7-bit I²C Device Select Code. They are used for
hardwired addressing, allowing up to eight CRX14
devices to be addressed on the same I²C bus.
These inputs may be driven dynamically or tied to
must be connected across the RF
GND.
pin and
OUT
Antenna Input Filter (RF ). The antenna input
IN
filter of the CRX14, RF , has to be connected to
IN
the external antenna through an adapter circuit, as
shown in Figure 5.
V
or GND to establish the Device Select Code
CC
(note that the V and V levels for the inputs are
CMOS compatible, not TTL compatible).
When left open, E0, E1 and E2 are internally read
at the logic level 0 due to the internal pull-down re-
sistors connected to each inputs.
IL
IH
The input filter demodulates the signal generated
on the antenna by the load variation of the PICC.
The resulting signal is then decoded by the
847kHz BPSK decoder.
Transmitter Reference Voltage (V ). The
REF
Transmitter Reference Voltage input, V
vides a reference voltage used by the output driver
for ASK modulation.
, pro-
Power Supply (V , GND, GND_RF). Power is
REF
CC
supplied to the CRX14 using the V , GND and
CC
GND_RF pins.
The Transmitter Reference Voltage input should
be connected to an external capacitor, as shown in
Figure 5.
V
is the Power Supply pin that supplies the pow-
CC
er (+5V) for all CRX14 operations.
The GND and GND_RF pins are ground connec-
tions. They must be connected together.
Decoupling capacitors should be connected be-
tween the V
Serial Clock (SCL). The SCL input pin is used to
strobe all I²C data in and out of the CRX14. In ap-
plications where this line is used by slave devices
to synchronize the bus to a slower clock, the mas-
ter must have an open drain output, and a pull-up
Supply Voltage pin, the GND
CC
Ground pin and the GND_REF Ground pin to filter
the power line, as shown in Figure 5.
7/40
CRX14
Figure 5. CRX14 Application Schematic
D1
1N4148 (OPTIONAL)
V
C6 CC
C8
100pF50V
V
CC
100nF50V
C5
R8
10pF50V
OPT
R1
ANT1
OPT
R3
C8'
8pF50V
0R
OPT C3 WURTH 742-792-042U1
C1 7pF50V
FL7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
CC
REF
IN
R5
RF
E0
E1
E2
RF
OUT
GND_RF
OSC1
22nF50V
X1
E0
0R
13.56MHz
C7
C7'
E1
0R
OSC2
120pF50V 33pF50V
E2
0R
GND_RF GND
GND
GND
R2
SCL
SDA
R4
R6
C2 7pF50V
CRX14
R7
ANT2
0R
J1
SDASCL
0R
FL5
4
3
2
1
FL4
V
CC
0R
0R
FL6
C4
22uF 10V
+
AI10952
²
Figure 6. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
L
R
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
8/40
CRX14
CRX14 REGISTERS
The CRX14 chip coupler contains six volatile reg-
isters. It is entirely controlled, at both digital and
analog level, using the four registers listed below
and shown in Table 2.:
The other 2 registers are located at addresses 04h
and 05h. They are “ST Reserved”, and must not
be used in end-user applications.
In the I²C protocol, all data Bytes are transmitted
Most Significant Byte first, with each Byte transmit-
ted Most significant bit first.
■
■
■
■
Parameter Register
Input/Output Frame Register
Authentication Register
Slot Marker Register
Table 2. CRX14 Control Registers
Address
Length
Access
Purpose
Set parameter register
W
R
00h
01h
02h
03h
Parameter Register
1 Byte
Read parameter register
Store and send request frame to the PICC.
Wait for PICC answer frame
W
Input/output Frame Register
Authenticate Register
Slot Marker Register
36 Bytes
NA
R
Transfer PICC answered frame data to Host
Start the Authentication process
Get the Authentication status
W
R
Launch the automated anti-collision process
from Slot_0 to Slot_15
W
1 Byte
R
Return data FFh
04h
05h
ST Reserved
ST Reserved
NA
NA
R and W ST Reserved. Must not be used
R and W ST Reserved. Must not be used
Parameter Register (00h)
located at the I²C address 00h and it is accessible
in I²C Read and Write modes. Its default value,
00h, puts the CRX14 in standard ISO14443 type-
B configuration.
The Parameter Register is an 8-bit volatile register
used to configure the CRX14, and thus, to custom-
ize the circuit behavior. The Parameter Register is
Table 3. Parameter Register Bits Description
Bit
Control
Frame Standard
RFU
Value
Description
0
ISO14443 type-B frame management
b
0
1
2
1
0
0
1
0
1
0
1
RFU
b
b
Not used
Answer PICC Frames are delimited by SOF and EOF
Answer PICC Frames do not provide SOF and EOF delimiters
10% ASK modulation depth mode
RFU
Answer Frame Format
b
ASK Modulation Depth
Carrier Frequency
3
13.56MHz carrier on RF OUT is OFF
13.56MHz carrier on RF OUT is ON
b
b
b
b
4
5
6
7
b5=0, b6=0: Watchdog time-out = 500µs to be used for read
b5=0, b6=1: Watchdog time-out = 5ms to be used for authentication
b5=1, b6=0: Watchdog time-out = 10ms to be used for write
b5=1, b6=1: Watchdog time-out = 309ms to be used for MCU timings
t
WDG
Answer delay watchdog
RFU
0
Not used
Note: RFU = Reserved for Future Use.
9/40
CRX14
Input/Output Frame Register (01h)
Byte 1 onwards. Byte 0 stores the number of Bytes
received from the PICC.
When accessed in I²C Read mode, the Input/Out-
put Register sends back the last PICC answer
frame Bytes, if any, with Byte 0 transmitted first.
The 16-bit CRC is not stored, and it is not sent
back on the I²C bus.
The Input/Output Frame Register is set to all 00h
between transmission and reception. If there is no
answer from the PICC, Byte 0 is set to 00h. In the
case of a CRC error, Byte 0 is set to FFh, and the
data Bytes are discarded and not appended in the
register.
The Input/Output Frame Register is a 36-Byte
buffer that is accessed serially from Byte 0 through
to Byte 35 (see Table 4.). It is located at the I²C ad-
dress 01h.
The Input/Output Frame Register is the buffer in
which the CRX14 stores the data Bytes of the re-
quest frame to be sent to the PICC. It automatical-
ly stores the data Bytes of the answer frame
received from the PICC. The first Byte (Byte 0) of
the Input/Output Frame Register is used to store
the frame length for both transmission and recep-
tion.
The CRX14 Input/Output Frame Register is so de-
signed as to generate all the ST short range mem-
ory command frames. It can also generate all
standardized ISO14443 type-B command frames
like REQB, SLOT-MARKER, ATTRIB, HALT, and
get all the answers like ATQB, or answer to AT-
TRIB. All ISO14443 type-B compliant PICCs can
be accessed by the CRX14 provided that their
data frame exchange is not longer than 35 Bytes
in both request and answer.
When accessed in I²C Write mode , the register
stores the request frame Bytes that are to be
transmitted to the PICC. Byte 0 must be set with
the request frame length (in Bytes) and the frame
is stored from Byte 1 onwards. At the end of the
transmission, the 16-bit CRC is automatically add-
ed. After the transmission, the CRX14 wait for the
PICC to send back an answer frame. When cor-
rectly decoded, the PICC answer frame Bytes are
stored in the Input/Output Frame Register from
Table 4. Input/Output Frame Register Description
Byte 0
Byte 1
Byte 2
Byte 3
...
Byte 34
Byte 35
Frame Length
First data Byte
Second data Byte
Last data Byte
<------------- Request and Answer Frame Bytes exchanged on the RF ------------->
00h No Byte transmitted
FFh CRC Error
xxh Number of transmitted Bytes
Authenticate Register (02h)
collision sequence between the CRX14 and any
ST short range memory present in the electromag-
netic field. With one I²C access, the CRX14
launches a complete stream of commands starting
The Authenticate Register is used to trigger the
complete authentication exchange between the
CRX14 and the secured ST short range memory.
It is located at the I²C address 02h.
The Authentication system is based on a propri-
etary challenge/response mechanism that allows
the application software to authenticate a secured
ST short range memory of the SRXxxx family. A
reader designed with the CRX14 can check the
authenticity of a memory device and protect the
application system against silicon copies or emu-
lators.
A complete description of the Authentication sys-
tem is available under Non Disclosure Agreement
(NDA) with STMicroelectronics. For more details
about this CRX14 function, please contact the
nearest STMicroelectronics sales office.
from
PCALL16(),
SLOT_MARKER(1),
SLOT_MARKER(2) up to SLOT_MARKER(15),
and stores all the identified Chip_IDs into the In-
put/Output Frame Register (I²C address 01h).
This automated anti-collision sequence simplifies
the host software development and reduces the
time needed to interrogate the 16 slots of the ST-
Microelectronics anti-collision mechanism.
When accessed in I²C Write mode, the Slot Marker
Register starts generating the sequence of anti-
collision commands. After each command, the
CRX14 wait for the ST short range memory an-
swer frame which contains the Chip_ID. The valid-
ity of the answer is checked and stored into the
corresponding Status Slot Bit (Byte 1 and Byte 2
as described in Table 6.). If the answer is correct,
the Status Slot Bit is set to ‘1’ and the Chip_ID is
stored into the corresponding Slot_Register. If no
answer is detected, the Status Slot Bit is set to ‘0’,
and the corresponding Slot_Register is set to 00h.
Slot Marker Register (03h)
The slot Marker Register is located at the I²C ad-
dress 03h. It is used to trigger an automated anti-
10/40
CRX14
If a CRC error is detected, the Status Slot Bit is set
to ‘0’, and the corresponding Slot_Register is set
to FFh.
Each time the Slot Marker Register is accessed in
I²C Write mode, Byte 0 of the Input/Output Frame
Register is set to 18, Bytes 1 and 2 provide Status
Bits Slot information, and Bytes 3 to 18 store the
corresponding Chip_ID or error code.
The Slot Marker Register cannot be accessed in
I²C Read mode. All the anti-collision data can be
accessed by reading the Input/Output Frame Reg-
ister at the I²C address 01h.
Table 5. Slot Marker Register Description
b
b
b
b
b
b
b
b
0
7
6
5
4
3
2
1
Byte 0
Byte 1
Number of stored Bytes: fixed to 18
Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte n
Byte 17
Byte 18
Slot_Register 0 = Chip_ID value detected in Slot 0
Slot_Register 1 = Chip_ID value detected in Slot 1
Slot_Register 2 = Chip_ID value detected in Slot 2
Slot_Register 3 = Chip_ID value detected in Slot 3
.....
Slot_Register 14 = Chip_ID value detected in Slot 14
Slot_Register 15 = Chip_ID value detected in Slot 15
Status bit value description:
1: No error detected. The Chip_ID stored in the Slot register is valid.
0: Error detected
- Slot register = 00h: No answer frame detected from ST short range memory
- Slot register = FFh: Answer Frame detected with CRC error. Collision may have occurred
11/40
CRX14
CRX14 I²C PROTOCOL DESCRIPTION
The CRX14 is compatible with the I²C serial bus
memory standard, which is a two-wire serial inter-
face that uses a bi-directional data bus and serial
clock.
The CRX14 has a pre-programmed, 4-bit identifi-
cation code, ’1010’ (as shown in Table 6.), that
corresponds to the I²C bus definition. With this
code and the three Chip Enable inputs (E2, E1,
E0) up to eight CRX14 devices can be connected
to the I²C bus, and selected individually.
The CRX14 behaves as a slave device in the I²C
protocol, with all CRX14 operations synchronized
to the serial clock.
I²C Read and Write operations are initiated by a
START condition, generated by the bus master.
When data is written to the CRX14, the device in-
serts an acknowledge bit (9th bit) after the bus
master’s 8-bit transmission.
When the bus master reads data, it also acknowl-
edges the receipt of the data Byte by inserting an
acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition
after an ACK for Write, or after a NoACK for Read.
The CRX14 supports the I²C protocol, as summa-
rized in Figure 7.
Any device that sends data on to the bus, is de-
fined as a transmitter, and any device that reads
the data, as a receiver.
The device that controls the data transfer is known
as the master, and the other, as the slave. A data
transfer can only be initiated by the master, which
also provides the serial clock for synchronization.
The CRX14 is always a slave device in all I²C com-
munications. All data are transmitted Most Signifi-
cant Bit (MSB) first.
The START condition is followed by the Device
Select Code and by a Read/Write bit (R/W). It is
terminated by an acknowledge bit. The Device Se-
lect Code consists of seven bits (as shown in Ta-
ble 6.):
■
the Device Code (first four bits)
■
plus three bits corresponding to the states of
the three Chip Enable inputs, E2, E1 and E0,
respectively
Table 6. Device Select Code
Device Code
b6 b5
Chip Enable
RW
b0
b7
b4
0
b3
E2
b2
E1
b1
E0
1
0
1
RW
CRX14 Select
I²C Start Condition
A STOP condition at the end of an I²C Write com-
mand triggers the Radio Frequency data ex-
change between the CRX14 and the PICC.
START is identified by a High-to-Low transition of
the Serial Data line, SDA, while the Serial Clock,
SCL, is stable in the High state. A START condi-
tion must precede any data transfer command.
I²C Acknowledge Bit (ACK)
An acknowledge bit is used to indicate a success-
ful data transfer on the I²C bus.
The bus transmitter, either master or slave, releas-
es the Serial Data line, SDA, after sending 8 bits of
data. During the 9th clock pulse the receiver pulls
the SDA line Low to acknowledge the receipt of
the 8 data bits.
The CRX14 continuously monitors the SDA and
SCL lines for a START condition (except during
Radio Frequency data exchanges), and will not re-
spond unless one is sent.
I²C Stop Condition
STOP is identified by a Low-to-High transition of
the Serial Data line, SDA, while the Serial Clock,
SCL, is stable in the High state.
I²C Data Input
During data input, the CRX14 samples the SDA
bus signal on the rising edge of the Serial Clock,
SCL. For correct device operation, the SDA signal
must be stable during the Low-to-High Serial
Clock transition, and the data must change only
when the SCL line is Low
A STOP condition terminates communications be-
tween the CRX14 and the bus master.
A STOP condition at the end of an I²C Read com-
mand, after (and only after) a NoACK, forces the
CRX14 into its stand-by state.
12/40
CRX14
Figure 7. I²C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
I²C Memory Addressing
ACK. They deselect themselves from the bus and
go into stand-by mode.
To start up communication with the CRX14, the
bus master must initiate a START condition. Then,
the bus master sends 8 bits (with the most signifi-
cant bit first) on the Serial Data line, SDA. These
bits consist of the Device Select Code (7 bits) plus
a RW bit.
According to the I²C bus definition, the seven most
significant bits of the Device Select Code are the
Device Type Identifier. For the CRX14, these bits
are defined as shown in Table 6.
CRX14 I²C Write Operations
The bus master sends a START condition, fol-
lowed by a Device Select Code and the R/W bit set
to ’0’. The CRX14 that corresponds to the Device
Select Code, acknowledges and waits for the bus
master to send the Byte address of the register
that is to be written to. After receipt of the address,
the CRX14 returns another ACK, and waits for the
bus master to send the data Bytes that are to be
written.
The 8th bit is the Read/Write bit (RW). It is set to
‘1’ for I²C Read, and to ‘0’ for I²C Write operations.
In the CRX14 I²C Write mode, the bus master may
sends one or more data Bytes depending on the
selected register.
The CRX14 replies with an ACK after each data
Byte received. The bus master terminates the
transfer by generating a STOP condition.
If the data sent by the bus master matches the De-
vice Select Code of a CRX14 device, the corre-
sponding device returns an acknowledgment on
the SDA bus during the 9 bit time.
The CRX14 devices whose Device Select Codes
do not correspond to the data sent, generate a No-
th
13/40
CRX14
The STOP condition at the end of a Write access
to the Input/Output Frame, Authenticate or Anti-
Collision Register, causes the Radio Frequency
data exchange between the CRX14 and the PICC
to be started.
■
■
Initial condition: a Radio Frequency data
exchange is in progress.
Step 1: the master issues a START condition
followed by the first Byte of the new instruction
(Device Select Code plus R/W bit).
During the Radio Frequency data exchange, the
CRX14 disconnects itself from the I²C bus. The
■
Step 2: if the CRX14 is busy, no ACK is
returned and the master goes back to Step 1.
If the CRX14 has completed the Radio
Frequency data exchange, it responds with an
ACK, indicating that it is ready to receive the
second part of the next instruction (the first
Byte of this instruction being sent during Step
1).
time (t
) needed to complete the exchange is
RFEX
not fixed as it depends on the PICC command for-
mat. To know when the exchange is complete, the
bus master uses an ACK polling sequence as
shown in Figure 9. It consists of the following:
Figure 8. CRX14 I²C Write Mode Sequence
R/W
DEV SEL
BYTE ADDR
DATA 1
DATA 2
DATA 3
DATA N
BUS Master
CRX14 WRITE
BUS Slave
ACK
ACK
ACK
ACK
ACK
ACK
AI09265
14/40
CRX14
Figure 9. I²C Polling Flowchart using ACK
Radio Frequency
data exchange
in progress
START Condition
DEVICE SELECT
CODE with R/W=1
ACK
NO
returned
First byte of instruction
with R/W = 1 already
decoded by the CRX14
YES
Next
operation is
addressing
the CRX14
NO
YES
Proceed to READ
Operation
ReSTART
STOP
STOP
ai09234
15/40
CRX14
CRX14 I²C Read Operations
In the I²C Read mode, the CRX14 may read one
or more data Bytes depending on the selected reg-
ister. The bus master has to generate an ACK af-
ter each data Byte to read all the register data in a
continuous stream. Only the last data Byte should
not be followed by an ACK. The master then termi-
nates the transfer with a STOP condition, as
shown in Figure 10.
To send a Read command, the bus master sends
a START condition, followed by a Device Select
Code and the R/W bit set to ’1’.
The CRX14 that corresponds to the Device Select
Code acknowledges and outputs the first data
Byte of the addressed register.
To select a specific register, a dummy Write com-
mand must first be issued, giving an address Byte
but no data Bytes, as shown in the bottom half of
Figure 10. This causes the new address to be
stored in the internal address pointer, for use by
the Read command that immediately follows the
dummy Write command.
After reading each Byte, the CRX14 waits for the
master to send an ACK during the 9 bit time. If
the master does not return an ACK within this time,
the CRX14 terminates the data transfer and
switches to stand-by mode.
th
Figure 10. CRX14 I²C Read Modes Sequences
I²C CURRENT ADDRESS READ
ACK
ACK
ACK
ACK
NoACK
R/W
DEV SEL
BUS Master
CRX14 READ
BUS Slave
DATA 1
DATA 2
DATA 3
DATA 4
DATA N
ACK
I²C RANDOM ADDRESS READ
R/W
R/W
DEV SEL
ACK
ACK
NoACK
BUS Master
CRX14 READ
BUS Slave
DEV SEL
ADDRESS
DATA 1
DATA 2
DATA N
ACK
ACK
ACK
AI09266
16/40
CRX14
APPLYING THE I²C PROTOCOL TO THE CRX14 REGISTERS
I²C Parameter Register Protocol
Parameter Register contents until it receives a
NoACK from the I²C Host.
The CRX14 supports the I²C Current Address and
Random Address Read modes. The Current Ad-
dress Read mode can be used if the previous
command was issued to the register where the
Read is to take place.
Figure 11. shows how new data is written to the
Parameter Register. The new value becomes ac-
tive after the I²C STOP condition.
Figure 12. shows how to read the Parameter Reg-
ister contents. The CRX14 sends and re-sends the
Figure 11. Host-to-CRX14 Transfer: I²C Write to Parameter Register
S
T
R/W
S
T
O
P
A
R
T
Bus Master
Device Select
Code
Parameter Register
Address
Register Byte
Value
CRX14 Write
Bus Slave
1 0 1 0 X X X
00h
data
ACK
ACK
ACK
ai09240
Figure 12. CRX14-to-Host Transfer: I²C Random Address Read from Parameter Register
R
E
S
T
A
R
T
S
T
A
R
T
R/W
R/W
NoACK
S
T
O
P
Device Select
Code
Parameter Register
Address
Device Select
Code
Bus Master
1 0 1 0 X X X
00h
1 0 1 0 X X X
data
CRX14 Read
Bus Slave
Register Byte
Value
ACK
ACK
ACK
ai09241
Figure 13. CRX14-to-Host Transfer: I²C Current Address Read from Parameter Register
S
R/W
NoACK
T
A
R
T
S
T
Device Select
Code
Bus Master
O
P
1 0 1 0 X X X
data
CRX14 Read
Bus Slave
Register Byte
Value
ACK
ai09242
17/40
CRX14
I²C Input/Output Frame Register Protocol
The two CRC Bytes generated by the PICC are
not stored.
Figure 14. shows how to store a PICC request
frame command of N Bytes into the Input/Output
Frame Register.
After the I²C STOP condition, the request frame is
RF transmitted in the ISO14443 type-B format.
The CRX14 then waits for the PICC answer frame
which will also be stored in the Input/Output Frame
Register. The request frame is over-written by the
answer frame.
The CRX14 continues to output data Bytes until a
NoACK has been generated by the I²C Host, and
received by the CRX14. After all 36 Bytes have
been output, the CRX14 “rolls over”, and starts
outputting from the start of the Input/Output Frame
Register again.
The CRX14 supports the I²C Current Address and
Random Address Read modes. The Current Ad-
dress Read mode can be used if the previous
command was issued to the register where the
Read is to take place.
Figure 15. shows how to read an N-Byte PICC an-
swer frame.
Figure 14. Host-to-CRX14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B
S
T
A
R
T
R/W
S
T
O
P
Device
Select
Code
Input/Output
Register
Address
PICC
Command
Code
PICC
Command
Parameter
PICC
Command
Parameter
PICC
Command
Parameter
Bus
Master
Request Frame
Length N
CRX14
Write
1 0 1 0 XX X
01h
N
Data 1
Data 2
Data N
Bus
Slave
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ai09243
Figure 15. CRX14-to-Host Transfer: I²C Random Address Read
from Input/Output Frame Register for ISO14443B
R
E
S
T
A
R
T
R/W
R/W
ACK
ACK
ACK
ACK
NoACK
S
T
A
R
T
Device
Select
Code
Input/Output
Register
Address
Device
Select
Code
S
T
O
P
Bus
Master
CRX14
Read
1 0 1 0XXX
01h
1 0 1 0 XXX
N
Data1
Data 2
Data N
Received
Frame
Length
Answer
Frame
Data
Answer
Frame
Data
Answer
Frame
Data
Answer
Frame
Data
Bus
Slave
ACK
ACK
ACK
ai09243
Figure 16. CRX14-to-Host Transfer: I²C Current Address Read
from I/O Frame Register for ISO14443B
S
ACK
ACK
ACK
ACK
NoACK
R/W
T
A
R
T
Device
Select
Code
S
T
O
P
Bus Master
CRX14 Write
Bus Slave
1 0 1 0 XX X
N
Data 1
Data 2
Data N
Received
Frame Length
Answer Frame Answer Frame Answer Frame Answer Frame
Data Data Data Data
ACK
ai09245
18/40
CRX14
I²C Authenticate Register Protocol
Read from the I²C Slot Marker Register is not sup-
ported by the CRX14. If the I²C Host tries to read
the Slot Marker Register, the CRX14 will return the
data value FFh in both Random Address and Cur-
rent Address Read modes until NoACK is generat-
ed by the I²C Host.
For information please contact your nearest STMi-
croelectronics sales office.
I²C Slot Marker Register Protocol
The result of the detection sequence is stored in
the Input/Output Frame Register. This Register
can be read by the host by using I²C Random Ad-
dress Read.
An I²C Write command to the Slot Marker Register
generates an automated sixteen-command loop
(See Figure 17. for a description of the command).
All the answers from the ST short range memory
devices that are detected, are written in the Input/
Output Frame Register.
Figure 17. Host-to-CRX14 Transfer: I²C Write to Slot Marker Register
S
R/W
T
S
T
Slot Marker
A
Device Select
Code
Bus Master
Register
Address
R
T
O
P
1 0 1 0 X X X
03h
CRX14 Write
Bus Slave
ACK
ACK
ai09246
Figure 18. CRX14-to-Host Transfer: I²C Random Address Read from Slot Marker Register
R
E
S
T
A
R
T
S
T
A
R
T
R/W
R/W
NoACK
S
T
O
P
Slot Marker
Register
Address
Device Select
Code
Device Select
Code
Bus Master
1 0 1 0 X X X
00h
1 0 1 0 X X X
FFh
CRX14 Read
Bus Slave
ACK
ACK
ACK
ai09247
Figure 19. CRX14-to-Host Transfer: I²C Current Address Read from Slot Marker Register
S
R/W
NoACK
T
A
R
T
S
T
Device Select
Code
Bus Master
O
P
1 0 1 0 X X X
FFh
CRX14 Read
Bus Slave
ACK
ai09248
19/40
CRX14
Addresses above Location 06h
the 9th bit time. The SDA line stays High until the
STOP condition is issued.
In I²C Write mode, when the CRX14 receives the
8-bit register address, and the address is above lo-
cation 06h, the device does not acknowledge
(NoACK) and deselects itself from the bus. The
Serial Data line, SDA, stays at logic ‘1’ (pull-up re-
sistor), and the I²C Host receives a NoACK during
In the I²C Current and Random Address Read
modes, when the CRX14 receives the 8-bit regis-
ter address, and the address is above location
06h, the device does not acknowledge the Device
Select Code after the START condition, and dese-
lects itself from the bus.
20/40
CRX14
CRX14 ISO14443 TYPE-B RADIO FREQUENCY DATA TRANSFER
Output RF Data Transfer from the CRX14 to the
PICC (Request Frame)
If the antenna is correctly tuned, it emits an H-field
of a large enough magnitude to power a contact-
less PICC from a short distance. The energy re-
ceived on the PICC antenna is converted to a
Power Supply Voltage by a regulator, and turned
into data bits by the ASK demodulator. The
CRX14 amplitude modulates the 13.56MHz wave
by 10% as represented in Figure 20. The data
transfer rate is 106 kbit/s.
The CRX14 output buffer is controlled by the
13.56MHz clock signal generated by the external
oscillator and by the request frame generator. The
CRX14 can be directly connected to an external
matching circuit to generate a 13.56MHz sinusoi-
dal carrier frequency on its antenna.
The current driven into the antenna coil is directly
generated by the CRX14 RFOUT output driver.
Figure 20. Wave Transmitted using ASK Modulation
DATA BIT TRANSMITTED
BY THE CRX14
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE RF
DRIVER
OUT
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED ON THE CRX14
ANTENNA
Transfer time for one data bit is 1/106 kHz
AI10912
Transmission Format of Request Frame
Characters
Frame (EOF), constitute a Request Frame, as
shown in Figure 27.
A Request Frame includes the SOF, instructions,
addresses, data, CRC and the EOF as defined in
the ISO14443 type-B.
The CRX14 transmits characters of 10 bits, with
the Least Significant Bit (b ) transmitted first, as
0
shown in Figure 21.
Each bit duration is called an Elementary Time
Unit (ETU). One ETU is equal to 9.44µs (1/
106kHz).
Several 10-bit characters, preceded by the Start
Of Frame (SOF) and followed by the End Of
Figure 21. CRX14 Request Frame Character Format
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
1
ETU
Start
'0'
Stop
'1'
LSB
Information Byte
MSB
ai09250
21/40
CRX14
Table 7. CRX14 Request Frame Character Format
Bit
Description
Value
b
b = 0
0
Start bit used to synchronize the transmission
0
Information Byte is sent Least Significant Bit
first
b to b
Information Byte (instruction, address or data)
Stop bit used to indicate the end of the character
1
8
b
b = 1
9
9
Request Start Of Frame
The Start Of Frame (SOF) described in Figure 22.
consists of:
–
–
a falling edge,
followed by ten Elementary Time Units (ETU)
each containing a logical ‘0’
–
–
followed by a single rising edge
followed by two ETUs, each containing a
logical ‘1’.
Figure 22. Request Start Of Frame
b
b
b
b
b
b
b
b
b
b
b
b
11
0
1
2
3
4
5
6
7
8
9
10
ETU
0
0
0
0
0
0
0
0
0
0
1
1
ai09251
Request End Of Frame
The End Of Frame (EOF) shown in Figure 23. con-
sists of:
–
–
a falling edge,
followed by ten Elementary Time Units (ETU)
containing each a logical ‘0’,
–
followed by a single rising edge.
Figure 23. Request End Of Frame
b
b
b
b
b
b
b
b
b
b
9
0
1
2
3
4
5
6
7
8
ETU
0
0
0
0
0
0
0
0
0
0
ai09252
22/40
CRX14
Input RF Data Transfer from the PICC to the
CRX14 (Answer Frame)
a voltage variation on the antenna. The RF input
demodulates this variation and decodes the infor-
mation received from the PICC.
IN
The CRX14 uses the ISO14443 type-B retro-mod-
ulation scheme which is demodulated and decod-
Data must be transmitted using a 847kHz, BPSK
modulated sub-carrier frequency, f , as shown in
S
ed by the RF circuitry.
IN
Figure 24., and as specified in ISO14443 type-B.
In BPSK, all data state transitions (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) are encoded by phase shift keying
the sub-carrier.
The modulation is obtained by modifying the PICC
current consumption (load modulation). This load
modulation induces an H-field variation, by cou-
pling, that is detected by the CRX14 RF input as
IN
Figure 24. Wave Received using BPSK Sub-carrier Modulation
1/106kHz
PICC data bit to be transmitted
to the CRX14.
847kHz BPSK, resulting signal
generated by the PICC for the
load modulation.
1/847kHz
phase shift
V
RFIN
V
RET
Load modulation effect on
the H-Field received on the
V
DYN
CRX14 RF input pad
IN
V
OFFSET
t
ai09253
Transmission Format of Answer Frame
Characters
An Answer Frame includes the SOF, data, CRC
and the EOF, as illustrated in Figure 27.. The data
transfer rate is 106 kbit/s.
The CRX14 will also accept Answer Frames that
do not contain the SOF and EOF delimiters, pro-
vided that these Frames are correctly set in the
Parameter Register. (See Figure 27.).
The PICC should use the same character format
as that used for output data transfer (see Figure
21.).
23/40
CRX14
Answer Start Of Frame
The PICC SOF must be compliant with the
ISO14443 type-B, and is shown in Figure 25.
–
Ten or eleven Elementary Time Units (ETU)
each containing a logical ‘0’,
–
Two ETUs containing a logical ‘1’.
Figure 25. Answer Start Of Frame
b
b
b
b
b
b
b
b
b
b
b
b
11
b
0
1
2
3
4
5
6
7
8
9
10
12
ETU
0
0
0
0
0
0
0
0
0
0
1
1
1
ai09254
Answer End Of Frame
The PICC EOF must be compliant with the
ISO14443 type-B, and is shown in Figure 26.
–
Ten or eleven Elementary Time Units (ETU)
each containing a logical ‘0’,
–
Two ETUs containing a logical ‘1’
Figure 26. Answer End Of Frame
b
b
b
b
b
b
b
b
b
b
b
b
b
0
1
2
3
4
5
6
7
8
9
10
11
12
ETU
0
0
0
0
0
0
0
0
0
0
1
1
1
ai09254
24/40
CRX14
Transmission Frame
13.56MHz carrier frequency is modulated by the
PICC at 847kHz for a minimum time of t (see Ta-
1
The Request Frame transmission must be fol-
lowed by a minimum delay, t (see Table 13.), in
which no ASK or BPSK modulation occurs, before
the Answer Frame can be transmitted. t is the
minimum time required by the CRX14 to switch
from transmission mode to reception mode, and
ble 13.) to allow the CRX14 to synchronize. After
0
t , the first phase transition generated by the PICC
1
represents the start bit (‘0’) of the Answer SOF (or
the start bit ‘0’ of the first data character in non
SOF/EOF mode).
0
should be inserted after each frame. After t , the
0
Figure 27. Example of a Complete Transmission Frame
SOF
Cmd
Data
CRC
CRC
EOF
Sent by
12 bits
10 bits
10 bits
10 bits
10 bits
10 bits
the CRX14
at 106Kb/s
t
DR
f
= 847.5kHz
Sync
s
SOF
Data
CRC
CRC
EOF
Case of Answer Frame with SOF & EOF
Sent by the PICC
t
t
12 or 13 10 bits 10 bits 10 bits 12 or 13
0
1
bits
64/f Min
80/f Min
bits
s
s
t
WDG
Sync
Data
Data
Data
CRC
CRC
Case of Answer Frame without SOF & EOF
t
t
1
10 bits 10 bits 10 bits 10 bits 10 bits
0
64/f Min
s
80/f Min
s
t
WDG
Output Data Transfer using ASK Modulation
Input Data Transfer using 847kHz BPSK Modulation
ai09255
CRC
invalid, it stores the value FFh in the Input/Output
Frame Register.
The CRC is transmitted Least Significant Byte first.
Each Byte is transmitted Least Significant Bit first.
The 16-bit CRC used by the CRX14 follows the
ISO14443 type B recommendation. For further in-
formation, please see APPENDIX A., page 38.
The two CRC Bytes are present in all Request and
Answer Frames, just before the EOF. The CRC is
calculated on all the Bytes between the SOF and
the CRC Bytes.
Upon transmission of a Request from the CRX14,
the PICC verifies that the CRC value is valid. If it is
invalid, it discards the frame and does not answer
the CRX14.
Figure 28. CRC Transmission Rules
LSByte
MSByte
LSBit
MSBit LSBit
MSBit
CRC 16 (8 bits)
CRC 16 (8 bits)
Upon reception of an Answer from the PICC, the
CRX14 verifies that the CRC value is valid. If it is
ai09256
25/40
CRX14
TAG ACCESS USING THE CRX14 COUPLER
In all the following I²C commands, the last three
bits of the Device Select Code can be replaced by
any of the three-bit binary values (000, 001, 010,
011, 100, 101, 110, 111). These values are linked
to the logic levels applied to the E2, E1 and E0
pads of the CRX14.
ure 14., page 18. After the I²C STOP condition, the
CRX14 inserts the I²C Bytes in the required ISO
character format ( Figure 21.) and starts to trans-
mit the request frame to the PICC. Once the RF
transmission is over, the CRX14 waits for the
PICC to send an answer frame.
If the PICC answers, the characters received ( Fig-
ure 27.) are demodulated, decoded and stored
into the Input/Output Frame Register, as specified
in Table 4. During the entire RF transmission, the
CRX14 disconnects itself from the I²C bus. On re-
ception of the PICC EOF, the CRX14 checks the
CRC and reconnects itself to the I²C bus.
The host can then get the PICC answer frame by
issuing an Input/Output Frame Register Read on
the I²C bus, as specified in Figures 15 and 16.
Standard TAG Command Access Description
Standard PICC commands, like Read and Write,
are generated by the CRX14 using the Input/Out-
put Frame Register.
When the host needs to send a standard frame
command to the PICC, it first has to internally gen-
erate the complete frame, with the command code
followed by the command parameters. Only the
two CRC Bytes should not be generated, as the
CRX14 automatically adds them during the RF
transmission.
If no answer from the PICC is detected after a
time-out delay, fixed in the Parameter Register
(bits b and b ), the Input/Output Frame Register
5
6
When the frame is ready, the host has to write the
request frame into the Input/Output Frame Regis-
ter using the I²C write command specified in Fig-
is set as specified in Table 4.
Figure 29. Standard TAG Command: Request Frame Transmission
S
Input/
T
A
R
T
S
T
O
P
Output
Register
Address
Device
Select
Code
Request
Frame
TAG
Cmd
Code
TAG
Cmd
Code
CRX14
SOF
SRX14
EOF
Param
Data 2
Param
Data
Param
Data N
Param
Param
Param
CRC
CRC
CRC
CRC
Length
01h
N
Data 1
I²C
RF
SOF
Data 1
Data 2
Data
Data N
EOF
ai09260
Figure 30. Standard TAG Command: Answer Frame Reception
S
Input/
Output
Register
Address
T
A
R
T
S
T
O
P
Device
Select
Code
Answer
Frame
Length
TAG
SOF
TAG
Data
TAG
Data
TAG
Data
TAG
Data
TAG
CRC
TAG
CRC
TAG
EOF
TAG
Data
TAG
Data
TAG
Data
TAG
Data
01h
P
Data 1
Data 2
Data
Data P
I²C
RF
SOF
Data 1
Data 2
Data
Data P
CRC
CRC
EOF
ai09261
26/40
CRX14
Figure 31. Standard TAG Command: Complete TAG Access Description
Device
Device
Select
Code
Answer Request
Frame Frame
Length Bytes
I/O
Request Request
Select
Code
Write
I²C
RF
Register Frame Frame
Address Length Bytes
Read
START
STOP
SOF
START
EOF
CRC
STOP
EOF
SOF
Request
Frame
TAG
T
T
1
0
Answer Frame
Characters
CRC
<--> <-->
Characters
ai09262
Anti-Collision TAG Sequence
command followed by fifteen SLOT_MARKER
commands, from SLOT_MARKER(1) to
The CRX14 can identify an ST short range memo-
ry using a proprietary anti-collision system.
SLOT_MARKER(15). After each command, the
CRX14 waits for a tag answer. If the answer is cor-
rectly decoded, the corresponding Chip_ID is
stored in the Input/Output Frame Register. If there
is no answer, or if the answer is wrong (with a CRC
error, for example), the CRX14 stores an error
code in the Input/Output Frame Register. At the
end of the sequence, the host has to read the In-
put/Output Frame Register to retrieve all the iden-
tified Chip_IDs.
Issuing an I²C Write command to the Slot Marker
Register ( Figure 17.) causes the CRX14 TO auto-
matically generate a 16-slot anti-collision se-
quence, and to store the identified Chip_ID in the
Input/Output Frame Register, as specified in Table
5.
After receiving the Slot Marker Register I²C Write
command, the CRX14 generates an RF PCALL16
27/40
CRX14
Figure 32. Anti-Collision ST short range memory Sequence (1)
S
Slot
S
T
O
P
T
A
R
T
Device
Select
Code
CRX14
SOF
PCALL 16 TAG
Command
CRC
CRC
CRX14
EOF
TAG
SOF
TAG
Chip_ID
TAG
CRC
TAG
CRC
TAG
EOF
Marker
Register
Address
I²C
RF
03h
Slot 0
SOF
06h
04h
CRC
CRC
CRC
EOF
t
t
SOF
Chip_ID
CRC
CRC
EOF
0
1
<--> <-->
CRX14 Slot Marker CRC
SOF
CRX14
EOF
TAG
SOF
TAG
Chip_ID
TAG
CRC
TAG
CRC
TAG
EOF
Command
I²C
RF...
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
SOF
16h
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
EOF
EOF
EOF
EOF
EOF
EOF
EOF
EOF
EOF
t
t
SOF
SOF
SOF
SOF
SOF
SOF
SOF
SOF
SOF
Chip_ID
Chip_ID
Chip_ID
Chip_ID
Chip_ID
Chip_ID
Chip_ID
Chip_ID
Chip_ID
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
EOF
EOF
EOF
EOF
EOF
EOF
EOF
EOF
EOF
0
1
<--> <-->
I²C
RF...
SOF
SOF
SOF
SOF
SOF
SOF
SOF
SOF
26h
36h
46h
56h
66h
76h
86h
96h
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
I²C
RF...
t
t
1
0
<--> <-->
ai09263
28/40
CRX14
Figure 33. Anti-Collision ST short range memory Sequence Continued
I²C
RF ...
Slot 10
SOF
96h
CRC
CRC
EOF
t
t
SOF
Chip_ID
CRC
CRC
EOF
0
1
<--> <-->
I²C
RF ...
Slot 11
Slot 12
Slot 13
Slot 14
Slot 15
SOF
SOF
SOF
SOF
56h
66h
76h
86h
96h
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
EOF
EOF
EOF
EOF
t
t
SOF
SOF
SOF
SOF
Chip_ID
Chip_ID
Chip_ID
Chip_ID
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
CRC
EOF
EOF
EOF
EOF
EOF
0
1
<--> <-->
I²C
RF ...
t
t
1
0
<--> <-->
I²C
RF ...
t
t
1
0
<--> <-->
I²C
RF ...
t
t
1
0
<--> <-->
I²C
RF ...
SOF
EOF
t
t
SOF
Chip_ID
Slot 5
0
1
<--> <-->
R
E
S
T
A
R
T
S
T
A
R
T
Device
Select Register
Code Address
I/O
Device Answer Status
Status
Slot 0
Slot 1
Slot 2
Slot 3
Slot 4
Slot 6
Slot 7
Slot 8
Select Frame Slot Bits Slot Bits Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
Code Length
b
to b
b
to b Answer Answer Answer Answer Answer Answer Answer Answer Answer
0
7
8
15
01h
12h
Status Status Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
I²C ...
RF
S
Slot 9
Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15
Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
Answer Answer Answer Answer Answer Answer Answer
T
O
P
Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
I²C ...
RF
ai09264
29/40
CRX14
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Symbol
TSTG
TLEAD
VIO
Parameter
Value
Unit
°C
°C
V
Storage Temperature
–65 to 150
(1)
(2)
Lead Temperature during Soldering
Input or Output range (SDA)
215
–0.3 to 6.5
–0.3 to Vcc+0.3
–0.3 to 6.5
100
VIO
Input or Output range (others pads)
Supply Voltage
V
VCC
V
P
Output Power on Antenna Output Driver (RF
)
mW
OUT
OUT
(3)
4000
500
V
V
Electrostatic Discharge Voltage (Human Body model)
VESD
(4)
Electrostatic Discharge Voltage (Machine model)
Note: 1. Compliant with the JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. No longer than 40 seconds.
3. MIL-STD-883C, 3015.7 (100pF, 1500Ω).
4. EIAJ IC-121 (Condition C) (200pF, 0Ω)
30/40
CRX14
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 9. I²C AC Measurement Conditions
Parameter
Min.
4.5
Max.
5.5
Unit
V
V
CC Supply Voltage
Ambient Operating Temperature (TA)
Input Rise and Fall Times
−20
85
°C
ns
V
50
0.2V
0.8V
Input Pulse Voltages
CC
CC
CC
0.3V
0.7V
CC
Input and Output Timing Reference Voltages
V
Figure 34. I²C AC Testing I/O Waveform
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI09235
(1,2)
Table 10. I²C Input Parameters
Symbol
CIN
Parameter
Input Capacitance (SDA)
Input Capacitance (SCL, E0, E1, E2))
Low Pass Filter Input Time Constant (SCL & SDA Inputs)
Test Condition
Min.
Max.
8
Unit
pF
pF
ns
CIN
6
tNS
100
400
Note: 1. Sampled only, not 100% tested.
2. T = 25 °C, f = 400kHz.
A
31/40
CRX14
Table 11. I²C DC Characteristics
Symbol
Parameter
Test Condition
Min.
Max.
Unit
Input Leakage Current (SCL,
SDA, E0, E1, E2)
ILI
0V ≤VIN ≤VCC
±2
µA
Output Leakage Current (SCL,
SDA, E0, E1, E2)
ILO
0V ≤VOUT ≤VCC, SDA in Hi-Z
±2
6
µA
mA
mA
V
V
CC = 5V, f = 400kHz (rise/fall time < 30ns),
c
RF OFF
ICC
Supply Current
CC = 5V, f = 400kHz (rise/fall time < 30ns),
c
20
RF ON
ICC1
VIL
Supply Current (Stand-by)
V
IN = VSS or VCC, VCC = 5V, RF OFF
5
mA
V
Input Low Voltage (SCL, SDA)
Input Low Voltage (E0, E1, E2)
Input High Voltage (SCL, SDA)
Input High Voltage (E0, E1, E2)
Output Low Voltage (SDA)
−0.3
−0.3
0.3VCC
0.3VCC
VCC + 1
VCC + 1
0.4
V
0.7VCC
0.7VCC
V
VIH
V
VOL
IOL = 3mA, VCC = 5V
V
Figure 35. I²C AC Waveforms
tCHCL
SCL
CLCH
tDXCX
tDLCL
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
STOP &
START
SDA
BUS FREE
CONDITION
INPUT CHANGE
SCL
tCLQV
DATA VALID
tCLQX
SDA OUT
DATA OUTPUT
SCL
tRFEX
SDA IN
tCHDH
tCHDX
CRX14 command execution
STOP
START
CONDITION
CONDITION
ai09236
32/40
CRX14
Table 12. I²C AC Characteristics
Fast I²C
400 kHz
I²C
100 kHz
Symbol
Alt.
Parameter
Unit
Min
Max
Min
Max
2
tR
tF
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
300
300
300
300
1000
300
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
kHz
tCH1CH2
2
tCL1CL2
2
tR
20
20
20
20
1000
300
tDH1DH2
2
tF
tDL1DL2
1
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
tSU:DAT
tSU:STO
tBUF
tAA
Clock High to Input Transition
Clock Pulse Width High
600
600
600
0
4700
4000
4000
0
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
tCLQV
tCLQX
fC
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
1.3
100
600
1.3
4.7
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Data Out Valid
Data Out Hold Time After Clock Low
Clock Frequency
250
4000
4.7
1000
400
3500
100
tDH
200
200
fSCL
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested
33/40
CRX14
Figure 36. CRX14 Synchronous Timing
RF
ASK Modulated Signal
OUT
V
RFOUT
t
RFSBL
t
RFF
t
RFR
A
B
f
CC
t
POR
FRAME transmission between the reader and the contactless device
t
t
DR
DR
1
0
DATA
1
EOF
FRAME transmitted by the CRX14 in ASK
847kHz
SOF
1 1 0 DATA 1 0 DATA 1 0
t
FRAME transmitted by the PICC in BPSK
t
t
t
0
1
DA
DA
Data jitter on FRAME transmitted by the CRX14 in ASK
t
t
t
t
t
JIT
JIT
JIT
JIT
JIT
0
START
t
t
t
RFSBL
RFSBL
RFSBL
t
t
RFSBL
RFSBL
ai09258
34/40
CRX14
Table 13. RF
Symbol
AC Characteristics
Parameter
OUT
Condition
Min.
Max.
Unit
f
V
= 5V
CC
External Oscillator Frequency
Carrier Modulation Index
10% Rise and Fall time
13.553 13.567 MHz
CC
MI
MI=(A-B)/(A+B)
1 ETU = 128/f
CC
10
14
%
CARRIER
t
t
t
t
t
t
t
t
t
t
, t
0.5
9.44
-0.5
75
1.5
µs
RFR RFF
Pulse Width on RF
µs
RFSBL
JIT
OUT
ASK modulation bit jitter
0.5
µs
CRX14 to PICC
Min = 64/f
Antenna Reversal delay
µs
0
S
Min = 80/f
Synchronization delay
94
µs
1
S
Answer delay watchdog (b =0, b =0)
500
5
µs
WDG
WDG
WDG
WDG
DR
5
6
Request EOF
rising edge
to
first Answer
start bit
Answer delay watchdog (b =0, b =1)
ms
ms
ms
µs
5
6
Answer delay watchdog (b =1, b =0)
10
5
6
Answer delay watchdog (b =1, b =1)
309
5
6
Time Between Request characters
RF output power
9.44
CRX14 to PICC
P
90
20
mW
ms
A
OUT
t
CRX14 Power-On delay
POR
Note: 1. Note:Data specified in the table above are estimated or target values. All values can be updated during product qualification.
Table 14. RF AC Characteristics
IN
Symbol
Parameter
PICC Pulse Width
Condition
Min.
Max.
Unit
µs
t
1 ETU = 128/f
9.44
847.5
1, 2, 3
RFSBL
CC
f
S
f
/16
PICC Sub-carrier Frequency
KHz
ETU
V
CC
t
Time Between Answer characters
PICC to CRX14
DA
V
RF Dynamic Voltage Level
V
Max for V
= V /2
V
/2
CC
0.5
2
DYN
IN
DYN
OFFSET
CC
V
RF Offset Voltage Level
3
V
OFFSET
IN
V
RF Retro-modulation Level
120
mV
RET
IN
Note: 1. Note:Data specified in the table above are estimated or target values. All values can be updated during product qualification.
35/40
CRX14
PACKAGE MECHANICAL
Figure 37. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
1.75
0.25
1.60
8°
Typ.
Max.
0.069
0.010
0.063
8°
A
A1
A2
α
0.10
0.004
0°
0°
B
0.35
0.19
0.46
0.25
0.10
10.00
–
0.014
0.007
0.018
0.010
0.004
0.394
–
C
CP
D
9.80
–
0.386
–
e
1.27
0.050
E
3.80
0.40
16
4.00
1.27
0.150
0.016
16
0.157
0.050
L
N
36/40
CRX14
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
CRX14
–
MQ
/ XXX
Device Type
CRX14
Package
MQ = SO16 Narrow (150 mils width)
MQP = SO16 Narrow (150 mils width) Lead-Free and RoHS compliant
Customer Code
XXX = Given by the issuer
For a list of available options (speed, package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
37/40
CRX14
APPENDIX A. ISO14443 TYPE B CRC CALCULATION
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#define BYTE
unsigned char
#define USHORT unsigned short
unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc)
{
ch = (ch^(BYTE)((*lpwCrc) & 0x00FF));
ch = (ch^(ch<<4));
*lpwCrc = (*lpwCrc >> 8)^((USHORT)ch << 8)^((USHORT)ch<<3)^((USHORT)ch>>4);
return(*lpwCrc);
}
void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE
*TransmitSecond)
{
BYTE chBlock; USHORTt wCrc;
wCrc = 0xFFFF; // ISO 3309
do
{
chBlock = *Data++;
UpdateCrc(chBlock, &wCrc);
} while (--Length);
wCrc = ~wCrc; // ISO 3309
*TransmitFirst = (BYTE) (wCrc & 0xFF);
*TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF);
return;
}
int main(void)
{
BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i;
printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1");
printf("CRC_B of [ ");
for(i=0; i<4; i++)
printf("%02X ",BuffCRC_B[i]);
ComputeCrc(BuffCRC_B, 4, &First, &Second);
printf("] Transmitted: %02X then %02X.", First, Second);
return(0);
}
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CRX14
REVISION HISTORY
Table 17. Document Revision History
Date
Version
1.0
Revision Details
4-Aug-2004
23-Feb-2005
21-Jul-2005
First issue
2.0
Document put into new template.
3.0
Added Package information in Table 16., Ordering Information Scheme.
39/40
CRX14
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
40/40
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