E-TDA7437N [STMICROELECTRONICS]
Digitally controlled audio processor; 数字控制音频处理器
| 型号： | E-TDA7437N |
| 厂家： | 
ST |
| 描述： | Digitally controlled audio processor |
| 文件： | 总34页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA7437N
Digitally controlled audio processor
Features
■ Input multiplexer
– Four stereo, one mono input, and one
differential input
– Selectable input gain for optimal adaptation
to different sources
■ Fully programmable loudness function
■ Volume control in 1dB steps including gain up
to 16dB
■ Zero crossing mute, soft mute and direct mute
■ Bass and treble control
LQFP44
■ Four speaker attenuators- four independent
speakers control in 1dB steps for balance and
fader facilities
■ Pause detector programmable threshold
low noise are obtained. Several new features like
softmute, and zero-crossing mute are
2
■ All functions programmable via serial I C bus
implemented. The soft Mute function can be
activated in two ways either via the serial bus
(Mute byte, bit D0), or directly on pin 28 through
an I/O line of the microcontroller
Description
The audioprocessor TDA7437N is an upgrade of
the TDA731X audioprocessor family.
Very low DC stepping is obtained by use of a
BICMOS technology.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
Order codes
Part numbers
Package
Packing
E-TDA7437N
LQFP44 (10x 10x 1.4mm)
LQFP44 (10x 10x 1.4mm)
Tray
E-TDA7437NTR
Tape and reel
December 2006
Rev 2
1/34
www.st.com
1
TDA7437N
Contents
1
2
3
PIN descriptions and electrical specifications . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transmission without acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
4.3
4.4
4.5
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Mute and pause features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Direct mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Speakers mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Zero crossing mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pause function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
No symmetrical bass cut response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmitted data (send mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TDA7437N I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C bus read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.10 Loudness stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11 Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.12 IN-OUT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.13 Bass & mid filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/34
TDA7437N
5.14 Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Curves of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
7
8
3/34
TDA7437N
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bass treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input stage gain middle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/34
TDA7437N
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CLD and CDR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Timing diagram of I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Acknowledge on the I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power on time constant vs CREF capacitor CREF = 4.7mF . . . . . . . . . . . . . . . . . . . . . . . 28
Power on time constant vs CREF capacitor CREF = 10mF . . . . . . . . . . . . . . . . . . . . . . . . 28
Power on time constant vs CREF capacitor CREF = 22mF . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. SVRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Soft mute ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Soft mute OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Zero crossing mute ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. Zero crossing mute OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Pause detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Pause detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Symmetrical bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. unsymmetrical bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Test board diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. LQFP44 (10x10) Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . 32
5/34
PIN descriptions and electrical specifications
TDA7437N
1
PIN descriptions and electrical specifications
Figure 1.
Pin description
44 43 42 41 40 39 38 37 36 35 34
1
TREB_R
IN_R
33
32
31
30
29
28
27
26
25
24
23
OUT_RF
OUT_LR
MID_LI
2
3
4
5
6
7
8
9
MUXOUT_R
LOUD_R
MID_LO
OUT_RR
SMEXT
DIFFGND_R
DIFF_R
STEREO4_R
STEREO1_R
STEREO2_R
STEREO3_R
MONO
BASS_RO
BASS_RI
BASS_LO
BASS_LI
MID_RO
10
11
12 13 14 15 16 17 18 19 20 21 22
D96AU435B
Table 1.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
AVDD, DVDD Operating supply voltage
10.5
V
Tamb
Tstg
Operating ambient temperature
Storage temperature range
-40 to 85
-55 to 150
°C
°C
Table 2.
Symbol
Thermal data
Parameter
Value
Unit
Rth j-amb Thermal resistance junction to pins Max.
150
°C/W
Table 3.
Quick reference data
Parameter
Symbol
Min. Typ. Max.
Unit
Supply voltage (AVDD and DVDD must be at the same
potential)
AVDD, DVDD
6
9
10.2
V
VCL
THD
S/N
SC
Max. input signal handling
2.1
2.6
0.01
111
95
Vrms
%
Total harmonic distortion V = 1Vrms f = 1KHz
Signal to noise ratio
0.8
dB
Channel separation f = 1KHz
dB
6/34
TDA7437N
PIN descriptions and electrical specifications
Table 3.
Symbol
Quick reference data (continued)
Parameter
Min. Typ. Max.
Unit
Input gain 1dB step
0
15
16
dB
dB
dB
dB
dB
dB
dB
dB
Volume control 1dB step
Treble control 2dB step
Bass control 2dB step
-63
-14
-14
-14
-79
0
+14
+14
+14
0
Middle control 2dB step
Fader and balance control 1dB step
Loudness control 1dB step
Mute attenuation
20
100
7/34
PIN descriptions and electrical specifications
TDA7437N
Figure 2.
Block diagram
5DAU294B
P A U S E
S M E X T
B A S S _ R O )
T R E B L _ L
T R E B _ R
I N _ L
I N _ R
M U X O U T _ R
M U L T I P L E X E R
8/34
TDA7437N
Electrical characteristics
2
Electrical characteristics
(AVDD, DVDD = 9V; RL = 10K
Ω; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the
test circuit, unless otherwise specified.)
Table 4.
Symbol
Electrical characteristics
Parameter
Test condition
Min. Typ. Max. Unit
Input selector (mono and stereo inputs)
RI
VCL
SI
Input resistance
Clipping level
pin 7 to 11 and 15 to 18
70
2.1
80
100
2.6
95
130
KΩ
d ≤ 0.3%
V
RMS
Input separation
Output load resistance
dB
RL
2
KΩ
dB
dB
dB
dB
mV
mV
GI MIN Minimum input gain
GI MAX Maximum input gain
Gstep Step resolution
-0.75
14
0
15
1.0
0
+0.75
16
0.5
-1.0
1.5
1.0
10
Ea
Set error
Adjacent gain steps
GIMIN to GIMAX
0.5
3
VDC
DC steps
Differential input (Pin 5, 6, 13, 14)
Input selector BIT D4 = 0
(0dB)
10
14
45
15
20
20
26
KΩ
KΩ
RI
Input resistance
Input selector BIT D4 = 1(-
6dB)
Common mode rejection
ratio
CMRR
d
VCM = 1VRMS ; f = 1KHz
VI = 1VRMS
70
0.01
5
dB
%
Distortion
0.08
20Hz to 20KHz; Flat; D6 =
0
eIN
Input noise
μV
D4 = 0
D4 = 1
-1
-7
0
1
dB
dB
GDIFF Differential gain
-6
-5
Volume control
RI
Input resistance
Pin 2 and 20
31
15
44
16
57
17
KΩ
dB
dB
dB
dB
dB
dB
GMAX Maximum gain
AMAX Maximum attenuation
ASTEPC Step resolution coarse atten.
61
63.75 66.5
0.5
1.0
0
1.5
1.0
2.75
2
G = 16 to -20dB
G = -20 to -63dB
-1.0
-2.75
EA
Et
Attenuation set error
Tracking error
9/34
Electrical characteristics
TDA7437N
Table 4.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Min. Typ. Max. Unit
Adjacent gain steps
Adjacent attenuation steps
From 0dB to AMAX
-5
-3
+5
+3
5
mV
mV
mV
VDC
DC steps
0.5
Loudness control (Pin 4, 12)
RI Internal resistor
AMAX Maximum attenuation
Astep Step resolution
Zero crossing mute
Loud = On
35
19
50
20
1
65
21
KΩ
dB
dB
0.5
1.5
WIN = 11
WIN = 10
WIN = 01
WIN = 00
35
70
mV
mV
mV
mV
dB
VTH
Zero crossing threshold (1)
140
280
100
0.1
AMUTE Mute attenuation
80
VDC
DC step
0dB to Mute
3
mV
Soft mute
AMUTE Mute attenuation
50
65
dB
ms
CCSM = 22nF; 0 to -20dB; I
= IMAX
0.8
1.5
2.0
TDON ON delay time
CCSM = 22nF; 0 to -20dB; I
= IMIN
25
20
45
60
60
ms
VCSM = 0V; I = IMAX
40
2
mA
μA
KΩ
V
TDOFF OFF current
VCSM = 0V; I = IMIN
(2)
RINT
Pullup resistor (pin 28)
100
VSMH (pin 28) Level high
VSML (pin 28) Level low
3.5
Soft mute active
1
V
Bass control
Crange Control range
±11.5 ±14
±16
3
dB
dB
KΩ
Astep
Rg
Step resolution
1
2
Internal feedback resistance
31
44
57
Middle control
Crange Control range
±11.5 ±14
±16
3
dB
dB
KΩ
Astep
Rg
Step resolution
1
2
Internal feedback resistance
17.5
25
32.5
10/34
TDA7437N
Electrical characteristics
Min. Typ. Max. Unit
Table 4.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Treble control
CRANGE Control range
Astep Step resolution
±13
±14
±15
dB
dB
1
2
3
Speaker attenuators
CRANGE Control range
79
1
dB
dB
dB
dB
mV
Astep
Step resolution
AV = 0 to -40dB
0.5
80
1.5
AMUTE Output mute attenuation
Data word = 1111XXXX
AV = 0 to -40dB
100
EA
Attenuation set error
DC steps
1.5
3
VDC
Adjacent attenuation steps
0.1
2.6
Audio output
Vclip
RL
Clipping level
d = 0.3%
2.1
2
Vrms
KΩ
W
Output load resistance
Output impedance
DC voltage level
RO
50
3.5
90
140
4.1
VDC
3.8
V
Pause detector
WIN = 11
WIN = 10
WIN = 01
WIN = 00
35
70
mV
mV
mV
mV
μA
V
VTH
Pause threshold
140
280
25
IDELAY Pull-up current
VTHP Pause threshold
15
35
3.0
General
VCC
ICC
Supply voltage
Supply current
6
7
9
10.2
13
V
10
90
mA
dB
PSRR Power supply rejection ratio f = 1KHz
70
Output muted (B = 20 to
20kHz flat)
Output noise
4
6
μV
μV
eNO
All gains 0dB (B = 200 to
20kHz flat)
15
Et
Total tracking error
AV = 0 to -20dB
0
0
1
2
dB
dB
AV = -20 to -60dB
All Gains = 0dB; VO =
2.1Vrms
S/N
SC
Signal to noise ratio
111
95
dB
dB
Channel separation L - R
80
11/34
Electrical characteristics
TDA7437N
Table 4.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min. Typ. Max. Unit
0.01
0.08
%
d
Distortion
VIN =1V all gain = 0dB
Bus inputs
VIL
VlN
IlN
Input low voltage
1
V
V
Input high voltage
Input current
3
VIN = 0.4V
IO = 1.6mA
-5
5
μA
Output voltage SDA
acknowledge
VO
0.1
0.4
V
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
2. Internal pullup resistor to Vs/2; "LOW" = softmute active
Note:
The ANGND and DIGGND layout wires must be kept separated. A 50Ω resistor is
recommended to be put as far as possible from the device.
The CLD - and CDR - can be short-circuited in applications providing 3 wires CD signal
Figure 3.
CLD and CDR
L+
L+
∼
L- R-
L-
R-
=
CD
TDA7437N
R+
R+
D02AU1384
CLD - = DIFFINLGND
CDR - = DIFFINRGND
12/34
TDA7437N
I2C bus interface
2
3
I C bus interface
Data transmission from the microprocessor to the TDA7437N, and vice versa, takes place
2
through the 2 wires of the I C BUS interface, consisting of the two lines SDA and SCL (pull-
up resistors to positive supply voltage must be externally connected).
3.1
3.2
Data validity
As shown in Figure 4, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Start and stop conditions
As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP conditions must be sent before each START condition.
3.3
3.4
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 6). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been
addressed has to generate an acknowledgment after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the
master transmitter can generate the STOP information in order to abort the transfer.
3.5
Transmission without acknowledgment
To avoid detection of the acknowledge clock pulse of the audioprocessor, the microprocessor can
use a simpler transmission: it simply waits one clock pulse, and sends the new data. This is less
protected from any errors and will decrease the immunity to noise.
13/34
I2C bus interface
Figure 4.
TDA7437N
Data validity
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
2
Figure 5.
Timing diagram of I C Bus
SCL
I2CBUS
SDA
START
2
D99AU1032
STOP
Figure 6.
Acknowledge on the I C Bus
SCL
1
2
3
7
8
9
SDA
MSB
ACKNOWLEDGMENT
FROM RECEIVER
START
D99AU1033
14/34
TDA7437N
Software specification
4
Software specification
4.1
Interface protocol
The interface protocol comprises of:
●
●
●
●
●
A start condition (s)
A chip address byte, (the LSB bit determines read (=1)/write (=0) transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
DATA
MSB
LSB
MSB
LSB
A3 A2 A1 A0 ACK
MSB
LSB
S
1
0
0
0
1
0
A
R/W ACK
X
X
X
I
ACK
P
ACK = Acknowledge; S = Start; P = Stop; I = Auto increment; X = Not used
Max clock speed 500kbits/s
ADDRpin open A = 0
ADDRpin close to Vs A = 1
4.2
4.3
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled.
Subaddress (receive mode)
Table 5.
MSB
Subaddress (receive mode)
LSB
FUNCTION
X
X
X
I
A3
0
A2
0
A1
0
A0
0
Input selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker attenuator LF
Speaker attenuator LR
Speaker attenuator RF
Speaker Attenuator RR
Input gain middle
Mute
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
15/34
Software specification
TDA7437N
4.4
Transmitted data
Table 6.
MSB
Send mode
LSB
X
X
X
X
X
SM
ZM
P
P = Pause (Active low)
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
4.5
Data byte specification
Table 7.
MSB
Data byte specification
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
1
1
1
1
1
1
0
0
0
0
0
1
1
X
0
0
1
1
0
0
X
0
1
0
1
0
1
X
Differential
Stereo 1
Stereo 2
Stereo 3
Stereo 4
Mono
X
X
X
0
0
1
1
X
0
1
0
1
DC connect (1)
Half-diff 0dB (2)
Half-diff -6dB (2)
Full-diff 0dB (3)
Full-diff -6dB (3)
1. Selected when using a 3 wire differential source (pins 5 and 13 shorted)
2. Selected when using a 4 wire differential source
3. OUTR-INR (OUTL-INR) short circuited internally (no need for external connection
Table 8.
MSB
Loudness
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
Loudness step
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0dB
1dB
2dB
3dB
16/34
TDA7437N
Software specification
Table 8.
MSB
Loudness (continued)
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
Loudness step
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
16dB
17dB
18dB
19dB
20dB
Loudness off
Fine volume
0dB
0
0
1
1
0
1
0
1
-0.25dB
-0.5dB
-0.75dB
Table 9.
MSB
Mute
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
1
1
1
1
Soft mute on
0
1
soft mute with fast slope
Soft mute with slow slope
Zero mute
0
1
1
Direct mute
Reset
17/34
Software specification
TDA7437N
Table 9.
MSB
Mute (continued)
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
Zero cross window
(280mV)
0
0
0
Zero cross window
(140mV)
0
1
0
1
1
0
1
0
0
Zerocross window (70mV)
Zerocross window (35mV)
Non symmetrical bass
Symmetrical bass
0
1
Table 10. Volume
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
0
0
0
0
0
0
0
0
1
1
X
0
0
0
0
1
1
1
1
0
0
X
0
0
1
1
0
0
1
1
0
0
X
0
1
0
1
0
1
0
1
0
1
X
16dB
8dB
0dB
-8dB
-16dB
-24dB
-32dB
-40dB
-48dB
-56dB
Mute
X
X
X
18/34
TDA7437N
Software specification
Table 11. Speaker
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
1.25dB step
0dB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0dB
-8dB
-16dB
-24dB
-32dB
-40dB
-48dB
-56dB
-64dB
-72dB
Mute
X
X
X
Table 12. Bass treble
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
Treble step
-14dB
-12dB
-10dB
-8dB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-6dB
-4dB
-2dB
0dB
19/34
Software specification
Table 12. Bass treble (continued)
TDA7437N
MSB
D7
LSB
D0
Function
D6
D5
D4
D3
D2
D1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
Bass steps
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0dB
2dB
1
1
4dB
6dB
8dB
10dB
126B
14dB
1
1
Table 13. Input stage gain middle
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
In-gain step
0dB
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1dB
2dB
3dB
20/34
TDA7437N
Software specification
Table 13. Input stage gain middle (continued)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
Middle step
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0dB
2dB
4dB
6dB
8dB
10dB
126B
14dB
21/34
Mute and pause features
TDA7437N
5
Mute and pause features
2
The TDA7437N provides three types of mute, controlled via I C bus (see Table 9 Mute byte
register).
5.1
Soft mute
Bit D0 = 1 → Soft mute ON
Bit D0 = 0 → Soft mute OFF
It allows an automatic soft muting and unmuting of the signal.
The time constant is fixed by an external capacitor Csm inserted between pin Csm and
ground.
Once the external capacitor is fixed, two different slopes (time constant) are selectable by
programming of bit D1.
Bit D1 = 0 → fast slope (I=Imax)
Bit D1 = 1 → slow slope (I=Imin)
The soft mute generates a gradually decreasing signal, avoiding big click noise of an
immediate high attenuation, without necessity to program a sequence of decreasing volume
levels. A response example is reported in Figure 11 (mute), and Figure 12 (unmute). The
final attenuation obtained with soft mute ON is 60dB typical. The used reference parameter
is the delay time taken to reach 20dB attenuation (no matter what the signal level is).
Using a capacitor Csm = 22nF this delay is:
d = 1. 8mswhen selected Fast slope mode (bit D1=0)
d = 25 ms when selected Slow slope mode (bit D1=1
In the application, the soft mute ON programming should be followed by programming of
direct mute on (see 5.2), in order to achieve a final 100dB attenuation. In addition to the I C
2
bus programming, the Soft Mute ON can be generated in a fast way by forcing a LOW level
at pin SMEXT (TTL Level compatible). This approach is recommended for fast RDS AF
switching.
2
The Soft Mute status can be detected via I C bus, reading the Transmitted Byte, bit SM
(see Table 6).
read bit SM = 1 soft mute status ON
read bit SM = 0 soft mute status OFF
5.2
Direct mute
bit D3 = 1 Direct mute ON
bit D3 = 0 Direct mute OFF
The direct mute bit forces an internal immediate signal connection to ground.
It is located just before the Volume/Loudness stage, and gives a typical 100dB attenuation.
22/34
TDA7437N
Mute and pause features
5.3
Speakers mute
An additional direct mute function is included in the speakers attenuators stage.
The four output LF, RF, LR, RR can be separately muted by setting the speaker attenuator
byte to the value 01111111 binary.
Typical attenuation level 100dB. This mute is useful for fader and balance functions. It
should not be applied for system mute/unmute, because it can generate noise due to the
offset of previous stages (bass / treble).
5.4
Zero crossing mute
bit D2 = 1 D4 = 0 zero crossing mute ON
bit D2 = 0 D4 = 0 zero crossing mute OFF
The mute activation/deactivation is delayed until the signal waveform crosses the DC zero
level (Vref level).
The detection works separately for left and right channels (see Figure 13 and Figure 14).
Four different window thresholds are software selectable by two dedicated bits.
bit
D6 bit D5 Window
0
0
1
1
0
1
0
1
Vref DC +/-280mV
Vref DC +/-140mV
Vref DC +/-70mV
Vref DC +/-35mV
The zero crossing mute activation/deactivation starts when the AC signal level falls inside
the selected window (internal comparator).
The zero crossing mute (and pause) detector is always active. It can be disabled, if the
feature is not used, by forcing the bit D4 = 1 Zero crossing and pause detector reset.
In this way the internal comparator logic is stopped, eliminating its switching noise.
The zero cross mute status is detected reading the transmitted byte bit ZM.
bit ZM = 1 zero cross mute status ON
bit ZM = 0 zero cross mute status OFF
5.5
Pause function
On chip is implemented by a pause detector block.
It uses the same 4 windows threshold selectable for the zero crossing mute, bit D6,D5 byte
MUTE (see above). The detector can be put into OFF by forcing bit D4 = 1, otherwise it is
active.
Pause detector information is available at the PAUSE pin. A capacitor must be connected
between the PAUSE pin and ground.
23/34
Mute and pause features
TDA7437N
When the incoming signal is detected to be outside the selected window, the external
capacitor is discharged. When the signal is inside the window, the capacitor is integrating up
(see Figure 15 and Figure 16).
a) by reading directly the Pause pin level.The ON/OFF voltage threshold is 3.0V
typical. Pause OFF = level low (< 3.0V) Pause ON = level high ( ; 3.0V)
b) by reading via I2C bus the transmitted byte, bit PP = 0 pause active. P = 1 no
pause detected. The external capacitor value fixes the time constant.
The pull up current is 25uV typical, with input signal
Vin = 1Vrm --; Vdc pin pause = 15mV
Vin = 0Vrms --; Vdc pin pause = 5.62V
For example choosing Cpause = 100nF the charge up constant is about 22ms. Instead with
Cpause = 15nF the charge up constant is about 360μs.
The pause detection is useful in applications like RDS, to perform noiseless tuning
frequency jumps, avoiding the use of the mute.
5.6
No symmetrical bass cut response
bit D7 = 0 No symmetrical
bit D7 = 1 Symmetrical
The bass stage has the option to generate an unsymmetrical response, for cut mode
settings (bass level from -2db to - 14dB)
For example using a T-type band pass external
The feature is useful for human ear equalization in a noisy environment, like a car.
See examples in Figure 17 (symmetrical response) and Figure 18 (unsymmetrical
response).
5.7
Transmitted data (send mode)
bitP = 0Pause active
bitP = 1No pause detected
bitZM = 1Zero cross mute ON
bitZM = 0Zero cross mute OFF
bitSM = 1Soft mute ON
bitSM = 0Soft mute OFF
bitST = 1Stereo signal detected (input MPX)
bitST = 0Mono signal detected (input MPX)
The TDA7437N allows the reading of four info bits.
24/34
TDA7437N
Mute and pause features
The type (stereo/mono) of received broadcasting signal is easily checked and displayed by
using the ST bit.
The P bit check is useful in tuning jumps without signal muting.
The SM soft mute status becomes active immediately, when bit D0 is set to 1 (soft mute ON,
MUTE byte) and not when the signal level has reached the 60 dB final attenuation.
5.8
TDA7437N I2C bus protocol
2
The protocol is standard I C, using subaddress byte plus data bytes (as shown within
Chapter 4).
The optional autoincrement mode allows to refresh all the bytes registers with transmission
of a single subaddress, reducing drastically the total transmission time.
Without autoincrement, subaddress bit I = 0, to refresh all the bytes registers (10), it is
necessary to transmit 10 times the chip address, the subaddress and the data byte.
Working with a 100Kb/s clock speed the total time would be :
[(9*3+2)*10]bits*10us=2.9ms
Instead using autoincrement mode, subaddress bit I=1, the total time will be:
(9*12+2)*10us=1.1ms.
The autoincrement mode is useful also to refresh partially the data. For example to refresh
the 4 speakers attenuators it is possible to program the subaddress Spkr LF (code
XX010100), followed by the data byte of SPKR LF, LR, RF, RR in sequence.
Note: that the autoincrement mode has a module 16 counter, whereas the total used
register bytes are 10.
It is not correct to refresh all the 10 bytes starting from a subaddress different than
XX010000.
For example; using subaddress XX010010 (volume), the registers from Volume to Mute (see
Table 5) are correctly updated, but the next two transmitted bytes, refer instead to the
wanted Input selector, and Loudness are discharged. (the solution in this case is to send
two separate patterns in autoincrement mode, the first composed by address, subaddress
XX010010, 8 data bytes, and the second composed by address, subaddress XX010000, 2
data bytes).
With autoincrement disabled, the protocol allows the transmission in sequence of N data
bytes of a specific register, without the necessity to resend the address and subaddress
bytes, each time.
This feature can be implemented, for example, if a gradual volume change has to be
performed (the MCU does not send the STOP condition, but keeps the TDA7437N
communication active).
Warning: The TDA7437N always needs to receive a STOP condition,
before beginning a new START condition. The device doesn't
recognize a START condition if a previously active
communication was not ended by a STOP condition.
25/34
Mute and pause features
TDA7437N
5.9
I2C bus read mode
2
The TDA7437N sends the master a 1 byte "transmitted info" via I C bus in read mode.
The read mode is master activated by sending the chip address with LSB set to 1, followed
by an acknowledge bit.
The TDA7437N recognizes the request. At the following master generated clock bits, the
TDA7437N issues the transmitted inFO byte on the SDA data bus line (MSB transmitted
first).
At the ninth clock bit the MCU master can:
●
●
acknowledge the reception, starting in this way the transmission of another byte from
the TDA7437N.
no acknowledge, stopping the read mode communication.
5.10
Loudness stage
The previous SGS-THOMSON audioprocessors implemented a fixed loudness response,
only ON/OFF sw programmable.
No possibility to change the loud boost rate at a certain volume level. The TDA7437N
implements a fully programmable loudness control in 20 steps of 1dB.
It allows a customized loudness response for each application. The external network
connected to the loudness pins LOUD_L and LOUD_R fixes the type of loudness response.
1. Simple capacitor. The loudness effect is only a boost of low frequencies.
(see Figure 19)
2. Second order loudness (boost of low and high frequencies).
3. Second order decreased type loudness (lower boost of low and high frequencies).
4. Second order modified type loudness (higher boost of low and high frequencies).
5.11
5.12
Treble stage
The treble stage is a simple high pass filter, it’s time constant is fixed by internal resistor
(typically 50Kohm), and an external capacitor, connected between pins TREB_R/TREB_L
and ground.
IN-OUT pins
The multiplexer output is available at OUT_R and OUT_L pins for the optional connection of
an external graphic equalizer (TDA7316/TDA7317), surround chip (TDA7346) etc. The
signal is fed in again at pins IN_L and IN-R. In the case of an application without any
external devices, the pins OUT_L/OUT_R and IN_L/IN_R can be left unconnected, if bit D3
byte input selector is forced = 0 (DC connect). Instead if bit D3 is kept = 1 an external
decoupling capacitor must be provided between OUTR/INR and OUTL/INR to avoid signal
DC jumps, generating "clicking" output noise. The input impedance of the next volume stage
is 44Kohm typical (minimum 31Kohm). A capacitor no lower than 1mF should be used.
26/34
TDA7437N
Mute and pause features
5.13
Bass & mid filters
Several bass filter types can be implemented. Normally it is the basic T-type bandpass filter
that is used. Starting from the filter component values (R1 internal and R2, C1, C2 external),
the centre frequency Fc, the gain Av at max bass boost and the filter Q factor are computed
as follows:
1
F
= ------------------------------------------------------------------
c
2 ⋅ Π ⋅ R1 ⋅ R2 ⋅ C1 ⋅ C2
R2 ⋅ C2 + R2 ⋅ C1 + R1 ⋅ C1
A
= -------------------------------------------------------------------------
v
R2 ⋅ C1 + R2 ⋅ C2
Vice versa fixed Fc, Av, and R1 (internal typ. 30%), the external component values are
A – 1
v
C1 = ---------------------------------
2 ⋅ Π ⋅ R1 ⋅ Q
Q ⋅ Q ⋅ C1
C2 = -----------------------------------
A – 1 – Q ⋅ Q
v
(R1 ⋅ R2 ⋅ C1 ⋅ C2)
Q = ------------------------------------------------------
R2 ⋅ C1 + R2 ⋅ C2
A – 1 – Q ⋅ Q
v
R2 = ----------------------------------------------------------------------
2 ⋅ Π ⋅ C1 ⋅ F ⋅ (A – 1) ⋅ Q
c
v
5.14
Input selector
The multiplexer selector can choose one of the following inputs:
●
●
●
a differential CD stereo input.
a mono input.
four stereo input
The signal fed to the input pins must be decoupled via series capacitors. The minimum
allowed value depends on the correspondent input impedance. For the CD diff input (Zi =
10Kohm worst case) a Cin = 4.7uF is recommended. For the other inputs (70Kohm worst
case, a Cin=1uF is recommended.
27/34
Curves of electrical characteristics
TDA7437N
6
Curves of electrical characteristics
Figure 7.
Power on time constant vs CREF
capacitor CREF = 4.7μF
Figure 8.
Power on time constant vs CREF
capacitor CREF = 10μF
D95AU381
D95AU380
V
V
(1V/div)
(1V/div)
2
1
2
1
OUT LF
CREF
OUT LF
CREF
BWL
0.5s/DIV TIME
BWL
0.5s/DIV TIME
Figure 9.
Power on time constant vs CREF
Figure 10. SVRR vs. frequency
capacitor CREF = 22μF
D95AU382
D95AU383
V
S
VRR
(1V)
(dB)
-40
-50
-60
-70
-80
-90
-100
4.7μF
47μF
2
1
OUT LF
CREF
VS=8V
Ripple=0.2VRMS
AV=-15dB
10
100
1K
10K
Freq(Hz)
BWL
1s/DIV TIME
Figure 11. Soft mute ON
(a)
(b)
V
SOFT MUTE=ON SLOPE=FAST Vout=500mVrms
V
D95AU384
Main Menu
Pin Csm
Chan 2
1ms 0.2V
Vout
Chan 3
1ms 2V
CH1 9V DC
CH1 0.5V1x0
~
~
=
TIME
CH2 20mV1x0
CH3 0.2V1x0
SOFT MUTE
CH4 20mV x
10 = T/div 1ms
28/34
TDA7437N
Curves of electrical characteristics
Figure 12. Soft mute OFF
(a)
(b)
V
V
Main Menu
Vout
Chan 2
1ms 0.2V
SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms
D95AU387
Chan 1
1ms 2V
Pin Csm
CH1 9V DC
TIME
SOFT MUTE
Figure 13. Zero crossing mute ON
Figure 14. Zero crossing mute OFF
ZERO CROSSING MUTE = ON
ZERO CROSSING MUTE = OFF
D95AU389
D95AU390
V
V
x Chan 1
0.5ms 0.2V
x Chan 2
0.2ms 1V
LEFT
Panel
LEFT
RIGHT
Main Menu
STATUS
Memory
x Chan 2
0.5ms 0.2V
x Chan 1
0.2ms 0.5V
Save
PANEL
Multi Zoom
off
Recall
Auxiliary
Setups
Memory
Card
X-Y mode
Persistance
mode
CH2 528mV DC
TIME
2ms
CH1 2.7V DC
TIME
RIGHT
Return
Figure 15. Pause detector
Figure 16. Pause detector
D02AU1386
PAUSE DETECTOR ZCW=140mV Cpause=100nF
Vout
D02AU1385
V
Main Menu
Vout
Main Menu
Chan 1
20ms 0.2V
Chan 2
20ms 2V
Chan 3
20ms 0.2V
Chan 2
20ms 2V
CH2 4.08V DC
CH1 20mV1x0
~
CH2 0.2V1x0
=
CH2 4.12V DC
TIME
BWL
CH3 20mV1x0
~
CH4 5mV x
10 ~ T/div 20ms
29/34
Curves of electrical characteristics
Figure 17. Symmetrical bass
TDA7437N
Figure 18. unsymmetrical bass
D95AU393
ATT
(dB)
D95AU394
(dB)
10
5
10
5
0
0
-5
-10
-15
-20
-25
-5
-10
-15
10
100
1K
10K
Freq(Hz)
10
100
1K
10K
Freq(Hz)
Figure 19. Loudness
ATT
(dB)
D98AU887
18
16
14
12
10
8
6
4
2
0
10
100
1K
10K
Freq(Hz)
30/34
TDA7437N
Curves of electrical characteristics
Figure 20. Test board diagram
GND VCC
CON1
C17
22μF
C18
100nF
R4
2.7K
R3
5.6K
JP2 JP1
C11
C10
C8
C7
C19
5.6nF
18nF
22nF
100nF
100nF
C16 22μF
TRL
MIDRI
MIDRO
BASSRO
BASSRI
CREF
25
C6 100nF
C5 100nF
C4 22nF
C3 18nF
C20 5.6nF
BASSLO
BASSLI
MIDLO
44
43
42
41
40
31
30
27
26
39
TRR
1
IN_R
2
3
4
24
23
C21
2.2μF
R2
5.6K
O_R
C22 4.7nF
MIDLI
I_L
CON4
22
20
LOUDR
R1
2.7K
C23 4.7μF
C24 4.7μF
C25 470nF
C26 470nF
C27 470nF
C28 470nF
C29 470nF
C2
2.2μF
DIFG_R
DIFF_R
ST4_R
ST1_R
ST2_R
ST3_R
MONO
5
DIFG_R
DIFF_R
ST4_R
ST1_R
ST2_R
ST3_R
MONO
21
38
28
37
36
O_L
CON2
6
SCL
SCL
JP3
7
SMEX
SDA
SMEX
SDA
8
DGND
DGND
9
R5
50
10
11
C14
C13
C12
C9
CON3
34
33
LF
OUTLF
RF
RF
LR
RR
C30 4.7nF
12
LOUDR
32
13
14
15
16
17
18
19
35
29
CON5
LR
DIFG_R
DIFF_R
ST4_R
ST1_R
ST2_R
ST3_R
CSM
PAUSE
OUTRR
DIFG_L
DIFF_L
ST4_L
ST1_L
ST2_L
ST3_L
GND
C31 4.7μF
C32 4.7μF
C33 470nF
C34 470nF
C35 470nF
C36 470nF
C1
2.2nF
C15
10μF
D98AU882
31/34
Package information
TDA7437N
7
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 21. LQFP44 (10x10) Mechanical data and package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
1.60
TYP. MAX.
0.0630
A
A1
A2
b
0.05
1.35
0.30
0.09
0.15 0.0020
0.0059
1.40
0.37
1.45 0.0531 0.0551 0.0571
0.45 0.0118 0.0146 0.0177
c
0.20 0.0035
0.0079
D
11.80 12.00 12.20 0.4646 0.4724 0.4803
9.80 10.00 10.20 0.3858 0.3937 0.4016
D1
D2
D3
E
2.00
0.0787
8.00
0.3150
11.80 12.00 12.20 0.4646 0.4724 0.4803
9.80 10.00 10.20 0.3858 0.3937 0.4016
E1
E2
E3
e
2.00
0.0787
8.00
0.80
0.60
1.00
0.3150
0.0315
L
0.45
0.75 0.0177
0.0295
0.0039
L1
K
0.0394
3.5˚(min.),7˚(max.)
0.10
ccc
LQFP44 (10 x 10 x 1.40mm)
Exposed Pad Down
Note: 1. The size of exposed pad is variable depending of lead-
frame design pad size. End user should verify “D2” and
“E2” dimensions for each device application.
7278839 C
32/34
TDA7437N
Revision history
8
Revision history
Table 14. Document revision history
Date
Revision
Changes
24-Jan-06
01-Dec-06
1
2
Initial release.
Package changed, layout change, text modifications.
33/34
TDA7437N
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34/34
相关型号：
E-TDA7454
Quad BTL output, high efficiency (class SB) power amplifier with clip detection, stand-by and mute inputs
STMICROELECTR
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