EMIF10-LCD02F3 [STMICROELECTRONICS]
10 line EMI filter and ESD protection for LCD and cameras; 10号线EMI滤波器和ESD保护LCD和相机
| 型号： | EMIF10-LCD02F3 |
| 厂家： | 
ST |
| 描述： | 10 line EMI filter and ESD protection for LCD and cameras |
| 文件： | 总8页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EMIF10-LCD02F3
10 line EMI filter and ESD protection for
LCD and cameras
Main product characteristics:
Where EMI filtering in ESD sensitive equipment is
required :
■ LCD for Mobile phones
■ Computers and printers
■ Communication systems
■ MCU Boards
Flip-Chip
(24 bumps)
Description
Pin Configuration (bump side)
The EMIF10-LCD02F3 is a 10 lines highly
integrated devices designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interferences. The EMIF10 flip chip packaging
means the package size is equal to the die size.
5
3
4
2
1
GND
O1
O2
I1
I2
A
B
C
D
E
O3
O5
O7
O9
O4
O6
I3
I5
I7
I9
I4
I6
This filter includes ESD protection circuitry, which
prevents damage to
subjected to ESD surges up 15kV.
GND
GND
GND
the application when
O8
I8
O10
I10
Benefits
■ Lead free package
Basic Cell Configuration
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ 400 µm pitch
Low-pass Filter
Output
Input
■ Compatible with high speed data rate
■ Very low PCB space consuming: < 4mm2
■ Very thin package: 0.60 mm
Ri/o = 70Ω
Cline = 30pF
GND
GND
GND
■ High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reducing of parasitic elements through
Complies with the following standards:
IEC61000-4-2:
integration and wafer level packaging
Level 4
15 kV (air discharge)
Order Code
8 kV ( contact discharge)
Part Number
Marking
on inputs and outputs
EMIF10-LCD02F3
GY
MIL STD 833E - Method 3015-6 Class 3
Rev 1
1/8
July 2005
www.st.com
8
1 Electrical characteristics (Tamb = 25°C)
EMIF10-LCD02F3
Table 1.
Symbol
Absolute Maximum Ratings
Parameter
Value
125
Unit
°C
Tj
Junction temperature
Top
Tstg
Operating temperature range
Storage temperature range
-40 to + 85
-55 to +150
°C
°C
1
Electrical characteristics (T
= 25°C)
amb
Symbol
VBR
IRM
Parameter
I
Breakdown voltage
IF
Leakage current @ VRM
VRM
VCL
IPP
Stand-off voltage
VF
V
CL VBR VRM
V
IRM
IR
Clamping voltage
Peak pulse current
RI/O
IPP
Series resistance between Input & Output
Cline
Input capacitance per line
Symbol
VBR
IRM
Test conditions
Min.
Typ.
8
Max.
10
Unit
V
IR = 1 mA
6
VRM = 3V
50
70
200
nA
Ω
RI/O
Cline
Tolerance 20%
Vline = 0V, VOSE = 30 mV, F =1 MHz
30
pF
2/8
EMIF10-LCD02F3
1 Electrical characteristics (Tamb = 25°C)
Figure 1. S21(dB) all lines attenuation
measurement and Aplac simulation
Figure 2. Analog cross talk measurements
0.00
dB
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
100.0k
1.0M
10.0M
100.0M
Xtalk 1/2
1.0G
f/Hz
Figure 3. ESD response to IEC61000-4-2
(+15kV air discharge) on one input
and on one output
Figure 4.
ESD response to IEC61000-4-2
(-15kV air discharge) on one input
and on one output
Input
10V/d
Input
10V/d
Output
10V/d
Output
10V/d
100ns/d
100ns/d
Figure 5. Line capacitance versus applied
voltage
Cline (pF)
30
25
20
15
10
5
Vline (V)
0
0
1
2
3
4
5
6
3/8
2 Aplac model
EMIF10-LCD02F3
2
Aplac model
Figure 6. Device structure (one cell)
Lbump Rbump
Rline
Rbump Lbump
MODEL = D2
O1
I1
MODEL = D1
bulk
bulk
MODEL = D3
Rbump
Rbump
Rbump
Rbump
Lbump
Cbump
Cbump
Lbump
Cbump
Cbump
Lbump
Lbump
Rgnd
Lgnd
Rgnd
Lgnd
Rgnd
Lgnd
Rgnd
Lgnd
Figure 7. Aplac model variables
aplacvar Rline 70
aplacvar C_d1 15p
aplacvar C_d2 15p
aplacvar C_d3 600p
aplacvar Ls 950pH
aplacvar Rs 150m
aplacvar Lbump 50pH
aplacvar Rbump 20m
aplacvar Cbump 150f
aplacvar Lgnd 50pH
aplacvar Rgnd 100m
aplacvar Rsub 10m
Diode D1
BV=7
IBV=1m
CJO=C_d1
M=0.28
RS=0.1
VJ=0.6
TT=100n
Diode D2
BV=7
IBV=1m
CJO=C_d2
M=0.28
RS=0.1
VJ=0.6
TT=100n
Diode D3
BV=7
IBV=1m
CJO=C_d3
M=0.28
RS=0.01
VJ=0.6
TT=100n
4/8
EMIF10-LCD02F3
3 Ordering information scheme
3
Ordering information scheme
EMIF yy - xxx zz F3
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
3 = Lead free Pitch = 400µm, Bump = 255µm
5/8
4 Package information
EMIF10-LCD02F3
4
Package information
Figure 8. Mechanical data
605µm 55
400µm 40
185µm 10
255µm 40
1.97mm 30µm
Figure 9. Foot print recommendations
Figure 10. Marking
Dot, ST logo
Copper pad Diameter:
220µm recommended
260µm maximum
xx = marking
z = packaging location
yww = datecode
(y = year
ww = week)
E
Solder mask opening:
300µm minimium
x x z
Solder stencil opening :
220µm recommended
y
w w
6/8
EMIF10-LCD02F3
5 Flip-chip tape and reel specifications
5
Flip-chip tape and reel specifications
Dot identifying Pin A1 location
Ø 1.5 +/- 0.1
4 +/- 0.1
ST
ST
ST
0.73 +/- 0.05
4 +/- 0.1
User direction of unreeling
All dimensions in mm
6
7
Ordering information
Part Number
Marking
Package
Flip-Chip
Weight
Base qty
5000
Delivery mode
EMIF10-LCD02F3
GY
5.0 mg
Tape & reel (7”)
Revision history
Date
Revision
Changes
11-Jul-2005
1
Initial release.
7/8
7 Revision history
EMIF10-LCD02F3
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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8/8
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