ETC5067D [STMICROELECTRONICS]
POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE; 功率放大器串行接口CODEC / FILTERWITH接收
| 型号： | ETC5067D |
| 厂家： | 
ST |
| 描述： | POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE |
| 文件： | 总18页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ETC5064/64-X
ETC5067/67-X
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE
POWER AMPLIFIER
.
COMPLETE CODEC AND FILTERING SYS-
TEM INCLUDING :
Transmit high-pass and low-pass filtering.
Receive low-pass filter with sin x/x correction.
Active RC noise filter.
µ-law or A-law compatible CODER and DE-
-
-
-
-
CODER.
Internal precision voltage reference.
Serial I/O interface.
Internal auto-zero circuitry.
Receive push-pull power amplifiers.
DIP20
(Plastic) N
-
-
-
-
ORDERING NUMBERS:
ETC5064N
.
.
.
µ-LAW ETC5064
A-LAW ETC5067
MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.
± 5 V OPERATION.
ETC5064N-X
ETC5067N
ETC5067N-X
.
.
.
LOW OPERATING POWER-TYPICALLY 70 mW
POWER-DOWN STANDBY MODE-TYPICALLY
3 mW
AUTOMATIC POWER DOWN
TTL OR CMOS COMPATIBLE DIGITAL INTER-
FACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0°C TO 70°C OPERATION:ETC5064/67
–40°C TO 85°C OPERATION: ETC5064-X/67-X
.
.
.
PLCC20
.
FN
.
ORDERING NUMBERS:
ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
DESCRIPTION
The ETC5064 (µ-law), ETC5067 (A-law) are mono-
lithic PCM CODEC/FILTERS utilizing the A/D and
D/Aconversion architectureshown in the BlockDia-
grams and a serial PCM interface. The devices are
fabricated using double-polyCMOS process.
Similar to the ETC505X family, these devices fea-
ture an additional Receive Power Amplifier to pro-
vide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two ex-
ternal resistors for an output level of up to ± 6.6 V
across a balanced600Ω load.
SO20
D
ORDERING NUMBERS:
ETC5064D
ETC5064D-X
Also included is an Analog Loopback switch and
TSX output.
ETC5067D
ETC5067D-X
November 1994
1/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN CONNECTIONS (Top views)
DIP20 &
SO20
PLCC20
BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X)
2/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN DESCRIPTION
Name
Pin
Type (*)
N
Description
VPO+
GNDA
VPO-
VPI
O
GND
O
1
2
3
4
The Non-inverting Output of the Receive Power Amplifier
Analog Ground. All signals are referenced to this pin.
The Inverting Output of the Receive Power Amplifier
I
Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to VBB
.
VFRO
VCC
O
S
I
5
6
7
Analog Output of the Receive Filter.
Positive Power Supply Pin. VCC = +5V ±5%
FSR
Receive Frame Sync Pulse which enable BCLKR to shift PCM data into
DR. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.
DR
I
I
8
9
Receive Data Input. PCM data is shifted into DR following the FSR leading
edge
BCLKR/CLKSEL
The bit Clock which shifts data into DR after the FSR leading edge. May
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLKX is used
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
MCKLR/PDN
I
10
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKX, but should be synchronous with MCLKX for
best performance. When MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
MCLKX
BCLKX
I
I
11
12
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKR.
The bit clock which shifts out the PCM data on DX. May vary from 64KHz
to 2.048MHz, but must be synchronous with MCLKX.
DX
O
I
13
14
The TRI-STATE PCM data output which is enabled by FSX.
FSX
Transmit frame sync pulse input which enables BCLKX to shift out the
PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for
timing details.
TSX
O
I
15
16
Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
ANLB
Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO+
output of the receive power amplifier.
GSX
VFXI-
VFXI+
VBB
O
I
17
18
19
20
Analog output of the transmit input amplifier. Used to set gain externally.
Inverting input of the transmit input amplifier.
I
Non-inverting input of the transmit input amplifier.
Negative Power Supply Pin. VBB = -5V ±5%
S
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE is a trademark of National Semiconductor Corp.
3/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
FUNCTIONAL DESCRIPTION
POWER-UP
Each FSX pulse begins the encoding cycle and the
PCM data from the previous encode cycle is shift out
of the enabled DX output on the positive edge of
BCLKX. After 8 bit clock periods, the TRISTATE DX
outputis returnedto a high impedancestate. With an
FSR pulse, PCM data is latched via the DR input on
thenegativeedgeof BCLKX (or on BCKLR if running).
FSX and FSR must be synchronous with MCLKX/R.
When poweris first applied, power-on resetcircuitry
initializes the device and places it into the power-
down mode. All non-essential circuits are deacti-
vated and the DX and VFRO outputsare put in high
impedancestates.To power-upthe device,a logical
low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must
be present. Thus 2 power-down control modes are
available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR in-
puts continuouslylow. The device will power-down
approximately 2 ms after the last FSX pulse. The
TRI-STATE PCM data output, DX, will remain in the
high impedance state until the second FSX pulse.
ASYNCHRONOUS OPERATION
For asynchronousoperation,separate transmit and
receive clocks may be applied. MCLKX and MCLKR
must be 2.048MHz for the ETC5067 or 1.536MHz,
1.544 MHz for the ETC5064, and need not be syn-
chronous.For best transmissionperformance,how-
ever, MCLKR shouldbe synchronouswith MCLKX,
which is easily achievedby applyingonly staticlogic
levels to theMCLKR/PDNpin.Thiswill automatically
connectMCLKX toall internalMCLKR functions(see
pin description). For 1.544 MHz operation, the de-
vice automaticallycompensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and BCLKX.
FSR starts each decoding cycle and must be syn-
chronous with BCLKR. BCLKR must be a clock, the
logic levels shown in Table 1 are not valid in asyn-
chronous mode. BCLKX and BCLKR may operate
from 64kHz to 2.048 MHz.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock
and bit clock should be used for both the transmit
and receive directions.In thismode,a clockmust be
applied to MCLKX and the MCLKR/PDN pin can be
used as a power-down control. A low level on
MCLKR/PDN powers up the device and a high level
powersdown the device. In either case, MCLKX will
be selectedas the master clock for boththe transmit
and receive circuits. A bit clock mustalso be applied
to BCLKX and theBCLR/CLKSELcan be usedto se-
lect the proper internal divider for a master clock of
1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544
MHz operation, the device automatically compen-
sates for the 193 rd clock pulse each frame.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse ora longframe sync pulse.Uponpowerinitiali-
zation, the device assumes a short frame mode. In
this mode, both frame sync pulses. FSX and FSR,
must be one bit clock period long, with timing rela-
tionships specified in figure 2. With FSX high during
a falling edge of BCLKR, the next rising edge of
BCLKX enables the DX TRI-STATE output buffer,
which willoutputthesignbit. Thefollowingsevenris-
ing edges clock out the remaining seven bits, and
the next falling edge disables the DX output. With
FSR high during a falling edge of BCLKR (BCLKX in
synchronousmode), the nextfalling edgeof BCLKR
latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. Both de-
vices may utilize the short frame sync pulse in syn-
chronous or asynchronousoperating mode.
With a fixed level onthe BCLKR/CKSEL pin, BCLKX
will be selected as the bit clock for both the transmit
and receive directions. Table 1 indicates the fre-
quencies of operation which can be selected, de-
pendingon the state ofBCLKR/CLKSEL.In thissyn-
chronousmode, the bit clock, BCLKX, may be from
64 kHz to2.048 MHz, but must be synchronouswith
MCLKX.
Table 1: Selection of Master Clock Frequencies.
Master Clock
Frequency Selected
BCLKR/CLKSEL
ETC5067
ETC5064
ETC5067-X
ETC5064-X
Clocked
2.048MHz
1.536MHz or
1.544MHz
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FSX andFSR, mustbethree ormorebit clock
periods long, with timing relationships specified in
figure 3. Based on the transmit frame sync FSX, the
device will sense whether short or long frame sync
0
1.536MHz or
1.544MHz
2.048MHz
1 (or open circuit)
2.048MHz
1.536MHz or
1.544MHz
4/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
pulses are being used. For 64 kHz operation, the
frame sync pulses must be kept low for a minimum
of 160 ns (see Fig 1). The DX TRI-STATE output
buffer is enabledwith the rising edge of FSX or the
rising edge of BCLKX, whichever comes later, and
the first bit clocked out is the sign bit. The following
seven BCLKX rising edges clock out the remaining
seven bits. The DX outputis disabled by the falling
BCLKX edge following the eighth rising edge, or by
FSX goinglow, whichevercomeslater. Arising edge
on thereceive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKx in synchronous
mode).Bothdevicesmay utilize the longframe sync
pulse in synchronous or asynchronousmode.
RECEIVE SECTION
The receive section consist of an expanding DAC
which drives a fifth order switched-capacitor low
pass filter clocked at 256kHz. The decoderis A-law
(ETC5067 and ETC5067-X) or µ–law (ETC5064
and ETC5064-X) and the 5 th order low pass filter
corrects for the sin x/x attenuation due to the 8kHz
sample and hold. The filter is then followed by a 2
nd order RC active post-filter and power amplifier
capableof driving a 600Ω load to a levelof 7.2dBm.
The receive section is unity-gain. Upon the oc-
curence of FSR, the data at the DR input is clocked
in on the falling edge of the next eight BCLKR
(BCKLX) periods.At the endofthedecodertime slot,
the decoding cycle begins, and 10µs later the de-
coder DAC outputis updated.Thetotaldecoder de-
lay is about10µs (decoderup-date) plus 110µs (fil-
ter delay) plus 62.5µs (1/2 frame), which gives ap-
proximately 180µs.
TRANSMIT SECTION
The transmitsectioninput isan operationalamplifier
with provision for gainadjustmentusingtwoexternal
resistors,seefigure4. Thelownoiseandwide band-
width allow gains in excess of 20 dB across the
audio passband to be realized. The op amp drives
a unity gain filter consisting of RC active pre-filter,
followed by an eighth order switched-capacitor
bandpass filter directly drives the encodersample-
and-hold circuit. The A/D is of companding type ac-
cording to A-law (ETC5067 and ETC5067-X) or µ-
law (ETC5064 and ETC5064-X) coding conven-
tions. A precision voltage reference is trimmed in
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided
for directly driving a matched line interface trans-
former. The gain of the first power amplifier can be
adjustedto boostthe± 2.5Vpeakoutputsignalfrom
the receive filter up ± 3.3V peak into an unbalanced
300Ω load,or ±4.0V into an unbalanced15kΩ load.
The second power amplifier is internally connected
in unity-gain inverting mode to give 6dB of signal
gainfor balancedloads. Maximumpowertransferto
a 600Ω subscriber line termination is obtained by
differientially driving a balanced transformer with a
√2 : 1 turns ratio, as shown in figure 4. A total peak
power of 15.6dBmcan be delivered to the load plus
termination. Both power amplifier can be powered
downindependentlyfromthe PDNinputbyconnect-
ing the VPI input to VBB saving approximately 12
mW of power.
manufacturing to provide an input over load (tMAX
of nominally 2.5V peak (see table of Transmission
Characteristics). The FSX frame sync pulse controls
thesampling of thefileroutput,andthenthesucces-
sive-approximationencodingcyclebegins.The8-bit
code is then loaded into a buffer and shifted out
throughDX atthe next FSX pulse.the total encoding
delaywill be approximately165µs (due to the trans-
mit filter) plus 125µs (due to encodingdelay), which
totals 290µs. Any offset voltage due to the filters or
comparator is cancelled by sign bit integration.
)
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
V
VCC to GNDA
VBB to GNDA
7
VBB
-7
V
VIN, VOUT Voltage at any Analog Input or Output
Voltage at any Digital Input or Output
VCC +0.3 to VBB -0.3
VCC +0.3 to GNDA -0.3
V
V
Toper
Operating Temperature Range: ETC5064/67
ETC5064-X/67-X
-25 to +125
-40 to +125
°C
°C
Tstg
Storage Temperature Range
-65 to +150
300
°C
°C
Lead Temperature (soldering, 10 seconds)
5/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS
VCC =5.0V±5%,VBB =-5V±5%, GNDA =0V, TA =0°C to70°C (ETC5064-X/67-X:TA =–40°C to85°), unless
otherwise noted; typical characteristics specified at VCC = 5.0V, VBB =-5.0V, TA = 25°C; all signals are refer-
enced to GNDA.
DIGITAL INTERFACE (All devices)
Symbol
VIL
Parameter
Min.
Typ.
Max.
Unit
V
Input Low Voltage
Input High Voltage
0.6
VIH
2.2
V
VOL
Output Low Voltage
IL = 3.2 mA
DX
TSX
0.4
0.4
V
V
IL = 3.2 mA, Open Drain
VOH
IIL
Output High Voltage
IH = 3.2 mA
DX
2.4
V
Input Low Current (GNDA ≤ VIN ≤ VIL )all digital inputs
Except BCLKR
– 10
10
10
10
µA
IIH
Input High Current (VIH ≤ VIN ≤ VCC) Except ANLB
– 10
– 10
µA
µA
IOZ
Output Current in High Impedance State (TRI-STATE)
(GNDA ≤ VO ≤ VCC
)
DX
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol
Parameter
Min.
Typ.
Max.
Unit
IIXA
Input Leakage Current
(– 2.5 V ≤ V ≤ + 2.5 V)
VFxI + or VFxI –
VFXI + or VFXI –
– 200
200
nA
RIXA
Input Resistance
(– 2.5 V ≤ V ≤ + 2.5 V)
10
10
MΩ
ROXA
RLXA
Output Resistance (closed loop, unity gain)
Load Resistance
1
3
Ω
kΩ
pF
V
GSX
GSX
GSX
CLXA
Load Capacitance
50
VOXA
Output Dynamic Range (RL ≥ 10 kΩ)
Voltage Gain (VFXI + to GSX)
Unity Gain Bandwidth
– 2.8
5000
1
+2.8
AVXA
V/V
MHz
mV
V
FUXA
2
VOSXA
VCMXA
CMRRXA
PSRRXA
Offset Voltage
– 20
– 2.5
60
20
Common-mode Voltage
2.5
Common-mode Rejection Ratio
Power Supply Rejection Ratio
dB
dB
60
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol
RORF
Parameter
Min.
10
Typ.
Max.
Unit
Ω
Output Resistance
VFRO
1
3
RLRF
Load Resistance (VFRO = ± 2.5 V)
Load Capacitance
kΩ
pF
CLRF
25
VOSRO
Output DC Offset Voltage
– 200
200
mV
6/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS (Continued)
ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices)
Symbol
IPI
Parameter
Input Leakage Current (– 1.0 V ≤ VPI ≤ 1.0 V)
Input Resistance (– 1.0 ≤ VPI ≤ 1.0 V)
Input Offset Voltage
Output Resistance (inverting unity–gain at VPO + or VPO –)
Unity–gain Bandwidth, Open Loop (VPO –)
Min.
– 100
10
Typ.
Max.
Unit
nA
100
RIPI
VIOS
ROP
FC
MΩ
mV
Ω
– 25
25
1
400
kHz
pF
CLP
Load Capacitance (VPO + or VPO – to GNDA)
RL ≥ 1500 Ω
RL = 600 Ω
RL = 300 Ω
100
500
1000
GAp +
Gain VPO to VPO + to GNDA, Level at VPO – = 1. 77 Vrms
– 1
V/V
dB
–
(+ 3 dBmO)
PSRRp
Power Supply Rejection of VCC or VBB
(VPO– connected to VPI)
0 kHz – 4 kHz
60
36
0 kHz – 50 kHz
POWER DISSIPATION (all devices)
Symbol
Parameter
Power-down Current at ETC6064/67
ETC5064-X/67-X
Power-down Current at ETC6064/67
ETC5064-X/67-X
Active Current at ETC6064/67
ETC5064-X/67-X
Active Current at ETC6064/67
ETC5064-X/67-X
Min.
Typ.
Max.
Unit
ICC
IBB
ICC
IBB
0
0.5
0.5
1.5
mA
mA
0
0.05
0.05
0.3
0.4
mA
mA
1
7.0
7.0
10.0
12.0
mA
mA
1
7.0
7.0
10.0
12.0
mA
mA
7/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
All TIMING SPECIFICATIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
1/tPM
Frequency of master clocks
MCLKX and MCLKR
1.536
2.048
MHz
Depends on the device used and the
BCLKR/CLKSEL Pin
1.544
tWMH
tWML
tRM
Width of Master Clock High
Width of Master Clock Low
MCLKX and MCLKR
MCLKX and MCLKR
MCLKX and MCLKR
MCLKX and MCLKR
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rise Time of Master Clock
50
50
tFM
Fall Time of Master Clock
tPB
Period of Bit Clock
485
160
160
488
15.725
tWBH
tWBL
tRB
Width of Bit Clock High (VIH = 2.2 V)
Width of Bit Clock Low (VIL = 0.6 V)
Rise Time of Bit Clock (tPB = 488 ns)
Fall Time of Bit Clock (tPB = 488 ns)
50
50
tFB
tSBFM
Set-up time from BCLKX high to MCLKX falling edge.
(first bit clock after the leading edge of FSX)
100
0
tHBF
Holding Time from Bit Clock Low to the Frame Sync
(long frame only)
ns
tSFB
Set-up Time from Frame Sync to Bit Clock (long frame only)
80
ns
ns
tHBFI
Hold Time from 3rd Period of Bit Clock
Low to Frame Sync (long frame only)
FSX or FSR
100
tDZF
Delay Time to valid data from FSX or BCLKX, whichever
comes later and delay time from FSX to data output disabled
(CL = 0 pF to 150 pF)
20
0
165
ns
ns
tDBD
Delay Time from BCLKX high to data valid
(load = 150 pF plus 2 LSTTL loads)
150
165
tDZC
tSDB
tHBD
tHOLD
tSF
Delay Time from BCLKX low to data output disabled
Set-up Time from DR valid to BCLKR/X low
50
50
50
0
ns
ns
ns
ns
ns
Hold Time from BCLKR/X low to DR invalid
Holding Time from Bit Clock High to Frame Sync (short frame only)
Set-up Time from FSX/R to BCLKX/R Low
(short frame sync pulse) - Note 1
80
tHF
Hold Time from BCLKX/R Low to FSX/R Low
(short frame sync pulse) - Note 1
100
160
ns
tXDP
tWFL
Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads)
140
ns
ns
Minimum Width of the Frame Sync Pulse (low level)
(64 bit/s operating mode)
Note : 1.For short frame sync timing. FSX and FSR must go high while their respective bit clocks are high.
Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)
8/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 2 : Short Frame Sync Timing.
9/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 3 : Long Frame Sync Timing.
10/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS
(all devices) TA = 0°C to 70°C (ETC5064-X/67-X: TA = –40°C to 85°), VCC = 5V ± 5%, VBB = – 5V ± 5%,
GNDA=0V, f =1.02kHz,V = 0dBm0transmit inputamplifierconnectedforunity–gainnon–inverting.(unless
IN
otherwise specified).
AMPLITUDE RESPONSE
Symbol
Parameter
Min.
Typ.
Max.
Unit
Absolute Levels - Nominal 0 dBm0 is 4 dBm (600Ω).
1.2276
Vrms
0 dBm0
tMAX
Max Overload Level
3.14 dBm0
ETC5067
ETC5064
2.492
2.501
VPK
dB
3.17 dBm0
GXA
Transmit Gain, Absolute (TA = 25°C, VCC = 5V, VBB = -5V)
-0.15
0.15
Input at GSX = 0dBm0 at 1020Hz
GXR
Transmit Gain, Relative to GXA
f = 16Hz
f = 50Hz
f = 60Hz
f = 180Hz
f = 200Hz
f = 300Hz -3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
-
-
-
-40
-30
-26
-0.2
-0.1
0.15
0.20
0.05
0
-2.8
-1.8
-0.15
-0.35
-0.35
-0.7
dB
f = 3400Hz
f = 4000Hz
-14
-32
f = 4600Hz and up, measure response from oHz to 4000Hz
GXAT
Absolute Transmit Gain Variation with Temperature
TA = 0°C to +70°C
TA = –40°C to +85°C (ETC5064-X/67-X)
dB
dB
-0.1
-0.15
0.1
0.15
GXAV
GXRL
Absolute Transmit Gain Variation with Supply Voltage
(VCC = 5V ±5%, VBB = -5V ±5%)
-0.05
0.05
Transmit Gain Variation with Level
Sinusolidal Test Method Reference Level = -10dBm0
VFXI+ = -40dBm0 to +3dBm0
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
VFXI+ = -50dBm0 to -40dBm0
VFXI+ = -55dBm0 to -50dBm0
GRA
GRR
Receive Gain, Absolute (TA = 25°C, VCC = 5V, VBB = -5V)
Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz
-0.15
0.15
Receive Gain, Relative to GRA
f = 0Hz to 3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
-0.15
-0.35
-0.35
-0.7
0.15
0.20
0.05
0
dB
f = 3400Hz
f = 4000Hz
-14
GRAT
Absolute Receive Gain Variation with Temeperature
TA = 0°C to +70°C
-0.1
-0.15
0.1
0.15
dB
dB
TA = –40°C to +85°C (ETC5064-X/67-X)
GRAV
GRRL
Absolute Receive Gain Variation with Supply Voltage
(VCC = 5V ±5%, VBB = -5V ±5%)
-0.05
0.05
Receive Gain Variation with Level
Sinusoidal Test Method; Reference Input PCM code
corresponds to an ideally encoded -10dBm0 signal
PCM level = -40dBm0 to +3dBm0
PCM level = -50dBm0 to -40dBm0
PCM level = -55dBm0 to -50dBm0
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
V
VRO
Receive Filter Output at VFRO RL = 10KΩ
-2.5
2.5
11/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued).
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol
DXA
Parameter
Min.
Typ.
Max.
Unit
Transmit Delay, Absolute (f = 1600 Hz)
290
315
µs
DXR
Transmit Delay, Relative to DXA
f = 500 Hz-600 Hz
195
120
50
20
55
220
145
75
40
75
f = 600 Hz-800 Hz
f = 800 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz
µs
80
130
105
155
DRA
DRR
Receive Delay, Absolute (f = 1600 Hz)
180
200
µs
µs
Receive Delay, Relative to DRA
f = 500 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600 Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz
– 40
– 30
– 25
– 20
70
100
145
90
125
175
NOISE
Symbol
Parameter
Min.
Typ.
Max.
Unit
NXP
Transmit Noise, P Message (A-LAW, VFXI + = 0 V) Weighted 1)
ETC5064
ETC5064-X
– 74
– 74
– 69 dBm0p
– 67 dBm0p
NRP
NXC
Receive Noise, P Message Weighted
(A-LAW, PCM Code Equals Positive Zero)
– 82
– 79 dBm0p
Transmit Noise, C Message Weighted
(µ-LAW, VFxI + = 0 V)
ETC5064
ETC5064-X
12
12
15
16
dBrnC0
dBrnC0
NRC
Receive Noise, C Message Weighted
(µ-LAW, PCM Code Equals Alternating Positive and Negative Zero)
8
11
dBrnC0
dBm0
NRS
Noise, Single Frequency
– 53
f = 0 kHz to 100 kHz, Loop around Measurement, VFXI + = 0 V
PPSRX
NPSRX
PPSRR
Positive Power Supply Rejection, Transmit (note 2)
VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
40
40
dBp
dBp
Negative Power Supply Rejection, Transmit (note 2)
VBB = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
Positive Power Supply Rejection, Receive (PCM code equals
positive zero, VCC = 5.0 VDC + 100 mVrms)
f = 0 Hz-4000Hz
A LAW
µ LAW
40
40
40
36
dBp
dBc
dB
f = 4 kHz-25 kHz
f = 25 kHz-50 kHz
dB
NPSRR
Negative Power Supply Rejection, Receive (PCM code equals
positive zero, VBB = – 5.0 VDC + 100 mVrms)
f = 0 Hz-4000Hz
A LAW
µ LAW
40
40
40
36
dBp
dBc
dB
f = 4 kHz-25 kHz
f = 25 kHz-50 kHz
dB
SOS
Spurious out-of-band Signals at the Channel Output
0 dBm0, 300 Hz-3400 Hz input PCM applied at DR
4600 Hz-7600 Hz
–32
–40
–32
dB
dB
dB
7600 Hz-8400 Hz
8400 Hz-100,000 Hz
12/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued).
DISTORTION
Symbol
Parameter
Min.
Typ.
Max.
Unit
STDX
or
Signal to Total Distortion (sinusoidal test method)
STDR
Transmit or Receive Half-channel
Level = 3.0 dBm0
= 0 dBm0 to – 30 dBm0
= – 40 dBm0
dBp
(ALAW)
33
36
29
30
14
15
XMT
RCV
XMT
RCV
dBc
(µLAW)
= – 55 dBm0
SFDX
SFDR
IMD
Single Frequency Distortion, Transmit (TA = 25°C)
Single Frequency Distortion, Receive (TA = 25°C)
– 46
– 46
– 41
dB
dB
dB
Intermodulation Distortion
Loop Around Measurement, VFXI + = – 4 dBm0 to
– 21 dBm0, two Frequencies in the Range 300 Hz-3400 Hz
CROSSTALK
Symbol
Parameter
Min.
Typ.
Max.
Unit
CTX-R
Transmit to Receive Crosstalk, 0dBm0 Transmit
f = 300 Hz-3400 Hz, DR = Steady PCM Code ETC5064/67
ETC5064-X/67-X
Receive to Transmit Crosstalk, 0dBm0 Receive Level (note 2)
– 90
– 75
– 65
dB
dB
CTR-X
f = 300 Hz-3400 Hz, VFXI = 0 V
ETC5064/67
ETC5064-X/67-X
– 90
– 70
– 65
dB
dB
POWER AMPLIFIERS
Symbol
Parameter
Min.
Typ.
Max.
Unit
VOL
Maximum 0 dBm0 Level for Better than ± 0.1 dB Linearity Over
Vrms
the Range 10 dBm0 to + 3 dBm0
(balanced load, RL connected between VPO + and VPO –)
RL = 600 Ω
RL = 1200 Ω
RL = 30 kΩ
33
3.5
4.0
S/DP
Signal/Distortion RL = 600 Ω, 0 dBm0
50
dB
Notes : 1. Measured by extrapolation from the distortion test results.
2. PPSRX, NPSRX, CTR–X measured with a –50dBm0 activating signal applied at VFXI+
ENCODING FORMAT AT DX OUTPUT
A-Law
µLaw
(Including even bit inversion)
VIN (at GSX) = + Full-scale
VIN (at GSX) = 0 V
1 0 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
VIN (at GSX) = – Full-scale
0 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
13/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
APPLICATION INFORMATION
Figure 4 : Typical Asynchronous Application.
POWER SUPPLIES
While the pins at the ETC506X family are well pro-
tected against electrical misure, it is recommended
that the standard CMOS practice be followed, en-
suring that ground is connectedtothe device before
any other connections are made. In applications
where the printed circuit board may be pluggedinto
a ”hot” socket with power and clocks already pre-
sent, an extra long ground pin in the connector
should be used.
All ground connectionsto each device should meet
at a common point ascloseas possible to theGNDA
pin. This minimizes the interaction of ground return
currentsflowing througha commonbusimpedance.
0.1µF supply decoupling capacitors should be con-
nected from this common ground point to VCC and
VBB as close to the device as possible.
For best performance, the ground point of each
CODEC/FILTER on a card should be connectedto
a commoncardgroundin star formation,rather than
via a ground bus. This common groundpoint should
be decoupled to VCC and VBB with 10µF capaci-
tors.
For best performance, TSx should be grounded if
not used.
14/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
SO20 PACKAGE MECHANICAL DATA
mm
inch
DIM.
MIN.
TYP.
MAX.
2.65
0.2
MIN.
TYP.
MAX.
0.104
0.008
0.096
0.019
0.013
A
a1
a2
b
0.1
0.004
2.45
0.49
0.32
0.35
0.23
0.014
0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
12.6
10
13.0
0.496
0.394
0.510
0.419
E
10.65
e
1.27
0.050
0.450
e3
F
11.43
7.4
0.5
7.6
0.291
0.020
0.300
0.050
0.030
L
1.27
0.75
M
S
8° (max.)
15/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PLCC20 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
9.78
8.89
4.2
TYP.
MAX.
10.03
9.04
MIN.
0.385
0.350
0.165
MAX.
0.395
0.356
0.180
A
B
D
4.57
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38
0.290
0.330
0.004
e
1.27
5.08
0.38
0.050
0.200
0.015
e3
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
16/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
DIP20 PACKAGE MECHANICAL DATA
mm
inch
DIM.
MIN.
0.254
1.39
TYP.
MAX.
MIN.
0.010
0.055
TYP.
MAX.
a1
B
b
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
2.54
22.86
0.335
0.100
0.900
e3
F
7.1
0.280
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
17/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica-
tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre-
viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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18/18
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